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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id g62sm21881331wmf.46.2021.02.14.09.59.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 09:59:20 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 01/42] linux-user/mips64: Restore setup_frame() for o32 ABI Date: Sun, 14 Feb 2021 18:58:31 +0100 Message-Id: <20210214175912.732946-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x334.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" 64-bit MIPS targets lost setup_frame() during the refactor in commit 8949bef18b9. Restore it declaring TARGET_ARCH_HAS_SETUP_FRAME, to be able to build the o32 ABI target. Fixes: 8949bef18b9 ("linux-user: move mips/mips64 signal.c parts to mips directory") Reviewed-by: Richard Henderson Reviewed-by: Laurent Vivier Signed-off-by: Philippe Mathieu-Daudé --- linux-user/mips64/target_signal.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/linux-user/mips64/target_signal.h b/linux-user/mips64/target_signal.h index 799f7a668cd..f1f0ed7f706 100644 --- a/linux-user/mips64/target_signal.h +++ b/linux-user/mips64/target_signal.h @@ -67,4 +67,8 @@ typedef struct target_sigaltstack { #define TARGET_MINSIGSTKSZ 2048 #define TARGET_SIGSTKSZ 8192 +#if defined(TARGET_ABI_MIPSO32) +/* compare linux/arch/mips/kernel/signal.c:setup_frame() */ +#define TARGET_ARCH_HAS_SETUP_FRAME +#endif #endif /* MIPS64_TARGET_SIGNAL_H */ From patchwork Sun Feb 14 17:58:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087311 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22E52C433DB for ; Sun, 14 Feb 2021 18:06:33 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C7A0B600CF for ; Sun, 14 Feb 2021 18:06:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C7A0B600CF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:48732 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBLmx-0004lJ-RR for qemu-devel@archiver.kernel.org; Sun, 14 Feb 2021 13:06:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33168) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBLg8-0006n1-Oj for qemu-devel@nongnu.org; Sun, 14 Feb 2021 12:59:28 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:40726) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBLg7-00049P-B0 for qemu-devel@nongnu.org; Sun, 14 Feb 2021 12:59:28 -0500 Received: by mail-wr1-x429.google.com with SMTP id v14so6083796wro.7 for ; Sun, 14 Feb 2021 09:59:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9/cqSvnjsoH/NNZePdyMLOBBlx6690wleUk2PleenZE=; b=dm9A+RQRX9ewSTex1RyZ+3J9b9P4rPNUXYv5f1afjVs+LEzZtic1obHO13u6vqGCZ6 pSFVQkifJJM+BaqBbm1CCsquwoAUWNMQSj0qxyYwK19NtV6W2QyZXjDkTQFXPnGG7AHt dM2Z3/fBfc0/up/oFv+Uu7kJi4K7IKWSetpaLysvE+84u03yWPYd6CTM+pgnz4nZUDhp EsVWtyEFxQxWXcg3IvmKJrfWWorW0Fl89pN+fEyoRx5qKOQ+1yISJ0gmzkZGHh3MTrN5 euHtZtZLv+ZLcmtRBmpZ7qk44LbRfyko6iiyeIjRSOg5rEWI2H5CGDs65Eik7yRpC3FT LdAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=9/cqSvnjsoH/NNZePdyMLOBBlx6690wleUk2PleenZE=; b=UI+4BcnL0ADq89ev+xP7oXjG9IZjMwIUgV6cQMRNVFkgGDBSWV3eRU+QB3+pD62GM0 JfqXRAfwBHNoJiSehRG8D/WtmGiODTI5SK3Sxp5L3Z2AHF0AvqGuOPfGQkggQSz4dr6V ND5K4M20buAse1igune2x2HkgBAmODi9Kx3N+JlmeiY3ErhNhFsx6k1ajDggtxG/sc3q 8eJxUQSzyUX5YX8qR814acARWT+LC/pMIXIT3ZFrZIPCiQ8zyu71DpIlT12HkDRdTiC2 ykBUMyl4yFDEp0hx9fKSfGB1RFk0YA8Jmfc6ru/Z41mmuojt+ajAdIk2PcXgGuZGA3SA tURg== X-Gm-Message-State: AOAM53375s2K79g0JHcOfJi9u7uWATqv5yUWk+s+t6wBWc85tPs00XMT Bh2gNpL+IWNpZmvCE+O/UJGn3hOEWrw= X-Google-Smtp-Source: ABdhPJxcPohmsCDU10+kIvnODxsU7GHL5qkKrrVDVFu/WDvCBZMsDdD3SY9F1Glh6mY+VLdM6URxmg== X-Received: by 2002:adf:92a6:: with SMTP id 35mr14835392wrn.193.1613325565504; Sun, 14 Feb 2021 09:59:25 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id c9sm21776048wmb.33.2021.02.14.09.59.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 09:59:25 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 02/42] linux-user/mips64: Support o32 ABI syscalls Date: Sun, 14 Feb 2021 18:58:32 +0100 Message-Id: <20210214175912.732946-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" o32 ABI syscalls start at offset 4000. Reviewed-by: Richard Henderson Reviewed-by: Laurent Vivier Signed-off-by: Philippe Mathieu-Daudé --- linux-user/mips64/syscall_nr.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/linux-user/mips64/syscall_nr.h b/linux-user/mips64/syscall_nr.h index 672f2fa51cb..6579421fa63 100644 --- a/linux-user/mips64/syscall_nr.h +++ b/linux-user/mips64/syscall_nr.h @@ -1,4 +1,7 @@ -#ifdef TARGET_ABI_MIPSN32 +#if defined(TARGET_ABI_MIPSO32) +#define TARGET_SYSCALL_OFFSET 4000 +#include "syscall_o32_nr.h" +#elif defined(TARGET_ABI_MIPSN32) #define TARGET_SYSCALL_OFFSET 6000 #include "syscall_n32_nr.h" #else From patchwork Sun Feb 14 17:58:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1241FC433E0 for ; Sun, 14 Feb 2021 18:08:33 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9DE9A64E29 for ; Sun, 14 Feb 2021 18:08:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9DE9A64E29 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:55918 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBLot-0007r2-Jg for qemu-devel@archiver.kernel.org; Sun, 14 Feb 2021 13:08:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33190) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBLgD-0006pS-HK for qemu-devel@nongnu.org; Sun, 14 Feb 2021 12:59:33 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:39163) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBLgC-0004B9-9d for qemu-devel@nongnu.org; Sun, 14 Feb 2021 12:59:33 -0500 Received: by mail-wr1-x435.google.com with SMTP id v1so6102040wrd.6 for ; Sun, 14 Feb 2021 09:59:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u+P4R7wX8AF+OGlD477IP+Y2yPBUc7P8DSYLD639hCU=; b=C9WDa3+3bo8STg8qP3QPPL1lTN/AiKQvXfwivEx22TCWccwjEGofl3SOFcTV6Fi7py BMYBvx219SlRBDx1aGKsAJyeOppFB4fVCJDqqACOQmy/nD1mGLkkFV9zIH1bHQAjEJnc 8p3Mnb/WCEP5n3Ia0UZnpnLwzfciqG56gd82+zYDqjxPHn4OIJ++Kg1aZeA/ojR/GZuh bYX/1msuRAsTZP4lRt26unZgMVGCkH4ypE1LmV/QZERiFOxGCbJ3cLTg94BuYE43ZsDt mONlCJUgeSwBJrcKq0nSMyseVxQbXXk1WlOIebs1LwA/LxLA8dc3bCwl1NQ8gQnL1d14 zCpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=u+P4R7wX8AF+OGlD477IP+Y2yPBUc7P8DSYLD639hCU=; b=qmrEd40IX77R7mhMA9JAJX0KdFTDKBz6czkUrPalABzVW30oW+mCP0jaOixMwx3NVb i3AjWSJ1NA8ZxzaGpmr56R2HsqeLb+rj/ef28iN57g/s8jOdxjuTszQy8ZgILpgPJb/S NAyjJVkI4KmneiUvhZg2kF1AQjJNOzYGMap1c2zqolHaOt4/8vD4n5+Prj2TVth27imS oX8ep3zYKdBVwE/5R4yjjZc+iXDPxGTA8UC+YFnOzOtbrgb51urIcFYt3v+Xyz6slHQD kgwCZ95QX7XDCC0iKIN3G8KdKJxZkDuS5M0pqv8EJmaaWaYPq9GfrqIq3ycD36bHl5dL 8qfQ== X-Gm-Message-State: AOAM533UTkX5ytj7Zws8noVBxAZcHC2cC6F/tvFCaLCc8XlXC6E5HkQ1 lBdSDV7eswZyXht4ukAF16emHsDttAA= X-Google-Smtp-Source: ABdhPJx4IiSJEthYHKZHTptQtxkWV3xmqNPSeizXe61bQLHeRPmDrVxioGjL9qJRatW6dFfqw0HgWw== X-Received: by 2002:a5d:51d0:: with SMTP id n16mr15428256wrv.382.1613325570755; Sun, 14 Feb 2021 09:59:30 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id o18sm20584458wmp.19.2021.02.14.09.59.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 09:59:30 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 03/42] target/mips/translate: Make cpu_HI/LO registers public Date: Sun, 14 Feb 2021 18:58:33 +0100 Message-Id: <20210214175912.732946-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We will access the cpu_HI/LO registers outside of translate.c. Make them publicly accessible. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/translate.h | 1 + target/mips/translate.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index f47b5f2c8d0..2a1d8f570bb 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -145,6 +145,7 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa); bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa); extern TCGv cpu_gpr[32], cpu_PC; +extern TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; extern TCGv_i32 fpu_fcr0, fpu_fcr31; extern TCGv_i64 fpu_f64[32]; extern TCGv bcond; diff --git a/target/mips/translate.c b/target/mips/translate.c index a5cf1742a8b..be40f79229f 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2179,7 +2179,7 @@ enum { /* global register indices */ TCGv cpu_gpr[32], cpu_PC; -static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; +TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; static TCGv cpu_dspctrl, btarget; TCGv bcond; static TCGv cpu_lladdr, cpu_llval; From patchwork Sun Feb 14 17:58:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7058C433E0 for ; Sun, 14 Feb 2021 18:02:45 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 53B0A64D9A for ; Sun, 14 Feb 2021 18:02:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 53B0A64D9A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:41078 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBLjI-00011U-CN for qemu-devel@archiver.kernel.org; Sun, 14 Feb 2021 13:02:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33222) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBLgJ-0006uN-4x for qemu-devel@nongnu.org; Sun, 14 Feb 2021 12:59:39 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:55100) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBLgH-0004C9-FZ for qemu-devel@nongnu.org; Sun, 14 Feb 2021 12:59:38 -0500 Received: by mail-wm1-x32d.google.com with SMTP id w4so4199208wmi.4 for ; Sun, 14 Feb 2021 09:59:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HIH/Qop6/6k2YrFoaMsBXNf5uQCyB+f+6cDo/DLbLyU=; b=L1Djrp3EmgbzHIb9r6F91UvVAePOJ/KUe4GuUJBeAGuwcZyHN5VBxSdq0eXUD/xixr pFZZpt6TmYL0dQjyTFwRRUZWIuhjvNRuIGvdFXsAf/rxZyyAaOy5Bm8sP9gSz4vc2U6V GCfwNfVSUbKzTxdmwWdNrqHaTtIcJTH5Fe5f6tx2qA01N0rw9ZUrBcCZWPqAxHzrMlek LTiHE3yaJe9VNCQPHEtfw5U1S6gA9xGzdd/rolWwG3qZZBul/lkqCiAAraIi1pELOQla LiVASQrWvwkcwkTVWXX6slCf7Oa81fUPwgz6+k/WbdSC2CHsAoOrqPyAq1eQ6waJ7u3Z tSvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=HIH/Qop6/6k2YrFoaMsBXNf5uQCyB+f+6cDo/DLbLyU=; b=pNbOv2QAlRpWCVE5NJiK2+Zshbpn/LlMocBUYJcjGfjfIeUILc/PHjhGw4m1XUC4ke 3BL8i0nTiu65xAhy1n0LmuWmb2QNBS8+VI88SgHtdC40MD9IT40RnLK9ylrO/cl2kDaL Af/IkSuDGDxuNN6IiYWQ8bnbPTTAt01vXgDIUY9u9FkJXh/LT/BTamHs5nmoalE1YcyJ mnqc+FE7XM/isNqjH1GltIAo0EpzFOb8evr8DRm0npsnW1LQrn4+V6LgegR1AMYv0pc4 xAKV+o7/5GzZTazc8R7D9k7/R8ZmmdOIdLjs+0ZovmmBftYP/1tiDq1ZfyQkKpfPZoIS wMUQ== X-Gm-Message-State: AOAM532ENwXweYNGCUUb55q6za9hWDdHkeygtpAqcnzufRz5XRhlOd8O IGR9A9ghM4WEk9y10aYVMw1p7Ce0G2k= X-Google-Smtp-Source: ABdhPJxjyYAK7SwPuJeEvhFYA0TmuZjoBKYRb2sGkIQOfU5UnSO9osfJhX8zMVAtRehqs1Oy3tGo+Q== X-Received: by 2002:a1c:20cf:: with SMTP id g198mr10723222wmg.173.1613325575777; Sun, 14 Feb 2021 09:59:35 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id o83sm22544318wme.37.2021.02.14.09.59.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 09:59:35 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 04/42] target/mips: Promote 128-bit multimedia registers as global ones Date: Sun, 14 Feb 2021 18:58:34 +0100 Message-Id: <20210214175912.732946-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The cpu::mmr[] array contains the upper halves of 128-bit GPR registers. While they are only used by the R5900 CPU, the concept is generic and could be used by another MIPS implementation. Rename 'cpu::mmr' as 'cpu::gpr_hi' and make them global. When the code is similar to the GPR lower halves, move it close by. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/cpu.h | 10 ++++++--- target/mips/translate.h | 3 +++ target/mips/translate.c | 48 ++++++++++++++++++++--------------------- 3 files changed, 34 insertions(+), 27 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index b9e227a30e9..7011d0dc707 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -460,6 +460,13 @@ typedef struct mips_def_t mips_def_t; typedef struct TCState TCState; struct TCState { target_ulong gpr[32]; +#if defined(TARGET_MIPS64) + /* + * For CPUs using 128-bit GPR registers, we put the lower halves in gpr[]) + * and the upper halves in gpr_hi[]. + */ + uint64_t gpr_hi[32]; +#endif /* TARGET_MIPS64 */ target_ulong PC; target_ulong HI[MIPS_DSP_ACC]; target_ulong LO[MIPS_DSP_ACC]; @@ -505,9 +512,6 @@ struct TCState { float_status msa_fp_status; - /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */ - uint64_t mmr[32]; - #define NUMBER_OF_MXU_REGISTERS 16 target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; target_ulong mxu_cr; diff --git a/target/mips/translate.h b/target/mips/translate.h index 2a1d8f570bb..3014c20cadb 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -145,6 +145,9 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa); bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa); extern TCGv cpu_gpr[32], cpu_PC; +#if defined(TARGET_MIPS64) +extern TCGv_i64 cpu_gpr_hi[32]; +#endif extern TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; extern TCGv_i32 fpu_fcr0, fpu_fcr31; extern TCGv_i64 fpu_f64[32]; diff --git a/target/mips/translate.c b/target/mips/translate.c index be40f79229f..ab9b0999c93 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2179,6 +2179,11 @@ enum { /* global register indices */ TCGv cpu_gpr[32], cpu_PC; +/* + * For CPUs using 128-bit GPR registers, we put the lower halves in cpu_gpr[]) + * and the upper halves in cpu_gpr_hi[]. + */ +TCGv_i64 cpu_gpr_hi[32]; TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; static TCGv cpu_dspctrl, btarget; TCGv bcond; @@ -2187,11 +2192,6 @@ static TCGv_i32 hflags; TCGv_i32 fpu_fcr0, fpu_fcr31; TCGv_i64 fpu_f64[32]; -#if defined(TARGET_MIPS64) -/* Upper halves of R5900's 128-bit registers: MMRs (multimedia registers) */ -static TCGv_i64 cpu_mmr[32]; -#endif - #if !defined(TARGET_MIPS64) /* MXU registers */ static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; @@ -24784,7 +24784,7 @@ static void gen_mmi_pcpyh(DisasContext *ctx) /* nop */ } else if (rt == 0) { tcg_gen_movi_i64(cpu_gpr[rd], 0); - tcg_gen_movi_i64(cpu_mmr[rd], 0); + tcg_gen_movi_i64(cpu_gpr_hi[rd], 0); } else { TCGv_i64 t0 = tcg_temp_new(); TCGv_i64 t1 = tcg_temp_new(); @@ -24802,7 +24802,7 @@ static void gen_mmi_pcpyh(DisasContext *ctx) tcg_gen_mov_i64(cpu_gpr[rd], t1); - tcg_gen_andi_i64(t0, cpu_mmr[rt], mask); + tcg_gen_andi_i64(t0, cpu_gpr_hi[rt], mask); tcg_gen_movi_i64(t1, 0); tcg_gen_or_i64(t1, t0, t1); tcg_gen_shli_i64(t0, t0, 16); @@ -24812,7 +24812,7 @@ static void gen_mmi_pcpyh(DisasContext *ctx) tcg_gen_shli_i64(t0, t0, 16); tcg_gen_or_i64(t1, t0, t1); - tcg_gen_mov_i64(cpu_mmr[rd], t1); + tcg_gen_mov_i64(cpu_gpr_hi[rd], t1); tcg_temp_free(t0); tcg_temp_free(t1); @@ -24844,9 +24844,9 @@ static void gen_mmi_pcpyld(DisasContext *ctx) /* nop */ } else { if (rs == 0) { - tcg_gen_movi_i64(cpu_mmr[rd], 0); + tcg_gen_movi_i64(cpu_gpr_hi[rd], 0); } else { - tcg_gen_mov_i64(cpu_mmr[rd], cpu_gpr[rs]); + tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr[rs]); } if (rt == 0) { tcg_gen_movi_i64(cpu_gpr[rd], 0); @@ -24885,13 +24885,13 @@ static void gen_mmi_pcpyud(DisasContext *ctx) if (rs == 0) { tcg_gen_movi_i64(cpu_gpr[rd], 0); } else { - tcg_gen_mov_i64(cpu_gpr[rd], cpu_mmr[rs]); + tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr_hi[rs]); } if (rt == 0) { - tcg_gen_movi_i64(cpu_mmr[rd], 0); + tcg_gen_movi_i64(cpu_gpr_hi[rd], 0); } else { if (rd != rt) { - tcg_gen_mov_i64(cpu_mmr[rd], cpu_mmr[rt]); + tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt]); } } } @@ -29285,6 +29285,16 @@ void mips_tcg_init(void) offsetof(CPUMIPSState, active_tc.gpr[i]), regnames[i]); +#if defined(TARGET_MIPS64) + cpu_gpr_hi[0] = NULL; + + for (unsigned i = 1; i < 32; i++) { + cpu_gpr_hi[i] = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUMIPSState, + active_tc.gpr_hi[i]), + regnames[i]); + } +#endif /* !TARGET_MIPS64 */ for (i = 0; i < 32; i++) { int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); @@ -29323,16 +29333,6 @@ void mips_tcg_init(void) cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval), "llval"); -#if defined(TARGET_MIPS64) - cpu_mmr[0] = NULL; - for (i = 1; i < 32; i++) { - cpu_mmr[i] = tcg_global_mem_new_i64(cpu_env, - offsetof(CPUMIPSState, - active_tc.mmr[i]), - regnames[i]); - } -#endif - #if !defined(TARGET_MIPS64) for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { mxu_gpr[i] = tcg_global_mem_new(cpu_env, @@ -29344,7 +29344,7 @@ void mips_tcg_init(void) mxu_CR = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, active_tc.mxu_cr), mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]); -#endif +#endif /* !TARGET_MIPS64 */ } void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, From patchwork Sun Feb 14 17:58:35 2021 Content-Type: text/plain; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id m13sm1444951wmc.22.2021.02.14.09.59.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 09:59:40 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 05/42] target/mips: Rename 128-bit upper halve GPR registers Date: Sun, 14 Feb 2021 18:58:35 +0100 Message-Id: <20210214175912.732946-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" TCG displays the upper halve registers with the same name as their lower halves. Rename the upper halves with the '[hi]' suffix. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index ab9b0999c93..9c034c934d5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29289,10 +29289,12 @@ void mips_tcg_init(void) cpu_gpr_hi[0] = NULL; for (unsigned i = 1; i < 32; i++) { + g_autofree char *rname = g_strdup_printf("%s[hi]", regnames[i]); + cpu_gpr_hi[i] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMIPSState, active_tc.gpr_hi[i]), - regnames[i]); + rname); } #endif /* !TARGET_MIPS64 */ for (i = 0; i < 32; i++) { From patchwork Sun Feb 14 17:58:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B5B2C433DB for ; Sun, 14 Feb 2021 18:07:05 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C64CC600CF for ; Sun, 14 Feb 2021 18:07:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C64CC600CF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:50358 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBLnT-0005Uo-Ve for qemu-devel@archiver.kernel.org; Sun, 14 Feb 2021 13:07:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33318) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBLgS-0007BQ-UH for qemu-devel@nongnu.org; Sun, 14 Feb 2021 12:59:48 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:55105) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBLgR-0004FD-1J for qemu-devel@nongnu.org; Sun, 14 Feb 2021 12:59:48 -0500 Received: by mail-wm1-x332.google.com with SMTP id w4so4199329wmi.4 for ; Sun, 14 Feb 2021 09:59:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5iC/ffrrmyVLY0EDOJ/UkLv4vuk3u7VA9Ue4o0gxHXk=; b=k/nhZ3n6V9zl28eL4Q0Nf+yLWMsIrqEBA5Oi34wtYHKKL9aLrnj2kcY21H4QjoOLnx 6507KeP4q6mIMTZDLVrkcSTGJFl7d3DDDTnhjsMpudoxw9ASnpL4dL8y7IT4ox/lNeUE wbfsEWB6DEJM4zjrL/4XlA2hIwY41ezdpkHCTQXOufaJDeK4YXQeG7VxpnCTPfwpF4sm NiWmrW2kgCdooH0luTbAEyk46Z0OWK45nGNwTqzcejizVKIBn8GvMIO5Usc1QxKDF1q/ Phdmi9Khz5VBJ06s2z4i9cFhO2bR6oYoXPr3AY6cc6iKHgy5/BqicHc+NFlLyQe+huVc ki1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=5iC/ffrrmyVLY0EDOJ/UkLv4vuk3u7VA9Ue4o0gxHXk=; b=Nl+VoskG7VaWVGUCVu1DFrjEGa0Z3AdsH+Slg77kx8LvcYcpkZwlj7uQvOhI3y3s7m tjGpajwbXx4HDdPFe4ZGEXZUDd+9+EstZqDGercjp0UYcI+lWAXWRNy2hXNCHEVl7Nld yK48X1IISIIO+PNUxaJ0GHxP4YXOWqKtedrSA7So2uP+z3qw2ZHhylZGCTKR/CvZVU2B fdEu3Z2tWkmhLOh8+q/i5XSweoSaqr6jGdhwByJ/h/0LUeePO7CNaAjV8Vd2IUYKyM9A H+RQsKJ98NKidI0ZXl6x86+NGdlnFH6NvyfgOxXJzrF669cxmB51rzbqgvP7nL0eoebG G8Ow== X-Gm-Message-State: AOAM533OME7D7u2VTzBx+LugLwE8pk9G2f+n/CcW6n0GNdH8Wh/OiKFJ HBQrZAIQHtTsFt1KovG711zPMbHXV50= X-Google-Smtp-Source: ABdhPJwx2RJ8pNLUw5R+K15D7lp+2uBOVt4SUUpS1JOihS6n9apVrMTK2I8G3/X3bgV7mFCWObYYGw== X-Received: by 2002:a7b:c5cc:: with SMTP id n12mr10929618wmk.123.1613325585575; Sun, 14 Feb 2021 09:59:45 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id t6sm11181283wrn.96.2021.02.14.09.59.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 09:59:45 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 06/42] target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers Date: Sun, 14 Feb 2021 18:58:36 +0100 Message-Id: <20210214175912.732946-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/translate.h | 4 ++++ target/mips/translate.c | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/target/mips/translate.h b/target/mips/translate.h index 3014c20cadb..468e29d7578 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -131,6 +131,10 @@ void gen_move_low32(TCGv ret, TCGv_i64 arg); void gen_move_high32(TCGv ret, TCGv_i64 arg); void gen_load_gpr(TCGv t, int reg); void gen_store_gpr(TCGv t, int reg); +#if defined(TARGET_MIPS64) +void gen_load_gpr_hi(TCGv_i64 t, int reg); +void gen_store_gpr_hi(TCGv_i64 t, int reg); +#endif /* TARGET_MIPS64 */ void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg); void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg); void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg); diff --git a/target/mips/translate.c b/target/mips/translate.c index 9c034c934d5..16a731d3f37 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -2291,6 +2291,24 @@ void gen_store_gpr(TCGv t, int reg) } } +#if defined(TARGET_MIPS64) +void gen_load_gpr_hi(TCGv_i64 t, int reg) +{ + if (reg == 0) { + tcg_gen_movi_i64(t, 0); + } else { + tcg_gen_mov_i64(t, cpu_gpr_hi[reg]); + } +} + +void gen_store_gpr_hi(TCGv_i64 t, int reg) +{ + if (reg != 0) { + tcg_gen_mov_i64(cpu_gpr_hi[reg], t); + } +} +#endif /* TARGET_MIPS64 */ + /* Moves to/from shadow registers. */ static inline void gen_load_srsgpr(int from, int to) { From patchwork Sun Feb 14 17:58:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91D6EC433DB for ; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id w25sm21512304wmc.42.2021.02.14.09.59.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 09:59:49 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 07/42] target/mips/translate: Use GPR move functions in gen_HILO1_tx79() Date: Sun, 14 Feb 2021 18:58:37 +0100 Message-Id: <20210214175912.732946-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We have handy functions to access GPR. Use gen_store_gpr() for Move From HI/LO Register and gen_load_gpr() for Move To opcodes. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/translate.c | 21 ++++----------------- 1 file changed, 4 insertions(+), 17 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 16a731d3f37..a2994eb0aa6 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -4126,31 +4126,18 @@ static void gen_shift(DisasContext *ctx, uint32_t opc, /* Copy GPR to and from TX79 HI1/LO1 register. */ static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg) { - if (reg == 0 && (opc == MMI_OPC_MFHI1 || opc == MMI_OPC_MFLO1)) { - /* Treat as NOP. */ - return; - } - switch (opc) { case MMI_OPC_MFHI1: - tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[1]); + gen_store_gpr(cpu_HI[1], reg); break; case MMI_OPC_MFLO1: - tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[1]); + gen_store_gpr(cpu_LO[1], reg); break; case MMI_OPC_MTHI1: - if (reg != 0) { - tcg_gen_mov_tl(cpu_HI[1], cpu_gpr[reg]); - } else { - tcg_gen_movi_tl(cpu_HI[1], 0); - } + gen_load_gpr(cpu_HI[1], reg); break; case MMI_OPC_MTLO1: - if (reg != 0) { - tcg_gen_mov_tl(cpu_LO[1], cpu_gpr[reg]); - } else { - tcg_gen_movi_tl(cpu_LO[1], 0); - } + gen_load_gpr(cpu_LO[1], reg); break; default: MIPS_INVAL("mfthilo1 TX79"); From patchwork Sun Feb 14 17:58:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A60B3C433DB for ; Sun, 14 Feb 2021 18:12:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 36EA464E4E for ; Sun, 14 Feb 2021 18:12:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 36EA464E4E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:38860 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBLsd-0004Kf-9P for qemu-devel@archiver.kernel.org; Sun, 14 Feb 2021 13:12:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33388) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBLgc-0007Hl-Po for qemu-devel@nongnu.org; Sun, 14 Feb 2021 13:00:00 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:46982) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBLga-0004G5-S0 for qemu-devel@nongnu.org; Sun, 14 Feb 2021 12:59:58 -0500 Received: by mail-wr1-x42d.google.com with SMTP id t15so6045299wrx.13 for ; Sun, 14 Feb 2021 09:59:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vZITEFgnUYwtQ6EJ1PixPBWXKAXmo7nnSQHi00WvakQ=; b=vQsBjiW7CRjK08z7P4rllTClsVDtXur9JOMQnpdrS8/dObG3aQkq2IO2DQJFSlgObO 7f3/9kR7IQ/pr/eCJqR2l/ZeQPrOsaYZEDjoZEXk62KsJVERORHvnfF7i+UGk10FswAe BTgeDX3ZGB6E75oqaOZX6bzpxtu38eAl+SOpHZkv9Hmv5mJPbFfKqCBAwttStmX7xXBZ 793BGfLqZzaipo97u2VTnZCIXdkEqZbsWSnoBkxRhmrm2+hmAtVp6tO22icncD2ZuKZu YXY7/BhyboZySaOU1Uhbs6XPyTt7BpvorQa+zza1yytKZH/XPoDPsMdJT26NKA7Z/zfG mfBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=vZITEFgnUYwtQ6EJ1PixPBWXKAXmo7nnSQHi00WvakQ=; b=dKkZ9UKj04H1PBVToR+eFZxNrkDca2NLT/riaKkVIHOvdblcfUvsFrCcJzLFUExVUk zDJkYD7i5XXvSA6vbsNtr2A8Jx7F4MtQ2YkBjnh7jpp0Y2I/tmbkKj0rDbaKP6VsEZVS /M01ctwYkixOsg0VBCD6Vj/qIj+FF28NJdMgQ/NlwAPQLfZKlvXussM9UQeMgr1f/AK6 1mSG2K8ztvj5q+llfG8uYQ5Rzb2p9ieSRUTu7LuMnnGtWRHORofNGSJ1tZghQLhpNqKk +XYAa9+npqgO4egEk/TJIvRuixW32s1kvI6H2yhb3y/7dn45hTSmLhPaGKCqz8zG5Kex ovuA== X-Gm-Message-State: AOAM5311D4WlfnQXrIUQ5+3J84ew2hSfg8mz0FBSiDrj0ZpEhLzBo9Ou AIynC1GFwDdJYjugzu/BIqitaN9oIUI= X-Google-Smtp-Source: ABdhPJzcI3vEpDgj2pJIZnb/xr/hgIApmWNL51uOLWyRGLP6qnLPiYxpSmTf550rCD+YsLqQbqghCg== X-Received: by 2002:adf:80c3:: with SMTP id 61mr14818227wrl.100.1613325595054; Sun, 14 Feb 2021 09:59:55 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id 101sm10400133wrk.4.2021.02.14.09.59.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 09:59:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 08/42] target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree Date: Sun, 14 Feb 2021 18:58:38 +0100 Message-Id: <20210214175912.732946-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce decodetree structure to decode the tx79 opcodes. Start it by moving the existing MFHI1 and MFLO1 opcodes. Remove unnecessary comments. As the TX79 share opcodes with the TX19/TX39/TX49 CPUs, we introduce the decode_ext_txx9() dispatcher where we will add the other decoders later. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/translate.h | 4 ++++ target/mips/tx79.decode | 25 ++++++++++++++++++++++++ target/mips/translate.c | 15 +++------------ target/mips/tx79_translate.c | 37 ++++++++++++++++++++++++++++++++++++ target/mips/txx9_translate.c | 20 +++++++++++++++++++ target/mips/meson.build | 5 +++++ 6 files changed, 94 insertions(+), 12 deletions(-) create mode 100644 target/mips/tx79.decode create mode 100644 target/mips/tx79_translate.c create mode 100644 target/mips/txx9_translate.c diff --git a/target/mips/translate.h b/target/mips/translate.h index 468e29d7578..bc91ac4f53f 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -181,5 +181,9 @@ void msa_translate_init(void); /* decodetree generated */ bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn); +bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); +#if defined(TARGET_MIPS64) +bool decode_ext_tx79(DisasContext *ctx, uint32_t insn); +#endif #endif diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode new file mode 100644 index 00000000000..2e287ebbf36 --- /dev/null +++ b/target/mips/tx79.decode @@ -0,0 +1,25 @@ +# Toshiba C790's instruction set +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Toshiba Appendix B C790-Specific Instruction Set Details + +########################################################################### +# Named attribute sets. These are used to make nice(er) names +# when creating helpers common to those for the individual +# instruction patterns. + +&rtype rs rt rd sa + +########################################################################### +# Named instruction formats. These are generally used to +# reduce the amount of duplication between instruction patterns. + +@rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0 + +########################################################################### + +MFHI1 011100 0000000000 ..... 00000 010000 @rd +MFLO1 011100 0000000000 ..... 00000 010010 @rd diff --git a/target/mips/translate.c b/target/mips/translate.c index a2994eb0aa6..de67e534121 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1973,9 +1973,7 @@ enum { MMI_OPC_PLZCW = 0x04 | MMI_OPC_CLASS_MMI, MMI_OPC_CLASS_MMI0 = 0x08 | MMI_OPC_CLASS_MMI, MMI_OPC_CLASS_MMI2 = 0x09 | MMI_OPC_CLASS_MMI, - MMI_OPC_MFHI1 = 0x10 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MFHI */ MMI_OPC_MTHI1 = 0x11 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MTHI */ - MMI_OPC_MFLO1 = 0x12 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MFLO */ MMI_OPC_MTLO1 = 0x13 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MTLO */ MMI_OPC_MULT1 = 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MULT */ MMI_OPC_MULTU1 = 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_MULTU */ @@ -4127,12 +4125,6 @@ static void gen_shift(DisasContext *ctx, uint32_t opc, static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg) { switch (opc) { - case MMI_OPC_MFHI1: - gen_store_gpr(cpu_HI[1], reg); - break; - case MMI_OPC_MFLO1: - gen_store_gpr(cpu_LO[1], reg); - break; case MMI_OPC_MTHI1: gen_load_gpr(cpu_HI[1], reg); break; @@ -28027,10 +28019,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx) case MMI_OPC_MTHI1: gen_HILO1_tx79(ctx, opc, rs); break; - case MMI_OPC_MFLO1: - case MMI_OPC_MFHI1: - gen_HILO1_tx79(ctx, opc, rd); - break; case MMI_OPC_PLZCW: /* TODO: MMI_OPC_PLZCW */ case MMI_OPC_PMFHL: /* TODO: MMI_OPC_PMFHL */ case MMI_OPC_PMTHL: /* TODO: MMI_OPC_PMTHL */ @@ -28997,6 +28985,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->opcode)) { return; } + if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opcode)) { + return; + } if (decode_opc_legacy(env, ctx)) { return; diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c new file mode 100644 index 00000000000..22bd6033e55 --- /dev/null +++ b/target/mips/tx79_translate.c @@ -0,0 +1,37 @@ +/* + * Toshiba TX79-specific instructions translation routines + * + * Copyright (c) 2018 Fredrik Noring + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "exec/helper-gen.h" +#include "translate.h" + +/* Include the auto-generated decoder. */ +#include "decode-tx79.c.inc" + +bool decode_ext_tx79(DisasContext *ctx, uint32_t insn) +{ + if (TARGET_LONG_BITS == 64 && decode_tx79(ctx, insn)) { + return true; + } + return false; +} + +static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a) +{ + gen_store_gpr(cpu_HI[1], a->rd); + + return true; +} + +static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a) +{ + gen_store_gpr(cpu_LO[1], a->rd); + + return true; +} diff --git a/target/mips/txx9_translate.c b/target/mips/txx9_translate.c new file mode 100644 index 00000000000..8a2c0b766bd --- /dev/null +++ b/target/mips/txx9_translate.c @@ -0,0 +1,20 @@ +/* + * Toshiba TXx9 instructions translation routines + * + * Copyright (c) 2021 Philippe Mathieu-Daudé + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "translate.h" + +bool decode_ext_txx9(DisasContext *ctx, uint32_t insn) +{ +#if defined(TARGET_MIPS64) + if (decode_ext_tx79(ctx, insn)) { + return true; + } +#endif + return false; +} diff --git a/target/mips/meson.build b/target/mips/meson.build index 9741545440c..8836978e24a 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -3,6 +3,7 @@ decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'), decodetree.process('msa32.decode', extra_args: '--static-decode=decode_msa32'), decodetree.process('msa64.decode', extra_args: '--static-decode=decode_msa64'), + decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), ] mips_ss = ss.source_set() @@ -22,6 +23,10 @@ 'tlb_helper.c', 'translate.c', 'translate_addr_const.c', + 'txx9_translate.c', +)) +mips_ss.add(when: ['CONFIG_TCG', 'TARGET_MIPS64'], if_true: files( + 'tx79_translate.c', )) mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) From patchwork Sun Feb 14 17:58:39 2021 Content-Type: text/plain; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id i10sm26058908wrp.0.2021.02.14.09.59.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 09:59:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 09/42] target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree Date: Sun, 14 Feb 2021 18:58:39 +0100 Message-Id: <20210214175912.732946-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tx79.decode | 3 +++ target/mips/translate.c | 25 ------------------------- target/mips/tx79_translate.c | 14 ++++++++++++++ 3 files changed, 17 insertions(+), 25 deletions(-) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 2e287ebbf36..30737da54e4 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -17,9 +17,12 @@ # Named instruction formats. These are generally used to # reduce the amount of duplication between instruction patterns. +@rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0 @rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0 ########################################################################### MFHI1 011100 0000000000 ..... 00000 010000 @rd +MTHI1 011100 ..... 0000000000 00000 010001 @rs MFLO1 011100 0000000000 ..... 00000 010010 @rd +MTLO1 011100 ..... 0000000000 00000 010011 @rs diff --git a/target/mips/translate.c b/target/mips/translate.c index de67e534121..7bd951d3a06 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1973,8 +1973,6 @@ enum { MMI_OPC_PLZCW = 0x04 | MMI_OPC_CLASS_MMI, MMI_OPC_CLASS_MMI0 = 0x08 | MMI_OPC_CLASS_MMI, MMI_OPC_CLASS_MMI2 = 0x09 | MMI_OPC_CLASS_MMI, - MMI_OPC_MTHI1 = 0x11 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MTHI */ - MMI_OPC_MTLO1 = 0x13 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MTLO */ MMI_OPC_MULT1 = 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MULT */ MMI_OPC_MULTU1 = 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_MULTU */ MMI_OPC_DIV1 = 0x1A | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIV */ @@ -4120,25 +4118,6 @@ static void gen_shift(DisasContext *ctx, uint32_t opc, tcg_temp_free(t1); } -#if defined(TARGET_MIPS64) -/* Copy GPR to and from TX79 HI1/LO1 register. */ -static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg) -{ - switch (opc) { - case MMI_OPC_MTHI1: - gen_load_gpr(cpu_HI[1], reg); - break; - case MMI_OPC_MTLO1: - gen_load_gpr(cpu_LO[1], reg); - break; - default: - MIPS_INVAL("mfthilo1 TX79"); - gen_reserved_instruction(ctx); - break; - } -} -#endif - /* Arithmetic on HI/LO registers */ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) { @@ -28015,10 +27994,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx) case MMI_OPC_DIVU1: gen_div1_tx79(ctx, opc, rs, rt); break; - case MMI_OPC_MTLO1: - case MMI_OPC_MTHI1: - gen_HILO1_tx79(ctx, opc, rs); - break; case MMI_OPC_PLZCW: /* TODO: MMI_OPC_PLZCW */ case MMI_OPC_PMFHL: /* TODO: MMI_OPC_PMFHL */ case MMI_OPC_PMTHL: /* TODO: MMI_OPC_PMTHL */ diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 22bd6033e55..905245cece7 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -35,3 +35,17 @@ static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a) return true; } + +static bool trans_MTHI1(DisasContext *ctx, arg_rtype *a) +{ + gen_load_gpr(cpu_HI[1], a->rs); + + return true; +} + +static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) +{ + gen_load_gpr(cpu_LO[1], a->rs); + + return true; +} From patchwork Sun Feb 14 17:58:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B43E7C433E0 for ; Sun, 14 Feb 2021 18:10:00 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 560A464E29 for ; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id a84sm22132594wme.12.2021.02.14.10.00.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:00:04 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 10/42] target/mips/translate: Simplify PCPYH using deposit_i64() Date: Sun, 14 Feb 2021 18:58:40 +0100 Message-Id: <20210214175912.732946-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Simplify the PCPYH (Parallel Copy Halfword) instruction by using multiple calls to deposit_i64() which can be optimized by some TCG backends. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- v3: Use missing rt, optimize (Richard) --- target/mips/translate.c | 34 ++++------------------------------ 1 file changed, 4 insertions(+), 30 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 7bd951d3a06..a13ad4959b4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24762,36 +24762,10 @@ static void gen_mmi_pcpyh(DisasContext *ctx) tcg_gen_movi_i64(cpu_gpr[rd], 0); tcg_gen_movi_i64(cpu_gpr_hi[rd], 0); } else { - TCGv_i64 t0 = tcg_temp_new(); - TCGv_i64 t1 = tcg_temp_new(); - uint64_t mask = (1ULL << 16) - 1; - - tcg_gen_andi_i64(t0, cpu_gpr[rt], mask); - tcg_gen_movi_i64(t1, 0); - tcg_gen_or_i64(t1, t0, t1); - tcg_gen_shli_i64(t0, t0, 16); - tcg_gen_or_i64(t1, t0, t1); - tcg_gen_shli_i64(t0, t0, 16); - tcg_gen_or_i64(t1, t0, t1); - tcg_gen_shli_i64(t0, t0, 16); - tcg_gen_or_i64(t1, t0, t1); - - tcg_gen_mov_i64(cpu_gpr[rd], t1); - - tcg_gen_andi_i64(t0, cpu_gpr_hi[rt], mask); - tcg_gen_movi_i64(t1, 0); - tcg_gen_or_i64(t1, t0, t1); - tcg_gen_shli_i64(t0, t0, 16); - tcg_gen_or_i64(t1, t0, t1); - tcg_gen_shli_i64(t0, t0, 16); - tcg_gen_or_i64(t1, t0, t1); - tcg_gen_shli_i64(t0, t0, 16); - tcg_gen_or_i64(t1, t0, t1); - - tcg_gen_mov_i64(cpu_gpr_hi[rd], t1); - - tcg_temp_free(t0); - tcg_temp_free(t1); + tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rt], cpu_gpr[rt], 16, 16); + tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rd], cpu_gpr[rd], 32, 32); + tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt], cpu_gpr_hi[rt], 16, 16); + tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rd], cpu_gpr_hi[rd], 32, 32); } } From patchwork Sun Feb 14 17:58:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087331 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5A9CC433E0 for ; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id v204sm22373706wmg.38.2021.02.14.10.00.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:00:09 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 11/42] target/mips/tx79: Move PCPYH opcode to decodetree Date: Sun, 14 Feb 2021 18:58:41 +0100 Message-Id: <20210214175912.732946-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Move the existing PCPYH opcode (Parallel Copy Halfword) to decodetree. Remove unnecessary code / comments. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tx79.decode | 5 +++++ target/mips/translate.c | 39 ------------------------------------ target/mips/tx79_translate.c | 22 ++++++++++++++++++++ 3 files changed, 27 insertions(+), 39 deletions(-) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 30737da54e4..7af35458b0a 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -17,6 +17,7 @@ # Named instruction formats. These are generally used to # reduce the amount of duplication between instruction patterns. +@rt_rd ...... ..... rt:5 rd:5 ..... ...... &rtype rs=0 sa=0 @rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0 @rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0 @@ -26,3 +27,7 @@ MFHI1 011100 0000000000 ..... 00000 010000 @rd MTHI1 011100 ..... 0000000000 00000 010001 @rs MFLO1 011100 0000000000 ..... 00000 010010 @rd MTLO1 011100 ..... 0000000000 00000 010011 @rs + +# MMI3 + +PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd diff --git a/target/mips/translate.c b/target/mips/translate.c index a13ad4959b4..b81a66ed373 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24733,42 +24733,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) * PEXTUW */ -/* - * PCPYH rd, rt - * - * Parallel Copy Halfword - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---------+---------+-----------+ - * | MMI |0 0 0 0 0| rt | rd | PCPYH | MMI3 | - * +-----------+---------+---------+---------+---------+-----------+ - */ -static void gen_mmi_pcpyh(DisasContext *ctx) -{ - uint32_t pd, rt, rd; - uint32_t opcode; - - opcode = ctx->opcode; - - pd = extract32(opcode, 21, 5); - rt = extract32(opcode, 16, 5); - rd = extract32(opcode, 11, 5); - - if (unlikely(pd != 0)) { - gen_reserved_instruction(ctx); - } else if (rd == 0) { - /* nop */ - } else if (rt == 0) { - tcg_gen_movi_i64(cpu_gpr[rd], 0); - tcg_gen_movi_i64(cpu_gpr_hi[rd], 0); - } else { - tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rt], cpu_gpr[rt], 16, 16); - tcg_gen_deposit_i64(cpu_gpr[rd], cpu_gpr[rd], cpu_gpr[rd], 32, 32); - tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt], cpu_gpr_hi[rt], 16, 16); - tcg_gen_deposit_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rd], cpu_gpr_hi[rd], 32, 32); - } -} - /* * PCPYLD rd, rs, rt * @@ -27923,9 +27887,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx) case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */ break; - case MMI_OPC_3_PCPYH: - gen_mmi_pcpyh(ctx); - break; case MMI_OPC_3_PCPYUD: gen_mmi_pcpyud(ctx); break; diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 905245cece7..d58b4fcd7b3 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -49,3 +49,25 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) return true; } + +/* Parallel Copy Halfword */ +static bool trans_PCPYH(DisasContext *s, arg_rtype *a) +{ + if (a->rd == 0) { + /* nop */ + return true; + } + + if (a->rt == 0) { + tcg_gen_movi_i64(cpu_gpr[a->rd], 0); + tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); + return true; + } + + tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], cpu_gpr[a->rt], 16, 16); + tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], cpu_gpr[a->rd], 32, 32); + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt], cpu_gpr_hi[a->rt], 16, 16); + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], 32, 32); + + return true; +} From patchwork Sun Feb 14 17:58:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B71C2C433E6 for ; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id r124sm22213789wmr.16.2021.02.14.10.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:00:14 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 12/42] target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree Date: Sun, 14 Feb 2021 18:58:42 +0100 Message-Id: <20210214175912.732946-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Move PCPYLD (Parallel Copy Lower Doubleword) and PCPYUD (Parallel Copy Upper Doubleword) to decodetree. Remove unnecessary code / comments. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tx79.decode | 6 +++ target/mips/translate.c | 84 ------------------------------------ target/mips/tx79_translate.c | 46 ++++++++++++++++++++ 3 files changed, 52 insertions(+), 84 deletions(-) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 7af35458b0a..0f748b53a64 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -17,6 +17,7 @@ # Named instruction formats. These are generally used to # reduce the amount of duplication between instruction patterns. +@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &rtype sa=0 @rt_rd ...... ..... rt:5 rd:5 ..... ...... &rtype rs=0 sa=0 @rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0 @rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0 @@ -28,6 +29,11 @@ MTHI1 011100 ..... 0000000000 00000 010001 @rs MFLO1 011100 0000000000 ..... 00000 010010 @rd MTLO1 011100 ..... 0000000000 00000 010011 @rs +# MMI2 + +PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd + # MMI3 +PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd diff --git a/target/mips/translate.c b/target/mips/translate.c index b81a66ed373..cf5a6a83ae5 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -24733,84 +24733,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) * PEXTUW */ -/* - * PCPYLD rd, rs, rt - * - * Parallel Copy Lower Doubleword - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---------+---------+-----------+ - * | MMI | rs | rt | rd | PCPYLD | MMI2 | - * +-----------+---------+---------+---------+---------+-----------+ - */ -static void gen_mmi_pcpyld(DisasContext *ctx) -{ - uint32_t rs, rt, rd; - uint32_t opcode; - - opcode = ctx->opcode; - - rs = extract32(opcode, 21, 5); - rt = extract32(opcode, 16, 5); - rd = extract32(opcode, 11, 5); - - if (rd == 0) { - /* nop */ - } else { - if (rs == 0) { - tcg_gen_movi_i64(cpu_gpr_hi[rd], 0); - } else { - tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr[rs]); - } - if (rt == 0) { - tcg_gen_movi_i64(cpu_gpr[rd], 0); - } else { - if (rd != rt) { - tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr[rt]); - } - } - } -} - -/* - * PCPYUD rd, rs, rt - * - * Parallel Copy Upper Doubleword - * - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+---------+---------+---------+-----------+ - * | MMI | rs | rt | rd | PCPYUD | MMI3 | - * +-----------+---------+---------+---------+---------+-----------+ - */ -static void gen_mmi_pcpyud(DisasContext *ctx) -{ - uint32_t rs, rt, rd; - uint32_t opcode; - - opcode = ctx->opcode; - - rs = extract32(opcode, 21, 5); - rt = extract32(opcode, 16, 5); - rd = extract32(opcode, 11, 5); - - if (rd == 0) { - /* nop */ - } else { - if (rs == 0) { - tcg_gen_movi_i64(cpu_gpr[rd], 0); - } else { - tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr_hi[rs]); - } - if (rt == 0) { - tcg_gen_movi_i64(cpu_gpr_hi[rd], 0); - } else { - if (rd != rt) { - tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt]); - } - } - } -} - #endif @@ -27859,9 +27781,6 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx) case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI2 */ break; - case MMI_OPC_2_PCPYLD: - gen_mmi_pcpyld(ctx); - break; default: MIPS_INVAL("TX79 MMI class MMI2"); gen_reserved_instruction(ctx); @@ -27887,9 +27806,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx) case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */ break; - case MMI_OPC_3_PCPYUD: - gen_mmi_pcpyud(ctx); - break; default: MIPS_INVAL("TX79 MMI class MMI3"); gen_reserved_instruction(ctx); diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index d58b4fcd7b3..de09bb0d314 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -71,3 +71,49 @@ static bool trans_PCPYH(DisasContext *s, arg_rtype *a) return true; } + +/* Parallel Copy Lower Doubleword */ +static bool trans_PCPYLD(DisasContext *s, arg_rtype *a) +{ + if (a->rd == 0) { + /* nop */ + return true; + } + + if (a->rs == 0) { + tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); + } else { + tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr[a->rs]); + } + + if (a->rt == 0) { + tcg_gen_movi_i64(cpu_gpr[a->rd], 0); + } else if (a->rd != a->rt) { + tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]); + } + + return true; +} + +/* Parallel Copy Upper Doubleword */ +static bool trans_PCPYUD(DisasContext *s, arg_rtype *a) +{ + if (a->rd == 0) { + /* nop */ + return true; + } + + if (a->rs == 0) { + tcg_gen_movi_i64(cpu_gpr[a->rd], 0); + } else { + tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr_hi[a->rs]); + } + + if (a->rt == 0) { + tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); + } else if (a->rd != a->rt) { + tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt]); + } + + return true; +} From patchwork Sun Feb 14 17:58:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087349 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBF0DC433E9 for ; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id o13sm27879362wrs.45.2021.02.14.10.00.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:00:19 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 13/42] target/mips: Remove 'C790 Multimedia Instructions' dead code Date: Sun, 14 Feb 2021 18:58:43 +0100 Message-Id: <20210214175912.732946-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We have almost 400 lines of code full of /* TODO */ comments which end calling gen_reserved_instruction(). As we are not going to implement them, and all the caller's switch() default cases already call gen_reserved_instruction(), we can remove this altogether. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/translate.c | 372 ---------------------------------------- 1 file changed, 372 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index cf5a6a83ae5..22d106405c6 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1970,207 +1970,12 @@ enum { enum { MMI_OPC_MADD = 0x00 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADD */ MMI_OPC_MADDU = 0x01 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADDU */ - MMI_OPC_PLZCW = 0x04 | MMI_OPC_CLASS_MMI, - MMI_OPC_CLASS_MMI0 = 0x08 | MMI_OPC_CLASS_MMI, - MMI_OPC_CLASS_MMI2 = 0x09 | MMI_OPC_CLASS_MMI, MMI_OPC_MULT1 = 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_MULT */ MMI_OPC_MULTU1 = 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_MULTU */ MMI_OPC_DIV1 = 0x1A | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIV */ MMI_OPC_DIVU1 = 0x1B | MMI_OPC_CLASS_MMI, /* Same minor as OPC_DIVU */ MMI_OPC_MADD1 = 0x20 | MMI_OPC_CLASS_MMI, MMI_OPC_MADDU1 = 0x21 | MMI_OPC_CLASS_MMI, - MMI_OPC_CLASS_MMI1 = 0x28 | MMI_OPC_CLASS_MMI, - MMI_OPC_CLASS_MMI3 = 0x29 | MMI_OPC_CLASS_MMI, - MMI_OPC_PMFHL = 0x30 | MMI_OPC_CLASS_MMI, - MMI_OPC_PMTHL = 0x31 | MMI_OPC_CLASS_MMI, - MMI_OPC_PSLLH = 0x34 | MMI_OPC_CLASS_MMI, - MMI_OPC_PSRLH = 0x36 | MMI_OPC_CLASS_MMI, - MMI_OPC_PSRAH = 0x37 | MMI_OPC_CLASS_MMI, - MMI_OPC_PSLLW = 0x3C | MMI_OPC_CLASS_MMI, - MMI_OPC_PSRLW = 0x3E | MMI_OPC_CLASS_MMI, - MMI_OPC_PSRAW = 0x3F | MMI_OPC_CLASS_MMI, -}; - -/* - * MMI instructions with opcode field = MMI and bits 5..0 = MMI0: - * - * 31 26 10 6 5 0 - * +--------+----------------------+--------+--------+ - * | MMI | |function| MMI0 | - * +--------+----------------------+--------+--------+ - * - * function bits 7..6 - * bits | 0 | 1 | 2 | 3 - * 10..8 | 00 | 01 | 10 | 11 - * -------+-------+-------+-------+------- - * 0 000 | PADDW | PSUBW | PCGTW | PMAXW - * 1 001 | PADDH | PSUBH | PCGTH | PMAXH - * 2 010 | PADDB | PSUBB | PCGTB | * - * 3 011 | * | * | * | * - * 4 100 | PADDSW| PSUBSW| PEXTLW| PPACW - * 5 101 | PADDSH| PSUBSH| PEXTLH| PPACH - * 6 110 | PADDSB| PSUBSB| PEXTLB| PPACB - * 7 111 | * | * | PEXT5 | PPAC5 - */ - -#define MASK_MMI0(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF)) -enum { - MMI_OPC_0_PADDW = (0x00 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PSUBW = (0x01 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PCGTW = (0x02 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PMAXW = (0x03 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PADDH = (0x04 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PSUBH = (0x05 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PCGTH = (0x06 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PMAXH = (0x07 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PADDB = (0x08 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PSUBB = (0x09 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PCGTB = (0x0A << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PADDSW = (0x10 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PSUBSW = (0x11 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PEXTLW = (0x12 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PPACW = (0x13 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PADDSH = (0x14 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PSUBSH = (0x15 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PEXTLH = (0x16 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PPACH = (0x17 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PADDSB = (0x18 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PSUBSB = (0x19 << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PEXTLB = (0x1A << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PPACB = (0x1B << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PEXT5 = (0x1E << 6) | MMI_OPC_CLASS_MMI0, - MMI_OPC_0_PPAC5 = (0x1F << 6) | MMI_OPC_CLASS_MMI0, -}; - -/* - * MMI instructions with opcode field = MMI and bits 5..0 = MMI1: - * - * 31 26 10 6 5 0 - * +--------+----------------------+--------+--------+ - * | MMI | |function| MMI1 | - * +--------+----------------------+--------+--------+ - * - * function bits 7..6 - * bits | 0 | 1 | 2 | 3 - * 10..8 | 00 | 01 | 10 | 11 - * -------+-------+-------+-------+------- - * 0 000 | * | PABSW | PCEQW | PMINW - * 1 001 | PADSBH| PABSH | PCEQH | PMINH - * 2 010 | * | * | PCEQB | * - * 3 011 | * | * | * | * - * 4 100 | PADDUW| PSUBUW| PEXTUW| * - * 5 101 | PADDUH| PSUBUH| PEXTUH| * - * 6 110 | PADDUB| PSUBUB| PEXTUB| QFSRV - * 7 111 | * | * | * | * - */ - -#define MASK_MMI1(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF)) -enum { - MMI_OPC_1_PABSW = (0x01 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PCEQW = (0x02 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PMINW = (0x03 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PADSBH = (0x04 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PABSH = (0x05 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PCEQH = (0x06 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PMINH = (0x07 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PCEQB = (0x0A << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PADDUW = (0x10 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PSUBUW = (0x11 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PEXTUW = (0x12 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PADDUH = (0x14 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PSUBUH = (0x15 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PEXTUH = (0x16 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PADDUB = (0x18 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PSUBUB = (0x19 << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_PEXTUB = (0x1A << 6) | MMI_OPC_CLASS_MMI1, - MMI_OPC_1_QFSRV = (0x1B << 6) | MMI_OPC_CLASS_MMI1, -}; - -/* - * MMI instructions with opcode field = MMI and bits 5..0 = MMI2: - * - * 31 26 10 6 5 0 - * +--------+----------------------+--------+--------+ - * | MMI | |function| MMI2 | - * +--------+----------------------+--------+--------+ - * - * function bits 7..6 - * bits | 0 | 1 | 2 | 3 - * 10..8 | 00 | 01 | 10 | 11 - * -------+-------+-------+-------+------- - * 0 000 | PMADDW| * | PSLLVW| PSRLVW - * 1 001 | PMSUBW| * | * | * - * 2 010 | PMFHI | PMFLO | PINTH | * - * 3 011 | PMULTW| PDIVW | PCPYLD| * - * 4 100 | PMADDH| PHMADH| PAND | PXOR - * 5 101 | PMSUBH| PHMSBH| * | * - * 6 110 | * | * | PEXEH | PREVH - * 7 111 | PMULTH| PDIVBW| PEXEW | PROT3W - */ - -#define MASK_MMI2(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF)) -enum { - MMI_OPC_2_PMADDW = (0x00 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PSLLVW = (0x02 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PSRLVW = (0x03 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PMSUBW = (0x04 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PMFHI = (0x08 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PMFLO = (0x09 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PINTH = (0x0A << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PMULTW = (0x0C << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PDIVW = (0x0D << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PCPYLD = (0x0E << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PMADDH = (0x10 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PHMADH = (0x11 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PAND = (0x12 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PXOR = (0x13 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PMSUBH = (0x14 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PHMSBH = (0x15 << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PEXEH = (0x1A << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PREVH = (0x1B << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PMULTH = (0x1C << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PDIVBW = (0x1D << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PEXEW = (0x1E << 6) | MMI_OPC_CLASS_MMI2, - MMI_OPC_2_PROT3W = (0x1F << 6) | MMI_OPC_CLASS_MMI2, -}; - -/* - * MMI instructions with opcode field = MMI and bits 5..0 = MMI3: - * - * 31 26 10 6 5 0 - * +--------+----------------------+--------+--------+ - * | MMI | |function| MMI3 | - * +--------+----------------------+--------+--------+ - * - * function bits 7..6 - * bits | 0 | 1 | 2 | 3 - * 10..8 | 00 | 01 | 10 | 11 - * -------+-------+-------+-------+------- - * 0 000 |PMADDUW| * | * | PSRAVW - * 1 001 | * | * | * | * - * 2 010 | PMTHI | PMTLO | PINTEH| * - * 3 011 |PMULTUW| PDIVUW| PCPYUD| * - * 4 100 | * | * | POR | PNOR - * 5 101 | * | * | * | * - * 6 110 | * | * | PEXCH | PCPYH - * 7 111 | * | * | PEXCW | * - */ - -#define MASK_MMI3(op) (MASK_OP_MAJOR(op) | ((op) & 0x7FF)) -enum { - MMI_OPC_3_PMADDUW = (0x00 << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PSRAVW = (0x03 << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PMTHI = (0x08 << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PMTLO = (0x09 << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PINTEH = (0x0A << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PMULTUW = (0x0C << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PDIVUW = (0x0D << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PCPYUD = (0x0E << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_POR = (0x12 << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PNOR = (0x13 << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PEXCH = (0x1A << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PCPYH = (0x1B << 6) | MMI_OPC_CLASS_MMI3, - MMI_OPC_3_PEXCW = (0x1E << 6) | MMI_OPC_CLASS_MMI3, }; /* global register indices */ @@ -24713,29 +24518,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) } -#if defined(TARGET_MIPS64) - -/* - * - * MMI (MultiMedia Interface) ASE instructions - * =========================================== - */ - -/* - * MMI instructions category: data communication - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - * - * PCPYH PEXCH PEXTLB PINTH PPACB PEXT5 PREVH - * PCPYLD PEXCW PEXTLH PINTEH PPACH PPAC5 PROT3W - * PCPYUD PEXEH PEXTLW PPACW - * PEXEW PEXTUB - * PEXTUH - * PEXTUW - */ - -#endif - - #if !defined(TARGET_MIPS64) /* MXU accumulate add/subtract 1-bit pattern 'aptn1' */ @@ -27682,137 +27464,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) #if defined(TARGET_MIPS64) -static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opc = MASK_MMI0(ctx->opcode); - - switch (opc) { - case MMI_OPC_0_PADDW: /* TODO: MMI_OPC_0_PADDW */ - case MMI_OPC_0_PSUBW: /* TODO: MMI_OPC_0_PSUBW */ - case MMI_OPC_0_PCGTW: /* TODO: MMI_OPC_0_PCGTW */ - case MMI_OPC_0_PMAXW: /* TODO: MMI_OPC_0_PMAXW */ - case MMI_OPC_0_PADDH: /* TODO: MMI_OPC_0_PADDH */ - case MMI_OPC_0_PSUBH: /* TODO: MMI_OPC_0_PSUBH */ - case MMI_OPC_0_PCGTH: /* TODO: MMI_OPC_0_PCGTH */ - case MMI_OPC_0_PMAXH: /* TODO: MMI_OPC_0_PMAXH */ - case MMI_OPC_0_PADDB: /* TODO: MMI_OPC_0_PADDB */ - case MMI_OPC_0_PSUBB: /* TODO: MMI_OPC_0_PSUBB */ - case MMI_OPC_0_PCGTB: /* TODO: MMI_OPC_0_PCGTB */ - case MMI_OPC_0_PADDSW: /* TODO: MMI_OPC_0_PADDSW */ - case MMI_OPC_0_PSUBSW: /* TODO: MMI_OPC_0_PSUBSW */ - case MMI_OPC_0_PEXTLW: /* TODO: MMI_OPC_0_PEXTLW */ - case MMI_OPC_0_PPACW: /* TODO: MMI_OPC_0_PPACW */ - case MMI_OPC_0_PADDSH: /* TODO: MMI_OPC_0_PADDSH */ - case MMI_OPC_0_PSUBSH: /* TODO: MMI_OPC_0_PSUBSH */ - case MMI_OPC_0_PEXTLH: /* TODO: MMI_OPC_0_PEXTLH */ - case MMI_OPC_0_PPACH: /* TODO: MMI_OPC_0_PPACH */ - case MMI_OPC_0_PADDSB: /* TODO: MMI_OPC_0_PADDSB */ - case MMI_OPC_0_PSUBSB: /* TODO: MMI_OPC_0_PSUBSB */ - case MMI_OPC_0_PEXTLB: /* TODO: MMI_OPC_0_PEXTLB */ - case MMI_OPC_0_PPACB: /* TODO: MMI_OPC_0_PPACB */ - case MMI_OPC_0_PEXT5: /* TODO: MMI_OPC_0_PEXT5 */ - case MMI_OPC_0_PPAC5: /* TODO: MMI_OPC_0_PPAC5 */ - gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI0 */ - break; - default: - MIPS_INVAL("TX79 MMI class MMI0"); - gen_reserved_instruction(ctx); - break; - } -} - -static void decode_mmi1(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opc = MASK_MMI1(ctx->opcode); - - switch (opc) { - case MMI_OPC_1_PABSW: /* TODO: MMI_OPC_1_PABSW */ - case MMI_OPC_1_PCEQW: /* TODO: MMI_OPC_1_PCEQW */ - case MMI_OPC_1_PMINW: /* TODO: MMI_OPC_1_PMINW */ - case MMI_OPC_1_PADSBH: /* TODO: MMI_OPC_1_PADSBH */ - case MMI_OPC_1_PABSH: /* TODO: MMI_OPC_1_PABSH */ - case MMI_OPC_1_PCEQH: /* TODO: MMI_OPC_1_PCEQH */ - case MMI_OPC_1_PMINH: /* TODO: MMI_OPC_1_PMINH */ - case MMI_OPC_1_PCEQB: /* TODO: MMI_OPC_1_PCEQB */ - case MMI_OPC_1_PADDUW: /* TODO: MMI_OPC_1_PADDUW */ - case MMI_OPC_1_PSUBUW: /* TODO: MMI_OPC_1_PSUBUW */ - case MMI_OPC_1_PEXTUW: /* TODO: MMI_OPC_1_PEXTUW */ - case MMI_OPC_1_PADDUH: /* TODO: MMI_OPC_1_PADDUH */ - case MMI_OPC_1_PSUBUH: /* TODO: MMI_OPC_1_PSUBUH */ - case MMI_OPC_1_PEXTUH: /* TODO: MMI_OPC_1_PEXTUH */ - case MMI_OPC_1_PADDUB: /* TODO: MMI_OPC_1_PADDUB */ - case MMI_OPC_1_PSUBUB: /* TODO: MMI_OPC_1_PSUBUB */ - case MMI_OPC_1_PEXTUB: /* TODO: MMI_OPC_1_PEXTUB */ - case MMI_OPC_1_QFSRV: /* TODO: MMI_OPC_1_QFSRV */ - gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI1 */ - break; - default: - MIPS_INVAL("TX79 MMI class MMI1"); - gen_reserved_instruction(ctx); - break; - } -} - -static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opc = MASK_MMI2(ctx->opcode); - - switch (opc) { - case MMI_OPC_2_PMADDW: /* TODO: MMI_OPC_2_PMADDW */ - case MMI_OPC_2_PSLLVW: /* TODO: MMI_OPC_2_PSLLVW */ - case MMI_OPC_2_PSRLVW: /* TODO: MMI_OPC_2_PSRLVW */ - case MMI_OPC_2_PMSUBW: /* TODO: MMI_OPC_2_PMSUBW */ - case MMI_OPC_2_PMFHI: /* TODO: MMI_OPC_2_PMFHI */ - case MMI_OPC_2_PMFLO: /* TODO: MMI_OPC_2_PMFLO */ - case MMI_OPC_2_PINTH: /* TODO: MMI_OPC_2_PINTH */ - case MMI_OPC_2_PMULTW: /* TODO: MMI_OPC_2_PMULTW */ - case MMI_OPC_2_PDIVW: /* TODO: MMI_OPC_2_PDIVW */ - case MMI_OPC_2_PMADDH: /* TODO: MMI_OPC_2_PMADDH */ - case MMI_OPC_2_PHMADH: /* TODO: MMI_OPC_2_PHMADH */ - case MMI_OPC_2_PAND: /* TODO: MMI_OPC_2_PAND */ - case MMI_OPC_2_PXOR: /* TODO: MMI_OPC_2_PXOR */ - case MMI_OPC_2_PMSUBH: /* TODO: MMI_OPC_2_PMSUBH */ - case MMI_OPC_2_PHMSBH: /* TODO: MMI_OPC_2_PHMSBH */ - case MMI_OPC_2_PEXEH: /* TODO: MMI_OPC_2_PEXEH */ - case MMI_OPC_2_PREVH: /* TODO: MMI_OPC_2_PREVH */ - case MMI_OPC_2_PMULTH: /* TODO: MMI_OPC_2_PMULTH */ - case MMI_OPC_2_PDIVBW: /* TODO: MMI_OPC_2_PDIVBW */ - case MMI_OPC_2_PEXEW: /* TODO: MMI_OPC_2_PEXEW */ - case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */ - gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI2 */ - break; - default: - MIPS_INVAL("TX79 MMI class MMI2"); - gen_reserved_instruction(ctx); - break; - } -} - -static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx) -{ - uint32_t opc = MASK_MMI3(ctx->opcode); - - switch (opc) { - case MMI_OPC_3_PMADDUW: /* TODO: MMI_OPC_3_PMADDUW */ - case MMI_OPC_3_PSRAVW: /* TODO: MMI_OPC_3_PSRAVW */ - case MMI_OPC_3_PMTHI: /* TODO: MMI_OPC_3_PMTHI */ - case MMI_OPC_3_PMTLO: /* TODO: MMI_OPC_3_PMTLO */ - case MMI_OPC_3_PINTEH: /* TODO: MMI_OPC_3_PINTEH */ - case MMI_OPC_3_PMULTUW: /* TODO: MMI_OPC_3_PMULTUW */ - case MMI_OPC_3_PDIVUW: /* TODO: MMI_OPC_3_PDIVUW */ - case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */ - case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */ - case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */ - case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */ - gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */ - break; - default: - MIPS_INVAL("TX79 MMI class MMI3"); - gen_reserved_instruction(ctx); - break; - } -} - static void decode_mmi(CPUMIPSState *env, DisasContext *ctx) { uint32_t opc = MASK_MMI(ctx->opcode); @@ -27821,18 +27472,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx) int rd = extract32(ctx->opcode, 11, 5); switch (opc) { - case MMI_OPC_CLASS_MMI0: - decode_mmi0(env, ctx); - break; - case MMI_OPC_CLASS_MMI1: - decode_mmi1(env, ctx); - break; - case MMI_OPC_CLASS_MMI2: - decode_mmi2(env, ctx); - break; - case MMI_OPC_CLASS_MMI3: - decode_mmi3(env, ctx); - break; case MMI_OPC_MULT1: case MMI_OPC_MULTU1: case MMI_OPC_MADD: @@ -27845,17 +27484,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx) case MMI_OPC_DIVU1: gen_div1_tx79(ctx, opc, rs, rt); break; - case MMI_OPC_PLZCW: /* TODO: MMI_OPC_PLZCW */ - case MMI_OPC_PMFHL: /* TODO: MMI_OPC_PMFHL */ - case MMI_OPC_PMTHL: /* TODO: MMI_OPC_PMTHL */ - case MMI_OPC_PSLLH: /* TODO: MMI_OPC_PSLLH */ - case MMI_OPC_PSRLH: /* TODO: MMI_OPC_PSRLH */ - case MMI_OPC_PSRAH: /* TODO: MMI_OPC_PSRAH */ - case MMI_OPC_PSLLW: /* TODO: MMI_OPC_PSLLW */ - case MMI_OPC_PSRLW: /* TODO: MMI_OPC_PSRLW */ - case MMI_OPC_PSRAW: /* TODO: MMI_OPC_PSRAW */ - gen_reserved_instruction(ctx); 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id f17sm19694283wrx.57.2021.02.14.10.00.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:00:24 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 14/42] target/mips/tx79: Salvage instructions description comment Date: Sun, 14 Feb 2021 18:58:44 +0100 Message-Id: <20210214175912.732946-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This comment describing the tx79 opcodes is helpful. As we will implement these instructions in tx79_translate.c, move the comment there. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/translate.c | 160 ----------------------------- target/mips/tx79_translate.c | 188 +++++++++++++++++++++++++++++++++++ 2 files changed, 188 insertions(+), 160 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 22d106405c6..109f7f80f3d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1743,166 +1743,6 @@ enum { }; /* - * Overview of the TX79-specific instruction set - * ============================================= - * - * The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits - * are only used by the specific quadword (128-bit) LQ/SQ load/store - * instructions and certain multimedia instructions (MMIs). These MMIs - * configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit - * or sixteen 8-bit paths. - * - * Reference: - * - * The Toshiba TX System RISC TX79 Core Architecture manual, - * https://wiki.qemu.org/File:C790.pdf - * - * Three-Operand Multiply and Multiply-Add (4 instructions) - * -------------------------------------------------------- - * MADD [rd,] rs, rt Multiply/Add - * MADDU [rd,] rs, rt Multiply/Add Unsigned - * MULT [rd,] rs, rt Multiply (3-operand) - * MULTU [rd,] rs, rt Multiply Unsigned (3-operand) - * - * Multiply Instructions for Pipeline 1 (10 instructions) - * ------------------------------------------------------ - * MULT1 [rd,] rs, rt Multiply Pipeline 1 - * MULTU1 [rd,] rs, rt Multiply Unsigned Pipeline 1 - * DIV1 rs, rt Divide Pipeline 1 - * DIVU1 rs, rt Divide Unsigned Pipeline 1 - * MADD1 [rd,] rs, rt Multiply-Add Pipeline 1 - * MADDU1 [rd,] rs, rt Multiply-Add Unsigned Pipeline 1 - * MFHI1 rd Move From HI1 Register - * MFLO1 rd Move From LO1 Register - * MTHI1 rs Move To HI1 Register - * MTLO1 rs Move To LO1 Register - * - * Arithmetic (19 instructions) - * ---------------------------- - * PADDB rd, rs, rt Parallel Add Byte - * PSUBB rd, rs, rt Parallel Subtract Byte - * PADDH rd, rs, rt Parallel Add Halfword - * PSUBH rd, rs, rt Parallel Subtract Halfword - * PADDW rd, rs, rt Parallel Add Word - * PSUBW rd, rs, rt Parallel Subtract Word - * PADSBH rd, rs, rt Parallel Add/Subtract Halfword - * PADDSB rd, rs, rt Parallel Add with Signed Saturation Byte - * PSUBSB rd, rs, rt Parallel Subtract with Signed Saturation Byte - * PADDSH rd, rs, rt Parallel Add with Signed Saturation Halfword - * PSUBSH rd, rs, rt Parallel Subtract with Signed Saturation Halfword - * PADDSW rd, rs, rt Parallel Add with Signed Saturation Word - * PSUBSW rd, rs, rt Parallel Subtract with Signed Saturation Word - * PADDUB rd, rs, rt Parallel Add with Unsigned saturation Byte - * PSUBUB rd, rs, rt Parallel Subtract with Unsigned saturation Byte - * PADDUH rd, rs, rt Parallel Add with Unsigned saturation Halfword - * PSUBUH rd, rs, rt Parallel Subtract with Unsigned saturation Halfword - * PADDUW rd, rs, rt Parallel Add with Unsigned saturation Word - * PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word - * - * Min/Max (4 instructions) - * ------------------------ - * PMAXH rd, rs, rt Parallel Maximum Halfword - * PMINH rd, rs, rt Parallel Minimum Halfword - * PMAXW rd, rs, rt Parallel Maximum Word - * PMINW rd, rs, rt Parallel Minimum Word - * - * Absolute (2 instructions) - * ------------------------- - * PABSH rd, rt Parallel Absolute Halfword - * PABSW rd, rt Parallel Absolute Word - * - * Logical (4 instructions) - * ------------------------ - * PAND rd, rs, rt Parallel AND - * POR rd, rs, rt Parallel OR - * PXOR rd, rs, rt Parallel XOR - * PNOR rd, rs, rt Parallel NOR - * - * Shift (9 instructions) - * ---------------------- - * PSLLH rd, rt, sa Parallel Shift Left Logical Halfword - * PSRLH rd, rt, sa Parallel Shift Right Logical Halfword - * PSRAH rd, rt, sa Parallel Shift Right Arithmetic Halfword - * PSLLW rd, rt, sa Parallel Shift Left Logical Word - * PSRLW rd, rt, sa Parallel Shift Right Logical Word - * PSRAW rd, rt, sa Parallel Shift Right Arithmetic Word - * PSLLVW rd, rt, rs Parallel Shift Left Logical Variable Word - * PSRLVW rd, rt, rs Parallel Shift Right Logical Variable Word - * PSRAVW rd, rt, rs Parallel Shift Right Arithmetic Variable Word - * - * Compare (6 instructions) - * ------------------------ - * PCGTB rd, rs, rt Parallel Compare for Greater Than Byte - * PCEQB rd, rs, rt Parallel Compare for Equal Byte - * PCGTH rd, rs, rt Parallel Compare for Greater Than Halfword - * PCEQH rd, rs, rt Parallel Compare for Equal Halfword - * PCGTW rd, rs, rt Parallel Compare for Greater Than Word - * PCEQW rd, rs, rt Parallel Compare for Equal Word - * - * LZC (1 instruction) - * ------------------- - * PLZCW rd, rs Parallel Leading Zero or One Count Word - * - * Quadword Load and Store (2 instructions) - * ---------------------------------------- - * LQ rt, offset(base) Load Quadword - * SQ rt, offset(base) Store Quadword - * - * Multiply and Divide (19 instructions) - * ------------------------------------- - * PMULTW rd, rs, rt Parallel Multiply Word - * PMULTUW rd, rs, rt Parallel Multiply Unsigned Word - * PDIVW rs, rt Parallel Divide Word - * PDIVUW rs, rt Parallel Divide Unsigned Word - * PMADDW rd, rs, rt Parallel Multiply-Add Word - * PMADDUW rd, rs, rt Parallel Multiply-Add Unsigned Word - * PMSUBW rd, rs, rt Parallel Multiply-Subtract Word - * PMULTH rd, rs, rt Parallel Multiply Halfword - * PMADDH rd, rs, rt Parallel Multiply-Add Halfword - * PMSUBH rd, rs, rt Parallel Multiply-Subtract Halfword - * PHMADH rd, rs, rt Parallel Horizontal Multiply-Add Halfword - * PHMSBH rd, rs, rt Parallel Horizontal Multiply-Subtract Halfword - * PDIVBW rs, rt Parallel Divide Broadcast Word - * PMFHI rd Parallel Move From HI Register - * PMFLO rd Parallel Move From LO Register - * PMTHI rs Parallel Move To HI Register - * PMTLO rs Parallel Move To LO Register - * PMFHL rd Parallel Move From HI/LO Register - * PMTHL rs Parallel Move To HI/LO Register - * - * Pack/Extend (11 instructions) - * ----------------------------- - * PPAC5 rd, rt Parallel Pack to 5 bits - * PPACB rd, rs, rt Parallel Pack to Byte - * PPACH rd, rs, rt Parallel Pack to Halfword - * PPACW rd, rs, rt Parallel Pack to Word - * PEXT5 rd, rt Parallel Extend Upper from 5 bits - * PEXTUB rd, rs, rt Parallel Extend Upper from Byte - * PEXTLB rd, rs, rt Parallel Extend Lower from Byte - * PEXTUH rd, rs, rt Parallel Extend Upper from Halfword - * PEXTLH rd, rs, rt Parallel Extend Lower from Halfword - * PEXTUW rd, rs, rt Parallel Extend Upper from Word - * PEXTLW rd, rs, rt Parallel Extend Lower from Word - * - * Others (16 instructions) - * ------------------------ - * PCPYH rd, rt Parallel Copy Halfword - * PCPYLD rd, rs, rt Parallel Copy Lower Doubleword - * PCPYUD rd, rs, rt Parallel Copy Upper Doubleword - * PREVH rd, rt Parallel Reverse Halfword - * PINTH rd, rs, rt Parallel Interleave Halfword - * PINTEH rd, rs, rt Parallel Interleave Even Halfword - * PEXEH rd, rt Parallel Exchange Even Halfword - * PEXCH rd, rt Parallel Exchange Center Halfword - * PEXEW rd, rt Parallel Exchange Even Word - * PEXCW rd, rt Parallel Exchange Center Word - * QFSRV rd, rs, rt Quadword Funnel Shift Right Variable - * MFSA rd Move from Shift Amount Register - * MTSA rs Move to Shift Amount Register - * MTSAB rs, immediate Move Byte Count to Shift Amount Register - * MTSAH rs, immediate Move Halfword Count to Shift Amount Register - * PROT3W rd, rt Parallel Rotate 3 Words - * * MMI (MultiMedia Instruction) encodings * ====================================== * diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index de09bb0d314..243a81c3c5e 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -14,6 +14,22 @@ /* Include the auto-generated decoder. */ #include "decode-tx79.c.inc" +/* + * Overview of the TX79-specific instruction set + * ============================================= + * + * The R5900 and the C790 have 128-bit wide GPRs, where the upper 64 bits + * are only used by the specific quadword (128-bit) LQ/SQ load/store + * instructions and certain multimedia instructions (MMIs). These MMIs + * configure the 128-bit data path as two 64-bit, four 32-bit, eight 16-bit + * or sixteen 8-bit paths. + * + * Reference: + * + * The Toshiba TX System RISC TX79 Core Architecture manual, + * https://wiki.qemu.org/File:C790.pdf + */ + bool decode_ext_tx79(DisasContext *ctx, uint32_t insn) { if (TARGET_LONG_BITS == 64 && decode_tx79(ctx, insn)) { @@ -22,6 +38,30 @@ bool decode_ext_tx79(DisasContext *ctx, uint32_t insn) return false; } +/* + * Three-Operand Multiply and Multiply-Add (4 instructions) + * -------------------------------------------------------- + * MADD [rd,] rs, rt Multiply/Add + * MADDU [rd,] rs, rt Multiply/Add Unsigned + * MULT [rd,] rs, rt Multiply (3-operand) + * MULTU [rd,] rs, rt Multiply Unsigned (3-operand) + */ + +/* + * Multiply Instructions for Pipeline 1 (10 instructions) + * ------------------------------------------------------ + * MULT1 [rd,] rs, rt Multiply Pipeline 1 + * MULTU1 [rd,] rs, rt Multiply Unsigned Pipeline 1 + * DIV1 rs, rt Divide Pipeline 1 + * DIVU1 rs, rt Divide Unsigned Pipeline 1 + * MADD1 [rd,] rs, rt Multiply-Add Pipeline 1 + * MADDU1 [rd,] rs, rt Multiply-Add Unsigned Pipeline 1 + * MFHI1 rd Move From HI1 Register + * MFLO1 rd Move From LO1 Register + * MTHI1 rs Move To HI1 Register + * MTLO1 rs Move To LO1 Register + */ + static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a) { gen_store_gpr(cpu_HI[1], a->rd); @@ -50,6 +90,154 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) return true; } +/* + * Arithmetic (19 instructions) + * ---------------------------- + * PADDB rd, rs, rt Parallel Add Byte + * PSUBB rd, rs, rt Parallel Subtract Byte + * PADDH rd, rs, rt Parallel Add Halfword + * PSUBH rd, rs, rt Parallel Subtract Halfword + * PADDW rd, rs, rt Parallel Add Word + * PSUBW rd, rs, rt Parallel Subtract Word + * PADSBH rd, rs, rt Parallel Add/Subtract Halfword + * PADDSB rd, rs, rt Parallel Add with Signed Saturation Byte + * PSUBSB rd, rs, rt Parallel Subtract with Signed Saturation Byte + * PADDSH rd, rs, rt Parallel Add with Signed Saturation Halfword + * PSUBSH rd, rs, rt Parallel Subtract with Signed Saturation Halfword + * PADDSW rd, rs, rt Parallel Add with Signed Saturation Word + * PSUBSW rd, rs, rt Parallel Subtract with Signed Saturation Word + * PADDUB rd, rs, rt Parallel Add with Unsigned saturation Byte + * PSUBUB rd, rs, rt Parallel Subtract with Unsigned saturation Byte + * PADDUH rd, rs, rt Parallel Add with Unsigned saturation Halfword + * PSUBUH rd, rs, rt Parallel Subtract with Unsigned saturation Halfword + * PADDUW rd, rs, rt Parallel Add with Unsigned saturation Word + * PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word + */ + +/* + * Min/Max (4 instructions) + * ------------------------ + * PMAXH rd, rs, rt Parallel Maximum Halfword + * PMINH rd, rs, rt Parallel Minimum Halfword + * PMAXW rd, rs, rt Parallel Maximum Word + * PMINW rd, rs, rt Parallel Minimum Word + */ + +/* + * Absolute (2 instructions) + * ------------------------- + * PABSH rd, rt Parallel Absolute Halfword + * PABSW rd, rt Parallel Absolute Word + */ + +/* + * Logical (4 instructions) + * ------------------------ + * PAND rd, rs, rt Parallel AND + * POR rd, rs, rt Parallel OR + * PXOR rd, rs, rt Parallel XOR + * PNOR rd, rs, rt Parallel NOR + */ + +/* + * Shift (9 instructions) + * ---------------------- + * PSLLH rd, rt, sa Parallel Shift Left Logical Halfword + * PSRLH rd, rt, sa Parallel Shift Right Logical Halfword + * PSRAH rd, rt, sa Parallel Shift Right Arithmetic Halfword + * PSLLW rd, rt, sa Parallel Shift Left Logical Word + * PSRLW rd, rt, sa Parallel Shift Right Logical Word + * PSRAW rd, rt, sa Parallel Shift Right Arithmetic Word + * PSLLVW rd, rt, rs Parallel Shift Left Logical Variable Word + * PSRLVW rd, rt, rs Parallel Shift Right Logical Variable Word + * PSRAVW rd, rt, rs Parallel Shift Right Arithmetic Variable Word + */ + +/* + * Compare (6 instructions) + * ------------------------ + * PCGTB rd, rs, rt Parallel Compare for Greater Than Byte + * PCEQB rd, rs, rt Parallel Compare for Equal Byte + * PCGTH rd, rs, rt Parallel Compare for Greater Than Halfword + * PCEQH rd, rs, rt Parallel Compare for Equal Halfword + * PCGTW rd, rs, rt Parallel Compare for Greater Than Word + * PCEQW rd, rs, rt Parallel Compare for Equal Word + */ + +/* + * LZC (1 instruction) + * ------------------- + * PLZCW rd, rs Parallel Leading Zero or One Count Word + */ + +/* + * Quadword Load and Store (2 instructions) + * ---------------------------------------- + * LQ rt, offset(base) Load Quadword + * SQ rt, offset(base) Store Quadword + */ + +/* + * Multiply and Divide (19 instructions) + * ------------------------------------- + * PMULTW rd, rs, rt Parallel Multiply Word + * PMULTUW rd, rs, rt Parallel Multiply Unsigned Word + * PDIVW rs, rt Parallel Divide Word + * PDIVUW rs, rt Parallel Divide Unsigned Word + * PMADDW rd, rs, rt Parallel Multiply-Add Word + * PMADDUW rd, rs, rt Parallel Multiply-Add Unsigned Word + * PMSUBW rd, rs, rt Parallel Multiply-Subtract Word + * PMULTH rd, rs, rt Parallel Multiply Halfword + * PMADDH rd, rs, rt Parallel Multiply-Add Halfword + * PMSUBH rd, rs, rt Parallel Multiply-Subtract Halfword + * PHMADH rd, rs, rt Parallel Horizontal Multiply-Add Halfword + * PHMSBH rd, rs, rt Parallel Horizontal Multiply-Subtract Halfword + * PDIVBW rs, rt Parallel Divide Broadcast Word + * PMFHI rd Parallel Move From HI Register + * PMFLO rd Parallel Move From LO Register + * PMTHI rs Parallel Move To HI Register + * PMTLO rs Parallel Move To LO Register + * PMFHL rd Parallel Move From HI/LO Register + * PMTHL rs Parallel Move To HI/LO Register + */ + +/* + * Pack/Extend (11 instructions) + * ----------------------------- + * PPAC5 rd, rt Parallel Pack to 5 bits + * PPACB rd, rs, rt Parallel Pack to Byte + * PPACH rd, rs, rt Parallel Pack to Halfword + * PPACW rd, rs, rt Parallel Pack to Word + * PEXT5 rd, rt Parallel Extend Upper from 5 bits + * PEXTUB rd, rs, rt Parallel Extend Upper from Byte + * PEXTLB rd, rs, rt Parallel Extend Lower from Byte + * PEXTUH rd, rs, rt Parallel Extend Upper from Halfword + * PEXTLH rd, rs, rt Parallel Extend Lower from Halfword + * PEXTUW rd, rs, rt Parallel Extend Upper from Word + * PEXTLW rd, rs, rt Parallel Extend Lower from Word + */ + +/* + * Others (16 instructions) + * ------------------------ + * PCPYH rd, rt Parallel Copy Halfword + * PCPYLD rd, rs, rt Parallel Copy Lower Doubleword + * PCPYUD rd, rs, rt Parallel Copy Upper Doubleword + * PREVH rd, rt Parallel Reverse Halfword + * PINTH rd, rs, rt Parallel Interleave Halfword + * PINTEH rd, rs, rt Parallel Interleave Even Halfword + * PEXEH rd, rt Parallel Exchange Even Halfword + * PEXCH rd, rt Parallel Exchange Center Halfword + * PEXEW rd, rt Parallel Exchange Even Word + * PEXCW rd, rt Parallel Exchange Center Word + * QFSRV rd, rs, rt Quadword Funnel Shift Right Variable + * MFSA rd Move from Shift Amount Register + * MTSA rs Move to Shift Amount Register + * MTSAB rs, immediate Move Byte Count to Shift Amount Register + * MTSAH rs, immediate Move Halfword Count to Shift Amount Register + * PROT3W rd, rt Parallel Rotate 3 Words + */ + /* Parallel Copy Halfword */ static bool trans_PCPYH(DisasContext *s, arg_rtype *a) { From patchwork Sun Feb 14 17:58:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087337 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id c62sm22338051wmd.43.2021.02.14.10.00.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:00:29 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 15/42] target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic) Date: Sun, 14 Feb 2021 18:58:45 +0100 Message-Id: <20210214175912.732946-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce the parallel logic opcodes: - PAND (Parallel AND) - POR (Parallel OR) - PXOR (Parallel XOR) - PNOR (Parallel NOR) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tx79.decode | 4 +++ target/mips/tx79_translate.c | 54 ++++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 0f748b53a64..26c80b9bce5 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -32,8 +32,12 @@ MTLO1 011100 ..... 0000000000 00000 010011 @rs # MMI2 PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd +PAND 011100 ..... ..... ..... 10010 001001 @rs_rt_rd +PXOR 011100 ..... ..... ..... 10011 001001 @rs_rt_rd # MMI3 PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd +POR 011100 ..... ..... ..... 10010 101001 @rs_rt_rd +PNOR 011100 ..... ..... ..... 10011 101001 @rs_rt_rd PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 243a81c3c5e..28d07baaa73 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -2,6 +2,7 @@ * Toshiba TX79-specific instructions translation routines * * Copyright (c) 2018 Fredrik Noring + * Copyright (c) 2021 Philippe Mathieu-Daudé * * SPDX-License-Identifier: GPL-2.0-or-later */ @@ -139,6 +140,59 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) * PNOR rd, rs, rt Parallel NOR */ +static bool trans_parallel_logic(DisasContext *ctx, arg_rtype *a, + void (*gen_logic_i64)(TCGv_i64, TCGv_i64, TCGv_i64)) +{ + TCGv_i64 ax, bx; + + if (a->rd == 0) { + /* nop */ + return true; + } + + ax = tcg_temp_new_i64(); + bx = tcg_temp_new_i64(); + + /* Lower halve */ + gen_load_gpr(ax, a->rs); + gen_load_gpr(bx, a->rt); + gen_logic_i64(cpu_gpr[a->rd], ax, bx); + + /* Upper halve */ + gen_load_gpr_hi(ax, a->rs); + gen_load_gpr_hi(bx, a->rt); + gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx); + + tcg_temp_free(bx); + tcg_temp_free(ax); + + return true; +} + +/* Parallel And */ +static bool trans_PAND(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_logic(ctx, a, tcg_gen_and_i64); +} + +/* Parallel Or */ +static bool trans_POR(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_logic(ctx, a, tcg_gen_or_i64); +} + +/* Parallel Exclusive Or */ +static bool trans_PXOR(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_logic(ctx, a, tcg_gen_xor_i64); +} + +/* Parallel Not Or */ +static bool trans_PNOR(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_logic(ctx, a, tcg_gen_nor_i64); +} + /* * Shift (9 instructions) * ---------------------- From patchwork Sun Feb 14 17:58:46 2021 Content-Type: text/plain; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id t9sm15791314wrw.76.2021.02.14.10.00.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:00:34 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 16/42] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract) Date: Sun, 14 Feb 2021 18:58:46 +0100 Message-Id: <20210214175912.732946-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce the 'Parallel Subtract' opcodes: - PSUBB (Parallel Subtract Byte) - PSUBH (Parallel Subtract Halfword) - PSUBW (Parallel Subtract Word) Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tx79.decode | 6 ++++ target/mips/tx79_translate.c | 61 ++++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 26c80b9bce5..d1c07c7d901 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -29,6 +29,12 @@ MTHI1 011100 ..... 0000000000 00000 010001 @rs MFLO1 011100 0000000000 ..... 00000 010010 @rd MTLO1 011100 ..... 0000000000 00000 010011 @rs +# MMI0 + +PSUBW 011100 ..... ..... ..... 00001 001000 @rs_rt_rd +PSUBH 011100 ..... ..... ..... 00101 001000 @rs_rt_rd +PSUBB 011100 ..... ..... ..... 01001 001000 @rs_rt_rd + # MMI2 PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 28d07baaa73..23146f6bfac 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -115,6 +115,67 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) * PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Word */ +static bool trans_parallel_substract(DisasContext *ctx, arg_rtype *a, unsigned wlen) +{ + TCGv_i64 ax, bx, t0, t1, t2; + + if (a->rd == 0) { + /* nop */ + return true; + } + + ax = tcg_temp_new_i64(); + bx = tcg_temp_new_i64(); + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + t2 = tcg_temp_new_i64(); + + /* Lower halve */ + gen_load_gpr(ax, a->rs); + gen_load_gpr(bx, a->rt); + for (int i = 0; i < (64 / wlen); i++) { + tcg_gen_sextract_i64(t0, ax, wlen * i, wlen); + tcg_gen_sextract_i64(t1, bx, wlen * i, wlen); + tcg_gen_sub_i64(t2, t0, t1); + tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], t2, wlen * i, wlen); + } + /* Upper halve */ + gen_load_gpr_hi(ax, a->rs); + gen_load_gpr_hi(bx, a->rt); + for (int i = 0; i < (64 / wlen); i++) { + tcg_gen_sextract_i64(t0, ax, wlen * i, wlen); + tcg_gen_sextract_i64(t1, bx, wlen * i, wlen); + tcg_gen_sub_i64(t2, t0, t1); + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], t2, wlen * i, wlen); + } + + tcg_temp_free(t2); + tcg_temp_free(t1); + tcg_temp_free(t0); + tcg_temp_free(bx); + tcg_temp_free(ax); + + return true; +} + +/* Parallel Subtract Byte */ +static bool trans_PSUBB(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_substract(ctx, a, 8); +} + +/* Parallel Subtract Halfword */ +static bool trans_PSUBH(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_substract(ctx, a, 16); +} + +/* Parallel Subtract Word */ +static bool trans_PSUBW(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_substract(ctx, a, 32); +} + /* * Min/Max (4 instructions) * ------------------------ From patchwork Sun Feb 14 17:58:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AE85C433E0 for ; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id o13sm27880973wrs.45.2021.02.14.10.00.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:00:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 17/42] target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word) Date: Sun, 14 Feb 2021 18:58:47 +0100 Message-Id: <20210214175912.732946-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce the PEXTUW opcode (Parallel Extend Upper from Word). Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tx79.decode | 4 ++++ target/mips/tx79_translate.c | 26 ++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index d1c07c7d901..ead5f8281e5 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -35,6 +35,10 @@ PSUBW 011100 ..... ..... ..... 00001 001000 @rs_rt_rd PSUBH 011100 ..... ..... ..... 00101 001000 @rs_rt_rd PSUBB 011100 ..... ..... ..... 01001 001000 @rs_rt_rd +# MMI1 + +PEXTUW 011100 ..... ..... ..... 10010 101000 @rs_rt_rd + # MMI2 PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 23146f6bfac..0a2fb28600b 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -332,6 +332,32 @@ static bool trans_PNOR(DisasContext *ctx, arg_rtype *a) * PEXTLW rd, rs, rt Parallel Extend Lower from Word */ +/* Parallel Extend Upper from Word */ +static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *a) +{ + TCGv_i64 ax, bx; + + if (a->rd == 0) { + /* nop */ + return true; + } + + ax = tcg_temp_new_i64(); + bx = tcg_temp_new_i64(); + + gen_load_gpr_hi(ax, a->rs); + gen_load_gpr_hi(bx, a->rt); + + tcg_gen_deposit_i64(cpu_gpr[a->rd], bx, ax, 32, 32); + tcg_gen_shri_i64(bx, bx, 32); + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], ax, bx, 0, 32); + + tcg_temp_free(bx); + tcg_temp_free(ax); + + return true; +} + /* * Others (16 instructions) * ------------------------ From patchwork Sun Feb 14 17:58:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49B24C433E0 for ; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id f7sm10918378wmh.39.2021.02.14.10.00.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:00:44 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 18/42] target/mips/tx79: Introduce PEXTU[BHW] opcodes (Parallel Extend Lower) Date: Sun, 14 Feb 2021 18:58:48 +0100 Message-Id: <20210214175912.732946-19-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce the 'Parallel Extend Lower' opcodes: - PEXTLB (Parallel Extend Upper from Byte) - PEXTLH (Parallel Extend Upper from Halfword) - PEXTLW (Parallel Extend Upper from Word) Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tx79.decode | 3 ++ target/mips/tx79_translate.c | 78 ++++++++++++++++++++++++++++++++++++ 2 files changed, 81 insertions(+) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index ead5f8281e5..98f21d33e3f 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -34,6 +34,9 @@ MTLO1 011100 ..... 0000000000 00000 010011 @rs PSUBW 011100 ..... ..... ..... 00001 001000 @rs_rt_rd PSUBH 011100 ..... ..... ..... 00101 001000 @rs_rt_rd PSUBB 011100 ..... ..... ..... 01001 001000 @rs_rt_rd +PEXTLW 011100 ..... ..... ..... 10010 001000 @rs_rt_rd +PEXTLH 011100 ..... ..... ..... 10110 001000 @rs_rt_rd +PEXTLB 011100 ..... ..... ..... 11010 001000 @rs_rt_rd # MMI1 diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 0a2fb28600b..11968d6edab 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -332,6 +332,84 @@ static bool trans_PNOR(DisasContext *ctx, arg_rtype *a) * PEXTLW rd, rs, rt Parallel Extend Lower from Word */ +static bool trans_PEXTLx(DisasContext *ctx, arg_rtype *a, unsigned wlen) +{ + TCGv_i64 ax, bx; + + if (a->rd == 0) { + /* nop */ + return true; + } + + ax = tcg_temp_new_i64(); + bx = tcg_temp_new_i64(); + + gen_load_gpr(ax, a->rs); + gen_load_gpr(bx, a->rt); + + /* Lower halve */ + for (int i = 0; i < 64 / (2 * wlen); i++) { + tcg_gen_deposit_i64(cpu_gpr[a->rd], + cpu_gpr[a->rd], bx, 2 * wlen * i, wlen); + tcg_gen_deposit_i64(cpu_gpr[a->rd], + cpu_gpr[a->rd], ax, 2 * wlen * i + wlen, wlen); + tcg_gen_shri_i64(bx, bx, wlen); + tcg_gen_shri_i64(ax, ax, wlen); + } + /* Upper halve */ + for (int i = 0; i < 64 / (2 * wlen); i++) { + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], + cpu_gpr_hi[a->rd], bx, 2 * wlen * i, wlen); + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], + cpu_gpr_hi[a->rd], ax, 2 * wlen * i + wlen, wlen); + tcg_gen_shri_i64(bx, bx, wlen); + tcg_gen_shri_i64(ax, ax, wlen); + } + + tcg_temp_free(bx); + tcg_temp_free(ax); + + return true; +} + +/* Parallel Extend Lower from Byte */ +static bool trans_PEXTLB(DisasContext *ctx, arg_rtype *a) +{ + return trans_PEXTLx(ctx, a, 8); +} + +/* Parallel Extend Lower from Halfword */ +static bool trans_PEXTLH(DisasContext *ctx, arg_rtype *a) +{ + return trans_PEXTLx(ctx, a, 16); +} + +/* Parallel Extend Lower from Word */ +static bool trans_PEXTLW(DisasContext *ctx, arg_rtype *a) +{ + TCGv_i64 ax, bx; + + if (a->rd == 0) { + /* nop */ + return true; + } + + ax = tcg_temp_new_i64(); + bx = tcg_temp_new_i64(); + + gen_load_gpr(ax, a->rs); + gen_load_gpr(bx, a->rt); + + tcg_gen_deposit_i64(cpu_gpr[a->rd], bx, ax, 32, 32); + tcg_gen_shri_i64(bx, bx, 32); + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], ax, bx, 0, 32); + + tcg_temp_free(bx); + tcg_temp_free(ax); + + return true; +} + /* Parallel Extend Upper from Word */ static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *a) { From patchwork Sun Feb 14 17:58:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087347 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41C8FC433E0 for ; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id j40sm20223076wmp.47.2021.02.14.10.00.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:00:49 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 19/42] target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal) Date: Sun, 14 Feb 2021 18:58:49 +0100 Message-Id: <20210214175912.732946-20-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce the 'Parallel Compare for Equal' opcodes: - PCEQB (Parallel Compare for Equal Byte) - PCEQH (Parallel Compare for Equal Halfword) - PCEQW (Parallel Compare for Equal Word) Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tx79.decode | 3 ++ target/mips/tx79_translate.c | 66 ++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 98f21d33e3f..cfe721755ca 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -40,6 +40,9 @@ PEXTLB 011100 ..... ..... ..... 11010 001000 @rs_rt_rd # MMI1 +PCEQW 011100 ..... ..... ..... 00010 101000 @rs_rt_rd +PCEQH 011100 ..... ..... ..... 00110 101000 @rs_rt_rd +PCEQB 011100 ..... ..... ..... 01010 101000 @rs_rt_rd PEXTUW 011100 ..... ..... ..... 10010 101000 @rs_rt_rd # MMI2 diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 11968d6edab..f084faa48a7 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -279,6 +279,72 @@ static bool trans_PNOR(DisasContext *ctx, arg_rtype *a) * PCEQW rd, rs, rt Parallel Compare for Equal Word */ +static bool trans_parallel_compare(DisasContext *ctx, arg_rtype *a, + TCGCond cond, unsigned wlen) +{ + TCGv_i64 c0, c1, ax, bx, t0, t1, t2; + + if (a->rd == 0) { + /* nop */ + return true; + } + + c0 = tcg_const_tl(0); + c1 = tcg_const_tl(0xffffffff); + ax = tcg_temp_new_i64(); + bx = tcg_temp_new_i64(); + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + t2 = tcg_temp_new_i64(); + + /* Lower halve */ + gen_load_gpr(ax, a->rs); + gen_load_gpr(bx, a->rt); + for (int i = 0; i < (64 / wlen); i++) { + tcg_gen_sextract_i64(t0, ax, wlen * i, wlen); + tcg_gen_sextract_i64(t1, bx, wlen * i, wlen); + tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0); + tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], t2, wlen * i, wlen); + } + /* Upper halve */ + gen_load_gpr_hi(ax, a->rs); + gen_load_gpr_hi(bx, a->rt); + for (int i = 0; i < (64 / wlen); i++) { + tcg_gen_sextract_i64(t0, ax, wlen * i, wlen); + tcg_gen_sextract_i64(t1, bx, wlen * i, wlen); + tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0); + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], t2, wlen * i, wlen); + } + + tcg_temp_free(t2); + tcg_temp_free(t1); + tcg_temp_free(t0); + tcg_temp_free(bx); + tcg_temp_free(ax); + tcg_temp_free(c1); + tcg_temp_free(c0); + + return true; +} + +/* Parallel Compare for Equal Byte */ +static bool trans_PCEQB(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_compare(ctx, a, TCG_COND_EQ, 8); +} + +/* Parallel Compare for Equal Halfword */ +static bool trans_PCEQH(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_compare(ctx, a, TCG_COND_EQ, 16); +} + +/* Parallel Compare for Equal Word */ +static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_compare(ctx, a, TCG_COND_EQ, 32); +} + /* * LZC (1 instruction) * ------------------- From patchwork Sun Feb 14 17:58:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087333 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E112AC433DB for ; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id v17sm15268445wru.85.2021.02.14.10.00.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:00:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 20/42] target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than) Date: Sun, 14 Feb 2021 18:58:50 +0100 Message-Id: <20210214175912.732946-21-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce the 'Parallel Compare for Greater Than' opcodes: - PCGTB (Parallel Compare for Greater Than Byte) - PCGTH (Parallel Compare for Greater Than Halfword) - PCGTW (Parallel Compare for Greater Than Word) Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tx79.decode | 3 +++ target/mips/tx79_translate.c | 18 ++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index cfe721755ca..63fbe9694bb 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -32,8 +32,11 @@ MTLO1 011100 ..... 0000000000 00000 010011 @rs # MMI0 PSUBW 011100 ..... ..... ..... 00001 001000 @rs_rt_rd +PCGTW 011100 ..... ..... ..... 00010 001000 @rs_rt_rd PSUBH 011100 ..... ..... ..... 00101 001000 @rs_rt_rd +PCGTH 011100 ..... ..... ..... 00110 001000 @rs_rt_rd PSUBB 011100 ..... ..... ..... 01001 001000 @rs_rt_rd +PCGTB 011100 ..... ..... ..... 01010 001000 @rs_rt_rd PEXTLW 011100 ..... ..... ..... 10010 001000 @rs_rt_rd PEXTLH 011100 ..... ..... ..... 10110 001000 @rs_rt_rd PEXTLB 011100 ..... ..... ..... 11010 001000 @rs_rt_rd diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index f084faa48a7..04249b0c20a 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -327,18 +327,36 @@ static bool trans_parallel_compare(DisasContext *ctx, arg_rtype *a, return true; } +/* Parallel Compare for Greater Than Byte */ +static bool trans_PCGTB(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_compare(ctx, a, TCG_COND_GE, 8); +} + /* Parallel Compare for Equal Byte */ static bool trans_PCEQB(DisasContext *ctx, arg_rtype *a) { return trans_parallel_compare(ctx, a, TCG_COND_EQ, 8); } +/* Parallel Compare for Greater Than Halfword */ +static bool trans_PCGTH(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_compare(ctx, a, TCG_COND_GE, 16); +} + /* Parallel Compare for Equal Halfword */ static bool trans_PCEQH(DisasContext *ctx, arg_rtype *a) { return trans_parallel_compare(ctx, a, TCG_COND_EQ, 16); } +/* Parallel Compare for Greater Than Word */ +static bool trans_PCGTW(DisasContext *ctx, arg_rtype *a) +{ + return trans_parallel_compare(ctx, a, TCG_COND_GE, 32); +} + /* Parallel Compare for Equal Word */ static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a) { From patchwork Sun Feb 14 17:58:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087355 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F72BC433E0 for ; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id s10sm20256521wrm.5.2021.02.14.10.00.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:00:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 21/42] target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word) Date: Sun, 14 Feb 2021 18:58:51 +0100 Message-Id: <20210214175912.732946-22-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce the PPACW opcode (Parallel Pack to Word). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tx79.decode | 1 + target/mips/tx79_translate.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 63fbe9694bb..653910371d2 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -38,6 +38,7 @@ PCGTH 011100 ..... ..... ..... 00110 001000 @rs_rt_rd PSUBB 011100 ..... ..... ..... 01001 001000 @rs_rt_rd PCGTB 011100 ..... ..... ..... 01010 001000 @rs_rt_rd PEXTLW 011100 ..... ..... ..... 10010 001000 @rs_rt_rd +PPACW 011100 ..... ..... ..... 10011 001000 @rs_rt_rd PEXTLH 011100 ..... ..... ..... 10110 001000 @rs_rt_rd PEXTLB 011100 ..... ..... ..... 11010 001000 @rs_rt_rd diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 04249b0c20a..ac75d95b82b 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -416,6 +416,36 @@ static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a) * PEXTLW rd, rs, rt Parallel Extend Lower from Word */ +/* Parallel Pack to Word */ +static bool trans_PPACW(DisasContext *ctx, arg_rtype *a) +{ + TCGv_i64 a0, b0, t0; + + if (a->rd == 0) { + /* nop */ + return true; + } + + a0 = tcg_temp_new_i64(); + b0 = tcg_temp_new_i64(); + t0 = tcg_temp_new_i64(); + + gen_load_gpr(a0, a->rs); + gen_load_gpr(b0, a->rt); + + gen_load_gpr_hi(t0, a->rt); /* b1 */ + tcg_gen_deposit_i64(cpu_gpr[a->rd], b0, t0, 32, 32); + + gen_load_gpr_hi(t0, a->rs); /* a1 */ + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], a0, t0, 32, 32); + + tcg_temp_free(t0); + tcg_temp_free(b0); + tcg_temp_free(a0); + + return true; +} + static bool trans_PEXTLx(DisasContext *ctx, arg_rtype *a, unsigned wlen) { TCGv_i64 ax, bx; From patchwork Sun Feb 14 17:58:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087341 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29999C433E0 for ; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id h18sm5547186wmm.30.2021.02.14.10.01.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:01:04 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 22/42] target/mips/tx79: Introduce PINTEH (Parallel Interleave Even Halfword) Date: Sun, 14 Feb 2021 18:58:52 +0100 Message-Id: <20210214175912.732946-23-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce the PINTEH opcode (Parallel Interleave Even Halfword). Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tx79.decode | 1 + target/mips/tx79_translate.c | 45 ++++++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 653910371d2..fbd2be569ad 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -57,6 +57,7 @@ PXOR 011100 ..... ..... ..... 10011 001001 @rs_rt_rd # MMI3 +PINTEH 011100 ..... ..... ..... 01010 101001 @rs_rt_rd PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd POR 011100 ..... ..... ..... 10010 101001 @rs_rt_rd PNOR 011100 ..... ..... ..... 10011 101001 @rs_rt_rd diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index ac75d95b82b..47d84c465a2 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -638,3 +638,48 @@ static bool trans_PCPYUD(DisasContext *s, arg_rtype *a) return true; } + +/* Parallel Interleave Even Halfword */ +static bool trans_PINTEH(DisasContext *ctx, arg_rtype *a) +{ + TCGv_i64 ax, bx; + + if (a->rd == 0) { + /* nop */ + return true; + } + + if (unlikely(a->rs == 0 && a->rt == 0)) { + tcg_gen_movi_i64(cpu_gpr[a->rd], 0); + tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); + return true; + } + + ax = tcg_temp_new_i64(); + bx = tcg_temp_new_i64(); + + /* Lower halve */ + gen_load_gpr(ax, a->rs); + gen_load_gpr(bx, a->rt); + if (a->rd != a->rt) { + tcg_gen_mov_i64(cpu_gpr[a->rd], bx); + } + tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], ax, 16, 16); + tcg_gen_shri_i64(ax, ax, 32); + tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], ax, 48, 16); + + /* Upper halve */ + gen_load_gpr_hi(ax, a->rs); + gen_load_gpr_hi(bx, a->rt); + if (a->rd != a->rt) { + tcg_gen_mov_i64(cpu_gpr_hi[a->rd], bx); + } + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], ax, 16, 16); + tcg_gen_shri_i64(ax, ax, 32); + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], ax, 48, 16); + + tcg_temp_free(bx); + tcg_temp_free(ax); + + return true; +} From patchwork Sun Feb 14 17:58:53 2021 Content-Type: text/plain; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id t198sm12710979wmt.7.2021.02.14.10.01.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:01:09 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 23/42] target/mips/tx79: Introduce PEXE[HW] opcodes (Parallel Exchange Even) Date: Sun, 14 Feb 2021 18:58:53 +0100 Message-Id: <20210214175912.732946-24-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce the PEXEH (Parallel Exchange Even Halfword) and PEXEW (Parallel Exchange Even Word) opcodes. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tx79.decode | 2 ++ target/mips/tx79_translate.c | 70 ++++++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index fbd2be569ad..0ea9fc95568 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -54,6 +54,8 @@ PEXTUW 011100 ..... ..... ..... 10010 101000 @rs_rt_rd PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd PAND 011100 ..... ..... ..... 10010 001001 @rs_rt_rd PXOR 011100 ..... ..... ..... 10011 001001 @rs_rt_rd +PEXEH 011100 00000 ..... ..... 11010 001001 @rt_rd +PEXEW 011100 00000 ..... ..... 11110 001001 @rt_rd # MMI3 diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 47d84c465a2..59451a043a4 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -683,3 +683,73 @@ static bool trans_PINTEH(DisasContext *ctx, arg_rtype *a) return true; } + +/* Parallel Exchange Even Halfword */ +static bool trans_PEXEH(DisasContext *ctx, arg_rtype *a) +{ + TCGv_i64 ax; + + if (a->rd == 0) { + /* nop */ + return true; + } + if (a->rt == 0) { + tcg_gen_movi_i64(cpu_gpr[a->rd], 0); + tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); + return true; + } + + ax = tcg_temp_new_i64(); + + /* Lower halve */ + tcg_gen_mov_i64(ax, cpu_gpr[a->rt]); + if (a->rd != a->rt) { + tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]); + } + tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], ax, 32, 16); + tcg_gen_shri_i64(ax, ax, 32); + tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], ax, 0, 16); + + /* Upper halve */ + tcg_gen_mov_i64(ax, cpu_gpr_hi[a->rt]); + if (a->rd != a->rt) { + tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt]); + } + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], ax, 32, 16); + tcg_gen_shri_i64(ax, ax, 32); + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], ax, 0, 16); + + tcg_temp_free(ax); + + return true; +} + +/* Parallel Exchange Even Word */ +static bool trans_PEXEW(DisasContext *ctx, arg_rtype *a) +{ + TCGv_i64 ah, al; + + if (a->rd == 0) { + /* nop */ + return true; + } + if (a->rt == 0) { + tcg_gen_movi_i64(cpu_gpr[a->rd], 0); + tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); + return true; + } + + ah = tcg_temp_new_i64(); + al = tcg_temp_new_i64(); + + gen_load_gpr(ah, a->rt); + gen_load_gpr_hi(al, a->rt); + + tcg_gen_deposit_i64(cpu_gpr[a->rd], ah, al, 0, 32); + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], al, ah, 0, 32); + + tcg_temp_free(al); + tcg_temp_free(ah); + + return true; +} From patchwork Sun Feb 14 17:58:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087343 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3121C433DB for ; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id g136sm7512538wme.10.2021.02.14.10.01.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:01:14 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 24/42] target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words) Date: Sun, 14 Feb 2021 18:58:54 +0100 Message-Id: <20210214175912.732946-25-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce the PROT3W opcode (Parallel Rotate 3 Words). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tx79.decode | 1 + target/mips/tx79_translate.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 0ea9fc95568..79001359242 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -56,6 +56,7 @@ PAND 011100 ..... ..... ..... 10010 001001 @rs_rt_rd PXOR 011100 ..... ..... ..... 10011 001001 @rs_rt_rd PEXEH 011100 00000 ..... ..... 11010 001001 @rt_rd PEXEW 011100 00000 ..... ..... 11110 001001 @rt_rd +PROT3W 011100 00000 ..... ..... 11111 001001 @rt_rd # MMI3 diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 59451a043a4..c25f61d382c 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -753,3 +753,31 @@ static bool trans_PEXEW(DisasContext *ctx, arg_rtype *a) return true; } + +/* Parallel Rotate 3 Words Left */ +static bool trans_PROT3W(DisasContext *ctx, arg_rtype *a) +{ + TCGv_i64 ax; + + if (a->rd == 0) { + /* nop */ + return true; + } + if (a->rt == 0) { + tcg_gen_movi_i64(cpu_gpr[a->rd], 0); + tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0); + return true; + } + + ax = tcg_temp_new_i64(); + + tcg_gen_mov_i64(ax, cpu_gpr_hi[a->rt]); + tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], ax, cpu_gpr[a->rt], 0, 32); + + tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], ax, 0, 32); + tcg_gen_rotri_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], 32); + + tcg_temp_free(ax); + + return true; +} From patchwork Sun Feb 14 17:58:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087373 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FA36C433DB for ; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id x4sm19853110wrn.64.2021.02.14.10.01.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:01:19 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 25/42] target/mips/tx79: Introduce LQ opcode (Load Quadword) Date: Sun, 14 Feb 2021 18:58:55 +0100 Message-Id: <20210214175912.732946-26-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce the LQ opcode (Load Quadword) and remove unreachable code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tx79.decode | 8 ++++++++ target/mips/translate.c | 16 ++-------------- target/mips/tx79_translate.c | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+), 14 deletions(-) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index 79001359242..b5396f48c2d 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -13,6 +13,8 @@ &rtype rs rt rd sa +&itype base rt offset + ########################################################################### # Named instruction formats. These are generally used to # reduce the amount of duplication between instruction patterns. @@ -22,6 +24,8 @@ @rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0 @rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0 +@ldst ...... base:5 rt:5 offset:16 &itype + ########################################################################### MFHI1 011100 0000000000 ..... 00000 010000 @rd @@ -65,3 +69,7 @@ PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd POR 011100 ..... ..... ..... 10010 101001 @rs_rt_rd PNOR 011100 ..... ..... ..... 10011 101001 @rs_rt_rd PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd + +# SPECIAL + +LQ 011110 ..... ..... ................ @ldst diff --git a/target/mips/translate.c b/target/mips/translate.c index 109f7f80f3d..bed0489997a 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1780,7 +1780,6 @@ enum { enum { MMI_OPC_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */ - MMI_OPC_LQ = 0x1E << 26, /* Same as OPC_MSA */ MMI_OPC_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */ }; @@ -27331,11 +27330,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx) } } -static void gen_mmi_lq(CPUMIPSState *env, DisasContext *ctx) -{ - gen_reserved_instruction(ctx); /* TODO: MMI_OPC_LQ */ -} - static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset) { gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */ @@ -28229,14 +28223,8 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) gen_compute_branch(ctx, op, 4, rs, rt, offset, 4); } break; - case OPC_MDMX: /* MMI_OPC_LQ */ - if (ctx->insn_flags & INSN_R5900) { -#if defined(TARGET_MIPS64) - gen_mmi_lq(env, ctx); -#endif - } else { - /* MDMX: Not implemented. */ - } + case OPC_MDMX: + /* MDMX: Not implemented. */ break; case OPC_PCREL: check_insn(ctx, ISA_MIPS_R6); diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index c25f61d382c..293efd7bd06 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -376,6 +376,41 @@ static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a) * SQ rt, offset(base) Store Quadword */ +static bool trans_LQ(DisasContext *ctx, arg_itype *a) +{ + TCGv_i64 t0; + TCGv addr; + + if (a->rt == 0) { + /* nop */ + return true; + } + + t0 = tcg_temp_new_i64(); + addr = tcg_temp_new(); + + gen_base_offset_addr(ctx, addr, a->base, a->offset); + /* + * Clear least-significant four bits of the effective + * address, effectively creating an aligned address. + */ + tcg_gen_andi_tl(addr, addr, ~0xf); + + /* Lower halve */ + tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEQ); + gen_store_gpr(t0, a->rt); + + /* Upper halve */ + tcg_gen_addi_i64(addr, addr, 8); + tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEQ); + gen_store_gpr_hi(t0, a->rt); + + tcg_temp_free(t0); + tcg_temp_free(addr); + + return true; +} + /* * Multiply and Divide (19 instructions) * ------------------------------------- From patchwork Sun Feb 14 17:58:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087353 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E62C9C433DB for ; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id d15sm16117354wru.80.2021.02.14.10.01.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:01:24 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 26/42] target/mips/tx79: Introduce SQ opcode (Store Quadword) Date: Sun, 14 Feb 2021 18:58:56 +0100 Message-Id: <20210214175912.732946-27-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce the SQ opcode (Store Quadword). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tx79.decode | 1 + target/mips/tx79_translate.c | 27 +++++++++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode index b5396f48c2d..f1cb7ebfa3c 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tx79.decode @@ -73,3 +73,4 @@ PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd # SPECIAL LQ 011110 ..... ..... ................ @ldst +SQ 011111 ..... ..... ................ @ldst diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 293efd7bd06..386bae7808b 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -411,6 +411,33 @@ static bool trans_LQ(DisasContext *ctx, arg_itype *a) return true; } +static bool trans_SQ(DisasContext *ctx, arg_itype *a) +{ + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv addr = tcg_temp_new(); + + gen_base_offset_addr(ctx, addr, a->base, a->offset); + /* + * Clear least-significant four bits of the effective + * address, effectively creating an aligned address. + */ + tcg_gen_andi_tl(addr, addr, ~0xf); + + /* Lower halve */ + gen_load_gpr(t0, a->rt); + tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ); + + /* Upper halve */ + tcg_gen_addi_i64(addr, addr, 8); + gen_load_gpr_hi(t0, a->rt); + tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEQ); + + tcg_temp_free(addr); + tcg_temp_free(t0); + + return true; +} + /* * Multiply and Divide (19 instructions) * ------------------------------------- From patchwork Sun Feb 14 17:58:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087351 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A51FC433E0 for ; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id f8sm20100594wrp.65.2021.02.14.10.01.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:01:29 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 27/42] target/mips/translate: Make gen_rdhwr() public Date: Sun, 14 Feb 2021 18:58:57 +0100 Message-Id: <20210214175912.732946-28-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We will use gen_rdhwr() outside of translate.c, make it public. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/translate.h | 2 ++ target/mips/translate.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/mips/translate.h b/target/mips/translate.h index bc91ac4f53f..d2ba3524b51 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -148,6 +148,8 @@ void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1); bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa); bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa); +void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel); + extern TCGv cpu_gpr[32], cpu_PC; #if defined(TARGET_MIPS64) extern TCGv_i64 cpu_gpr_hi[32]; diff --git a/target/mips/translate.c b/target/mips/translate.c index bed0489997a..c1d07a4591d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -12655,7 +12655,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, } } -static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) +void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) { TCGv t0; From patchwork Sun Feb 14 17:58:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087363 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5E78C433E0 for ; Sun, 14 Feb 2021 18:28:27 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5C91B64DD8 for ; Sun, 14 Feb 2021 18:28:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5C91B64DD8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:50590 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBM8A-0005Hl-9w for qemu-devel@archiver.kernel.org; Sun, 14 Feb 2021 13:28:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34174) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBLiE-0000OB-DO for qemu-devel@nongnu.org; Sun, 14 Feb 2021 13:01:38 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:52630) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBLiC-0004bi-K1 for qemu-devel@nongnu.org; Sun, 14 Feb 2021 13:01:38 -0500 Received: by mail-wm1-x331.google.com with SMTP id l17so4228079wmq.2 for ; Sun, 14 Feb 2021 10:01:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d546qymlao/rzWtR36sSyopsQgU3D8u3O18dLCPSATQ=; b=ZMjnLcRY1+EILKAApUubkZ0uzZnVCg5UfW1UOttGln5PJ5eR2aAQoWXTkcuBIbUeQG /fGFj4raEFC4n4aOP92hwOTIzhIm4cgAZcWb1hwUvd8AMIZoZ82WgTLef/nhIq1TOE+r UEs7dhEnhaNj9CYtTc2FGMgdTYcUu+QwZMKOtuXblLvl/KhYpXcKPANdD41BDdnZqJOv TIdbqzqAvPid0aO2EOsy2U6LnfLcV3t1wwEHXL3/OZdxiuBL7Qq9V2mMwLIIbvo2+nZZ 2exF/t0zNoroX61qmi9sbqD+xU9yL+J3VJFw/yHkGs3NBoCtwdjxhNgR7YsTNMFCb5Jg nGJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=d546qymlao/rzWtR36sSyopsQgU3D8u3O18dLCPSATQ=; b=NKFbB4afp+LZwcoh7n/O0miALxMp6viu8tQLktqDkVPhUhKG6Haxz5857Fa/lcyzDd BmYy22tvWcYQXdMyoQReA0Zf2CufO38r/+lJ7DsvqjohTREZ7Kw604oBVIRJ8XzsJF7A 2WdzQveHTjxyrIN8ppdYUxCxLdWT5EfJewfhcyt+PYIPLI9BY+PI0yea1w6ZVDMOwLp/ KNaCzwmSgMD7ybbYO1zNXKWKAL6tdnvS+yYJAc+ghUVrS8urxlduh7YkAw+pR27YrioJ s1YuSghDx+kGL63rN74tZqoc1wRXj0elrkWD+7vjHOxpIoEW+WOQ6WplfRu/NC7OrcMt wang== X-Gm-Message-State: AOAM531+o3W2QsD8w/nZ3TtphnW1DTRfv943zoniZW/lrcZclrldFTV6 cPxoF6HAaFI0hmY2dEHtOqkkzAnPPZ8= X-Google-Smtp-Source: ABdhPJzIEuXfnUmiISWhrN/Tu/rLJ0f60OjCGa57Eq49WB5yvf3BShtly44I8uakgAerqc4H+Jjf+A== X-Received: by 2002:a7b:cf33:: with SMTP id m19mr11031041wmg.53.1613325695015; Sun, 14 Feb 2021 10:01:35 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id c3sm7167927wrr.29.2021.02.14.10.01.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:01:34 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 28/42] target/mips/tx79: Move RDHWR usermode kludge to trans_SQ() Date: Sun, 14 Feb 2021 18:58:58 +0100 Message-Id: <20210214175912.732946-29-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Now than SQ is properly implemented, we can move the RDHWR kludge required to have usermode working with recent glibc. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 56 ------------------------------------ target/mips/tx79_translate.c | 34 +++++++++++++++++++++- 2 files changed, 33 insertions(+), 57 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index c1d07a4591d..0fa2b3bcc15 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1780,7 +1780,6 @@ enum { enum { MMI_OPC_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */ - MMI_OPC_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */ }; /* @@ -27330,53 +27329,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx) } } -static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset) -{ - gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */ -} - -/* - * The TX79-specific instruction Store Quadword - * - * +--------+-------+-------+------------------------+ - * | 011111 | base | rt | offset | SQ - * +--------+-------+-------+------------------------+ - * 6 5 5 16 - * - * has the same opcode as the Read Hardware Register instruction - * - * +--------+-------+-------+-------+-------+--------+ - * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR - * +--------+-------+-------+-------+-------+--------+ - * 6 5 5 5 5 6 - * - * that is required, trapped and emulated by the Linux kernel. However, all - * RDHWR encodings yield address error exceptions on the TX79 since the SQ - * offset is odd. Therefore all valid SQ instructions can execute normally. - * In user mode, QEMU must verify the upper and lower 11 bits to distinguish - * between SQ and RDHWR, as the Linux kernel does. - */ -static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx) -{ - int base = extract32(ctx->opcode, 21, 5); - int rt = extract32(ctx->opcode, 16, 5); - int offset = extract32(ctx->opcode, 0, 16); - -#ifdef CONFIG_USER_ONLY - uint32_t op1 = MASK_SPECIAL3(ctx->opcode); - uint32_t op2 = extract32(ctx->opcode, 6, 5); - - if (base == 0 && op2 == 0 && op1 == OPC_RDHWR) { - int rd = extract32(ctx->opcode, 11, 5); - - gen_rdhwr(ctx, rt, rd, 0); - return; - } -#endif - - gen_mmi_sq(ctx, base, rt, offset); -} - #endif static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) @@ -27561,15 +27513,7 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx) } break; case OPC_SPECIAL3: -#if defined(TARGET_MIPS64) - if (ctx->insn_flags & INSN_R5900) { - decode_mmi_sq(env, ctx); /* MMI_OPC_SQ */ - } else { - decode_opc_special3(env, ctx); - } -#else decode_opc_special3(env, ctx); -#endif break; case OPC_REGIMM: op1 = MASK_REGIMM(ctx->opcode); diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c index 386bae7808b..2aa3182d21d 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tx79_translate.c @@ -411,7 +411,7 @@ static bool trans_LQ(DisasContext *ctx, arg_itype *a) return true; } -static bool trans_SQ(DisasContext *ctx, arg_itype *a) +static bool trans_SQ_real(DisasContext *ctx, arg_itype *a) { TCGv_i64 t0 = tcg_temp_new_i64(); TCGv addr = tcg_temp_new(); @@ -438,6 +438,38 @@ static bool trans_SQ(DisasContext *ctx, arg_itype *a) return true; } +static bool trans_SQ(DisasContext *ctx, arg_itype *a) +{ + /* + * The TX79-specific instruction Store Quadword + * + * +--------+-------+-------+------------------------+ + * | 011111 | base | rt | offset | SQ + * +--------+-------+-------+------------------------+ + * 6 5 5 16 + * + * has the same opcode as the Read Hardware Register instruction + * + * +--------+-------+-------+-------+-------+--------+ + * | 011111 | 00000 | rt | rd | 00000 | 111011 | RDHWR + * +--------+-------+-------+-------+-------+--------+ + * 6 5 5 5 5 6 + * + * that is required, trapped and emulated by the Linux kernel. However, all + * RDHWR encodings yield address error exceptions on the TX79 since the SQ + * offset is odd. Therefore all valid SQ instructions can execute normally. + * In user mode, QEMU must verify the upper and lower 13 bits to distinguish + * between SQ and RDHWR, as the Linux kernel does. + */ +#if defined(CONFIG_USER_ONLY) + if (!a->base && extract32(a->offset, 0, 11) == 0b00000111011) { + gen_rdhwr(ctx, a->rt, extract32(ctx->opcode, 11, 5), 0); + return true; + } +#endif + return trans_SQ_real(ctx, a); +} + /* * Multiply and Divide (19 instructions) * ------------------------------------- From patchwork Sun Feb 14 17:58:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087359 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB4C4C433E0 for ; Sun, 14 Feb 2021 18:27:03 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3B14B64E05 for ; Sun, 14 Feb 2021 18:27:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3B14B64E05 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:46026 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBM6o-0003LS-7R for qemu-devel@archiver.kernel.org; Sun, 14 Feb 2021 13:27:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34204) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBLiK-0000Ww-Vh for qemu-devel@nongnu.org; Sun, 14 Feb 2021 13:01:45 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:38286) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBLiJ-0004c2-8r for qemu-devel@nongnu.org; Sun, 14 Feb 2021 13:01:44 -0500 Received: by mail-wr1-x42a.google.com with SMTP id b3so6108979wrj.5 for ; Sun, 14 Feb 2021 10:01:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TFe7rNxsyeddhlBqR6Hor/4xHDWb1CnQmr8o6p9Au7E=; b=J3Dpl81YbZnCLeorYdgQJY+bXN2UQr0AiYPkE/6GrElm43ZY5kVLzVTpJH21XtwKcU j2GeRSkLkU8cCHn5i+nj/O9w0Yj61bAEpp7dZENMJa6WBmpaOeiRPgfraKQngDOYoWWl 8SbN2QuY8phZy5SfwmEIVfTN1b5fOutyGcM3vyzsYLonluIxZiT5MQRrj4Pa8IBVcOh6 fQNXCXJaTh/4Fl0bQ/su9YxbtAivlDJPGCPCXbSe/TDN0GU2EdjdX3g2RpkPE0IF0bzK jpdHiTkDp9K0uycgnjVLQMNNQETVOaN/+dR9u2ZvjLAtvFcyPrVSiR6XMFmUK867uRlh h2Cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=TFe7rNxsyeddhlBqR6Hor/4xHDWb1CnQmr8o6p9Au7E=; b=DlSZhIFIRgmicoDa8bnrIvWdTP2xXNCx/Uydd3uETCEu5yghoRRTEljPR1ilm4rPSY h+FyhQ4KNNVOCJbtoXs4+inzZuiL4+SCkCjUJztyo7NHNCc3d3UW9m3WMrPEL70k9cYU nFUfCY8+vPJFx4Zd0s5r3+NX5cdhHRk1XRNPRznHJ9bqyFG9i6iVjuXhbL0z6naPBbHw o6Pp+QfbyXltiJF5+QTHfnbFBYaBpxW1oZTFnmlA8hggy0ZgbejU7NmSCLfYtYpVus03 XeGbkrY48KmJZxCdXgvz6jGTFfSUzmpQ5TpL2rN4PBX9YoQJY2T+ARHKJ6IMMGXqgwNn 0jDA== X-Gm-Message-State: AOAM532XnhZ11GS7U9/ejhtHjvl0HkuNgkrQPs31dsuMd5k7Z9MPIRyI XThmIGNuAHVydve4FqFeN7LR9NmU6jc= X-Google-Smtp-Source: ABdhPJyQblBH1j/6HA1/BuXe53lnWPfN4LBzEaZgB75nUkPamE6oeXlBQzb/kCb09DVb6rzp0WT21A== X-Received: by 2002:adf:fc4e:: with SMTP id e14mr2032831wrs.310.1613325700084; Sun, 14 Feb 2021 10:01:40 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id q20sm22392771wmc.14.2021.02.14.10.01.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:01:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 29/42] linux-user/mips64: Support the n32 ABI for the R5900 Date: Sun, 14 Feb 2021 18:58:59 +0100 Message-Id: <20210214175912.732946-30-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Fredrik Noring Recognise the R5900, which reports itself as MIPS III, as a 64-bit CPU supporting the n32 ABI. Signed-off-by: Fredrik Noring Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-Id: <5bea109f0c140da6a821aa7f9705d4b3717e86dc.1541701393.git.noring@nocrew.org> Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- linux-user/mips64/target_elf.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux-user/mips64/target_elf.h b/linux-user/mips64/target_elf.h index ec55d8542ae..5f2f2df29f7 100644 --- a/linux-user/mips64/target_elf.h +++ b/linux-user/mips64/target_elf.h @@ -12,6 +12,9 @@ static inline const char *cpu_get_model(uint32_t eflags) if ((eflags & EF_MIPS_ARCH) == EF_MIPS_ARCH_64R6) { return "I6400"; } + if ((eflags & EF_MIPS_MACH) == EF_MIPS_MACH_5900) { + return "R5900"; + } return "5KEf"; } #endif From patchwork Sun Feb 14 17:59:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087365 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FF0AC433DB for ; Sun, 14 Feb 2021 18:29:55 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B0F1E64E05 for ; Sun, 14 Feb 2021 18:29:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B0F1E64E05 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:54580 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBM9Z-0006y3-UP for qemu-devel@archiver.kernel.org; Sun, 14 Feb 2021 13:29:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34266) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBLiP-0000fS-1E for qemu-devel@nongnu.org; Sun, 14 Feb 2021 13:01:49 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:33152) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBLiM-0004dg-Fc for qemu-devel@nongnu.org; Sun, 14 Feb 2021 13:01:48 -0500 Received: by mail-wm1-x32b.google.com with SMTP id a16so3371753wmm.0 for ; Sun, 14 Feb 2021 10:01:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=w8KBiau7pxpcFArtHKInYNOJC++ctebYYHvQWPSfPYU=; b=HFdo+YCVCeJ/csdY//CBARPlfmAksJ1IKm2NJZifRVqfWyruj2TJ9kwxnMoTNB9HHi UakyMFbl+3cr1hjhKAF+mcj6W+K4BVGRc95ylg1HAARrzwjujNm5VoYB5pDcgco8j816 cC8svLcDPDPV5jPJ90YO6KhAbb7aBMkLYrJzPKXgpDPvEqWVBGTcbubvu8r3rUPALBQf elkDo9UaZvikzKnFEqzpEXrxrZyc7VQNMJhxdk/l8mPPz6+8/r4aq+bKqFK9cQSGtqQC gSN5jdj36O3L+Msu+G1FI1YdimVQ749/TnRxFkmt9skbLb/401kD4MKWa9eGoIYvnq/N 3hbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=w8KBiau7pxpcFArtHKInYNOJC++ctebYYHvQWPSfPYU=; b=K+124jnFva2YXujJP4Vi/Wrw8knVnutHBsEANiKWyPv9pdqm0E3b7H6NCmNtblfMXQ /0d+g+62BEXLLMeJAlSezEHHzyy8ExcSVy+QaJaQLvm22Mf/Jx/W/Ka9ijRchsn2rOqL eeI6+RskNErd484LqTuixGsOCsmSw7MwpB1WSWgVRtVjSfaUgWwMChA7U1Z/ivJlWMXD hZwQkkUH/C1Q80d/FT9oIH3vPluyqZTDOW7RFkV4Zd6TQxN6lqRkRTvncI424Z3v+rd0 WUHj2F92Mv2ZB1iMwFx0MxQ08BFxSq09DEVLqzMXhA04o32dH165wYms5mHfUfATkrqL XYOQ== X-Gm-Message-State: AOAM5302Bmg9zE51LV2WOJQpJQdasD8scpdCTtXTBasuyx/bIFY3/phH pxeKrKoMyQgS2nH0gkpS5/8AewIlsJQ= X-Google-Smtp-Source: ABdhPJxQJdlN7FbDv8GKNWVb5qfez/7eV3JRoX5jnu0HHpAr4+3zZSIfv7ZprKR5KiwDXqwISbGiHQ== X-Received: by 2002:a05:600c:33a7:: with SMTP id o39mr11131253wmp.10.1613325705039; Sun, 14 Feb 2021 10:01:45 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id z63sm22397684wme.8.2021.02.14.10.01.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:01:44 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 30/42] target/mips: Reintroduce the R5900 CPU Date: Sun, 14 Feb 2021 18:59:00 +0100 Message-Id: <20210214175912.732946-31-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Now that we have the minimum prerequisites to support the R5900 CPU, we can reintroduce it. While we are reverting commit 823f2897bdd ("Disable R5900 support"), we effectively cherry-pick commit ed4f49ba9bb ("target/mips: Define the R5900 CPU"). This reverts commit 823f2897bdd78185f3ba33292a25105ba8bad1b5. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/cpu-defs.c.inc | 59 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index e03b2a998cd..1a73b5409f0 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -411,6 +411,65 @@ const mips_def_t mips_defs[] = .insn_flags = CPU_MIPS32R5, .mmu_type = MMU_TYPE_R4000, }, + { + /* + * The Toshiba TX System RISC TX79 Core Architecture manual + * + * https://wiki.qemu.org/File:C790.pdf + * + * describes the C790 processor that is a follow-up to the R5900. + * There are a few notable differences in that the R5900 FPU + * + * - is not IEEE 754-1985 compliant, + * - does not implement double format, and + * - its machine code is nonstandard. + */ + .name = "R5900", + .CP0_PRid = 0x00002E00, + /* No L2 cache, icache size 32k, dcache size 32k, uncached coherency. */ + .CP0_Config0 = (0x3 << 9) | (0x3 << 6) | (0x2 << CP0C0_K0), + .CP0_Status_rw_bitmask = 0xF4C79C1F, +#ifdef CONFIG_USER_ONLY + /* + * R5900 hardware traps to the Linux kernel for IEEE 754-1985 and LL/SC + * emulation. For user only, QEMU is the kernel, so we emulate the traps + * by simply emulating the instructions directly. + * + * Note: Config1 is only used internally, the R5900 has only Config0. + */ + .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF, + .CP0_LLAddr_shift = 4, + .CP1_fcr0 = (0x38 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr31 = 0, + .CP1_fcr31_rw_bitmask = 0x0183FFFF, +#else + /* + * The R5900 COP1 FPU implements single-precision floating-point + * operations but is not entirely IEEE 754-1985 compatible. In + * particular, + * + * - NaN (not a number) and +/- infinities are not supported; + * - exception mechanisms are not fully supported; + * - denormalized numbers are not supported; + * - rounding towards nearest and +/- infinities are not supported; + * - computed results usually differs in the least significant bit; + * - saturations can differ more than the least significant bit. + * + * Since only rounding towards zero is supported, the two least + * significant bits of FCR31 are hardwired to 01. + * + * FPU emulation is disabled here until it is implemented. + * + * Note: Config1 is only used internally, the R5900 has only Config0. + */ + .CP0_Config1 = (47 << CP0C1_MMU), +#endif /* !CONFIG_USER_ONLY */ + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS3 | INSN_R5900 | ASE_MMI, + .mmu_type = MMU_TYPE_R4000, + }, { /* A generic CPU supporting MIPS32 Release 6 ISA. FIXME: Support IEEE 754-2008 FP. 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id l1sm20040169wmi.48.2021.02.14.10.01.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:01:49 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 31/42] default-configs: Support o32 ABI with R5900 64-bit MIPS CPU Date: Sun, 14 Feb 2021 18:59:01 +0100 Message-Id: <20210214175912.732946-32-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x336.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" MIPS o32 ABI on 64-bit CPUs looks like a ILP32-on-64bit data model, allowing 64-bit arithmetic and data movement instructions. Since this ABI seems to have only ever been used for the development of the PS2 with the "Sony Linux Toolkit for Playstation 2" targetting the R5900 CPU (little-endian), we name this user-mode target 'r5900o32el'. Inspired-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- v2: Rename qemu-mips64o32el -> qemu-r5900o32el (Fredrik) --- docs/user/main.rst | 3 +++ default-configs/targets/r5900o32el-linux-user.mak | 7 +++++++ 2 files changed, 10 insertions(+) create mode 100644 default-configs/targets/r5900o32el-linux-user.mak diff --git a/docs/user/main.rst b/docs/user/main.rst index 8dfe232a3af..405acb8155e 100644 --- a/docs/user/main.rst +++ b/docs/user/main.rst @@ -221,6 +221,9 @@ Other binaries * ``qemu-mipsn32el`` executes 32-bit little endian MIPS binaries (MIPS N32 ABI). + * ``qemu-r5900o32el`` executes 64-bit little endian MIPS R5900 binaries (MIPS + O32 ABI). + - user mode (NiosII) * ``qemu-nios2`` TODO. diff --git a/default-configs/targets/r5900o32el-linux-user.mak b/default-configs/targets/r5900o32el-linux-user.mak new file mode 100644 index 00000000000..ecd57ff949f --- /dev/null +++ b/default-configs/targets/r5900o32el-linux-user.mak @@ -0,0 +1,7 @@ +TARGET_ARCH=mips64 +TARGET_BASE_ARCH=mips +TARGET_ABI_MIPSO32=y +TARGET_ABI32=y +TARGET_SYSTBL_ABI=o32 +TARGET_SYSTBL=../mips/syscall_o32.tbl +TARGET_ALIGNED_ONLY=y From patchwork Sun Feb 14 17:59:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087375 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-21.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3744C433E0 for ; Sun, 14 Feb 2021 18:36:50 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6F23A64DFF for ; Sun, 14 Feb 2021 18:36:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6F23A64DFF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:39452 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBMGH-0004To-LY for qemu-devel@archiver.kernel.org; Sun, 14 Feb 2021 13:36:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34388) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBLid-0000pZ-6c for qemu-devel@nongnu.org; Sun, 14 Feb 2021 13:02:03 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:37199) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBLiZ-0004ez-Tl for qemu-devel@nongnu.org; Sun, 14 Feb 2021 13:02:02 -0500 Received: by mail-wm1-x335.google.com with SMTP id m1so5842222wml.2 for ; Sun, 14 Feb 2021 10:01:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0AWEhq001McQAH/89WIBVS1NfSah7AxRRJlHmFbgoT8=; b=PRa62vJbssrp3t/XYnAjmm+m9WM+b/JWW5S5ciaRMs4Vw5VI4I/eM/eHRBLXpOR4fa bVsmEbN8SxMqnKv2zLAPYqYffDhD14zaoYCbCaxtVsGHuneSsTYgDMuFzlu6dCfred42 /SCIFc+MCXgH50tbQ3cXlCaunVjeuVYj4l2eGpGzKVDjDwlVQzbh/VosfYDrpAs17mgz BD2uY0UlpeOOB04EKC3Ev5pGNizPv0W+YOP8Kk/jAvrJAf/g6eUa5HOrEJ3kToYEKDjw AAA5D/F+Y36Y/X4+XDfv6UqNbpSwQPLM8wvPrvIHiitkyigqi1BXNfuImJnIGDFq8Rvh dZDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=0AWEhq001McQAH/89WIBVS1NfSah7AxRRJlHmFbgoT8=; b=r5BdNx6acUNC+5dc63tmP1UzilByHGpW4s5Me6dFoYkuHqViJGAIBah3THy86sovyf utQGY7rv1cK1ISDI3JuwDVFJSeHcW/TzTZOgkI2DDt+0qQpq6vRGZaV+3FE+Ht5lnoAl 8OOo7TRFQR3iZD+DsilDmfqwlJs6GVUiUo0Xfmeb3lJKjfbNFyT30ntxoJUQa8x7oqmM KXlqHlQJq6GQNGtyuf7gLe6Q8wM94o4hqFyuzV1+U3zzaxxzIva09J6g1RQie4Fx9x/4 YxNzmUJCXEFFmK5MwCGE35O/QuKpm4PViUjvBdC6oLp3Amcqqoj8D/PB3lHPbJa//R3c rgGg== X-Gm-Message-State: AOAM5324FqQtYwy++YXs/jkTaB0o9Qgku8jnb2EvZPaUYbJGTROE/5dX OEx0quHEhrB19LeyU4e8XJrrbr9YGCg= X-Google-Smtp-Source: ABdhPJxW1jlZvwa9CaxhVXwWI/9uEiydyU2itHORIgIsLFlWGYPim7sMBRr84NJPF32hf0Y81lrtPw== X-Received: by 2002:a05:600c:4fcb:: with SMTP id o11mr10893805wmq.88.1613325715239; Sun, 14 Feb 2021 10:01:55 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id w3sm9097130wrr.62.2021.02.14.10.01.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:01:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 32/42] docker: Add gentoo-mipsr5900el-cross image Date: Sun, 14 Feb 2021 18:59:02 +0100 Message-Id: <20210214175912.732946-33-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x335.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Fredrik Noring , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add a Docker image providing cross toolchain for the MIPS R5900 CPU (used on the Sony PS2). This image is based on Gentoo and the toolchain is built using crossdev. Recipe from: https://lists.gnu.org/archive/html/qemu-devel/2018-09/msg03944.html Suggested-by: Fredrik Noring Signed-off-by: Philippe Mathieu-Daudé --- tests/docker/Makefile.include | 3 ++ .../gentoo-mipsr5900el-cross.docker | 35 +++++++++++++++++++ .../crossdev.conf | 5 +++ 3 files changed, 43 insertions(+) create mode 100644 tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker create mode 100644 tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.d/crossdev.conf diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include index 93b29ad823e..3d6306c7728 100644 --- a/tests/docker/Makefile.include +++ b/tests/docker/Makefile.include @@ -146,6 +146,9 @@ docker-image-debian-riscv64-cross: docker-image-debian10 docker-image-debian-s390x-cross: docker-image-debian10 docker-image-debian-sh4-cross: docker-image-debian10 docker-image-debian-sparc64-cross: docker-image-debian10 +docker-image-gentoo-mipsr5900el-cross: EXTRA_FILES:=$(addprefix \ + $(SRC_PATH)/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.d/,\ + crossdev.conf) docker-image-travis: NOUSER=1 diff --git a/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker b/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker new file mode 100644 index 00000000000..88ada20623d --- /dev/null +++ b/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker @@ -0,0 +1,35 @@ +# +# Docker mipsel (r5900) cross-compiler target +# +# Using multi-stage builds, this image requires docker-17.05.0 or later. +# (See: https://github.com/gentoo/gentoo-docker-images) +# +# SPDX-License-Identifier: GPL-2.0-or-later + +# name the portage image +FROM gentoo/portage:20201121 as portage + +# image is based on stage3-amd64 +FROM gentoo/stage3:latest + +# copy the entire portage volume in +COPY --from=portage /var/db/repos/gentoo /var/db/repos/gentoo + +MAINTAINER Philippe Mathieu-Daudé + +# set CROSSDEV_OVERLAY to /usr/local/portage-crossdev +RUN mkdir -p /usr/local/portage-crossdev/{profiles,metadata} && \ + echo 'crossdev' > /usr/local/portage-crossdev/profiles/repo_name && \ + echo 'masters = gentoo' > /usr/local/portage-crossdev/metadata/layout.conf && \ + chown -R portage:portage /usr/local/portage-crossdev && \ + mkdir -p /etc/portage/repos.conf +ADD crossdev.conf /etc/portage/repos.conf/crossdev.conf + +RUN emerge -qv \ + dev-vcs/git ">=dev-libs/glib-2.0" \ + sys-devel/crossdev \ + sys-libs/zlib dev-lang/python + +RUN crossdev -s4 -t mipsr5900el-unknown-linux-gnu + +ENV QEMU_CONFIGURE_OPTS --cross-prefix=mipsr5900el-unknown-linux-gnu- diff --git a/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.d/crossdev.conf b/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.d/crossdev.conf new file mode 100644 index 00000000000..b8fa368c1c3 --- /dev/null +++ b/tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.d/crossdev.conf @@ -0,0 +1,5 @@ +[crossdev] +location = /usr/local/portage-crossdev +priority = 10 +masters = gentoo +auto-sync = no From patchwork Sun Feb 14 17:59:03 2021 Content-Type: text/plain; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id l2sm21551953wmf.15.2021.02.14.10.01.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:01:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 33/42] gitlab-ci: Pass optional EXTRA_FILES when building docker images Date: Sun, 14 Feb 2021 18:59:03 +0100 Message-Id: <20210214175912.732946-34-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Pass EXTRA_FILES to tests/docker/docker.py to use its --extra-files command line option. Signed-off-by: Philippe Mathieu-Daudé --- .gitlab-ci.d/containers.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitlab-ci.d/containers.yml b/.gitlab-ci.d/containers.yml index 90fac85ce46..587bd4ba2e3 100644 --- a/.gitlab-ci.d/containers.yml +++ b/.gitlab-ci.d/containers.yml @@ -16,6 +16,7 @@ - ./tests/docker/docker.py --engine docker build -t "qemu/$NAME" -f "tests/docker/dockerfiles/$NAME.docker" -r $CI_REGISTRY_IMAGE + $(test -n "$EXTRA_FILES" && echo "--extra-files $EXTRA_FILES") - docker tag "qemu/$NAME" "$TAG" - docker push "$TAG" after_script: From patchwork Sun Feb 14 17:59:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087385 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 762D5C433E0 for ; Sun, 14 Feb 2021 18:44:13 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1311064E10 for ; Sun, 14 Feb 2021 18:44:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1311064E10 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:54364 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBMNQ-0002ay-1B for qemu-devel@archiver.kernel.org; Sun, 14 Feb 2021 13:44:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34434) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBLih-0000rs-QY for qemu-devel@nongnu.org; Sun, 14 Feb 2021 13:02:12 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:33165) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBLig-0004ff-FS for qemu-devel@nongnu.org; Sun, 14 Feb 2021 13:02:07 -0500 Received: by mail-wr1-x436.google.com with SMTP id 7so6167303wrz.0 for ; Sun, 14 Feb 2021 10:02:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Twme+gWXDR778jC4YebnrwyqPShuK2VSIsTo2Civx54=; b=VwmE/3r1M2iBkyrkmvuLhDibJN6OXHSVINP8i7r9044dgZHmXhQNj3f9wfPe+AWs7d RXoD2pRw5RTUn+INffLlrk42WGf3wcd/A+knkNVHsP4Kj6pLojzJ6o5ZLl6NRqoDMqHD rU74d/aUemUOUhXzQwtVf3xvD9SENZcOO/2h12CRYPdHq+rOc2aqkoRP+N1fh2aqEBd4 ECmeT4aKXXGZlFVwwb79pncqrDgdNEIE3whWyRT2XMV2IfYSRdXjXegQLdhiFqNEOfBD z+yk4a1qkIfJn/9DOIPEagXqc7/0J5Lr8t7/4AAijcW4h1atsb7Bdiu6MyUZk8Ldd2fH 7zxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Twme+gWXDR778jC4YebnrwyqPShuK2VSIsTo2Civx54=; b=Di21yqM9UiXZknLIbUdHVWhW3/QEqKS2hd+u4q1vzIb8au7FJ4yGuBJr2Ckm/x3Pmf i4pnyAeWTeuWjnmbT4jah9nAtUQGWvsBy6weCa7Z7quSLxDJZRWXdNhzFFAPaLB7sADp DVWZZpyrNUhRT/1lKi1ZNzEZkAYstFE8ynSJ1XB21kLZcx5rtTsDva98IfkpIWIPNrIv YX1Xwlbrr6U0uuPvIU82IDKmBAwGMxf+ZGCgwgxNPuyH915J53TYCMNgembI57QYsOt7 ObsrL+qirUePd3Y8eXblBQJmScePYm4HCgYcdcACA+ztxVkF0tDNI643EU322Iac4Ue2 TuIA== X-Gm-Message-State: AOAM532EQFQRpmrAVJne7+u8LQnNURw6UlNWIvFOFndkGzYzvwwNGPEt xWW8MJJ19cpQHuBG8rvwoy1/knFzQ/E= X-Google-Smtp-Source: ABdhPJwrap/KMyoG7tgmtAtQVe2cC4NvXaIEDYyGbRp7pLiEY7sC5J9RuoVnCD3Tvstr9jpudWx9Gg== X-Received: by 2002:adf:e98d:: with SMTP id h13mr15198324wrm.246.1613325725056; Sun, 14 Feb 2021 10:02:05 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id r124sm22218427wmr.16.2021.02.14.10.02.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:02:04 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 34/42] gitlab-ci: Build MIPS R5900 cross-toolchain (Gentoo based) Date: Sun, 14 Feb 2021 18:59:04 +0100 Message-Id: <20210214175912.732946-35-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add a job to build the Gentoo based MIPS R5900 cross-toolchain image. Signed-off-by: Philippe Mathieu-Daudé --- .gitlab-ci.d/containers.yml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/.gitlab-ci.d/containers.yml b/.gitlab-ci.d/containers.yml index 587bd4ba2e3..f441e608446 100644 --- a/.gitlab-ci.d/containers.yml +++ b/.gitlab-ci.d/containers.yml @@ -152,6 +152,13 @@ mipsel-debian-cross-container: variables: NAME: debian-mipsel-cross +mipsr5900el-gentoo-cross-container: + <<: *container_job_definition + variables: + NAME: gentoo-mipsr5900el-cross + EXTRA_FILES: tests/docker/dockerfiles/gentoo-mipsr5900el-cross.docker.d/crossdev.conf + timeout: 1h 30m + powerpc-debian-cross-container: <<: *container_job_definition stage: containers-layer2 From patchwork Sun Feb 14 17:59:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087371 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F33DC433DB for ; Sun, 14 Feb 2021 18:34:30 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0B59B64E05 for ; Sun, 14 Feb 2021 18:34:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0B59B64E05 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:34974 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBME1-0002Th-4s for qemu-devel@archiver.kernel.org; Sun, 14 Feb 2021 13:34:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34514) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBLip-0000zY-RU for qemu-devel@nongnu.org; Sun, 14 Feb 2021 13:02:15 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:34646) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBLin-0004g3-0d for qemu-devel@nongnu.org; Sun, 14 Feb 2021 13:02:15 -0500 Received: by mail-wr1-x42d.google.com with SMTP id n4so3122340wrx.1 for ; Sun, 14 Feb 2021 10:02:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UDYGyb10B7bTg3SKlpM1Yb6/DaGZTJ05b5VgebX2EjE=; b=sySQiFU9wJDs3qW27aidVdde/yZIOxFLR0vgsC6CfafJpn3FYjMYSg+Fi/7HgjSuqw Tw1uIxUJ+s47saCTwZpi4NgASB1kvO0d5OU7njoMz/s+f2a20MVJ28smOyGoGZQDn5N4 Lg1jsB9hbd3i2i0Ec+FoLoAbEGjn7b8BDnSD7T9m3/HoRyW8Hy7tpXVYPjjqzXWXchEr k0NJ3nkYOwsgGqUYMsxxoQL1MCfqY2CnrknoMGeIa82TwMx41u9NJlNBVbxe3W+4REqE r0FFr61kIRjMkDvEH2aeGldbyX9yv+oqsjuUisKAqgW2L0JB18oOqEkZxx+3OJLZhk59 dLBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=UDYGyb10B7bTg3SKlpM1Yb6/DaGZTJ05b5VgebX2EjE=; b=AdEGBogj2wG4gzjaASNWls1W1/VjHz/qsY+Ec3JknohypJpmGZwbbHk47mQMHCt1Yn xcNvjf75Sv51kp8+qqF2GygVk0wBqdlCQx2B6/O6TIHE4pw6U0JR+bAEHInpJDzR+REV dGYYDUnGImvPLuD1bCw7z6cuB5qzOQkAb2HakjOBtEBhzwP1i9LCNz65u6M0lXRw7XvI iLK/rIJ6E5WBPlsjDdQClBz5YhJpRYeGW5MnXxZy62QD6eF6+B+R3IRAyNYJZMKKcLwZ Io/hgIP+AXXhRYeCVAzvMYQ/9KuhkT4D6SalXEvxINtc2utPrTe9jBl4m+6/6EUc3O6t Plvw== X-Gm-Message-State: AOAM5334c8WWHC81+tW9jeKP9imlbv++m/tgjyHHfgEU9q/XKNHR/KLG x3PDdDv3fnZQDuOx6FPKf23LfmOeZwU= X-Google-Smtp-Source: ABdhPJwLnSi+M/p2dMnLjHgfbd8pf6kJDrmKWtotRdHD/DVKrb4Y9zq/3qFrNfedXPrNVnFFwPOdMQ== X-Received: by 2002:adf:82b3:: with SMTP id 48mr14549616wrc.22.1613325730024; Sun, 14 Feb 2021 10:02:10 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id s14sm1972355wmj.23.2021.02.14.10.02.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:02:09 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 35/42] tests/tcg: Add MIPS R5900 to arches filter Date: Sun, 14 Feb 2021 18:59:05 +0100 Message-Id: <20210214175912.732946-36-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Philippe Mathieu-Daudé --- tests/tcg/configure.sh | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index e1b70e25f23..64796ee11fc 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -57,6 +57,8 @@ fi : $(cross_cc_mips64="mips64-linux-gnuabi64-gcc") : $(cross_cc_mipsel="mipsel-linux-gnu-gcc") : $(cross_cc_mips="mips-linux-gnu-gcc") +: $(cross_cc_r5900o32el="mipsr5900el-unknown-linux-gnu-gcc") +: ${cross_cc_cflags_r5900o32el="-mabi=32 -march=r5900"} : ${cross_cc_ppc="powerpc-linux-gnu-gcc"} : ${cross_cc_cflags_ppc="-m32"} : ${cross_cc_ppc64="powerpc64-linux-gnu-gcc"} @@ -79,7 +81,7 @@ for target in $target_list; do aarch64|aarch64_be) arches="aarch64 arm" ;; - mips*) + mips*|r5900o32el*) arches=mips ;; ppc*) @@ -150,6 +152,10 @@ for target in $target_list; do container_image=debian-mips-cross container_cross_cc=mips-linux-gnu-gcc ;; + r5900o32el-*) + container_image=gentoo-mipsr5900el-cross + container_cross_cc=mipsr5900el-unknown-linux-gnu-gcc + ;; ppc-*|ppc64abi32-*) container_image=debian-powerpc-cross container_cross_cc=powerpc-linux-gnu-gcc From patchwork Sun Feb 14 17:59:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087361 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9AC0C433DB for ; Sun, 14 Feb 2021 18:28:23 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 51EC264DD8 for ; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id k11sm20150228wrl.84.2021.02.14.10.02.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:02:14 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 36/42] tests/tcg/mips: Test user mode DMULT for the R5900 Date: Sun, 14 Feb 2021 18:59:06 +0100 Message-Id: <20210214175912.732946-37-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Fredrik Noring The R5900 reports itself as MIPS III but does not implement DMULT. Verify that DMULT is emulated properly in user mode by multiplying two 64-bit numbers to produce a 128-bit number. Signed-off-by: Fredrik Noring Message-Id: Signed-off-by: Philippe Mathieu-Daudé --- tests/tcg/mips/mipsn32r5900/dmult.c | 40 ++++++++++++++++++++++++++++ tests/tcg/mips/mipsn32r5900/Makefile | 25 +++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 tests/tcg/mips/mipsn32r5900/dmult.c create mode 100644 tests/tcg/mips/mipsn32r5900/Makefile diff --git a/tests/tcg/mips/mipsn32r5900/dmult.c b/tests/tcg/mips/mipsn32r5900/dmult.c new file mode 100644 index 00000000000..2827ab5358f --- /dev/null +++ b/tests/tcg/mips/mipsn32r5900/dmult.c @@ -0,0 +1,40 @@ +/* + * Test DMULT. + */ + +#include +#include +#include + +struct hi_lo { int64_t hi; uint64_t lo; }; + +static struct hi_lo dmult(int64_t rs, int64_t rt) +{ + int64_t hi; + uint64_t lo; + + /* + * The R5900 reports itself as MIPS III but does not implement DMULT. + * Verify that DMULT is emulated properly in user mode. + */ + __asm__ __volatile__ ( + " .set mips3\n" + " dmult %2, %3\n" + " mfhi %0\n" + " mflo %1\n" + : "=r" (hi), "=r" (lo) + : "r" (rs), "r" (rt)); + + return (struct hi_lo) { .hi = hi, .lo = lo }; +} + +int main() +{ + /* Verify that multiplying two 64-bit numbers yields a 128-bit number. */ + struct hi_lo r = dmult(2760727302517, 5665449960167); + + assert(r.hi == 847887); + assert(r.lo == 7893651516417804947); + + return 0; +} diff --git a/tests/tcg/mips/mipsn32r5900/Makefile b/tests/tcg/mips/mipsn32r5900/Makefile new file mode 100644 index 00000000000..7dd16723fea --- /dev/null +++ b/tests/tcg/mips/mipsn32r5900/Makefile @@ -0,0 +1,25 @@ +-include ../../config-host.mak + +CROSS=mips64r5900el-unknown-linux-gnu- + +SIM=qemu-mipsn32el +SIM_FLAGS=-cpu R5900 + +CC = $(CROSS)gcc +CFLAGS = -Wall -mabi=n32 -march=r5900 -static + +TESTCASES = dmult.tst + +all: $(TESTCASES) + +%.tst: %.c + $(CC) $(CFLAGS) $< -o $@ + +check: $(TESTCASES) + @for case in $(TESTCASES); do \ + echo $(SIM) $(SIM_FLAGS) ./$$case;\ + $(SIM) $(SIM_FLAGS) ./$$case; \ + done + +clean: + $(RM) -rf $(TESTCASES) From patchwork Sun Feb 14 17:59:07 2021 Content-Type: text/plain; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id q2sm14134539wrx.79.2021.02.14.10.02.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:02:19 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 37/42] gitlab-ci: Add job to test the MIPS r5900o32el target Date: Sun, 14 Feb 2021 18:59:07 +0100 Message-Id: <20210214175912.732946-38-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add a job to build the MIPS r5900o32el (linux-user) target and run the TCG tests. Signed-off-by: Philippe Mathieu-Daudé --- .gitlab-ci.yml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 28a83afb914..7d7559416e3 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -622,6 +622,18 @@ build-without-default-features: --target-list-exclude=arm-softmmu,i386-softmmu,mipsel-softmmu,mips64-softmmu,ppc-softmmu MAKE_CHECK_ARGS: check-unit +build-r5900-user: + <<: *native_build_job_definition + variables: + IMAGE: fedora + CONFIGURE_ARGS: --disable-tools --disable-docs --disable-blobs --enable-debug-tcg + TARGETS: r5900o32el-linux-user + MAKE_CHECK_ARGS: run-tcg-tests-r5900o32el-linux-user + artifacts: + expire_in: 2 days + paths: + - build + check-patch: stage: build image: $CI_REGISTRY_IMAGE/qemu/centos8:latest From patchwork Sun Feb 14 17:59:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087367 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8E53C433E0 for ; Sun, 14 Feb 2021 18:32:45 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3D23164E05 for ; Sun, 14 Feb 2021 18:32:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3D23164E05 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:58692 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBMCK-0000UI-14 for qemu-devel@archiver.kernel.org; Sun, 14 Feb 2021 13:32:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34588) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBLj2-0001Hw-EE for qemu-devel@nongnu.org; Sun, 14 Feb 2021 13:02:28 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:37193) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBLj0-0004hT-UU for qemu-devel@nongnu.org; Sun, 14 Feb 2021 13:02:28 -0500 Received: by mail-wm1-x32c.google.com with SMTP id m1so5842922wml.2 for ; Sun, 14 Feb 2021 10:02:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tAIy7FUQhIbkzhnlwKrYWaoIdkoCcq/sJqrD/3OuL28=; b=L7kU2i88pK4c1X1MYEzU2BgcBam0+Ky3HFvwlyl47piV557P6LyLhIN0RhcfCPrsVN zz2FqWSQhyfjx56vN0pzKgmez3hZdemnKo7J34quLLvH8GnUf7sYHlGNm2M1/u6qUoUk yvWEkuYKxb2yneZ3LSDby2AojTi1aDBV9f6VQK+A6WZ0ee7o3NOphe9L7ZxO/KuT5IgC WIXWiB42HAjyGMJ/VV+fdU7mvgU3ijIa3bTYxpOGfbs9lkmIjKhjtErgRqSzpEsl6oSr 92GdaeYOUsY1j4msrpGre8gz/sXj+L79lVSC6qWrNAwpwdZ3vTDiAUCCe7Hiiug40siy yghg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=tAIy7FUQhIbkzhnlwKrYWaoIdkoCcq/sJqrD/3OuL28=; b=Z9+f4XA9rRiD2aiEtPBxNk4+KKIloIbaYazKhRGr9STA9FlY2d4WgRYexW6hpn69Aj +lOwyAM9nZKAC+J9O4CTeUb3XEaHH5BKbo6tCtaqPwhJXFS4b1PtNta3rk/r85Uz5Kzl 0OLybhxrUHaH3M1QOgkkxDEi0b7n5jDy05fkqHeT602QOlFj3TFoLOZUYwRaCE/BPYqE CejjzxIO1vNwtXTP5VdtIf3f8eaUkOc9OfeH6ewsoGe7p0i2+eIJjwkacdPDjHNG5HI5 Te2l40IdCzmEhye7VQHOqt3YwmGkdpcRhOTzjppgSVRJMw8o4rcRnFJBUnwKDy16XUvT JazQ== X-Gm-Message-State: AOAM533OXqGZ3WeVwWulXVQVEKnnuy/1EOSVrM81igmSGd05UiPxVcT9 8LZsH3tj8VpcbV7glKPVrW67fVERkak= X-Google-Smtp-Source: ABdhPJwhDsBPJJSpjDEErKfL4N7mN8WOG2ORpQYzFWPtVwOowa3xwqF9LM0C6J27pI5wfsMV36v0AA== X-Received: by 2002:a1c:de08:: with SMTP id v8mr11126032wmg.143.1613325745249; Sun, 14 Feb 2021 10:02:25 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id v11sm20863355wrr.3.2021.02.14.10.02.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:02:24 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 38/42] tests/acceptance: Extract QemuBaseTest from Test Date: Sun, 14 Feb 2021 18:59:08 +0100 Message-Id: <20210214175912.732946-39-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , Cleber Rosa , Thomas Huth , =?utf-8?q?A?= =?utf-8?q?lex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The Avocado Test::fetch_asset() is handy to download artifacts before running tests. The current class is named Test but only tests system emulation. As we want to test user emulation, refactor the common code as QemuBaseTest. Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/avocado_qemu/__init__.py | 35 +++++++++++++---------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/tests/acceptance/avocado_qemu/__init__.py b/tests/acceptance/avocado_qemu/__init__.py index bf54e419da2..31b7064c0e5 100644 --- a/tests/acceptance/avocado_qemu/__init__.py +++ b/tests/acceptance/avocado_qemu/__init__.py @@ -145,7 +145,7 @@ def exec_command_and_wait_for_pattern(test, command, """ _console_interaction(test, success_message, failure_message, command + '\r') -class Test(avocado.Test): +class QemuBaseTest(avocado.Test): def _get_unique_tag_val(self, tag_name): """ Gets a tag value, if unique for a key @@ -156,8 +156,6 @@ def _get_unique_tag_val(self, tag_name): return None def setUp(self): - self._vms = {} - self.arch = self.params.get('arch', default=self._get_unique_tag_val('arch')) @@ -170,6 +168,25 @@ def setUp(self): if self.qemu_bin is None: self.cancel("No QEMU binary defined or found in the build tree") + + def fetch_asset(self, name, + asset_hash=None, algorithm=None, + locations=None, expire=None, + find_only=False, cancel_on_missing=True): + return super(QemuBaseTest, self).fetch_asset(name, + asset_hash=asset_hash, + algorithm=algorithm, + locations=locations, + expire=expire, + find_only=find_only, + cancel_on_missing=cancel_on_missing) + +# a.k.a. QemuSystemTest for system emulation... +class Test(QemuBaseTest): + def setUp(self): + self._vms = {} + super(Test, self).setUp() + def _new_vm(self, *args): self._sd = tempfile.TemporaryDirectory(prefix="avo_qemu_sock_") vm = QEMUMachine(self.qemu_bin, sock_dir=self._sd.name) @@ -194,15 +211,3 @@ def tearDown(self): for vm in self._vms.values(): vm.shutdown() self._sd = None - - def fetch_asset(self, name, - asset_hash=None, algorithm=None, - locations=None, expire=None, - find_only=False, cancel_on_missing=True): - return super(Test, self).fetch_asset(name, - asset_hash=asset_hash, - algorithm=algorithm, - locations=locations, - expire=expire, - find_only=find_only, - cancel_on_missing=cancel_on_missing) From patchwork Sun Feb 14 17:59:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087377 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D831FC433E0 for ; Sun, 14 Feb 2021 18:38:20 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6497464DFF for ; Sun, 14 Feb 2021 18:38:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6497464DFF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:43784 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBMHj-0006NI-Fc for qemu-devel@archiver.kernel.org; Sun, 14 Feb 2021 13:38:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34610) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBLjA-0001P7-H3 for qemu-devel@nongnu.org; Sun, 14 Feb 2021 13:02:37 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:42291) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBLj5-0004hq-RB for qemu-devel@nongnu.org; Sun, 14 Feb 2021 13:02:33 -0500 Received: by mail-wr1-x42e.google.com with SMTP id r21so6084038wrr.9 for ; Sun, 14 Feb 2021 10:02:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xbl9/61wM37nBJWaz7/wAXPCJcp3ey0kqtBTl5rgBR4=; b=qGzTr9/PvCuaprwZhrz3F1W4/R4yIE/+GKJtiZD8Y0jeV5DjPHVdPLXMTusB/oiOfl q/FnShDy481dTAftmHSQq3xx9BCgdGge48Ox5TjC1e+1hWdpZaWqTrXCdx8DIrCMMTNG iohrcjua+bm7zkAYSiaBtKEoytBxfg42Ve7w9M+rU3y6XfS2IkIhtYAoupZZDQWK/NwZ +zmahm8vahEDZOGQnbqaKZMdCcEhAXqhBnnUq1JCSbp3mUAZhAViuNfLhY5HH17OvxzI eHn4U6qVvjmwXFQjdneRmmzyUZb5dEtp3PbBP+89AH1ksIMtmeFJ5vKojLnffRFLCaT/ PK+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=xbl9/61wM37nBJWaz7/wAXPCJcp3ey0kqtBTl5rgBR4=; b=VAgHf30vuFiYtEimBJtiqLa7U8HEXeCclg7/GTV57RZMouu3BXqK5/AuMHcJ7hQdQu 5YwGuE/eM0t1o8om2e9SbMUHbUTFVjXp6Quh78AtQeB/ieL4IkjOcQftaxt5JLKeIVtS TdyaJTAkbrDRF7P0vh2ePW/KihHwuEaraMsaRsXagUNo6s4zw8Xcvzehjky8x2XU3Hhu GByg5qSyVMhpOm5dYyihjOaijexBb9UT/uxwK8S93mF+3f58mXuhEBAATJMyvpbOlcff wI9JTSLUO77grvloNy7eVMggrDHT6fvdQzQOy0EPmD/uiv6jFyopgWxSFqcCYkkNShC1 eaJQ== X-Gm-Message-State: AOAM530LFsaY/I12bQDavwjBZMb2KWU3rlhhW4LZHNKhx1bp2JPsUxNi w8x86v5w9+u5BIg6lNkhsoU01AsW6mk= X-Google-Smtp-Source: ABdhPJwXS2FCGdhgqLXj/yRSvfRTIPhHY70AMqN/giruUifvEZc58fbjyMGJzRAKJeK8aE3JwP2rTw== X-Received: by 2002:a05:6000:143:: with SMTP id r3mr14787333wrx.357.1613325750310; Sun, 14 Feb 2021 10:02:30 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id u4sm19386083wrr.37.2021.02.14.10.02.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:02:29 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 39/42] tests/acceptance: Make pick_default_qemu_bin() more generic Date: Sun, 14 Feb 2021 18:59:09 +0100 Message-Id: <20210214175912.732946-40-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , Cleber Rosa , Thomas Huth , =?utf-8?q?A?= =?utf-8?q?lex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Make pick_default_qemu_bin() generic to find qemu-system or qemu-user binaries. Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/avocado_qemu/__init__.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/acceptance/avocado_qemu/__init__.py b/tests/acceptance/avocado_qemu/__init__.py index 31b7064c0e5..e0067abca61 100644 --- a/tests/acceptance/avocado_qemu/__init__.py +++ b/tests/acceptance/avocado_qemu/__init__.py @@ -38,7 +38,7 @@ def is_readable_executable_file(path): return os.path.isfile(path) and os.access(path, os.R_OK | os.X_OK) -def pick_default_qemu_bin(arch=None): +def pick_default_qemu_bin(bin_fmt, arch=None): """ Picks the path of a QEMU binary, starting either in the current working directory or in the source tree root directory. @@ -57,7 +57,7 @@ def pick_default_qemu_bin(arch=None): # qemu binary path does not match arch for powerpc, handle it if 'ppc64le' in arch: arch = 'ppc64' - qemu_bin_relative_path = "./qemu-system-%s" % arch + qemu_bin_relative_path = os.path.join(".", bin_fmt % arch) if is_readable_executable_file(qemu_bin_relative_path): return qemu_bin_relative_path @@ -155,14 +155,14 @@ def _get_unique_tag_val(self, tag_name): return vals.pop() return None - def setUp(self): + def setUp(self, bin_fmt): self.arch = self.params.get('arch', default=self._get_unique_tag_val('arch')) self.machine = self.params.get('machine', default=self._get_unique_tag_val('machine')) - default_qemu_bin = pick_default_qemu_bin(arch=self.arch) + default_qemu_bin = pick_default_qemu_bin(bin_fmt, arch=self.arch) self.qemu_bin = self.params.get('qemu_bin', default=default_qemu_bin) if self.qemu_bin is None: @@ -185,7 +185,7 @@ def fetch_asset(self, name, class Test(QemuBaseTest): def setUp(self): self._vms = {} - super(Test, self).setUp() + super(Test, self).setUp("qemu-system-%s") def _new_vm(self, *args): self._sd = tempfile.TemporaryDirectory(prefix="avo_qemu_sock_") From patchwork Sun Feb 14 17:59:10 2021 Content-Type: text/plain; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id n186sm4728191wmn.22.2021.02.14.10.02.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:02:34 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 40/42] tests/acceptance: Introduce QemuUserTest base class Date: Sun, 14 Feb 2021 18:59:10 +0100 Message-Id: <20210214175912.732946-41-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , Cleber Rosa , Thomas Huth , =?utf-8?q?A?= =?utf-8?q?lex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Similarly to the 'System' Test base class with methods for testing system emulation, the QemuUserTest class contains methods useful to test user-mode emulation. Signed-off-by: Philippe Mathieu-Daudé --- tests/acceptance/avocado_qemu/__init__.py | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/tests/acceptance/avocado_qemu/__init__.py b/tests/acceptance/avocado_qemu/__init__.py index e0067abca61..a293d228140 100644 --- a/tests/acceptance/avocado_qemu/__init__.py +++ b/tests/acceptance/avocado_qemu/__init__.py @@ -15,6 +15,7 @@ import tempfile import avocado +from avocado.utils import process #: The QEMU build root directory. It may also be the source directory #: if building from the source dir, but it's safer to use BUILD_DIR for @@ -211,3 +212,17 @@ def tearDown(self): for vm in self._vms.values(): vm.shutdown() self._sd = None + +class QemuUserTest(QemuBaseTest): + def setUp(self): + self._ldpath = [] + super(QemuUserTest, self).setUp("qemu-%s") + + def add_ldpath(self, ldpath): + self._ldpath += [os.path.abspath(ldpath)] + + def run(self, bin_path, args=[]): + qemu_args = " ".join(["-L %s" % ldpath for ldpath in self._ldpath]) + bin_args = " ".join(args) + return process.run("%s %s %s %s" % (self.qemu_bin, qemu_args, + bin_path, bin_args)) From patchwork Sun Feb 14 17:59:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12087387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3174AC433DB for ; Sun, 14 Feb 2021 18:46:01 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D816264E10 for ; Sun, 14 Feb 2021 18:46:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D816264E10 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:56840 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lBMP9-0003e8-FR for qemu-devel@archiver.kernel.org; Sun, 14 Feb 2021 13:45:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34672) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lBLjH-0001ge-EZ for qemu-devel@nongnu.org; Sun, 14 Feb 2021 13:02:43 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:47005) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lBLjF-0004ji-TP for qemu-devel@nongnu.org; Sun, 14 Feb 2021 13:02:43 -0500 Received: by mail-wr1-x435.google.com with SMTP id t15so6054380wrx.13 for ; Sun, 14 Feb 2021 10:02:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gZSzBZ5cwzLEMl1m4ueqOFOq71K8++arIDvi8B+RYEY=; b=ZJmI9sTO3d9Js+k0LaDPnWAlUubc7e4so0JyvQgsOxqnyDlcm/O/BqNAdy5G3maddK d74hzd6EMrVyrClBRKwEjCgtQsFbNguvDoJqMZGgRYaedWzrGWpfioej3s1L7a1ZKOuX vp3E6HaIZTYkWyNvofEU8xxPnUpFb/5BsMCiBjCg91LzvD+CZWWQlyLzLGMOmo2J/Kgj PnGN07o/uUjq0qAblADcwrg4PF3i1SBlqxXFKB7q/14WSpoyjUtquqYhtG/aK/WhaaxM EB5xuvzDeWNb1GGLXI0+vWOGxiv2Qo2l5ET2XH66JGuVAXfKy9xfCbUDkA5Ee7dIGzit PjeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=gZSzBZ5cwzLEMl1m4ueqOFOq71K8++arIDvi8B+RYEY=; b=WS48WTAiLzymPnjJxFiBEhoXY77XsQX36B/KUE10wdS9+cKXgHhNuf+HHIy5Pqgyv7 fnYmf4aM2DCT44p7XlmrKHHNc8Ioim0quf10iuNOr9RDIkByFrcTvm0tNc5nFzdP4bMR TE2m26OIA7yWE2JBKdtCKJHJJW+Eg48GW/yG9uRnfdl5/Ae8ayyGH9/7U/9c/jU0rnZQ Duz4sn7ydYU2pnU7+jiYYL3VvUBpN9DkED7Ikqr4G2x/LjnxMGuuF3HsaLYm/Dhqxzsa MqN4Qsi+dpaMUpAnbH0zB8IztmrXEsio4uCooMFyrmpYD40x4e7rIDYQQ5uZc3itijg3 qXfg== X-Gm-Message-State: AOAM530+msZU71xev1kSI6/kb7keOYeusIhguVB0IALEtRq4kbrrdqiH +Plccr4OhccNI5uLvFCiU/gm5XUELN4= X-Google-Smtp-Source: ABdhPJxGGozT7vVqFV87EM4Q6sd89GQ48EFSrEmraPjq4VV4K0SdCNJoTC2ZI1/Hj7qd9j+GycaIfA== X-Received: by 2002:a5d:5910:: with SMTP id v16mr4258464wrd.304.1613325760376; Sun, 14 Feb 2021 10:02:40 -0800 (PST) Received: from localhost.localdomain (68.red-83-57-175.dynamicip.rima-tde.net. [83.57.175.68]) by smtp.gmail.com with ESMTPSA id x18sm8701695wrs.16.2021.02.14.10.02.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:02:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 41/42] tests/acceptance: Test R5900 CPU with BusyBox from Sony PS2 Date: Sun, 14 Feb 2021 18:59:11 +0100 Message-Id: <20210214175912.732946-42-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , Cleber Rosa , Thomas Huth , =?utf-8?q?A?= =?utf-8?q?lex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Test BusyBox on the R5900 CPU with 2 different binaries: - o32 32-bit (statically linked) - o32 64-bit (dynamically linked, uses multimedia instructions) Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + tests/acceptance/mips_r5900_ps2.py | 69 ++++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) create mode 100644 tests/acceptance/mips_r5900_ps2.py diff --git a/MAINTAINERS b/MAINTAINERS index de5fe1c65f5..1a23f471b0e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -242,6 +242,7 @@ F: include/hw/mips/ F: include/hw/misc/mips_* F: include/hw/timer/mips_gictimer.h F: tests/tcg/mips/ +F: tests/acceptance/mips_r5900_ps2.py K: ^Subject:.*(?i)mips MIPS TCG CPUs (nanoMIPS ISA) diff --git a/tests/acceptance/mips_r5900_ps2.py b/tests/acceptance/mips_r5900_ps2.py new file mode 100644 index 00000000000..ff73f994e59 --- /dev/null +++ b/tests/acceptance/mips_r5900_ps2.py @@ -0,0 +1,69 @@ +# Test the MIPS R5900 CPU +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: GPL-2.0-or-later + +import os +import lzma +import shutil + +from avocado import skipUnless + +from avocado.utils import archive +from avocado_qemu import QemuUserTest + +class R5900(QemuUserTest): + + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code') + def test_gentoo_busybox_32bit(self): + """ + :avocado: tags=arch:r5900o32el + :avocado: tags=linux_user + :avocado: tags=quick + """ + busybox_url = ('https://raw.githubusercontent.com/philmd' + '/qemu-testing-blob/bf6a300cf0bc56e4a2c5b' + '/mips/ps2/busybox-gentoo-v1.32.0.xz') + busybox_hash = 'd2a0abc2c7c3adb6b2fdd63356be78bc5e99f324' + busybox_path_xz = self.fetch_asset(busybox_url, asset_hash=busybox_hash) + + busybox_path = os.path.join(self.workdir, "busybox") + with lzma.open(busybox_path_xz, 'rb') as f_in: + with open(busybox_path, 'wb') as f_out: + shutil.copyfileobj(f_in, f_out) + os.chmod(busybox_path, 0o755) + + res = self.run(busybox_path) + ver = 'BusyBox v1.32.0 (2021-02-09 15:13:23 -00) multi-call binary' + self.assertIn(ver, res.stdout_text) + + res = self.run(busybox_path, ['uname', '-a']) + unm = 'mips64 mips64 mips64 GNU/Linux' + self.assertIn(unm, res.stdout_text) + + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code') + def test_ps2_busybox_64bit(self): + """ + :avocado: tags=arch:r5900o32el + :avocado: tags=linux_user + :avocado: tags=quick + """ + rootfs_url = ('https://raw.githubusercontent.com/philmd' + '/qemu-testing-blob/bf6a300cf0bc56e4a2c5b/mips' + '/ps2/ps2linux_live_v5_pal_netsurf_usb_busybox.tar.gz') + rootfs_hash = '9aa8fdd974cd3332c7167bceb6dd7137853d3a10' + rootfs_path_tgz = self.fetch_asset(rootfs_url, asset_hash=rootfs_hash) + + archive.extract(rootfs_path_tgz, self.workdir) + busybox_path = self.workdir + "/bin/busybox" + + self.add_ldpath(self.workdir) + + res = self.run(busybox_path) + ver = 'BusyBox v0.60.5 (2010.06.06-16:16+0000) multi-call binary' + self.assertIn(ver, res.stderr_text) + + res = self.run(busybox_path, ['uname', '-a']) + unm = 'mips64 unknown' + self.assertIn(unm, res.stdout_text) From patchwork Sun Feb 14 17:59:12 2021 Content-Type: text/plain; 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[83.57.175.68]) by smtp.gmail.com with ESMTPSA id y15sm20280181wrm.93.2021.02.14.10.02.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Feb 2021 10:02:44 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 42/42] gitlab-ci: Add job to run integration tests for the r5900o32el target Date: Sun, 14 Feb 2021 18:59:12 +0100 Message-Id: <20210214175912.732946-43-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210214175912.732946-1-f4bug@amsat.org> References: <20210214175912.732946-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fredrik Noring , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Aleksandar Rikalo , Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , Thomas Huth , =?utf-8?q?Alex_Benn=C3=A9e?= , Aurelien Jarno , "Maciej W. Rozycki" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Run some integration tests for the r5900o32el-linux-user target. Signed-off-by: Philippe Mathieu-Daudé --- .gitlab-ci.yml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 7d7559416e3..ba2c9ac0b4d 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -634,6 +634,16 @@ build-r5900-user: paths: - build +acceptance-r5900-user: + <<: *native_test_job_definition + needs: + - job: build-r5900-user + artifacts: true + variables: + IMAGE: fedora + MAKE_CHECK_ARGS: check-acceptance + <<: *acceptance_definition + check-patch: stage: build image: $CI_REGISTRY_IMAGE/qemu/centos8:latest