From patchwork Wed Feb 17 00:13:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Jiang X-Patchwork-Id: 12090737 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64B70C433DB for ; Wed, 17 Feb 2021 00:15:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 315A764EB2 for ; Wed, 17 Feb 2021 00:15:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231367AbhBQAOx (ORCPT ); Tue, 16 Feb 2021 19:14:53 -0500 Received: from mga11.intel.com ([192.55.52.93]:5423 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231352AbhBQAOg (ORCPT ); Tue, 16 Feb 2021 19:14:36 -0500 IronPort-SDR: +GgmclksLsWa66QlgloLkzR7Ly1uGdIs5P8Or57BE/QGgVL7tlNvtJ6oFPbgsvf8nuLjQenTyO 3uY6FqXu4hhw== X-IronPort-AV: E=McAfee;i="6000,8403,9897"; a="179551229" X-IronPort-AV: E=Sophos;i="5.81,184,1610438400"; d="scan'208";a="179551229" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2021 16:13:53 -0800 IronPort-SDR: ruci5gFoBqykUi3stcpY0xjmjKzL3il1sbCL6HHr2Pdf+Qy/BC3zmue6Jc5aj2RJEtNOXB9QAN 0TKcU7L7FY8w== X-IronPort-AV: E=Sophos;i="5.81,184,1610438400"; d="scan'208";a="399728535" Received: from djiang5-desk3.ch.intel.com ([143.182.136.137]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2021 16:13:48 -0800 Subject: [PATCH] dmaengine: idxd: Fix clobbering of SWERR overflow bit on writeback From: Dave Jiang To: vkoul@kernel.org Cc: Sanjay Kumar , dmaengine@vger.kernel.org Date: Tue, 16 Feb 2021 17:13:42 -0700 Message-ID: <161352082229.3511254.1002151220537623503.stgit@djiang5-desk3.ch.intel.com> User-Agent: StGit/0.23-29-ga622f1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Current code blindly writes over the SWERR and the OVERFLOW bits. Write back the bits actually read instead so the driver avoids clobbering the OVERFLOW bit that comes after the register is read. Fixes: bfe1d56091c1 ("dmaengine: idxd: Init and probe for Intel data accelerators") Reported-by: Sanjay Kumar Signed-off-by: Dave Jiang --- drivers/dma/idxd/irq.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/dma/idxd/irq.c b/drivers/dma/idxd/irq.c index a60ca11a5784..f1463fc58112 100644 --- a/drivers/dma/idxd/irq.c +++ b/drivers/dma/idxd/irq.c @@ -124,7 +124,9 @@ static int process_misc_interrupts(struct idxd_device *idxd, u32 cause) for (i = 0; i < 4; i++) idxd->sw_err.bits[i] = ioread64(idxd->reg_base + IDXD_SWERR_OFFSET + i * sizeof(u64)); - iowrite64(IDXD_SWERR_ACK, idxd->reg_base + IDXD_SWERR_OFFSET); + + iowrite64(idxd->sw_err.bits[0] & IDXD_SWERR_ACK, + idxd->reg_base + IDXD_SWERR_OFFSET); if (idxd->sw_err.valid && idxd->sw_err.wq_idx_valid) { int id = idxd->sw_err.wq_idx;