From patchwork Wed Feb 17 22:11:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrey Konovalov X-Patchwork-Id: 12092479 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 411B4C433DB for ; Wed, 17 Feb 2021 22:13:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 18D4F64D7F for ; Wed, 17 Feb 2021 22:13:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233125AbhBQWNh (ORCPT ); Wed, 17 Feb 2021 17:13:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230488AbhBQWNc (ORCPT ); Wed, 17 Feb 2021 17:13:32 -0500 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14CA3C06178A for ; Wed, 17 Feb 2021 14:12:15 -0800 (PST) Received: by mail-lf1-x12c.google.com with SMTP id p21so298909lfu.11 for ; Wed, 17 Feb 2021 14:12:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HVfGu++4BV6PFNDSYzZjy9kAL54M880pQ5198FJAC0k=; b=t7IoIIYbHnXIIPlwrasi0osgAEbXYwl8rH+PJymHu8wmfpdIwrztDwGti0NkKVRJ0j pWi58wOUfZI6CHSl2MivrqWfkRlaiiNtMz2mkwpXRID38AM/crcwmdcu129SyRhp+nMp tXZOkGZZS8idsDKRpZ0TOpmSvm+sODWZd2x+Tq7NAdYUZXG8EmRKdTlkZhiJSd1tqan7 ZEll6hkrlRAeFautW5p2mnYGlaCQxRNthSpjz1oCmnseaoglBlYkgFGnzMNE1G62H7hJ UfqdYCRFaZq3VfhJcMzUFbyC8cva7Vryw7KOuBywvLmBYVMiHkYWQBuIwux+JlqzcbEx pWHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HVfGu++4BV6PFNDSYzZjy9kAL54M880pQ5198FJAC0k=; b=G0CH5EeAJ/U043uQWvd/4x1OedfzQZ/waKY7GFRXbHK/CqPiz2+gAF5jlxK7QVeaI7 RDmOzgTlPl6P5VdQpmcpD2JgD2uXEI0YBPRSLce41U9ZwY7yIRsnK40b7vkkkV089ku5 ZGx1spwE443nFmo9PcYJz2emWckjMMXXAZS/hT9H/Q8IF1+95get+QifuBCFgx8GELOI esZ8bqMRN2jPyyY2UcgekZFGgt1nuAkuOS4kjF6bIzHF9Lygix+n5EnX7LF3KVY8sxne lhSp9XwUgEHygafJfpIoRQKC/cFryNsV1wBSAbzs2HYR4WyfgGqRu0wSFdW2SHQb/kyB bK0g== X-Gm-Message-State: AOAM531G1N7Z1aoZrtj0U1WAN4qAfuk1N0CDEu7r4RJfaQJTIBeUol2C JATO9Le/fbUOeII21QDLP4ajBg== X-Google-Smtp-Source: ABdhPJwtLL4d6YOTdtI5gEmFRxi0+TOMhteGCHR0mfqNin1koBvqRKWhJIvDfnROUbBGKT1UuI28JQ== X-Received: by 2002:a19:5f0b:: with SMTP id t11mr587147lfb.193.1613599933526; Wed, 17 Feb 2021 14:12:13 -0800 (PST) Received: from localhost.localdomain ([85.249.43.69]) by smtp.googlemail.com with ESMTPSA id b7sm382926ljk.52.2021.02.17.14.12.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 14:12:12 -0800 (PST) From: Andrey Konovalov To: junak.pub@gmail.com, robert.foss@linaro.org, sakari.ailus@linux.intel.com Cc: todor.too@gmail.com, agross@kernel.org, bjorn.andersson@linaro.org, mchehab@kernel.org, laurent.pinchart@ideasonboard.com, jacopo@jmondi.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Andrey Konovalov Subject: [PATCH v2 1/3] v4l: common: v4l2_get_link_freq: add printing a warning Date: Thu, 18 Feb 2021 01:11:32 +0300 Message-Id: <20210217221134.2606-2-andrey.konovalov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210217221134.2606-1-andrey.konovalov@linaro.org> References: <20210217221134.2606-1-andrey.konovalov@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Print a warning if V4L2_CID_LINK_FREQ control is not implemented. Signed-off-by: Andrey Konovalov Reviewed-by: Jacopo Mondi --- drivers/media/v4l2-core/v4l2-common.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c index 133d20e40f82..f1abdf2ab4ec 100644 --- a/drivers/media/v4l2-core/v4l2-common.c +++ b/drivers/media/v4l2-core/v4l2-common.c @@ -461,6 +461,8 @@ s64 v4l2_get_link_freq(struct v4l2_ctrl_handler *handler, unsigned int mul, freq = qm.value; } else { + pr_warn("%s: V4L2_CID_LINK_FREQ not implemented\n", __func__); + if (!mul || !div) return -ENOENT; From patchwork Wed Feb 17 22:11:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrey Konovalov X-Patchwork-Id: 12092481 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C99B9C433E6 for ; Wed, 17 Feb 2021 22:13:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A342364D7F for ; Wed, 17 Feb 2021 22:13:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233159AbhBQWNl (ORCPT ); Wed, 17 Feb 2021 17:13:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233094AbhBQWNc (ORCPT ); Wed, 17 Feb 2021 17:13:32 -0500 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF00FC06178C for ; Wed, 17 Feb 2021 14:12:20 -0800 (PST) Received: by mail-lf1-x12f.google.com with SMTP id v30so379865lfq.6 for ; Wed, 17 Feb 2021 14:12:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KlAXZxX6qaM7ikCQGIwSQ88JryqPY77jU9rOs2ejT9I=; b=GEmFeZ19HgtuNalvRVCH8OCqNgbWZXLEx1WLIEDPWplCl/hxiGrYg/+EkNvwr4craW 5VyO2B0VYn9uSRfQCOsLxcfKUUm6ZAEWzamV4AN4NgSMjN017flA8EyUPmEG69gewW2R 6DBXjBaJObh9oUTGvZymHN+xRthc8dvF/AKrCUxlpwKVKHonf3bxboE/gPUFv8NF9NRG TkIJeyksM/wxJoXH/zEEQSAL+CvymsKfJ935rEG5/7hSql4p6ojDbrai5UPWplaHTe8W 3PCvaTSHGzWWi/T1qXI+x53+PsBnyi9VEfi4ZOXFlpiK1b6MGDMlaU6WMUZ9EaI3is7T CHsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KlAXZxX6qaM7ikCQGIwSQ88JryqPY77jU9rOs2ejT9I=; b=AZR5OF+icvVqUUk+SC3n+CNXjBT3Umxkaw1hxL7lby4UcHv2YY56SoCG65QeFB+qN7 0+TEW4JO8FhU0yeNWIhj1iU3g4qlg+ZbpufgBzwx+gxb8TpZ2box8aZjC24OyrkSlMTp KYn2PT2Tle6qBlB3TPWcitTPrzXNcUhwmzm/KECTjGat59alyrJljIbO6Qcip5Vih5OZ EM/9/qXsC6oIeaMqIO+7xXopid84lCp9r+AV8rA5+kRq6ZO0Xl6gkwKCPxpv26bwKh1r M9synSENFMvGjwAvOgC9L1qM7NycY/ZE3ZZ/YDw4nsznTn7p8/6oqb6dQA34BYPXG7fI hodQ== X-Gm-Message-State: AOAM531se+5AlcjSldo6+NVKw5fyE3wkDr9nUWDoKLtTNXI+9sDjeZtB yraYmL15cwzDHv3aaZXw14XclQ== X-Google-Smtp-Source: ABdhPJwuEVPuJ9MiqQOeSZme5b/AOQ4kc+b+sdQud1pmlGkb7Vd0Ay5AbJ+ACcG+qmvgHP7YBIc78A== X-Received: by 2002:a05:6512:694:: with SMTP id t20mr579643lfe.151.1613599939182; Wed, 17 Feb 2021 14:12:19 -0800 (PST) Received: from localhost.localdomain ([85.249.43.69]) by smtp.googlemail.com with ESMTPSA id b7sm382926ljk.52.2021.02.17.14.12.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Feb 2021 14:12:18 -0800 (PST) From: Andrey Konovalov To: junak.pub@gmail.com, robert.foss@linaro.org, sakari.ailus@linux.intel.com Cc: todor.too@gmail.com, agross@kernel.org, bjorn.andersson@linaro.org, mchehab@kernel.org, laurent.pinchart@ideasonboard.com, jacopo@jmondi.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Andrey Konovalov Subject: [PATCH v2 2/3] media: camss: use v4l2_get_link_freq() to calculate the relevant clocks Date: Thu, 18 Feb 2021 01:11:33 +0300 Message-Id: <20210217221134.2606-3-andrey.konovalov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210217221134.2606-1-andrey.konovalov@linaro.org> References: <20210217221134.2606-1-andrey.konovalov@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org There are places in the camss driver where camss_get_pixel_clock() is called to get the pixel rate (using V4L2_CID_PIXEL_RATE control) and to calculate the link frequency from it. There is a case when this would not work: when V4L2_CID_PIXEL_RATE gets the rate at which the pixels are read (sampled) from the sensor's pixel array, and this rate is different from the pixel transmission rate over the CSI link, the link frequency value can't be calculated from the pixel rate. One needs to use V4L2_CID_LINK_FREQ to get the link frequency in this case. Replace such calls to camss_get_pixel_clock() with calls to a wrapper around v4l2_get_link_freq(). v4l2_get_link_freq() tries V4L2_CID_LINK_FREQ first, and if it is not implemented by the camera sensor driver, falls back to V4L2_CID_PIXEL_RATE to calculate the link frequency value from. Calls to camss_get_pixel_clock() from vfe_[check,set]_clock_rates() are left intact as it looks like this VFE clock does depend on the rate the pixel samples comes out of the camera sensor, not on the frequency at which the link between the sensor and the CSI receiver operates. Signed-off-by: Andrey Konovalov Acked-by: Robert Foss Reviewed-by: Jacopo Mondi --- .../media/platform/qcom/camss/camss-csid.c | 20 +++++------ .../qcom/camss/camss-csiphy-2ph-1-0.c | 22 ++++++------ .../qcom/camss/camss-csiphy-3ph-1-0.c | 22 ++++++------ .../media/platform/qcom/camss/camss-csiphy.c | 36 +++++++++---------- .../media/platform/qcom/camss/camss-csiphy.h | 2 +- drivers/media/platform/qcom/camss/camss.c | 23 ++++++++++++ drivers/media/platform/qcom/camss/camss.h | 2 ++ 7 files changed, 71 insertions(+), 56 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c index be3fe76f3dc3..cff9759c9158 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -462,13 +462,17 @@ static irqreturn_t csid_isr(int irq, void *dev) static int csid_set_clock_rates(struct csid_device *csid) { struct device *dev = csid->camss->dev; - u32 pixel_clock; + const struct csid_format *fmt; + s64 link_freq; int i, j; int ret; - ret = camss_get_pixel_clock(&csid->subdev.entity, &pixel_clock); - if (ret) - pixel_clock = 0; + fmt = csid_get_fmt_entry(csid->formats, csid->nformats, + csid->fmt[MSM_CSIPHY_PAD_SINK].code); + link_freq = camss_get_link_freq(&csid->subdev.entity, fmt->bpp, + csid->phy.lane_cnt); + if (link_freq < 0) + link_freq = 0; for (i = 0; i < csid->nclocks; i++) { struct camss_clock *clock = &csid->clock[i]; @@ -477,13 +481,7 @@ static int csid_set_clock_rates(struct csid_device *csid) !strcmp(clock->name, "csi1") || !strcmp(clock->name, "csi2") || !strcmp(clock->name, "csi3")) { - const struct csid_format *f = csid_get_fmt_entry( - csid->formats, - csid->nformats, - csid->fmt[MSM_CSIPHY_PAD_SINK].code); - u8 num_lanes = csid->phy.lane_cnt; - u64 min_rate = pixel_clock * f->bpp / - (2 * num_lanes * 4); + u64 min_rate = link_freq / 4; long rate; camss_add_clock_margin(&min_rate); diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c index 12bce391d71f..30b454c369ab 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c @@ -51,16 +51,13 @@ static void csiphy_reset(struct csiphy_device *csiphy) * * Helper function to calculate settle count value. This is * based on the CSI2 T_hs_settle parameter which in turn - * is calculated based on the CSI2 transmitter pixel clock - * frequency. + * is calculated based on the CSI2 transmitter link frequency. * - * Return settle count value or 0 if the CSI2 pixel clock - * frequency is not available + * Return settle count value or 0 if the CSI2 link frequency + * is not available */ -static u8 csiphy_settle_cnt_calc(u32 pixel_clock, u8 bpp, u8 num_lanes, - u32 timer_clk_rate) +static u8 csiphy_settle_cnt_calc(s64 link_freq, u32 timer_clk_rate) { - u32 mipi_clock; /* Hz */ u32 ui; /* ps */ u32 timer_period; /* ps */ u32 t_hs_prepare_max; /* ps */ @@ -68,8 +65,10 @@ static u8 csiphy_settle_cnt_calc(u32 pixel_clock, u8 bpp, u8 num_lanes, u32 t_hs_settle; /* ps */ u8 settle_cnt; - mipi_clock = pixel_clock * bpp / (2 * num_lanes); - ui = div_u64(1000000000000LL, mipi_clock); + if (link_freq <= 0) + return 0; + + ui = div_u64(1000000000000LL, link_freq); ui /= 2; t_hs_prepare_max = 85000 + 6 * ui; t_hs_prepare_zero_min = 145000 + 10 * ui; @@ -83,15 +82,14 @@ static u8 csiphy_settle_cnt_calc(u32 pixel_clock, u8 bpp, u8 num_lanes, static void csiphy_lanes_enable(struct csiphy_device *csiphy, struct csiphy_config *cfg, - u32 pixel_clock, u8 bpp, u8 lane_mask) + s64 link_freq, u8 lane_mask) { struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg; u8 settle_cnt; u8 val, l = 0; int i = 0; - settle_cnt = csiphy_settle_cnt_calc(pixel_clock, bpp, c->num_data, - csiphy->timer_clk_rate); + settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_T_INIT_CFG0); diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 97cb9de85031..da7c3d3f9a10 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -107,24 +107,23 @@ static irqreturn_t csiphy_isr(int irq, void *dev) * * Helper function to calculate settle count value. This is * based on the CSI2 T_hs_settle parameter which in turn - * is calculated based on the CSI2 transmitter pixel clock - * frequency. + * is calculated based on the CSI2 transmitter link frequency. * - * Return settle count value or 0 if the CSI2 pixel clock - * frequency is not available + * Return settle count value or 0 if the CSI2 link frequency + * is not available */ -static u8 csiphy_settle_cnt_calc(u32 pixel_clock, u8 bpp, u8 num_lanes, - u32 timer_clk_rate) +static u8 csiphy_settle_cnt_calc(s64 link_freq, u32 timer_clk_rate) { - u32 mipi_clock; /* Hz */ u32 ui; /* ps */ u32 timer_period; /* ps */ u32 t_hs_prepare_max; /* ps */ u32 t_hs_settle; /* ps */ u8 settle_cnt; - mipi_clock = pixel_clock * bpp / (2 * num_lanes); - ui = div_u64(1000000000000LL, mipi_clock); + if (link_freq <= 0) + return 0; + + ui = div_u64(1000000000000LL, link_freq); ui /= 2; t_hs_prepare_max = 85000 + 6 * ui; t_hs_settle = t_hs_prepare_max; @@ -137,15 +136,14 @@ static u8 csiphy_settle_cnt_calc(u32 pixel_clock, u8 bpp, u8 num_lanes, static void csiphy_lanes_enable(struct csiphy_device *csiphy, struct csiphy_config *cfg, - u32 pixel_clock, u8 bpp, u8 lane_mask) + s64 link_freq, u8 lane_mask) { struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg; u8 settle_cnt; u8 val, l = 0; int i; - settle_cnt = csiphy_settle_cnt_calc(pixel_clock, bpp, c->num_data, - csiphy->timer_clk_rate); + settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); val = BIT(c->clk.pos); for (i = 0; i < c->num_data; i++) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c index 509c9a59c09c..40384d7ca78c 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -102,23 +102,23 @@ static u8 csiphy_get_bpp(const struct csiphy_format *formats, static int csiphy_set_clock_rates(struct csiphy_device *csiphy) { struct device *dev = csiphy->camss->dev; - u32 pixel_clock; + s64 link_freq; int i, j; int ret; - ret = camss_get_pixel_clock(&csiphy->subdev.entity, &pixel_clock); - if (ret) - pixel_clock = 0; + u8 bpp = csiphy_get_bpp(csiphy->formats, csiphy->nformats, + csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); + u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data; + + link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); + if (link_freq < 0) + link_freq = 0; for (i = 0; i < csiphy->nclocks; i++) { struct camss_clock *clock = &csiphy->clock[i]; if (csiphy->rate_set[i]) { - u8 bpp = csiphy_get_bpp(csiphy->formats, - csiphy->nformats, - csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); - u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data; - u64 min_rate = pixel_clock * bpp / (2 * num_lanes * 4); + u64 min_rate = link_freq / 4; long round_rate; camss_add_clock_margin(&min_rate); @@ -238,22 +238,18 @@ static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg) static int csiphy_stream_on(struct csiphy_device *csiphy) { struct csiphy_config *cfg = &csiphy->cfg; - u32 pixel_clock; + s64 link_freq; u8 lane_mask = csiphy_get_lane_mask(&cfg->csi2->lane_cfg); u8 bpp = csiphy_get_bpp(csiphy->formats, csiphy->nformats, csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); + u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data; u8 val; - int ret; - ret = camss_get_pixel_clock(&csiphy->subdev.entity, &pixel_clock); - if (ret) { - dev_err(csiphy->camss->dev, - "Cannot get CSI2 transmitter's pixel clock\n"); - return -EINVAL; - } - if (!pixel_clock) { + link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); + + if (link_freq < 0) { dev_err(csiphy->camss->dev, - "Got pixel clock == 0, cannot continue\n"); + "Cannot get CSI2 transmitter's link frequency\n"); return -EINVAL; } @@ -268,7 +264,7 @@ static int csiphy_stream_on(struct csiphy_device *csiphy) writel_relaxed(val, csiphy->base_clk_mux); wmb(); - csiphy->ops->lanes_enable(csiphy, cfg, pixel_clock, bpp, lane_mask); + csiphy->ops->lanes_enable(csiphy, cfg, link_freq, lane_mask); return 0; } diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h index f7967ef836dc..d71b8bc6ec00 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.h +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h @@ -50,7 +50,7 @@ struct csiphy_hw_ops { void (*reset)(struct csiphy_device *csiphy); void (*lanes_enable)(struct csiphy_device *csiphy, struct csiphy_config *cfg, - u32 pixel_clock, u8 bpp, u8 lane_mask); + s64 link_freq, u8 lane_mask); void (*lanes_disable)(struct csiphy_device *csiphy, struct csiphy_config *cfg); irqreturn_t (*isr)(int irq, void *dev); diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 7c0f669f8aa6..eb8fb8c34acd 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -548,6 +548,29 @@ struct media_entity *camss_find_sensor(struct media_entity *entity) } } +/** + * camss_get_link_freq - Get link frequency from sensor + * @entity: Media entity in the current pipeline + * @bpp: Number of bits per pixel for the current format + * @lanes: Number of lanes in the link to the sensor + * + * Return link frequency on success or a negative error code otherwise + */ +s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp, + unsigned int lanes) +{ + struct media_entity *sensor; + struct v4l2_subdev *subdev; + + sensor = camss_find_sensor(entity); + if (!sensor) + return -ENODEV; + + subdev = media_entity_to_v4l2_subdev(sensor); + + return v4l2_get_link_freq(subdev->ctrl_handler, bpp, 2 * lanes); +} + /* * camss_get_pixel_clock - Get pixel clock rate from sensor * @entity: Media entity in the current pipeline diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index 3a0484683cd6..86cdc25189eb 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -108,6 +108,8 @@ int camss_enable_clocks(int nclocks, struct camss_clock *clock, struct device *dev); void camss_disable_clocks(int nclocks, struct camss_clock *clock); struct media_entity *camss_find_sensor(struct media_entity *entity); +s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp, + unsigned int lanes); int camss_get_pixel_clock(struct media_entity *entity, u32 *pixel_clock); int camss_pm_domain_on(struct camss *camss, int id); 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Wed, 17 Feb 2021 14:12:23 -0800 (PST) From: Andrey Konovalov To: junak.pub@gmail.com, robert.foss@linaro.org, sakari.ailus@linux.intel.com Cc: todor.too@gmail.com, agross@kernel.org, bjorn.andersson@linaro.org, mchehab@kernel.org, laurent.pinchart@ideasonboard.com, jacopo@jmondi.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Andrey Konovalov Subject: [PATCH v2 3/3] media: qcom: camss: Fix overflows in clock rate calculations Date: Thu, 18 Feb 2021 01:11:34 +0300 Message-Id: <20210217221134.2606-4-andrey.konovalov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210217221134.2606-1-andrey.konovalov@linaro.org> References: <20210217221134.2606-1-andrey.konovalov@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Vladimir Lypak Because of u32 type being used to store pixel clock rate, expression used to calculate pipeline clocks (pixel_clock * bpp) produces wrong value due to integer overflow. This patch changes data type used to store, pass and retrieve pixel_clock from u32 to u64 to make this mistake less likely to be repeated in the future. Signed-off-by: Vladimir Lypak Acked-by: Robert Foss Signed-off-by: Andrey Konovalov Reviewed-by: Jacopo Mondi --- drivers/media/platform/qcom/camss/camss-vfe.c | 4 ++-- drivers/media/platform/qcom/camss/camss.c | 2 +- drivers/media/platform/qcom/camss/camss.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index fae2b513b2f9..b2c95b46ce66 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -1112,7 +1112,7 @@ static inline void vfe_isr_halt_ack(struct vfe_device *vfe) static int vfe_set_clock_rates(struct vfe_device *vfe) { struct device *dev = vfe->camss->dev; - u32 pixel_clock[MSM_VFE_LINE_NUM]; + u64 pixel_clock[MSM_VFE_LINE_NUM]; int i, j; int ret; @@ -1194,7 +1194,7 @@ static int vfe_set_clock_rates(struct vfe_device *vfe) */ static int vfe_check_clock_rates(struct vfe_device *vfe) { - u32 pixel_clock[MSM_VFE_LINE_NUM]; + u64 pixel_clock[MSM_VFE_LINE_NUM]; int i, j; int ret; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index eb8fb8c34acd..d82bbc2213a6 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -578,7 +578,7 @@ s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp, * * Return 0 on success or a negative error code otherwise */ -int camss_get_pixel_clock(struct media_entity *entity, u32 *pixel_clock) +int camss_get_pixel_clock(struct media_entity *entity, u64 *pixel_clock) { struct media_entity *sensor; struct v4l2_subdev *subdev; diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index 86cdc25189eb..e29466d07ad2 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -110,7 +110,7 @@ void camss_disable_clocks(int nclocks, struct camss_clock *clock); struct media_entity *camss_find_sensor(struct media_entity *entity); s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp, unsigned int lanes); -int camss_get_pixel_clock(struct media_entity *entity, u32 *pixel_clock); +int camss_get_pixel_clock(struct media_entity *entity, u64 *pixel_clock); int camss_pm_domain_on(struct camss *camss, int id); void camss_pm_domain_off(struct camss *camss, int id); void camss_delete(struct camss *camss);