From patchwork Fri Feb 19 21:53:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lyude Paul X-Patchwork-Id: 12096251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99E55C433E0 for ; Fri, 19 Feb 2021 21:58:02 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 48F5064E24 for ; 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Fri, 19 Feb 2021 16:55:14 -0500 X-MC-Unique: 9n8zAtl6OACJCfCCSY6BgA-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 3A136EC1A0; Fri, 19 Feb 2021 21:55:11 +0000 (UTC) Received: from Whitewolf.redhat.com (ovpn-118-5.rdu2.redhat.com [10.10.118.5]) by smtp.corp.redhat.com (Postfix) with ESMTP id A6DEC6A03C; Fri, 19 Feb 2021 21:55:07 +0000 (UTC) From: Lyude Paul To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, nouveau@lists.freedesktop.org, =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= , Jani Nikula , Rodrigo Vivi , Thomas Zimmermann Subject: [PATCH 19/30] drm/dp: Pass drm_dp_aux to drm_dp_link_train_clock_recovery_delay() Date: Fri, 19 Feb 2021 16:53:15 -0500 Message-Id: <20210219215326.2227596-20-lyude@redhat.com> In-Reply-To: <20210219215326.2227596-1-lyude@redhat.com> References: <20210219215326.2227596-1-lyude@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210219_165627_792523_32F7FA84 X-CRM114-Status: GOOD ( 14.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , Imre Deak , Joonas Lahtinen , Oleg Vasilev , Tanmay Shah , Laurent Pinchart , Lee Jones , Chandan Uddaraju , Emil Velikov , Michal Simek , Luben Tuikov , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Maarten Lankhorst , Maxime Ripard , Stephen Boyd , Kuogee Hsieh , =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= , Sean Paul , "moderated list:ARM/ZYNQ ARCHITECTURE" , Hyun Kwon , open list , Manasi Navare , Rob Clark , Daniel Vetter , Alex Deucher , "open list:DRM DRIVER FOR MSM ADRENO GPU" , =?utf-8?q?Christian_K=C3=B6nig?= Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org So that we can start using drm_dbg_*() in drm_dp_link_train_clock_recovery_delay(). Signed-off-by: Lyude Paul Reviewed-by: Laurent Pinchart Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +- drivers/gpu/drm/drm_dp_helper.c | 3 ++- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 2 +- drivers/gpu/drm/msm/dp/dp_ctrl.c | 2 +- drivers/gpu/drm/msm/edp/edp_ctrl.c | 2 +- drivers/gpu/drm/radeon/atombios_dp.c | 2 +- drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +- include/drm/drm_dp_helper.h | 4 +++- 8 files changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index 6d35da65e09f..4468f9d6b4dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -611,7 +611,7 @@ amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_i dp_info->tries = 0; voltage = 0xff; while (1) { - drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); + drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd); if (drm_dp_dpcd_read_link_status(dp_info->aux, dp_info->link_status) <= 0) { diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index 194e0c273809..ce08eb3bface 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -132,7 +132,8 @@ u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZ } EXPORT_SYMBOL(drm_dp_get_adjust_request_post_cursor); -void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, + const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & DP_TRAINING_AUX_RD_MASK; diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 892d7db7d94f..222073d46bdb 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -441,7 +441,7 @@ static void intel_dp_link_training_clock_recovery_delay(struct intel_dp *intel_d enum drm_dp_phy dp_phy) { if (dp_phy == DP_PHY_DPRX) - drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); + drm_dp_link_train_clock_recovery_delay(&intel_dp->aux, intel_dp->dpcd); else drm_dp_lttpr_link_train_clock_recovery_delay(); } diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 36b39c381b3f..2501a6b326a3 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1103,7 +1103,7 @@ static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl, tries = 0; old_v_level = ctrl->link->phy_params.v_level; for (tries = 0; tries < maximum_retries; tries++) { - drm_dp_link_train_clock_recovery_delay(ctrl->panel->dpcd); + drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd); ret = dp_ctrl_read_link_status(ctrl, link_status); if (ret) diff --git a/drivers/gpu/drm/msm/edp/edp_ctrl.c b/drivers/gpu/drm/msm/edp/edp_ctrl.c index 57af3d8b6699..6501598448b4 100644 --- a/drivers/gpu/drm/msm/edp/edp_ctrl.c +++ b/drivers/gpu/drm/msm/edp/edp_ctrl.c @@ -608,7 +608,7 @@ static int edp_start_link_train_1(struct edp_ctrl *ctrl) tries = 0; old_v_level = ctrl->v_level; while (1) { - drm_dp_link_train_clock_recovery_delay(ctrl->dpcd); + drm_dp_link_train_clock_recovery_delay(ctrl->drm_aux, ctrl->dpcd); rlen = drm_dp_dpcd_read_link_status(ctrl->drm_aux, link_status); if (rlen < DP_LINK_STATUS_SIZE) { diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c index c50c504bad50..299b9d8da376 100644 --- a/drivers/gpu/drm/radeon/atombios_dp.c +++ b/drivers/gpu/drm/radeon/atombios_dp.c @@ -680,7 +680,7 @@ static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) dp_info->tries = 0; voltage = 0xff; while (1) { - drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); + drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd); if (drm_dp_dpcd_read_link_status(dp_info->aux, dp_info->link_status) <= 0) { diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c index 8272eee03adc..5cc295d8ba9f 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -713,7 +713,7 @@ static int zynqmp_dp_link_train_cr(struct zynqmp_dp *dp) if (ret) return ret; - drm_dp_link_train_clock_recovery_delay(dp->dpcd); + drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd); ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status); if (ret < 0) return ret; diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 45ec74862212..e4681665231e 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -29,6 +29,7 @@ #include struct drm_device; +struct drm_dp_aux; /* * Unless otherwise noted, all values are from the DP 1.1a spec. Note that @@ -1475,7 +1476,8 @@ u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZ #define DP_LTTPR_COMMON_CAP_SIZE 8 #define DP_LTTPR_PHY_CAP_SIZE 3 -void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); +void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, + const u8 dpcd[DP_RECEIVER_CAP_SIZE]); void drm_dp_lttpr_link_train_clock_recovery_delay(void); void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); void drm_dp_lttpr_link_train_channel_eq_delay(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); From patchwork Fri Feb 19 21:53:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lyude Paul X-Patchwork-Id: 12096253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D8B9C433E0 for ; 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bh=qrUGx3vonj4oLS1FAH7nDpxh6uMpzmo9IxYyt75a2Yc=; b=ZsR13uvSXPfWgCvRlpQjOQyl+wIeQrGi/CSN2F2WRnOH7LBQGwE3LoCG9j9wFI8n1NA3ui UMkLQKo+ItdNG6uAJYscKrqDsDNUd5b9McGtZCX2bIPYGUXKxRybjirE2FQdaGnY1sBIIt byb9pKAPxfJy+CvMSst5I51woDobfmY= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-494-l95I3_ZsNqKYPnH24AJlhg-1; Fri, 19 Feb 2021 16:55:27 -0500 X-MC-Unique: l95I3_ZsNqKYPnH24AJlhg-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 3C2CB18A08BE; Fri, 19 Feb 2021 21:55:23 +0000 (UTC) Received: from Whitewolf.redhat.com (ovpn-118-5.rdu2.redhat.com [10.10.118.5]) by smtp.corp.redhat.com (Postfix) with ESMTP id BAA216A03C; Fri, 19 Feb 2021 21:55:19 +0000 (UTC) From: Lyude Paul To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org, nouveau@lists.freedesktop.org, =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= , Jani Nikula , Rodrigo Vivi , Thomas Zimmermann Subject: [PATCH 20/30] drm/dp: Pass drm_dp_aux to drm_dp*_link_train_channel_eq_delay() Date: Fri, 19 Feb 2021 16:53:16 -0500 Message-Id: <20210219215326.2227596-21-lyude@redhat.com> In-Reply-To: <20210219215326.2227596-1-lyude@redhat.com> References: <20210219215326.2227596-1-lyude@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210219_165702_595078_DD3BA431 X-CRM114-Status: GOOD ( 14.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , Imre Deak , Joonas Lahtinen , Oleg Vasilev , Tanmay Shah , Laurent Pinchart , Lee Jones , Chandan Uddaraju , Emil Velikov , Michal Simek , Luben Tuikov , Jeevan B , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Maarten Lankhorst , Maxime Ripard , Stephen Boyd , Kuogee Hsieh , =?utf-8?q?Jos=C3=A9_Roberto_de_Souza?= , Sean Paul , "moderated list:ARM/ZYNQ ARCHITECTURE" , Hyun Kwon , open list , Manasi Navare , Rob Clark , Daniel Vetter , Alex Deucher , "open list:DRM DRIVER FOR MSM ADRENO GPU" , =?utf-8?q?Christian_K=C3=B6nig?= Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org So that we can start using drm_dbg_*() for drm_dp_link_train_channel_eq_delay() and drm_dp_lttpr_link_train_channel_eq_delay(). Signed-off-by: Lyude Paul Reviewed-by: Laurent Pinchart --- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 2 +- drivers/gpu/drm/drm_dp_helper.c | 14 +++++++++----- .../gpu/drm/i915/display/intel_dp_link_training.c | 4 ++-- drivers/gpu/drm/msm/dp/dp_ctrl.c | 4 ++-- drivers/gpu/drm/msm/edp/edp_ctrl.c | 4 ++-- drivers/gpu/drm/radeon/atombios_dp.c | 2 +- drivers/gpu/drm/xlnx/zynqmp_dp.c | 2 +- include/drm/drm_dp_helper.h | 6 ++++-- 8 files changed, 22 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index 4468f9d6b4dd..59ce6f620fdc 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -676,7 +676,7 @@ amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_i dp_info->tries = 0; channel_eq = false; while (1) { - drm_dp_link_train_channel_eq_delay(dp_info->dpcd); + drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); if (drm_dp_dpcd_read_link_status(dp_info->aux, dp_info->link_status) <= 0) { diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c index ce08eb3bface..a9316c1ecb52 100644 --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c @@ -151,7 +151,8 @@ void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, } EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); -static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval) +static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, + unsigned long rd_interval) { if (rd_interval > 4) DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n", @@ -165,9 +166,11 @@ static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval) usleep_range(rd_interval, rd_interval * 2); } -void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, + const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { - __drm_dp_link_train_channel_eq_delay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & + __drm_dp_link_train_channel_eq_delay(aux, + dpcd[DP_TRAINING_AUX_RD_INTERVAL] & DP_TRAINING_AUX_RD_MASK); } EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); @@ -183,13 +186,14 @@ static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r) return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1]; } -void drm_dp_lttpr_link_train_channel_eq_delay(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) +void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, + const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) { u8 interval = dp_lttpr_phy_cap(phy_cap, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) & DP_TRAINING_AUX_RD_MASK; - __drm_dp_link_train_channel_eq_delay(interval); + __drm_dp_link_train_channel_eq_delay(aux, interval); } EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay); diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 222073d46bdb..fe8b5a5d9d1a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -593,11 +593,11 @@ intel_dp_link_training_channel_equalization_delay(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy) { if (dp_phy == DP_PHY_DPRX) { - drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); + drm_dp_link_train_channel_eq_delay(&intel_dp->aux, intel_dp->dpcd); } else { const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); - drm_dp_lttpr_link_train_channel_eq_delay(phy_caps); + drm_dp_lttpr_link_train_channel_eq_delay(&intel_dp->aux, phy_caps); } } diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 2501a6b326a3..33df288dd4eb 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1184,7 +1184,7 @@ static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl) static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl) { dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE); - drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd); + drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); } static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, @@ -1215,7 +1215,7 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, dp_ctrl_train_pattern_set(ctrl, pattern | DP_RECOVERED_CLOCK_OUT_EN); for (tries = 0; tries <= maximum_retries; tries++) { - drm_dp_link_train_channel_eq_delay(ctrl->panel->dpcd); + drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); ret = dp_ctrl_read_link_status(ctrl, link_status); if (ret) diff --git a/drivers/gpu/drm/msm/edp/edp_ctrl.c b/drivers/gpu/drm/msm/edp/edp_ctrl.c index 6501598448b4..4fb397ee7c84 100644 --- a/drivers/gpu/drm/msm/edp/edp_ctrl.c +++ b/drivers/gpu/drm/msm/edp/edp_ctrl.c @@ -665,7 +665,7 @@ static int edp_start_link_train_2(struct edp_ctrl *ctrl) return ret; while (1) { - drm_dp_link_train_channel_eq_delay(ctrl->dpcd); + drm_dp_link_train_channel_eq_delay(ctrl->drm_aux, ctrl->dpcd); rlen = drm_dp_dpcd_read_link_status(ctrl->drm_aux, link_status); if (rlen < DP_LINK_STATUS_SIZE) { @@ -743,7 +743,7 @@ static int edp_clear_training_pattern(struct edp_ctrl *ctrl) ret = edp_train_pattern_set_write(ctrl, 0); - drm_dp_link_train_channel_eq_delay(ctrl->dpcd); + drm_dp_link_train_channel_eq_delay(ctrl->drm_aux, ctrl->dpcd); return ret; } diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c index 299b9d8da376..4c1e551d9714 100644 --- a/drivers/gpu/drm/radeon/atombios_dp.c +++ b/drivers/gpu/drm/radeon/atombios_dp.c @@ -743,7 +743,7 @@ static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) dp_info->tries = 0; channel_eq = false; while (1) { - drm_dp_link_train_channel_eq_delay(dp_info->dpcd); + drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); if (drm_dp_dpcd_read_link_status(dp_info->aux, dp_info->link_status) <= 0) { diff --git a/drivers/gpu/drm/xlnx/zynqmp_dp.c b/drivers/gpu/drm/xlnx/zynqmp_dp.c index 5cc295d8ba9f..f6f2293db18d 100644 --- a/drivers/gpu/drm/xlnx/zynqmp_dp.c +++ b/drivers/gpu/drm/xlnx/zynqmp_dp.c @@ -778,7 +778,7 @@ static int zynqmp_dp_link_train_ce(struct zynqmp_dp *dp) if (ret) return ret; - drm_dp_link_train_channel_eq_delay(dp->dpcd); + drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); ret = drm_dp_dpcd_read_link_status(&dp->aux, link_status); if (ret < 0) return ret; diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index e4681665231e..2151aeb6c279 100644 --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h @@ -1479,8 +1479,10 @@ u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZ void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); void drm_dp_lttpr_link_train_clock_recovery_delay(void); -void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]); -void drm_dp_lttpr_link_train_channel_eq_delay(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); +void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, + const u8 dpcd[DP_RECEIVER_CAP_SIZE]); +void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, + const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); u8 drm_dp_link_rate_to_bw_code(int link_rate); int drm_dp_bw_code_to_link_rate(u8 link_bw);