From patchwork Mon Feb 22 19:05:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gwan-gyeong Mun X-Patchwork-Id: 12099313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19AB1C433E0 for ; Mon, 22 Feb 2021 19:04:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 664996186A for ; Mon, 22 Feb 2021 19:04:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 664996186A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E762A6E193; Mon, 22 Feb 2021 19:04:26 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5452E6E193 for ; Mon, 22 Feb 2021 19:04:26 +0000 (UTC) IronPort-SDR: w3N3PdKEPW+FZw29IkvZvw4Y7HK+GNd59qoqH0OpCsajCQD/ZvdK1KyzQ3GNRBtosumVXlp0+Z XIsNQ082EYDw== X-IronPort-AV: E=McAfee;i="6000,8403,9903"; a="203962661" X-IronPort-AV: E=Sophos;i="5.81,198,1610438400"; d="scan'208";a="203962661" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2021 11:04:24 -0800 IronPort-SDR: xS70y8s30vTm0xABKlSwUjsrWEO+JkzZ6YU7q2keBLjfx0EUUmDkkcfevlnUscBojgLlH8FV0b n1frd8i8WQyw== X-IronPort-AV: E=Sophos;i="5.81,198,1610438400"; d="scan'208";a="514894182" Received: from helsinki.fi.intel.com ([10.237.66.162]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2021 11:04:20 -0800 From: Gwan-gyeong Mun To: intel-gfx@lists.freedesktop.org Date: Mon, 22 Feb 2021 21:05:28 +0200 Message-Id: <20210222190528.1591188-1-gwan-gyeong.mun@intel.com> X-Mailer: git-send-email 2.30.0 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2] drm/i915/display: Do not allow DC3CO if PSR SF is enabled X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Even though GEN12+ HW supports PSR + DC3CO, DMC's HW DC3CO exit mechanism has an issue with using of Selective Fecth and PSR2 manual tracking. And as some GEN12+ platforms (RKL, ADL-S) don't support PSR2 HW tracking, Selective Fetch will be enabled by default on that platforms. Therefore if the system enables PSR Selective Fetch / PSR manual tracking, it does not allow DC3CO dc state, in that case. When this DC3CO exit issue is addressed while PSR Selective Fetch is enabled, this restriction should be removed. Cc: José Roberto de Souza Cc: Anshuman Gupta Signed-off-by: Gwan-gyeong Mun --- drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 7c6e561f86c1..7370de97e599 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -654,6 +654,14 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); u32 exit_scanlines; + /* + * DMC's DC3CO exit mechanism has an issue with Selective Fecth + * TODO: when the issue is addressed, this restriction should be removed. + */ + if (dev_priv->params.enable_psr2_sel_fetch || + intel_dp->psr.debug == I915_PSR_DEBUG_ENABLE_SEL_FETCH) + return; + if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) return;