From patchwork Tue Feb 23 06:18:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 12099945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF663C433E0 for ; Tue, 23 Feb 2021 06:20:49 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 359F564E6B for ; Tue, 23 Feb 2021 06:20:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 359F564E6B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=uKGAD9anlzx/5KjOtUKznptLp3w5Gi0zTwSofhsnQXc=; b=phEudfeZfctB+2/oA0HQ0pZ0k zjOF/yAvPOAdX3e8fSWGmkqqkYzLQg10dA9uX2Y7qf23gbeLYxY4PJwQyOnOYrnMyYCeUczUAC6Oj nFed492IlFgF41ymLTbtONQClMASe1+3UBLz4v4bgd1kUGFJsT73WuKkvEw+ykI7d0wCbIOl4KZYx OvlHV4aeNRLvPsytyxT3NJYkZIH5mIbnCu/sNTJIEVANsDrlZJLDhaxGZaigY9eCS/NDxm8ohZUw+ IcJxMFmoN468X6Rj94I9fddeGZ6Ucc/rKhaVt5Nq+IxrC2jiHOrAljxgN49wDo/mDAx7PUb4wHdre zLCIsY9YQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1lER2b-0006mb-5J; Tue, 23 Feb 2021 06:19:25 +0000 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1lER2T-0006kC-Qn for linux-arm-kernel@lists.infradead.org; Tue, 23 Feb 2021 06:19:18 +0000 Received: by mail-pj1-x1031.google.com with SMTP id cx11so1124238pjb.4 for ; Mon, 22 Feb 2021 22:19:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OhVat5LrE1fhESIUjnpbwIUbs1+uHdZHHpdx8ggYgCw=; b=jjuchHLCWGF1ErNoEErzLFpwqBimzUP/Th11yILb0nPHSuvnP8OMSacbRaJ7LcuyMd uRdAZQZT4Sa2ZlaMZCbiyXINMezClHcLza61IqCWH0t6QXJ+rxQc5rvgjfEp9blQrG6Q PPq5+dXItdUiZKqUniyqJABdhNqTf6cAr/Oc8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OhVat5LrE1fhESIUjnpbwIUbs1+uHdZHHpdx8ggYgCw=; b=eoqAXxtWaFeJSY4fVgVsHj4JNsvikCDAPy+amBy9gDmBfzYex9oGpEw7lq7c9SSErS ej/5KhrDdLBADYODUf6m1Xx/Bx9sahIl1+18xJQwc1deQJMwAkP8neFzgAhqQL/rfxxP zCI7I21HTZVVDbQxHPJ1NTgBaTmXfoigPQoBdUOho4YWwDPSAkY6/St4kz0zZJ7LwN73 l4V/Kjtb409y8MzSxWUaszR+5GSMCQbEhNFefFVSt9bX+a+xIa3H1lr4eeLMUkDKBLBR 4HwIG2yl1vKYxS3vb59WZf4zSLaKYLckNw0Ri6AeEZAjqjMLc2NCll5yEooWEltCI9nX +JzA== X-Gm-Message-State: AOAM531Qri4/a+IDoIuE28KRUNC0UVIwR2SxXO5t/0E39jyHQb3CnTjJ D6CK95UImgP5BU14BJ9Ik8A5oA== X-Google-Smtp-Source: ABdhPJyXXR+t7UNc7M5JbvOoe9YC9FsdP2ZLpFwkfCS9cnni/x9cZLknpqKBKyk/9ba9udsHt8d96g== X-Received: by 2002:a17:90a:ca11:: with SMTP id x17mr26126122pjt.201.1614061155775; Mon, 22 Feb 2021 22:19:15 -0800 (PST) Received: from shiro.work (p345188-ipngn200408sizuokaden.shizuoka.ocn.ne.jp. [124.98.97.188]) by smtp.googlemail.com with ESMTPSA id n10sm20135169pgk.91.2021.02.22.22.19.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 22:19:15 -0800 (PST) From: Daniel Palmer List-Id: To: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, soc@kernel.org, sboyd@kernel.org Subject: [PATCH 1/8] dt-bindings: clk: mstar msc313 cpupll binding description Date: Tue, 23 Feb 2021 15:18:23 +0900 Message-Id: <20210223061830.1913700-2-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210223061830.1913700-1-daniel@0x0f.com> References: <20210223061830.1913700-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210223_011917_903449_E1AB1861 X-CRM114-Status: GOOD ( 14.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Palmer , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a binding description for the MStar/SigmaStar CPU PLL block. Signed-off-by: Daniel Palmer --- .../bindings/clock/mstar,msc313-cpupll.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml diff --git a/Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml b/Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml new file mode 100644 index 000000000000..a9ad7ab5230c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mstar,msc313-cpupll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MStar/Sigmastar MSC313 CPU PLL + +maintainers: + - Daniel Palmer + +description: | + The MStar/SigmaStar MSC313 and later ARMv7 chips have a scalable + PLL that can be used as the clock source for the CPU(s). + +properties: + compatible: + const: mstar,msc313-cpupll + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - clocks + - reg + +additionalProperties: false + +examples: + - | + #include + cpupll: cpupll@206400 { + compatible = "mstar,msc313-cpupll"; + reg = <0x206400 0x200>; + #clock-cells = <1>; + clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>; + }; From patchwork Tue Feb 23 06:18:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 12099951 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 139CBC433E0 for ; Tue, 23 Feb 2021 06:20:54 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A0B6D64DA3 for ; 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[124.98.97.188]) by smtp.googlemail.com with ESMTPSA id n10sm20135169pgk.91.2021.02.22.22.19.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 22:19:17 -0800 (PST) From: Daniel Palmer List-Id: To: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, soc@kernel.org, sboyd@kernel.org Subject: [PATCH 2/8] clk: mstar: msc313 cpupll clk driver Date: Tue, 23 Feb 2021 15:18:24 +0900 Message-Id: <20210223061830.1913700-3-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210223061830.1913700-1-daniel@0x0f.com> References: <20210223061830.1913700-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210223_011920_412495_A3F954F0 X-CRM114-Status: GOOD ( 27.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Palmer , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a driver for the CPU pll/ARM pll/MIPS pll that is present in MStar SoCs. Currently there is no documentation for this block so it's possible this driver isn't entirely correct. Only tested on the version of this IP in the MStar/SigmaStar ARMv7 SoCs. Co-authored-by: Willy Tarreau Signed-off-by: Daniel Palmer --- drivers/clk/mstar/Kconfig | 7 + drivers/clk/mstar/Makefile | 1 + drivers/clk/mstar/clk-msc313-cpupll.c | 228 ++++++++++++++++++++++++++ 3 files changed, 236 insertions(+) create mode 100644 drivers/clk/mstar/clk-msc313-cpupll.c diff --git a/drivers/clk/mstar/Kconfig b/drivers/clk/mstar/Kconfig index de37e1bce2d2..a44ca2b180ff 100644 --- a/drivers/clk/mstar/Kconfig +++ b/drivers/clk/mstar/Kconfig @@ -7,3 +7,10 @@ config MSTAR_MSC313_MPLL help Support for the MPLL PLL and dividers block present on MStar/Sigmastar SoCs. + +config MSTAR_MSC313_CPUPLL + bool "MStar CPUPLL driver" + depends on ARCH_MSTARV7 || COMPILE_TEST + default ARCH_MSTARV7 + help + Support for the CPU PLL present on MStar/Sigmastar SoCs. diff --git a/drivers/clk/mstar/Makefile b/drivers/clk/mstar/Makefile index f8dcd25ede1d..9f05b73a0619 100644 --- a/drivers/clk/mstar/Makefile +++ b/drivers/clk/mstar/Makefile @@ -4,3 +4,4 @@ # obj-$(CONFIG_MSTAR_MSC313_MPLL) += clk-msc313-mpll.o +obj-$(CONFIG_MSTAR_MSC313_CPUPLL) += clk-msc313-cpupll.o diff --git a/drivers/clk/mstar/clk-msc313-cpupll.c b/drivers/clk/mstar/clk-msc313-cpupll.c new file mode 100644 index 000000000000..3f250404ecda --- /dev/null +++ b/drivers/clk/mstar/clk-msc313-cpupll.c @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Daniel Palmer + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * This IP is not documented outside of the messy vendor driver. + * Below is what we think the registers look like based on looking at + * the vendor code and poking at the hardware: + * + * 0x140 -- LPF low. Seems to store one half of the clock transition + * 0x144 / + * 0x148 -- LPF high. Seems to store one half of the clock transition + * 0x14c / + * 0x150 -- vendor code says "toggle lpf enable" + * 0x154 -- mu? + * 0x15c -- lpf_update_count? + * 0x160 -- vendor code says "switch to LPF". Clock source config? Register bank? + * 0x164 -- vendor code says "from low to high" which seems to mean transition from LPF low to LPF high. + * 0x174 -- Seems to be the PLL lock status bit + * 0x180 -- Seems to be the current frequency, this might need to be populated by software? + * 0x184 / The vendor driver uses these to set the initial value of LPF low + * + * Frequency seems to be calculated like this: + * (parent clock (432mhz) / register_magic_value) * 16 * 524288 + * Only the lower 24 bits of the resulting value will be used. In addition, the + * PLL doesn't seem to be able to lock on frequencies lower than 220 MHz, as + * divisor 0xfb586f (220 MHz) works but 0xfb7fff locks up. + * + * Vendor values: + * frequency - register value + * + * 400000000 - 0x0067AE14 + * 600000000 - 0x00451EB8, + * 800000000 - 0x0033D70A, + * 1000000000 - 0x002978d4, + */ + +#define REG_LPF_LOW_L 0x140 +#define REG_LPF_LOW_H 0x144 +#define REG_LPF_HIGH_BOTTOM 0x148 +#define REG_LPF_HIGH_TOP 0x14c +#define REG_LPF_TOGGLE 0x150 +#define REG_LPF_MYSTERYTWO 0x154 +#define REG_LPF_UPDATE_COUNT 0x15c +#define REG_LPF_MYSTERYONE 0x160 +#define REG_LPF_TRANSITIONCTRL 0x164 +#define REG_LPF_LOCK 0x174 +#define REG_CURRENT 0x180 + +#define MULTIPLIER_1 16 +#define MULTIPLIER_2 524288 +#define MULTIPLIER (MULTIPLIER_1 * MULTIPLIER_2) + +struct msc313_cpupll { + void __iomem *base; + struct clk_hw clk_hw; +}; + +#define to_cpupll(_hw) container_of(_hw, struct msc313_cpupll, clk_hw) + +static u32 msc313_cpupll_reg_read32(struct msc313_cpupll *cpupll, unsigned int reg) +{ + u32 value; + + value = ioread16(cpupll->base + reg + 4) << 16; + value |= ioread16(cpupll->base + reg); + + return value; +} + +static void msc313_cpupll_reg_write32(struct msc313_cpupll *cpupll, unsigned int reg, u32 value) +{ + u16 l = value & 0xffff, h = (value >> 16) & 0xffff; + + iowrite16(l, cpupll->base + reg); + iowrite16(h, cpupll->base + reg + 4); +} + +static void msc313_cpupll_setfreq(struct msc313_cpupll *cpupll, u32 regvalue) +{ + msc313_cpupll_reg_write32(cpupll, REG_LPF_HIGH_BOTTOM, regvalue); + + iowrite16(0x1, cpupll->base + REG_LPF_MYSTERYONE); + iowrite16(0x6, cpupll->base + REG_LPF_MYSTERYTWO); + iowrite16(0x8, cpupll->base + REG_LPF_UPDATE_COUNT); + iowrite16(BIT(12), cpupll->base + REG_LPF_TRANSITIONCTRL); + + iowrite16(0, cpupll->base + REG_LPF_TOGGLE); + iowrite16(1, cpupll->base + REG_LPF_TOGGLE); + + while (!(ioread16(cpupll->base + REG_LPF_LOCK))) + cpu_relax(); + + iowrite16(0, cpupll->base + REG_LPF_TOGGLE); + + msc313_cpupll_reg_write32(cpupll, REG_LPF_LOW_L, regvalue); +} + +static unsigned long msc313_cpupll_frequencyforreg(u32 reg, unsigned long parent_rate) +{ + unsigned long long prescaled = ((unsigned long long)parent_rate) * MULTIPLIER; + unsigned long long scaled; + + if (prescaled == 0 || reg == 0) + return 0; + scaled = DIV_ROUND_DOWN_ULL(prescaled, reg); + + return scaled; +} + +static u32 msc313_cpupll_regforfrequecy(unsigned long rate, unsigned long parent_rate) +{ + unsigned long long prescaled = ((unsigned long long)parent_rate) * MULTIPLIER; + unsigned long long scaled; + u32 reg; + + if (prescaled == 0 || rate == 0) + return 0; + + scaled = DIV_ROUND_UP_ULL(prescaled, rate); + reg = scaled; + + return reg; +} + +static unsigned long msc313_cpupll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct msc313_cpupll *cpupll = to_cpupll(hw); + + return msc313_cpupll_frequencyforreg(msc313_cpupll_reg_read32(cpupll, REG_LPF_LOW_L), parent_rate); +} + +static long msc313_cpupll_round_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long *parent_rate) +{ + u32 reg = msc313_cpupll_regforfrequecy(rate, *parent_rate); + long rounded = msc313_cpupll_frequencyforreg(reg, *parent_rate); + + /* + * This is my poor attempt at making sure the resulting + * rate doesn't overshoot the requested rate. + */ + for (; rounded >= rate && reg > 0; reg--) + rounded = msc313_cpupll_frequencyforreg(reg, *parent_rate); + + return rounded; +} + +static int msc313_cpupll_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct msc313_cpupll *cpupll = to_cpupll(hw); + u32 reg = msc313_cpupll_regforfrequecy(rate, parent_rate); + + msc313_cpupll_setfreq(cpupll, reg); + + return 0; +} + +static const struct clk_ops msc313_cpupll_ops = { + .recalc_rate = msc313_cpupll_recalc_rate, + .round_rate = msc313_cpupll_round_rate, + .set_rate = msc313_cpupll_set_rate, +}; + +static const struct of_device_id msc313_cpupll_of_match[] = { + { + .compatible = "mstar,msc313-cpupll", + }, + {} +}; + +static const struct clk_parent_data cpupll_parent = { + .index = 0, +}; + +static int msc313_cpupll_probe(struct platform_device *pdev) +{ + struct clk_init_data clk_init = {}; + struct device *dev = &pdev->dev; + struct msc313_cpupll *cpupll; + int ret; + + cpupll = devm_kzalloc(&pdev->dev, sizeof(*cpupll), GFP_KERNEL); + if (!cpupll) + return -ENOMEM; + + cpupll->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(cpupll->base)) + return PTR_ERR(cpupll->base); + + /* LPF might not contain the current frequency so fix that up */ + msc313_cpupll_reg_write32(cpupll, REG_LPF_LOW_L, + msc313_cpupll_reg_read32(cpupll, REG_CURRENT)); + + clk_init.name = dev_name(dev); + clk_init.ops = &msc313_cpupll_ops; + clk_init.flags = CLK_IS_CRITICAL; + clk_init.parent_data = &cpupll_parent; + clk_init.num_parents = 1; + cpupll->clk_hw.init = &clk_init; + + ret = devm_clk_hw_register(dev, &cpupll->clk_hw); + if (ret) + return ret; + + return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_simple_get, &cpupll->clk_hw); +} + +static struct platform_driver msc313_cpupll_driver = { + .driver = { + .name = "mstar-msc313-cpupll", + .of_match_table = msc313_cpupll_of_match, + }, + .probe = msc313_cpupll_probe, +}; +builtin_platform_driver(msc313_cpupll_driver); From patchwork Tue Feb 23 06:18:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 12099947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41A45C433E9 for ; Tue, 23 Feb 2021 06:20:51 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CB8EB64E62 for ; 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[124.98.97.188]) by smtp.googlemail.com with ESMTPSA id n10sm20135169pgk.91.2021.02.22.22.19.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 22:19:20 -0800 (PST) From: Daniel Palmer List-Id: To: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, soc@kernel.org, sboyd@kernel.org Subject: [PATCH 3/8] ARM: mstar: Add cpupll to base dtsi Date: Tue, 23 Feb 2021 15:18:25 +0900 Message-Id: <20210223061830.1913700-4-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210223061830.1913700-1-daniel@0x0f.com> References: <20210223061830.1913700-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210223_011922_868183_A23B8537 X-CRM114-Status: GOOD ( 11.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Palmer , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org All MStar/SigmaStar ARMv7 SoCs have the CPU PLL at the same place so add it to the base dtsi. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-v7.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 075d583d6f40..d323c1a3f3c2 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -132,6 +132,13 @@ mpll: mpll@206000 { clocks = <&xtal>; }; + cpupll: cpupll@206400 { + compatible = "mstar,msc313-cpupll"; + reg = <0x206400 0x200>; + #clock-cells = <0>; + clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>; + }; + gpio: gpio@207800 { #gpio-cells = <2>; reg = <0x207800 0x200>; From patchwork Tue Feb 23 06:18:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 12099955 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3991FC4332D for ; Tue, 23 Feb 2021 06:21:03 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E160464E2E for ; Tue, 23 Feb 2021 06:21:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E160464E2E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=8ez0DEYvkv3E9K4UHf4txWxZ8agA4+iHoB4xkZ/CrsI=; b=IgNrQV64vLhzSSM9Hlep9yNM+ ggX1cSiS11HQnVJMLOR+bacyC+6nKduOmFCiL/4Ikz+b6Lw03qgRaSmEomKNNrwd8ikG5dWymvbhc toVOMtG75e2l42DcBfiRQXlQ6shbQrvfINqBm8KbTSCmaWiBGDaPgBj3CKlxa+l3rLHPJ+W1m2dPs Z/Zdl1Yw6cROItnRCYPzTcKUPd0G1Mga8W41831MeSG0q2IesJ/QlBJAC3DLCqPwKzV4YNx1Hy+GN TrTrOqGtjcqkVuk0Vz5hB6cTr4ZNkLz+OrkZeHaPfXDspWQakqw2uD3/O7/o33jlK6x2yjUUs7Ofm 2+WhRWrlw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1lER2u-0006t1-O8; Tue, 23 Feb 2021 06:19:44 +0000 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1lER2a-0006lx-OK for linux-arm-kernel@lists.infradead.org; Tue, 23 Feb 2021 06:19:25 +0000 Received: by mail-pf1-x429.google.com with SMTP id j12so8134011pfj.12 for ; Mon, 22 Feb 2021 22:19:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F8U0f9JNY8hRMi39WPkD4ASf4aAhKNDuZAqXYiDMPnc=; b=OdafbEs6apuScIxtpkC5hbqj2hdH2BgCZ/p6xtr5NI/8lYsH/8jqbSc51l3+G+oxdm /HTWGZWDK2BndoVcYAnXd0cjugjc+PqdTeqTCSYl4njHNY1e7RWaWUsyGsoI42armolR q0pkImbhFou/3iRgFAQDzcMf3nJvz1jrtqflU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F8U0f9JNY8hRMi39WPkD4ASf4aAhKNDuZAqXYiDMPnc=; b=bje0Rqu06QERARgKs24/JbNk21ByVpP8ZgpayDktXZi7bMb0s2jcQd7X9lqfzrDHsi ButOl9mfr2a+xYKvDOFlSL1Z29VZnjUpIkyXU/tSxNQ8XzTr4pdJZwp+cbBmSO143g3s CBC3Ol6oGEBZQpaoa1gbnU34rtmOl/BjaMTdlBdFopLdqeVf+ncU+8fwe1GvxwWc7u+y p8dveIxX/cXheUvg3NuIdj/ivreh+COXyb3Xhg7+96gZt8ilthNI+GWnX4esv/z7LE5x tzm6O9cmreCQuVJxIjAS6kI1Ybr7Om2/fIPilyZimH7K+6GvqQXOPb5QsIT8EkWGJPFG j54w== X-Gm-Message-State: AOAM533d3OHRmBxQ+EsrzF6zCel5oAfLFipiNDUHGRI/IcacLd+KpmA+ Ip83X5nFX0XNF7zPFRFae3vtXQ== X-Google-Smtp-Source: ABdhPJxc6Ul/6qH9CfSEt6s256nfdmu2EHwQomQ8gqEAsR960hE9xL7M7oKKwskSClxqWd9Szf2f+A== X-Received: by 2002:a62:dd01:0:b029:1ed:6b67:1377 with SMTP id w1-20020a62dd010000b02901ed6b671377mr938433pff.48.1614061162681; Mon, 22 Feb 2021 22:19:22 -0800 (PST) Received: from shiro.work (p345188-ipngn200408sizuokaden.shizuoka.ocn.ne.jp. [124.98.97.188]) by smtp.googlemail.com with ESMTPSA id n10sm20135169pgk.91.2021.02.22.22.19.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 22:19:22 -0800 (PST) From: Daniel Palmer List-Id: To: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, soc@kernel.org, sboyd@kernel.org Subject: [PATCH 4/8] ARM: mstar: Link cpupll to cpu Date: Tue, 23 Feb 2021 15:18:26 +0900 Message-Id: <20210223061830.1913700-5-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210223061830.1913700-1-daniel@0x0f.com> References: <20210223061830.1913700-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210223_011924_857938_9FF2C80C X-CRM114-Status: GOOD ( 12.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Palmer , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The CPU clock is sourced from the CPU PLL. Link cpupll to the cpu so that frequency scaling can happen. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-v7.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index d323c1a3f3c2..4d9991294f7c 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -21,6 +21,8 @@ cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x0>; + clocks = <&cpupll>; + clock-names = "cpuclk"; }; }; From patchwork Tue Feb 23 06:18:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 12099953 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33CCAC43331 for ; Tue, 23 Feb 2021 06:21:04 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CE81B64DB1 for ; Tue, 23 Feb 2021 06:21:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CE81B64DB1 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ZUh6xhwnM1HjFpabNcCNYQ/KHF4AwheEPY7RX2nOgy0=; b=gxerCya4nt9T5jQKovDUqH+7q 8y9ks+CgGhs72Hb2QTx5cFOdk6wam+lUqfHWfh4JwJb5IssVeYVTkhjiJfEiY1G3WXlIH8hxBz7Ow 4ChhD0nrF6/6dWH/DGR+/2l6ZnALc31CUu54mN2nIG0DnVLTkp59kabLYDDISIbsAq2yiXtB56Emv Bq+SgHeokBI6cEbBT7w2yN0RnlCWPAE1KNqpHh6t4UKoefVIC+P7XHW5HY/EQ1U/vMg0AS5VcS2bQ dW0ll2yftTau8Eh1P7UdESgZLseO4gBi9mteUarApf2odlWNifxqt8PpvMwapHkIrMot2hFoHpcQO wniWwXkVg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1lER31-0006uh-4g; Tue, 23 Feb 2021 06:19:51 +0000 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1lER2c-0006mw-Tr for linux-arm-kernel@lists.infradead.org; Tue, 23 Feb 2021 06:19:27 +0000 Received: by mail-pl1-x635.google.com with SMTP id a24so9192925plm.11 for ; Mon, 22 Feb 2021 22:19:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d++YVA3eBO844Kl/OHoWYa8zWRWfXAymLgjqBL6Knr4=; b=vFAGl7k5isfUzWSj59UQ9XxA40uYRhdmVvNDxnrUzWu6FHtJTNyw0cqTm178md8yLh TsWHwYiOjHskw6l2yzhaeG+ZbGYvZa0EpXQq0EZx/4rJrMx5tPfnkcNq0l0o3/z67+mb 8xVP02vET2/tQ9CnwLCfKQhhhAa5OMwo9v0pg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d++YVA3eBO844Kl/OHoWYa8zWRWfXAymLgjqBL6Knr4=; b=twWqKPOb+JKVw1MoLiFrosLgUYMK9N7MJ8CoeELkZgU3KxmbB1yZf+HZbgC9qH6vwj TnsiVuts/ArGCHO3cMo166i/y4slqEXNlzskOuqCgq3GT13lZ9fhqGAJkWTNkeom9tM5 UhyKGAybNQ88JtwJoviKoAmDCVADY0zWV4vR9V6/vx1TDfl2VCUUlx+4l2OQc7nqc7z9 xHaCdziz++pdMdNIMu6XQZX/IErBla0PqGT4jkbn1WtuRsamY3V1o89BQ8kDj23+e1JZ CG8zZ1NI9JsvkYwevm8RL7NCAINmYx0Ze/MufHIAY53xiDdXpFw2e/0SVRfiC+jbL/WT DyvA== X-Gm-Message-State: AOAM530+Ao9kdS0S5dh1kC/XgxOUgmLbszH843LpmTownpOXavr3vS65 6hktsxXtGbTgtPEW1benJdptzQ== X-Google-Smtp-Source: ABdhPJwBsHIBaGuLGftBLh9hMsJ/IeKYQPrHF8GpHwdEz++2TYtHeK9N5CQJHYgT51bxWKcaM54eIg== X-Received: by 2002:a17:90a:1b4b:: with SMTP id q69mr25034810pjq.108.1614061164948; Mon, 22 Feb 2021 22:19:24 -0800 (PST) Received: from shiro.work (p345188-ipngn200408sizuokaden.shizuoka.ocn.ne.jp. [124.98.97.188]) by smtp.googlemail.com with ESMTPSA id n10sm20135169pgk.91.2021.02.22.22.19.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 22:19:24 -0800 (PST) From: Daniel Palmer List-Id: To: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, soc@kernel.org, sboyd@kernel.org Subject: [PATCH 5/8] ARM: mstar: Link cpupll to second core Date: Tue, 23 Feb 2021 15:18:27 +0900 Message-Id: <20210223061830.1913700-6-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210223061830.1913700-1-daniel@0x0f.com> References: <20210223061830.1913700-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210223_011927_035342_DDAE3FFF X-CRM114-Status: GOOD ( 12.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Palmer , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The second core also sources it's clock from the CPU PLL. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-infinity2m.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi index 6d4d1d224e96..dc339cd29778 100644 --- a/arch/arm/boot/dts/mstar-infinity2m.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -11,6 +11,8 @@ cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x1>; + clocks = <&cpupll>; + clock-names = "cpuclk"; }; }; From patchwork Tue Feb 23 06:18:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 12099957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A632C433E0 for ; Tue, 23 Feb 2021 06:21:10 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E8F8664DA3 for ; Tue, 23 Feb 2021 06:21:09 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E8F8664DA3 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=JoXfXiEWRhHS2jdNgwNc2kuAqkiesOiPG36OxtT3MPQ=; b=IYEB7o+Z7VnLfPNNaArHwSQFD pUntyRm5VnlusvZsKHUdyvHuVAVOve3JZHJON59JQ68TFtJ/2kuyi6vfiQLQkaIa/SWHzlwt1YDpR VILRgQXjZmNv0A0LWEFRKbCd2NSAciZZfkRV0zSzcdkMeuPSr05XeYxUmH363m8LSS7NXv7xajyDt yS1mBOh16lCZbzigc9HK5uzo+EroSMN+tY63bkNcf94ysNccjO5xp6cNTgv8Xoy81l5/wU2eV8m3R 1A3oWeoZJWGcqGKE7FuefcH4OgvGCH6qL8D3CERh3LT7hVRtW6FMvVJ6F/NwhDU1o57kbKnd8FksS 8z4vlrvAQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1lER36-0006wR-GS; Tue, 23 Feb 2021 06:19:56 +0000 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1lER2f-0006nc-2L for linux-arm-kernel@lists.infradead.org; Tue, 23 Feb 2021 06:19:32 +0000 Received: by mail-pj1-x1031.google.com with SMTP id o6so1176167pjf.5 for ; Mon, 22 Feb 2021 22:19:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SE8LvB13EoijNekrwFmw4zAb9BZgnUUKtus/CbxCO44=; b=Vzqnw822lH2lfVZnHFzXqgEjRR+CAv1klD1WlOha88yUivgU/HRzplnKxIRyISmh0c JbvmMk3JdaI2X1TDHww+2/w7j/gkEVZkZOQZS69erTcEV6JBiWyzuSXvc9JMPyGMs9Kw +Dn0H3PI6Wgd7h/fts19GzE8gCfBUHadG09JQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SE8LvB13EoijNekrwFmw4zAb9BZgnUUKtus/CbxCO44=; b=Byttl3f1I1DzbKGEigQ/Bt05ziqzMHIW9toCdSlx8+ZEAzemgXGU3mAJkH4szfaDo6 gYFfz8nUQH9iu55AbzT2d1kT4lvag5eQAAinscAu6GtVblR2IE+kNxFlCqW8g8OXP4kT nnGvtQUCeMvU+UKQZz5vod/xSSJfaOrkdcTwYNf5maugXdfy3qsnzswZFITRyGUjNpeQ QKIxM6ig7G0LoGv2nw+cJ9WkCGIkYM6kGr10hqMeVcCAGE72DAioLAcnh23fm7ag9527 Oow/psxgzkufFxufqoglDg+6DmWVnu1tfR1RQEbBIQrSykH9eVtj4i5BekOigzvjw4Hr oyXw== X-Gm-Message-State: AOAM531aX24FX5GNNxrwpdRzjAAaafV1NEfIBrxGoM9g3ZaImEkrIFsv YVFHXPUmVsct1Wzy/Xbn2aBshw== X-Google-Smtp-Source: ABdhPJzoIJDh0x+aPCJvQ3KGczLpHsrN+drRAIc5AD4BKUwfO1ZvK1x/0gzZUZpOaaY3vYvOJ8Z3MA== X-Received: by 2002:a17:90a:1d0a:: with SMTP id c10mr28899732pjd.142.1614061167210; Mon, 22 Feb 2021 22:19:27 -0800 (PST) Received: from shiro.work (p345188-ipngn200408sizuokaden.shizuoka.ocn.ne.jp. [124.98.97.188]) by smtp.googlemail.com with ESMTPSA id n10sm20135169pgk.91.2021.02.22.22.19.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 22:19:26 -0800 (PST) From: Daniel Palmer List-Id: To: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, soc@kernel.org, sboyd@kernel.org Subject: [PATCH 6/8] ARM: mstar: Add OPP table for infinity Date: Tue, 23 Feb 2021 15:18:28 +0900 Message-Id: <20210223061830.1913700-7-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210223061830.1913700-1-daniel@0x0f.com> References: <20210223061830.1913700-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210223_011929_242417_2A45A0F2 X-CRM114-Status: GOOD ( 11.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Palmer , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add an OPP table for the inifinity chips so that cpu frequency scaling can happen. Co-authored-by: Willy Tarreau Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-infinity.dtsi | 34 +++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity.dtsi b/arch/arm/boot/dts/mstar-infinity.dtsi index 0bee517797f4..441a917b88ba 100644 --- a/arch/arm/boot/dts/mstar-infinity.dtsi +++ b/arch/arm/boot/dts/mstar-infinity.dtsi @@ -8,6 +8,40 @@ #include +/ { + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu0_opp_table>; +}; + &imi { reg = <0xa0000000 0x16000>; }; From patchwork Tue Feb 23 06:18:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 12099959 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93544C433DB for ; Tue, 23 Feb 2021 06:21:10 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3FF6C64DB1 for ; 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[124.98.97.188]) by smtp.googlemail.com with ESMTPSA id n10sm20135169pgk.91.2021.02.22.22.19.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 22:19:29 -0800 (PST) From: Daniel Palmer List-Id: To: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, soc@kernel.org, sboyd@kernel.org Subject: [PATCH 7/8] ARM: mstar: Add OPP table for infinity3 Date: Tue, 23 Feb 2021 15:18:29 +0900 Message-Id: <20210223061830.1913700-8-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210223061830.1913700-1-daniel@0x0f.com> References: <20210223061830.1913700-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210223_011932_937984_D12B9AC4 X-CRM114-Status: GOOD ( 11.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Palmer , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The infinity3 has a slightly higher max frequency compared to the infinity so extend the OPP table. Co-authored-by: Willy Tarreau Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-infinity3.dtsi | 58 ++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm/boot/dts/mstar-infinity3.dtsi b/arch/arm/boot/dts/mstar-infinity3.dtsi index 9857e2a9934d..a56cf29e5d82 100644 --- a/arch/arm/boot/dts/mstar-infinity3.dtsi +++ b/arch/arm/boot/dts/mstar-infinity3.dtsi @@ -6,6 +6,64 @@ #include "mstar-infinity.dtsi" +&cpu0_opp_table { + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + }; + + // overclock frequencies below, shown to work fine up to 1.3 GHz + opp-108000000 { + opp-hz = /bits/ 64 <1080000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1188000000 { + opp-hz = /bits/ 64 <1188000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1350000000 { + opp-hz = /bits/ 64 <1350000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1404000000 { + opp-hz = /bits/ 64 <1404000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1458000000 { + opp-hz = /bits/ 64 <1458000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; + + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <300000>; + turbo-mode; + }; +}; + &imi { reg = <0xa0000000 0x20000>; }; From patchwork Tue Feb 23 06:18:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 12099961 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F9BAC433E0 for ; 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[124.98.97.188]) by smtp.googlemail.com with ESMTPSA id n10sm20135169pgk.91.2021.02.22.22.19.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Feb 2021 22:19:31 -0800 (PST) From: Daniel Palmer List-Id: To: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, soc@kernel.org, sboyd@kernel.org Subject: [PATCH 8/8] ARM: mstar: Add OPP table for mercury5 Date: Tue, 23 Feb 2021 15:18:30 +0900 Message-Id: <20210223061830.1913700-9-daniel@0x0f.com> X-Mailer: git-send-email 2.30.0.rc2 In-Reply-To: <20210223061830.1913700-1-daniel@0x0f.com> References: <20210223061830.1913700-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210223_011934_254354_00D6330F X-CRM114-Status: GOOD ( 11.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Palmer , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, w@1wt.eu Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add an OPP table for mercury5 so that cpu frequency scaling can happen. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-mercury5.dtsi | 36 +++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/mstar-mercury5.dtsi b/arch/arm/boot/dts/mstar-mercury5.dtsi index a7d0dd9d6132..80a19bd23c9c 100644 --- a/arch/arm/boot/dts/mstar-mercury5.dtsi +++ b/arch/arm/boot/dts/mstar-mercury5.dtsi @@ -6,6 +6,42 @@ #include "mstar-v7.dtsi" +/ { + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <800000 800000 850000>; + clock-latency-ns = <300000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <850000 850000 880000>; + clock-latency-ns = <300000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <880000 880000 890000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 900000 1000000>; + clock-latency-ns = <300000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000 900000 1000000>; + clock-latency-ns = <300000>; + }; + }; +}; + &imi { reg = <0xa0000000 0x20000>; };