From patchwork Tue Feb 23 18:08:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= X-Patchwork-Id: 12100663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CBB4C433DB for ; Tue, 23 Feb 2021 18:09:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 06699600EF for ; Tue, 23 Feb 2021 18:09:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233843AbhBWSJ2 (ORCPT ); Tue, 23 Feb 2021 13:09:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233167AbhBWSJ0 (ORCPT ); Tue, 23 Feb 2021 13:09:26 -0500 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2A98C06174A; Tue, 23 Feb 2021 10:08:45 -0800 (PST) Received: by mail-wr1-x432.google.com with SMTP id t15so23460846wrx.13; Tue, 23 Feb 2021 10:08:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FDqNjV640N+fZG6ZT5uNH9gvHou59xVjyGD1FaFKSKs=; b=LGhnwtAw4zed9PSaqk2CtUiHjfHnnl6F+qdH+thJyJkKkJNFplPPAhxYnvXXXwUAqJ HG49/53GpnXRy7UcEtVYC+HzZ9NzIVz4RmVYOPZkkRgfvWVUbOOCJ9YMm44Tm/JW7QtL ndkpJE5eD3lsECnpCIr9SU8HqjWmycBbowTcdvkDdLWSzFH1i7xOVAByxoGl2ooy/sR3 QCrelWOUSpl5bo5rS+oVXLWqQa5NP7IfAUT9vLhI40KgYbRKbYnzhG1s0Uim1OZqVO+M MLJ+bXDHjmki6NQJXTl7Rxgrq57aDRrEXWmeaeCKJ3Yi4BlDy1njL03INcRJ8o4CB0tT 4VQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FDqNjV640N+fZG6ZT5uNH9gvHou59xVjyGD1FaFKSKs=; b=GVNDWej7CqDYz2933h1gW3SoW8sL+y5VAEuOm0ADKrssC0J+mc9KPKsSBzraVGLgll +EE7H7JfZxMT1f2+EemgcwJ5ONUiSemYFgtXgPqvIdU+1h07IFAvwYeuezYFq0RCIZ1I yax0R/e3cEIPqzd20hOA5X6+WIVfV2eIJEEEuto2z7rB8RQhMOk5IgzGZ3thoViheLvj jNbJUYL5/GhBYWkylLw5VLpiuVvWbkgmEkJKfwSNtPcedwzOSGq8k1k2f3tqzvnbrp1n Yor52pg20BsqH+uSUA2nu8eDZijKzi9uM8Sb8h/lejcLPlPSLQ5hpjcFIzruwYEoizHj esqQ== X-Gm-Message-State: AOAM530OyNYbNuhLcLqHGoepNabU3l+Frjf7k22dUS84ea3czvkceq7V 7UU/KF077BSHlTY5/APeSW4= X-Google-Smtp-Source: ABdhPJyXpcpT5q48IXHL8o184o4yW+1nqBkQnC8Hl86JYaiCTWzeiJZmwqWs0sZx7Pq8D7WnBwKElw== X-Received: by 2002:adf:e8c2:: with SMTP id k2mr6450124wrn.401.1614103724535; Tue, 23 Feb 2021 10:08:44 -0800 (PST) Received: from skynet.lan (170.red-88-1-105.dynamicip.rima-tde.net. [88.1.105.170]) by smtp.gmail.com with ESMTPSA id v18sm31101709wrf.75.2021.02.23.10.08.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Feb 2021 10:08:44 -0800 (PST) From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= To: Thomas Gleixner , Marc Zyngier , Rob Herring , Florian Fainelli , =?utf-8?q?Fern=C3=A1ndez_Rojas?= , Jonas Gorski , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-mips@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: interrupt-controller: document BCM6345 external interrupt controller Date: Tue, 23 Feb 2021 19:08:39 +0100 Message-Id: <20210223180840.28771-2-noltari@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210223180840.28771-1-noltari@gmail.com> References: <20210223180840.28771-1-noltari@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Document the binding for the BCM6345 external interrupt controller. Signed-off-by: Álvaro Fernández Rojas Signed-off-by: Jonas Gorski Reported-by: kernel test robot --- .../brcm,bcm6345-ext-intc.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.yaml new file mode 100644 index 000000000000..9cc29fa03968 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/brcm,brcm6345-ext-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM6345 external interrupt controller + +maintainers: + - Álvaro Fernández Rojas + - Jonas Gorski + +properties: + compatible: + enum: + - brcm,bcm6318-ext-intc + - brcm,bcm6345-ext-intc + + interrupt-parent: + description: Specifies the phandle to the parent interrupt controller + this one is cascaded from. + + "#interrupt-cells": + const: 2 + + reg: + maxItems: 1 + + "#address-cells": + const: 0 + + interrupt-controller: true + + interrupts: + description: Specifies the interrupt line(s) in the interrupt-parent + controller node, valid values depend on the type of parent interrupt + controller. + maxItems: 4 + +required: + - compatible + - interrupt-parent + - "#interrupt-cells" + - reg + - "#address-cells" + - interrupt-controller + - interrupts + +additionalProperties: false + +examples: + - | + ext_intc: interrupt-controller@10000018 { + compatible = "brcm,bcm6345-ext-intc"; + interrupt-parent = <&periph_intc>; + #interrupt-cells = <2>; + reg = <0x10000018 0x4>; + #address-cells = <0>; + interrupt-controller; + interrupts = <24>, <25>, <26>, <27>; + }; From patchwork Tue Feb 23 18:08:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= X-Patchwork-Id: 12100665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0E1EC433E0 for ; Tue, 23 Feb 2021 18:09:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6B468600EF for ; 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[88.1.105.170]) by smtp.gmail.com with ESMTPSA id v18sm31101709wrf.75.2021.02.23.10.08.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Feb 2021 10:08:45 -0800 (PST) From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= To: Thomas Gleixner , Marc Zyngier , Rob Herring , Florian Fainelli , =?utf-8?q?Fern=C3=A1ndez_Rojas?= , Jonas Gorski , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-mips@vger.kernel.org Subject: [PATCH 2/2] irqchip: add support for BCM6345 interrupt controller Date: Tue, 23 Feb 2021 19:08:40 +0100 Message-Id: <20210223180840.28771-3-noltari@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210223180840.28771-1-noltari@gmail.com> References: <20210223180840.28771-1-noltari@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org This interrupt controller is present on bcm63xx SoCs in order to generate interrupts based on GPIO status changes. Signed-off-by: Álvaro Fernández Rojas Signed-off-by: Jonas Gorski Reported-by: kernel test robot --- drivers/irqchip/Kconfig | 4 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-bcm6345-ext.c | 271 ++++++++++++++++++++++++++++++ 3 files changed, 276 insertions(+) create mode 100644 drivers/irqchip/irq-bcm6345-ext.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index e74fa206240a..eaa101939a34 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -113,6 +113,10 @@ config I8259 bool select IRQ_DOMAIN +config BCM6345_EXT_IRQ + bool "BCM6345 External IRQ Controller" + select IRQ_DOMAIN + config BCM6345_L1_IRQ bool select GENERIC_IRQ_CHIP diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index c59b95a0532c..3cba65bc0aa5 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -62,6 +62,7 @@ obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o obj-$(CONFIG_XILINX_INTC) += irq-xilinx-intc.o obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o obj-$(CONFIG_SOC_VF610) += irq-vf610-mscm-ir.o +obj-$(CONFIG_BCM6345_EXT_IRQ) += irq-bcm6345-ext.o obj-$(CONFIG_BCM6345_L1_IRQ) += irq-bcm6345-l1.o obj-$(CONFIG_BCM7038_L1_IRQ) += irq-bcm7038-l1.o obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o diff --git a/drivers/irqchip/irq-bcm6345-ext.c b/drivers/irqchip/irq-bcm6345-ext.c new file mode 100644 index 000000000000..5721ac8de295 --- /dev/null +++ b/drivers/irqchip/irq-bcm6345-ext.c @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Broadcom BCM6345 style external interrupt controller driver + * + * Copyright (C) 2021 Álvaro Fernández Rojas + * Copyright (C) 2014 Jonas Gorski + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_IRQS 4 + +#define EXTIRQ_CFG_SENSE 0 +#define EXTIRQ_CFG_STAT 1 +#define EXTIRQ_CFG_CLEAR 2 +#define EXTIRQ_CFG_MASK 3 +#define EXTIRQ_CFG_BOTHEDGE 4 +#define EXTIRQ_CFG_LEVELSENSE 5 + +struct intc_data { + struct irq_chip chip; + struct irq_domain *domain; + raw_spinlock_t lock; + + int parent_irq[MAX_IRQS]; + void __iomem *reg; + int shift; + unsigned int toggle_clear_on_ack:1; +}; + +static void bcm6345_ext_intc_irq_handle(struct irq_desc *desc) +{ + struct intc_data *data = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned int irq = irq_desc_get_irq(desc); + unsigned int idx; + + chained_irq_enter(chip, desc); + + for (idx = 0; idx < MAX_IRQS; idx++) { + if (data->parent_irq[idx] != irq) + continue; + + generic_handle_irq(irq_find_mapping(data->domain, idx)); + } + + chained_irq_exit(chip, desc); +} + +static void bcm6345_ext_intc_irq_ack(struct irq_data *data) +{ + struct intc_data *priv = data->domain->host_data; + irq_hw_number_t hwirq = irqd_to_hwirq(data); + u32 reg; + + raw_spin_lock(&priv->lock); + reg = __raw_readl(priv->reg); + __raw_writel(reg | (1 << (hwirq + EXTIRQ_CFG_CLEAR * priv->shift)), + priv->reg); + if (priv->toggle_clear_on_ack) + __raw_writel(reg, priv->reg); + raw_spin_unlock(&priv->lock); +} + +static void bcm6345_ext_intc_irq_mask(struct irq_data *data) +{ + struct intc_data *priv = data->domain->host_data; + irq_hw_number_t hwirq = irqd_to_hwirq(data); + u32 reg; + + raw_spin_lock(&priv->lock); + reg = __raw_readl(priv->reg); + reg &= ~(1 << (hwirq + EXTIRQ_CFG_MASK * priv->shift)); + __raw_writel(reg, priv->reg); + raw_spin_unlock(&priv->lock); +} + +static void bcm6345_ext_intc_irq_unmask(struct irq_data *data) +{ + struct intc_data *priv = data->domain->host_data; + irq_hw_number_t hwirq = irqd_to_hwirq(data); + u32 reg; + + raw_spin_lock(&priv->lock); + reg = __raw_readl(priv->reg); + reg |= 1 << (hwirq + EXTIRQ_CFG_MASK * priv->shift); + __raw_writel(reg, priv->reg); + raw_spin_unlock(&priv->lock); +} + +static int bcm6345_ext_intc_set_type(struct irq_data *data, + unsigned int flow_type) +{ + struct intc_data *priv = data->domain->host_data; + irq_hw_number_t hwirq = irqd_to_hwirq(data); + bool levelsense = 0, sense = 0, bothedge = 0; + u32 reg; + + flow_type &= IRQ_TYPE_SENSE_MASK; + + if (flow_type == IRQ_TYPE_NONE) + flow_type = IRQ_TYPE_LEVEL_LOW; + + switch (flow_type) { + case IRQ_TYPE_EDGE_BOTH: + bothedge = 1; + break; + + case IRQ_TYPE_EDGE_RISING: + sense = 1; + break; + + case IRQ_TYPE_EDGE_FALLING: + break; + + case IRQ_TYPE_LEVEL_HIGH: + levelsense = 1; + sense = 1; + break; + + case IRQ_TYPE_LEVEL_LOW: + levelsense = 1; + break; + + default: + pr_err("bogus flow type combination given!\n"); + return -EINVAL; + } + + raw_spin_lock(&priv->lock); + reg = __raw_readl(priv->reg); + + if (levelsense) + reg |= 1 << (hwirq + EXTIRQ_CFG_LEVELSENSE * priv->shift); + else + reg &= ~(1 << (hwirq + EXTIRQ_CFG_LEVELSENSE * priv->shift)); + if (sense) + reg |= 1 << (hwirq + EXTIRQ_CFG_SENSE * priv->shift); + else + reg &= ~(1 << (hwirq + EXTIRQ_CFG_SENSE * priv->shift)); + if (bothedge) + reg |= 1 << (hwirq + EXTIRQ_CFG_BOTHEDGE * priv->shift); + else + reg &= ~(1 << (hwirq + EXTIRQ_CFG_BOTHEDGE * priv->shift)); + + __raw_writel(reg, priv->reg); + raw_spin_unlock(&priv->lock); + + irqd_set_trigger_type(data, flow_type); + if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + irq_set_handler_locked(data, handle_level_irq); + else + irq_set_handler_locked(data, handle_edge_irq); + + return 0; +} + +static int bcm6345_ext_intc_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hw) +{ + struct intc_data *priv = d->host_data; + + irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq); + + return 0; +} + +static const struct irq_domain_ops bcm6345_ext_domain_ops = { + .xlate = irq_domain_xlate_twocell, + .map = bcm6345_ext_intc_map, +}; + +static int __init bcm6345_ext_intc_init(struct device_node *node, + int num_irqs, int *irqs, + void __iomem *reg, int shift, + bool toggle_clear_on_ack) +{ + struct intc_data *data; + unsigned int i; + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + raw_spin_lock_init(&data->lock); + + for (i = 0; i < num_irqs; i++) { + data->parent_irq[i] = irqs[i]; + + irq_set_handler_data(irqs[i], data); + irq_set_chained_handler(irqs[i], bcm6345_ext_intc_irq_handle); + } + + data->reg = reg; + data->shift = shift; + data->toggle_clear_on_ack = toggle_clear_on_ack; + + data->chip.name = "bcm6345-ext-intc"; + data->chip.irq_ack = bcm6345_ext_intc_irq_ack; + data->chip.irq_mask = bcm6345_ext_intc_irq_mask; + data->chip.irq_unmask = bcm6345_ext_intc_irq_unmask; + data->chip.irq_set_type = bcm6345_ext_intc_set_type; + + data->domain = irq_domain_add_simple(node, num_irqs, 0, + &bcm6345_ext_domain_ops, data); + if (!data->domain) { + kfree(data); + return -ENOMEM; + } + + return 0; +} + +static int __init bcm6345_ext_intc_of_init(struct device_node *node, + struct device_node *parent) +{ + int num_irqs, ret = -EINVAL; + unsigned i; + void __iomem *base; + int irqs[MAX_IRQS] = { 0 }; + u32 shift; + bool toggle_clear_on_ack = false; + + num_irqs = of_irq_count(node); + + if (!num_irqs || num_irqs > MAX_IRQS) + return -EINVAL; + + if (of_property_read_u32(node, "brcm,field-width", &shift)) + shift = 4; + + /* On BCM6318 setting CLEAR seems to continuously mask interrupts */ + if (of_device_is_compatible(node, "brcm,bcm6318-ext-intc")) + toggle_clear_on_ack = true; + + for (i = 0; i < num_irqs; i++) { + irqs[i] = irq_of_parse_and_map(node, i); + if (!irqs[i]) + return -ENOMEM; + } + + base = of_iomap(node, 0); + if (!base) + return -ENXIO; + + ret = bcm6345_ext_intc_init(node, num_irqs, irqs, base, shift, + toggle_clear_on_ack); + if (!ret) + return 0; + + iounmap(base); + + for (i = 0; i < num_irqs; i++) + irq_dispose_mapping(irqs[i]); + + return ret; +} + +IRQCHIP_DECLARE(bcm6318_ext_intc, "brcm,bcm6318-ext-intc", + bcm6345_ext_intc_of_init); +IRQCHIP_DECLARE(bcm6345_ext_intc, "brcm,bcm6345-ext-intc", + bcm6345_ext_intc_of_init);