From patchwork Wed Feb 24 11:51:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12101775 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 569CEC433E6 for ; Wed, 24 Feb 2021 11:53:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EDED264EDD for ; Wed, 24 Feb 2021 11:52:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235123AbhBXLwp (ORCPT ); Wed, 24 Feb 2021 06:52:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49978 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235098AbhBXLwl (ORCPT ); Wed, 24 Feb 2021 06:52:41 -0500 Received: from mail-il1-x133.google.com (mail-il1-x133.google.com [IPv6:2607:f8b0:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A5AAC061574; Wed, 24 Feb 2021 03:52:01 -0800 (PST) Received: by mail-il1-x133.google.com with SMTP id e7so1447127ile.7; Wed, 24 Feb 2021 03:52:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=OtHK69XqkhA/jaimkYAZVFJcI+Rth0y3HJjsnP3488w=; b=p6YouBi4v9Djk6ErV7x33qioAlZ0X7OYOH3AJ3PPrA6oQGmvhEBBrObEb9705BQ9px 7ShymZDY9xabTp49q6bXX6LCczJrgV0mRtq0+XxGTduYe0RlkLwSd+rKnY8HCINjyUSp wDff1dVd0l1QAVdvZm88OZulH88XcSFrvX88f+X//taO88PZpzgC9FUWxnMlNjSxG64s KDC/YETZF32ny7cRuh4TpjaYgU/lH6UUwGDL/pYh7mSVxJzkNQX1tI4EQMuAS9q19glN oL6bI4PQTpGqu59HaPv0jPjX/OKkmodHoEv2zzttur8UtzLpjZLz7e8QMrUU0235ULTa U56Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=OtHK69XqkhA/jaimkYAZVFJcI+Rth0y3HJjsnP3488w=; b=IusHhjrq4kNyqX5mwPejYalB3Dm6uX7hF8rlaXhkhMiUQoO2ZSZ8ozPTgr0+bRNXeS o6iZuxlpI3Okxl0CLhPjK/i6c+wbts7ifZE99k8+cxiB0ExeFwaa4KgEOTyMzMTLszKq K4lWaQqLI84d1SnIHW5Kw5pbiFd+eIbQhqdFYzlVVv07Lbi571h2d4Ftt2IRkEZg5xGk 1GLGoavVGazD0j0dLfzgB7vs4c1EU8VdsESLNznqR3lfihkOpUMK5kt1YFANmyeZuQkF LpkYWYE6fPUrqMOwdkAP/OfN9Ii07yBkhCCHMZXssivdW6L9Afl6Kn7fjgy56zDpy2II oiJQ== X-Gm-Message-State: AOAM530ujieGiJG5aIOpH0fP2k8gQ4CC5mgsaIKYTk2YPCyKP16VCojh kuw0F1ymepwHMslK9lHfTMc+rwnxLMbiWA== X-Google-Smtp-Source: ABdhPJzjsLFyNlnOmCTyp4PANPyxSx8kr/XE/dEokyVc0yA4BsshfRoDgHmm5Sm+oq0EW2fZySWWuw== X-Received: by 2002:a05:6e02:20e8:: with SMTP id q8mr23219551ilv.205.1614167520501; Wed, 24 Feb 2021 03:52:00 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:de9c:d296:189b:385a]) by smtp.gmail.com with ESMTPSA id l16sm1500001ils.11.2021.02.24.03.51.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Feb 2021 03:52:00 -0800 (PST) From: Adam Ford To: netdev@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Geert Uytterhoeven , Rob Herring , Sergei Shtylyov , "David S. Miller" , Jakub Kicinski , Rob Herring , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 1/5] dt-bindings: net: renesas,etheravb: Add additional clocks Date: Wed, 24 Feb 2021 05:51:41 -0600 Message-Id: <20210224115146.9131-1-aford173@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The AVB driver assumes there is an external crystal, but it could be clocked by other means. In order to enable a programmable clock, it needs to be added to the clocks list and enabled in the driver. Since there currently only one clock, there is no clock-names list either. Update bindings to add the additional optional clock, and explicitly name both of them. Signed-off-by: Adam Ford Reviewed-by: Geert Uytterhoeven Acked-by: Rob Herring Reviewed-by: Sergei Shtylyov --- V3: No Change V2: No Change diff --git a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml index de9dd574a2f9..7b32363ad8b4 100644 --- a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml +++ b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml @@ -49,7 +49,16 @@ properties: interrupt-names: true clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 + items: + - description: AVB functional clock + - description: Optional TXC reference clock + + clock-names: + items: + - const: fck + - const: refclk iommus: maxItems: 1 From patchwork Wed Feb 24 11:51:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12101777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAA31C4332D for ; Wed, 24 Feb 2021 11:53:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B78C564ED6 for ; Wed, 24 Feb 2021 11:53:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235154AbhBXLwt (ORCPT ); Wed, 24 Feb 2021 06:52:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235121AbhBXLwo (ORCPT ); Wed, 24 Feb 2021 06:52:44 -0500 Received: from mail-io1-xd29.google.com (mail-io1-xd29.google.com [IPv6:2607:f8b0:4864:20::d29]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1518DC06174A; Wed, 24 Feb 2021 03:52:04 -0800 (PST) Received: by mail-io1-xd29.google.com with SMTP id y202so1708856iof.1; Wed, 24 Feb 2021 03:52:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=o65TUS3eViNoH1/o8q9/8liYwdZx2oTvg/nkERWMHtU=; b=nkOH4+uQQYtUnFA/AuqMEmpTHZsJVuTfAbOLZm+yFHKbfIcMd9Q12EyiB4af8SMX8e 318DgJ5x4F/Qp7G0KArHL9+uK53+yvVBRCiBe1M8ovPfxeUUyJkkUmM1zyXW+taC1dYB a6wcg/BibceaW73Gnui/Bsr3WAJELrtcgHiJtPcYnANOnQdnmiZyguKM5NaLhY9Ku+dI xsVYdc3wANU12JQBZTQOQe8IfKzs9MjNv8wfrk39DpVPsaF5ed6egsa8yO4Zbc7Lk1EP P/3HKZHkX+H0wzPgtWM+3w7LCQFokhfZyV1hP98VPjxPENTMDuRnmeWNsk36obAb/COT CPsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o65TUS3eViNoH1/o8q9/8liYwdZx2oTvg/nkERWMHtU=; b=cfozAv7mzAfje8i8gf1fr/BTWXGimsecRSw9O4So31K91rl8kaE7eSbTPwM7rzht+L SPRrHVFjcTzLy1cSh4CNDGWfg9NxEz2xAvUn+9C+ORAyRtGJZ9tskt/kMI9pwpBN1qgU kcwMt/dNvSFC0brPAIPNd2G1VzkAw4By90JV2X/quN21KscTHbaTZnEvuXYHEQ1sOo+u dC0KoTtP465gXzn39nrtQeI5sBRlC69IY5Aeoa2Frn2FDbnoHcZWjwFj6jl7It+qdbKa gfpYAz2d40CrAVlCgKi/HRFNHHEZrBLO7McU21wBtO82Qq+LnR1seyiuDnBv5q3/Z45p 57Qg== X-Gm-Message-State: AOAM532L0mKURUHBNFGtMzcHEiEJ6q02KBXrJ2L0KMOkjP+XA1rVlgga zvUXJk8yqAPDoq4fda34TNCFpRGQAcEBYA== X-Google-Smtp-Source: ABdhPJwxsG+6DFP2AY8TOGhSVHWhZRB9tbSGSvDBlHSP+At4BssZ9j6vHDBhbIf9XPi99a5YdcEH8Q== X-Received: by 2002:a6b:c997:: with SMTP id z145mr2945563iof.36.1614167523184; Wed, 24 Feb 2021 03:52:03 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:de9c:d296:189b:385a]) by smtp.gmail.com with ESMTPSA id l16sm1500001ils.11.2021.02.24.03.52.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Feb 2021 03:52:02 -0800 (PST) From: Adam Ford To: netdev@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Geert Uytterhoeven , Sergei Shtylyov , "David S. Miller" , Jakub Kicinski , Rob Herring , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 2/5] ARM: dts: renesas: Add fck to etheravb-rcar-gen2 clock-names list Date: Wed, 24 Feb 2021 05:51:42 -0600 Message-Id: <20210224115146.9131-2-aford173@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210224115146.9131-1-aford173@gmail.com> References: <20210224115146.9131-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The bindings have been updated to support two clocks, but the original clock now requires the name fck. Add a clock-names list in the device tree with fck in it. Signed-off-by: Adam Ford Reviewed-by: Geert Uytterhoeven Reviewed-by: Andrew Lunn --- V3: No Change V2: No Change diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 6a78c813057b..6b922f664fcd 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -750,6 +750,7 @@ avb: ethernet@e6800000 { reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index f444e418f408..084bf3e039cf 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -702,6 +702,7 @@ avb: ethernet@e6800000 { reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 0442aad4f9db..d01eba99ceb0 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -702,6 +702,7 @@ avb: ethernet@e6800000 { reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 0f14ac22921d..d0d45a369047 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -645,6 +645,7 @@ avb: ethernet@e6800000 { reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index 691b1a131c87..ae90a001d663 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -537,6 +537,7 @@ avb: ethernet@e6800000 { reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index b0569b4ea5c8..af9cd3324f4c 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -768,6 +768,7 @@ avb: ethernet@e6800000 { reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 87f0d6dc3e5a..2354af7fa83f 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -728,6 +728,7 @@ avb: ethernet@e6800000 { reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index f5b299bfcb23..60c184ab1b49 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -537,6 +537,7 @@ avb: ethernet@e6800000 { reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index cd5e2904068a..18cc6f6b588d 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -598,6 +598,7 @@ avb: ethernet@e6800000 { reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; resets = <&cpg 812>; #address-cells = <1>; From patchwork Wed Feb 24 11:51:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12101779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58955C433E0 for ; Wed, 24 Feb 2021 11:53:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 102AE64E90 for ; Wed, 24 Feb 2021 11:53:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235171AbhBXLxE (ORCPT ); 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Wed, 24 Feb 2021 03:52:05 -0800 (PST) From: Adam Ford To: netdev@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Geert Uytterhoeven , Sergei Shtylyov , "David S. Miller" , Jakub Kicinski , Rob Herring , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 3/5] arm64: dts: renesas: Add fck to etheravb-rcar-gen3 clock-names list Date: Wed, 24 Feb 2021 05:51:43 -0600 Message-Id: <20210224115146.9131-3-aford173@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210224115146.9131-1-aford173@gmail.com> References: <20210224115146.9131-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The bindings have been updated to support two clocks, but the original clock now requires the name fck. Add a clock-names list in the device tree with fck in it. Signed-off-by: Adam Ford Reviewed-by: Geert Uytterhoeven Reviewed-by: Andrew Lunn --- V3: No Change V2: No Change diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index d64fb8b1b86c..ec4feb7df775 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -1127,6 +1127,7 @@ avb: ethernet@e6800000 { "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 5b05474dc272..1ff62b2be1f3 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -1001,6 +1001,7 @@ avb: ethernet@e6800000 { "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 20fa3caa050e..a4d9c6b31574 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -957,6 +957,7 @@ avb: ethernet@e6800000 { "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 8eb006cbd9af..fec5839163ec 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1230,6 +1230,7 @@ avb: ethernet@e6800000 { "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 5c39152e4570..1e622ab8a044 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -1312,6 +1312,7 @@ avb: ethernet@e6800000 { "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 25d947a81b29..a3d1c33cbc1d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -1188,6 +1188,7 @@ avb: ethernet@e6800000 { "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index e8c31ebec097..55a3ba3c844f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1144,6 +1144,7 @@ avb: ethernet@e6800000 { "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 657b20d3533b..dd4c0e621b9c 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1050,6 +1050,7 @@ avb: ethernet@e6800000 { "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 5a5d5649332a..d4b0b9952619 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -612,6 +612,7 @@ avb: ethernet@e6800000 { "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index ec7ca72399ec..992a577a3b17 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -664,6 +664,7 @@ avb: ethernet@e6800000 { "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 5010f23fafcc..cc56267e0850 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1000,6 +1000,7 @@ avb: ethernet@e6800000 { "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 812>; phy-mode = "rgmii"; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 2319271c881b..84dba3719381 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -760,6 +760,7 @@ avb: ethernet@e6800000 { "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; + clock-names = "fck"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 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Wed, 24 Feb 2021 03:52:08 -0800 (PST) From: Adam Ford To: netdev@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Sergei Shtylyov , "David S. Miller" , Jakub Kicinski , Rob Herring , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 4/5] net: ethernet: ravb: Enable optional refclk Date: Wed, 24 Feb 2021 05:51:44 -0600 Message-Id: <20210224115146.9131-4-aford173@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210224115146.9131-1-aford173@gmail.com> References: <20210224115146.9131-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org For devices that use a programmable clock for the AVB reference clock, the driver may need to enable them. Add code to find the optional clock and enable it when available. Signed-off-by: Adam Ford Reviewed-by: Andrew Lunn --- V3: Change 'avb' to 'AVB' Remove unnessary else statement and pointer maniupluation when enabling the refclock. Add disable_unprepare call in remove funtion. V2: The previous patch to fetch the fclk was dropped. In its place is code to enable the refclk diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h index 7453b17a37a2..ff363797bd2b 100644 --- a/drivers/net/ethernet/renesas/ravb.h +++ b/drivers/net/ethernet/renesas/ravb.h @@ -994,6 +994,7 @@ struct ravb_private { struct platform_device *pdev; void __iomem *addr; struct clk *clk; + struct clk *refclk; struct mdiobb_ctrl mdiobb; u32 num_rx_ring[NUM_RX_QUEUE]; u32 num_tx_ring[NUM_TX_QUEUE]; diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c index bd30505fbc57..614448e6eb24 100644 --- a/drivers/net/ethernet/renesas/ravb_main.c +++ b/drivers/net/ethernet/renesas/ravb_main.c @@ -2148,6 +2148,13 @@ static int ravb_probe(struct platform_device *pdev) goto out_release; } + priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); + if (IS_ERR(priv->refclk)) { + error = PTR_ERR(priv->refclk); + goto out_release; + } + clk_prepare_enable(priv->refclk); + ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); ndev->min_mtu = ETH_MIN_MTU; @@ -2260,6 +2267,9 @@ static int ravb_remove(struct platform_device *pdev) if (priv->chip_id != RCAR_GEN2) ravb_ptp_stop(ndev); + if (priv->refclk) + clk_disable_unprepare(priv->refclk); + dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, priv->desc_bat_dma); /* Set reset mode */ From patchwork Wed Feb 24 11:51:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 12101783 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF37EC433E6 for ; Wed, 24 Feb 2021 11:54:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8A67764DF3 for ; Wed, 24 Feb 2021 11:54:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233445AbhBXLyA (ORCPT ); Wed, 24 Feb 2021 06:54:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235187AbhBXLxW (ORCPT ); Wed, 24 Feb 2021 06:53:22 -0500 Received: from mail-io1-xd31.google.com (mail-io1-xd31.google.com [IPv6:2607:f8b0:4864:20::d31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02B3DC06178C; Wed, 24 Feb 2021 03:52:12 -0800 (PST) Received: by mail-io1-xd31.google.com with SMTP id u20so1669209iot.9; Wed, 24 Feb 2021 03:52:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Vv8e+Q64O0YOnZPfFWuAU+JcY2c3un2uq0nf6BdI8TQ=; b=WUHmJpGd4JhuzwHrZklF4hnBIt30FW+aVavOfZzmRidKN66gbK85O+iCO9OGeZCn5J YHV0isOxRHoayg74DqGLs/GWDcKgbK6t2J6G5Nt29E91ILFf0HqMSmEUYhmpWAxB+puA zbv2uShMy5NN/a4zorI2zEjDf+FThgiEOAw40qrmnFo47KWHNdzeWHHUMCXkH0VOjjQ2 NHAlPGKLkXcEoS1S+voO5lt2aVqaqQGh1rjgYZv4AgichI4jlJZhZKpa8b4RJpBtF8Kx JirQu+CWF+s1lTvXW6+W3tUv5ZZQcGjFP0efAkDVZwCBlT7zkD8M1LdDQa1Li7UuZVQ7 sekg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Vv8e+Q64O0YOnZPfFWuAU+JcY2c3un2uq0nf6BdI8TQ=; b=d3ZRd+b16KbI3/FCm6kQiKDZVefs+Pgla/dlTLT/cII73ufqQAdfn/JSKO7OE2yyU7 e0/yxpmtZCu+sgXCN0BgO2ldXEfjnQsoyTG7aHM/AvGaCAz6NIM3eIEk44rA9y+ko+HA qVvuM9lOKB3hrDZLOHp5u6w2RY+p78ceUwKx8sOXgqGPt7aRoUMg2A61QcAs0hyrIlZE Wu9hh0XEMHX5GEOG+5wJvQEPjRgmyXuVw0jVwjeBIFpeexe9j0qJ0Od3giWEkgjFS0aQ MCBa2BOdF248YPwbh42k6/dGCAGPadMShaB/zNihwIeRrPDIiXG8CjJsXl1Vj96ujb9m +2/w== X-Gm-Message-State: AOAM532aat3Yzk7966ZD8wmpNCwMaCELXuKh1/IJoyJ17Td2woXZx3eQ sN571YccM5f4/ptLcGvWtCn2jVxKLUa+Fw== X-Google-Smtp-Source: ABdhPJzqMuYbUTFoFmYyOX4XzjuCRsBxFbouWEUNy31yHTK43kr8jwYdhgn296WX4/ec6XTGuNPzEA== X-Received: by 2002:a6b:b415:: with SMTP id d21mr1377811iof.149.1614167531229; Wed, 24 Feb 2021 03:52:11 -0800 (PST) Received: from aford-IdeaCentre-A730.lan ([2601:448:8400:9e8:de9c:d296:189b:385a]) by smtp.gmail.com with ESMTPSA id l16sm1500001ils.11.2021.02.24.03.52.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Feb 2021 03:52:10 -0800 (PST) From: Adam Ford To: netdev@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Sergei Shtylyov , "David S. Miller" , Jakub Kicinski , Rob Herring , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 5/5] arm64: dts: renesas: beacon kits: Setup AVB refclk Date: Wed, 24 Feb 2021 05:51:45 -0600 Message-Id: <20210224115146.9131-5-aford173@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210224115146.9131-1-aford173@gmail.com> References: <20210224115146.9131-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The AVB refererence clock assumes an external clock that runs automatically. Because the Versaclock is wired to provide the AVB refclock, the device tree needs to reference it in order for the driver to start the clock. Signed-off-by: Adam Ford Reviewed-by: Geert Uytterhoeven --- V3: New to series diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi index 8d3a4d6ee885..75355c354c38 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-som.dtsi @@ -53,6 +53,8 @@ &avb { phy-handle = <&phy0>; rx-internal-delay-ps = <1800>; tx-internal-delay-ps = <2000>; + clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>; + clock-names = "fck", "refclk"; status = "okay"; phy0: ethernet-phy@0 {