From patchwork Fri Feb 26 08:49:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wang Xingang X-Patchwork-Id: 12106123 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6CF40C433DB for ; Fri, 26 Feb 2021 08:51:48 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F15B464EC3 for ; Fri, 26 Feb 2021 08:51:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F15B464EC3 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:60236 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lFYqg-0006Eh-VN for qemu-devel@archiver.kernel.org; Fri, 26 Feb 2021 03:51:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50512) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lFYol-0004rN-G2; Fri, 26 Feb 2021 03:49:47 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:3373) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lFYoj-0003Yr-Aj; Fri, 26 Feb 2021 03:49:47 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4Dn3Fl0XCCz164BW; Fri, 26 Feb 2021 16:47:55 +0800 (CST) Received: from huawei.com (10.174.185.226) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.498.0; Fri, 26 Feb 2021 16:49:25 +0800 From: Wang Xingang To: Subject: [RFC PATCH 1/4] pci: Add PCI_BUS_IOMMU property Date: Fri, 26 Feb 2021 08:49:10 +0000 Message-ID: <1614329353-2124-2-git-send-email-wangxingang5@huawei.com> X-Mailer: git-send-email 2.6.4.windows.1 In-Reply-To: <1614329353-2124-1-git-send-email-wangxingang5@huawei.com> References: <1614329353-2124-1-git-send-email-wangxingang5@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.185.226] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.190; envelope-from=wangxingang5@huawei.com; helo=szxga04-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, peter.maydell@linaro.org, cenjiahui@huawei.com, wangxingang5@huawei.com, mst@redhat.com, shannon.zhaosl@gmail.com, qemu-arm@nongnu.org, imammedo@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Xingang Wang This property can be useful to check whether this bus is attached to iommu. Signed-off-by: Xingang Wang Signed-off-by: Jiahui Cen --- include/hw/pci/pci_bus.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h index 347440d42c..42109e8a06 100644 --- a/include/hw/pci/pci_bus.h +++ b/include/hw/pci/pci_bus.h @@ -24,6 +24,8 @@ enum PCIBusFlags { PCI_BUS_IS_ROOT = 0x0001, /* PCIe extended configuration space is accessible on this bus */ PCI_BUS_EXTENDED_CONFIG_SPACE = 0x0002, + /* Iommu is enabled on this bus */ + PCI_BUS_IOMMU = 0x0004, }; struct PCIBus { @@ -63,4 +65,15 @@ static inline bool pci_bus_allows_extended_config_space(PCIBus *bus) return !!(bus->flags & PCI_BUS_EXTENDED_CONFIG_SPACE); } +static inline bool pci_bus_has_iommu(PCIBus *bus) +{ + PCIBus *root_bus = bus; + + while (root_bus && !pci_bus_is_root(root_bus)) { + root_bus = pci_get_bus(root_bus->parent_dev); + } + + return !!(root_bus->flags & PCI_BUS_IOMMU); +} + #endif /* QEMU_PCI_BUS_H */ From patchwork Fri Feb 26 08:49:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wang Xingang X-Patchwork-Id: 12106127 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 984ECC433DB for ; Fri, 26 Feb 2021 08:53:55 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0F4B164EC3 for ; Fri, 26 Feb 2021 08:53:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0F4B164EC3 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:38332 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lFYsj-0000Nf-I1 for qemu-devel@archiver.kernel.org; Fri, 26 Feb 2021 03:53:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50522) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lFYol-0004rb-RK; Fri, 26 Feb 2021 03:49:47 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:2657) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lFYoj-0003Yq-Ae; Fri, 26 Feb 2021 03:49:47 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4Dn3Fl1mc8z7qQg; Fri, 26 Feb 2021 16:47:55 +0800 (CST) Received: from huawei.com (10.174.185.226) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.498.0; Fri, 26 Feb 2021 16:49:26 +0800 From: Wang Xingang To: Subject: [RFC PATCH 2/4] hw/pci: Add iommu option for pci root bus Date: Fri, 26 Feb 2021 08:49:11 +0000 Message-ID: <1614329353-2124-3-git-send-email-wangxingang5@huawei.com> X-Mailer: git-send-email 2.6.4.windows.1 In-Reply-To: <1614329353-2124-1-git-send-email-wangxingang5@huawei.com> References: <1614329353-2124-1-git-send-email-wangxingang5@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.185.226] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.35; envelope-from=wangxingang5@huawei.com; helo=szxga07-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, peter.maydell@linaro.org, cenjiahui@huawei.com, wangxingang5@huawei.com, mst@redhat.com, shannon.zhaosl@gmail.com, qemu-arm@nongnu.org, imammedo@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Xingang Wang This add iommu option for pci root bus, including primary bus and pxb root bus. Default option is set to true, and the option is valid only if the iommu option for machine is properly set. Signed-off-by: Xingang Wang Signed-off-by: Jiahui Cen --- hw/arm/virt.c | 29 +++++++++++++++++++++++++++++ hw/pci-bridge/pci_expander_bridge.c | 6 ++++++ hw/pci/pci.c | 2 +- include/hw/arm/virt.h | 1 + 4 files changed, 37 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 371147f3ae..0c9e549759 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -79,6 +79,7 @@ #include "hw/virtio/virtio-iommu.h" #include "hw/char/pl011.h" #include "qemu/guest-random.h" +#include "include/hw/pci/pci_bus.h" #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ @@ -1232,6 +1233,10 @@ static void create_smmu(const VirtMachineState *vms, dev = qdev_new("arm-smmuv3"); + if (vms->primary_bus_iommu) { + bus->flags |= PCI_BUS_IOMMU; + } + object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus), &error_abort); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); @@ -2305,6 +2310,20 @@ static void virt_set_iommu(Object *obj, const char *value, Error **errp) } } +static bool virt_get_primary_bus_iommu(Object *obj, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + return vms->primary_bus_iommu; +} + +static void virt_set_primary_bus_iommu(Object *obj, bool value, Error **errp) +{ + VirtMachineState *vms = VIRT_MACHINE(obj); + + vms->primary_bus_iommu = value; +} + static CpuInstanceProperties virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) { @@ -2629,6 +2648,13 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) "Set the IOMMU type. " "Valid values are none and smmuv3"); + object_class_property_add_bool(oc, "primary_bus_iommu", + virt_get_primary_bus_iommu, + virt_set_primary_bus_iommu); + object_class_property_set_description(oc, "primary_bus_iommu", + "Set on/off to enable/disable " + "iommu for primary bus"); + object_class_property_add_bool(oc, "ras", virt_get_ras, virt_set_ras); object_class_property_set_description(oc, "ras", @@ -2696,6 +2722,9 @@ static void virt_instance_init(Object *obj) /* Default disallows iommu instantiation */ vms->iommu = VIRT_IOMMU_NONE; + /* Iommu is enabled by default for primary bus */ + vms->primary_bus_iommu = true; + /* Default disallows RAS instantiation */ vms->ras = false; diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c index aedded1064..7971ce9bd9 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -57,6 +57,7 @@ struct PXBDev { uint8_t bus_nr; uint16_t numa_node; + bool iommu; }; static PXBDev *convert_to_pxb(PCIDevice *dev) @@ -254,6 +255,10 @@ static void pxb_dev_realize_common(PCIDevice *dev, bool pcie, Error **errp) bus->address_space_io = pci_get_bus(dev)->address_space_io; bus->map_irq = pxb_map_irq_fn; + if (pxb->iommu) { + bus->flags |= PCI_BUS_IOMMU; + } + PCI_HOST_BRIDGE(ds)->bus = bus; pxb_register_bus(dev, bus, &local_err); @@ -301,6 +306,7 @@ static Property pxb_dev_properties[] = { /* Note: 0 is not a legal PXB bus number. */ DEFINE_PROP_UINT8("bus_nr", PXBDev, bus_nr, 0), DEFINE_PROP_UINT16("numa_node", PXBDev, numa_node, NUMA_NODE_UNASSIGNED), + DEFINE_PROP_BOOL("iommu", PXBDev, iommu, true), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/pci/pci.c b/hw/pci/pci.c index a9ebef8a35..dc969989c9 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2712,7 +2712,7 @@ AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) iommu_bus = parent_bus; } - if (iommu_bus && iommu_bus->iommu_fn) { + if (pci_bus_has_iommu(bus) && iommu_bus && iommu_bus->iommu_fn) { return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, devfn); } return &address_space_memory; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index ee9a93101e..babe829486 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -147,6 +147,7 @@ struct VirtMachineState { OnOffAuto acpi; VirtGICType gic_version; VirtIOMMUType iommu; + bool primary_bus_iommu; VirtMSIControllerType msi_controller; uint16_t virtio_iommu_bdf; struct arm_boot_info bootinfo; From patchwork Fri Feb 26 08:49:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wang Xingang X-Patchwork-Id: 12106125 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2ADB8C433DB for ; Fri, 26 Feb 2021 08:53:53 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7CA1E64ECE for ; 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Fri, 26 Feb 2021 16:47:34 +0800 (CST) Received: from huawei.com (10.174.185.226) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.498.0; Fri, 26 Feb 2021 16:49:27 +0800 From: Wang Xingang To: Subject: [RFC PATCH 3/4] hw/pci: Add pci_root_bus_max_bus Date: Fri, 26 Feb 2021 08:49:12 +0000 Message-ID: <1614329353-2124-4-git-send-email-wangxingang5@huawei.com> X-Mailer: git-send-email 2.6.4.windows.1 In-Reply-To: <1614329353-2124-1-git-send-email-wangxingang5@huawei.com> References: <1614329353-2124-1-git-send-email-wangxingang5@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.185.226] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.191; envelope-from=wangxingang5@huawei.com; helo=szxga05-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, peter.maydell@linaro.org, cenjiahui@huawei.com, wangxingang5@huawei.com, mst@redhat.com, shannon.zhaosl@gmail.com, qemu-arm@nongnu.org, imammedo@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Xingang Wang This helps to find max bus number of a root bus. Signed-off-by: Xingang Wang Signed-off-by: Jiahui Cen --- hw/pci/pci.c | 33 +++++++++++++++++++++++++++++++++ include/hw/pci/pci.h | 1 + 2 files changed, 34 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index dc969989c9..ed92ce0971 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -516,6 +516,39 @@ int pci_bus_num(PCIBus *s) return PCI_BUS_GET_CLASS(s)->bus_num(s); } +int pci_root_bus_max_bus(PCIBus *bus) +{ + PCIHostState *host; + int max_bus = 0; + int type; + int devfn; + + if (!pci_bus_is_root(bus)) { + return 0; + } + + host = PCI_HOST_BRIDGE(BUS(bus)->parent); + max_bus = pci_bus_num(host->bus); + + for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { + PCIDevice *dev = host->bus->devices[devfn]; + + if (!dev) { + continue; + } + + type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; + if (type == PCI_HEADER_TYPE_BRIDGE) { + uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS]; + if (subordinate > max_bus) { + max_bus = subordinate; + } + } + } + + return max_bus; +} + int pci_bus_numa_node(PCIBus *bus) { return PCI_BUS_GET_CLASS(bus)->numa_node(bus); diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 1bc231480f..238b91817a 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -449,6 +449,7 @@ static inline PCIBus *pci_get_bus(const PCIDevice *dev) return PCI_BUS(qdev_get_parent_bus(DEVICE(dev))); } int pci_bus_num(PCIBus *s); +int pci_root_bus_max_bus(PCIBus *bus); static inline int pci_dev_bus_num(const PCIDevice *dev) { return pci_bus_num(pci_get_bus(dev)); From patchwork Fri Feb 26 08:49:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wang Xingang X-Patchwork-Id: 12106131 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF45EC433DB for ; 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Fri, 26 Feb 2021 03:49:48 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4Dn3FL19PbzMfG7; Fri, 26 Feb 2021 16:47:34 +0800 (CST) Received: from huawei.com (10.174.185.226) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.498.0; Fri, 26 Feb 2021 16:49:27 +0800 From: Wang Xingang To: Subject: [RFC PATCH 4/4] hw/arm/virt-acpi-build: Add explicit idmap info in IORT table Date: Fri, 26 Feb 2021 08:49:13 +0000 Message-ID: <1614329353-2124-5-git-send-email-wangxingang5@huawei.com> X-Mailer: git-send-email 2.6.4.windows.1 In-Reply-To: <1614329353-2124-1-git-send-email-wangxingang5@huawei.com> References: <1614329353-2124-1-git-send-email-wangxingang5@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.185.226] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.191; envelope-from=wangxingang5@huawei.com; helo=szxga05-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, peter.maydell@linaro.org, cenjiahui@huawei.com, wangxingang5@huawei.com, mst@redhat.com, shannon.zhaosl@gmail.com, qemu-arm@nongnu.org, imammedo@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Xingang Wang The idmap of smmuv3 and root complex covers the whole RID space for now, this patch add explicit idmap info according to root bus number range. This add smmuv3 idmap for certain bus which has enabled the iommu property. Signed-off-by: Xingang Wang Signed-off-by: Jiahui Cen --- hw/arm/virt-acpi-build.c | 88 +++++++++++++++++++++++++++++----------- 1 file changed, 65 insertions(+), 23 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index f9c9df916c..8bb8b251d0 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -54,6 +54,7 @@ #include "kvm_arm.h" #include "migration/vmstate.h" #include "hw/acpi/ghes.h" +#include "hw/pci/pci_bus.h" #define ARM_SPI_BASE 32 @@ -247,9 +248,34 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) AcpiIortSmmu3 *smmu; size_t node_size, iort_node_offset, iort_length, smmu_offset = 0; AcpiIortRC *rc; + PCIBus *bus = vms->bus; + GArray *root_bus_array; + size_t root_bus_count = 0; + size_t root_bus_smmu_count = 0; + int bus_num, max_bus, index; + + root_bus_array = g_array_new(false, true, sizeof(PCIBus *)); iort = acpi_data_push(table_data, sizeof(*iort)); + g_array_append_val(root_bus_array, bus); + root_bus_count++; + if (vms->iommu == VIRT_IOMMU_SMMUV3 && pci_bus_has_iommu(bus)) { + root_bus_smmu_count++; + } + + QLIST_FOREACH(bus, &bus->child, sibling) { + + if (!pci_bus_is_root(bus)) continue; + + g_array_append_val(root_bus_array, bus); + root_bus_count++; + + if (vms->iommu == VIRT_IOMMU_SMMUV3 && pci_bus_has_iommu(bus)) { + root_bus_smmu_count++; + } + } + if (vms->iommu == VIRT_IOMMU_SMMUV3) { nb_nodes = 3; /* RC, ITS, SMMUv3 */ } else { @@ -280,13 +306,13 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) /* SMMUv3 node */ smmu_offset = iort_node_offset + node_size; - node_size = sizeof(*smmu) + sizeof(*idmap); + node_size = sizeof(*smmu) + sizeof(*idmap) * root_bus_smmu_count; iort_length += node_size; smmu = acpi_data_push(table_data, node_size); smmu->type = ACPI_IORT_NODE_SMMU_V3; smmu->length = cpu_to_le16(node_size); - smmu->mapping_count = cpu_to_le32(1); + smmu->mapping_count = cpu_to_le32(root_bus_smmu_count); smmu->mapping_offset = cpu_to_le32(sizeof(*smmu)); smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base); smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE); @@ -295,23 +321,32 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) smmu->gerr_gsiv = cpu_to_le32(irq + 2); smmu->sync_gsiv = cpu_to_le32(irq + 3); - /* Identity RID mapping covering the whole input RID range */ - idmap = &smmu->id_mapping_array[0]; - idmap->input_base = 0; - idmap->id_count = cpu_to_le32(0xFFFF); - idmap->output_base = 0; - /* output IORT node is the ITS group node (the first node) */ - idmap->output_reference = cpu_to_le32(iort_node_offset); + index = 0; + for (int i = 0; i < root_bus_count; i++) { + bus = g_array_index(root_bus_array, PCIBus *, i); + + if (!pci_bus_has_iommu(bus)) continue; + + bus_num = pci_bus_num(bus); + max_bus = pci_root_bus_max_bus(bus); + + idmap = &smmu->id_mapping_array[index++]; + idmap->input_base = cpu_to_le32(bus_num << 8); + idmap->id_count = cpu_to_le32((max_bus - bus_num + 1) << 8); + idmap->output_base = cpu_to_le32(bus_num << 8); + /* output IORT node is the ITS group node (the first node) */ + idmap->output_reference = cpu_to_le32(iort_node_offset); + } } /* Root Complex Node */ - node_size = sizeof(*rc) + sizeof(*idmap); + node_size = sizeof(*rc) + sizeof(*idmap) * root_bus_count; iort_length += node_size; rc = acpi_data_push(table_data, node_size); rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX; rc->length = cpu_to_le16(node_size); - rc->mapping_count = cpu_to_le32(1); + rc->mapping_count = cpu_to_le32(root_bus_count); rc->mapping_offset = cpu_to_le32(sizeof(*rc)); /* fully coherent device */ @@ -319,18 +354,23 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */ rc->pci_segment_number = 0; /* MCFG pci_segment */ - /* Identity RID mapping covering the whole input RID range */ - idmap = &rc->id_mapping_array[0]; - idmap->input_base = 0; - idmap->id_count = cpu_to_le32(0xFFFF); - idmap->output_base = 0; - - if (vms->iommu == VIRT_IOMMU_SMMUV3) { - /* output IORT node is the smmuv3 node */ - idmap->output_reference = cpu_to_le32(smmu_offset); - } else { - /* output IORT node is the ITS group node (the first node) */ - idmap->output_reference = cpu_to_le32(iort_node_offset); + for (int i = 0; i < root_bus_count; i++) { + bus = g_array_index(root_bus_array, PCIBus *, i); + bus_num = pci_bus_num(bus); + max_bus = pci_root_bus_max_bus(bus); + + idmap = &rc->id_mapping_array[i]; + idmap->input_base = cpu_to_le32(bus_num << 8); + idmap->id_count = cpu_to_le32((max_bus - bus_num + 1) << 8); + idmap->output_base = cpu_to_le32(bus_num << 8); + + if (vms->iommu == VIRT_IOMMU_SMMUV3 && pci_bus_has_iommu(bus)) { + /* output IORT node is the smmuv3 node */ + idmap->output_reference = cpu_to_le32(smmu_offset); + } else { + /* output IORT node is the ITS group node (the first node) */ + idmap->output_reference = cpu_to_le32(iort_node_offset); + } } /* @@ -343,6 +383,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) build_header(linker, table_data, (void *)(table_data->data + iort_start), "IORT", table_data->len - iort_start, 0, vms->oem_id, vms->oem_table_id); + + g_array_free(root_bus_array, true); } static void