From patchwork Sat Feb 27 23:25:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 12107947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A342C433DB for ; Sat, 27 Feb 2021 23:27:49 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B7F6764DFF for ; Sat, 27 Feb 2021 23:27:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B7F6764DFF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:46024 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lG8zz-0003Ls-Jb for qemu-devel@archiver.kernel.org; Sat, 27 Feb 2021 18:27:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52958) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lG8xi-0001eo-Eo for qemu-devel@nongnu.org; Sat, 27 Feb 2021 18:25:26 -0500 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]:34667) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lG8xf-00037K-NZ for qemu-devel@nongnu.org; Sat, 27 Feb 2021 18:25:26 -0500 Received: by mail-pg1-x52e.google.com with SMTP id l2so8626921pgb.1 for ; Sat, 27 Feb 2021 15:25:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1wtxOXkgEIEKU8XQwNUeSlT4Y6Fve79jFtXE/YJnOWg=; b=VD6O8LM5bIqao7y1WVAbB4KIKXGosTea5lBURqVCX2bCCJH6WctJxmKKmC6CF4xfm0 2Skgpd9qX6IMGW9pXJsz9hS6CjMyXoSIv9Pf22KqSuG41FuqOeatnHtdwuhsXQpU3ZQt vIPBQt1FRoxB9zQyo7fjVOVdli4ut4KRAsTt4rdAl37ruFnznM1TwmUp+Fr0eI4LHD/F T42vqscRklgfISkwX6G3cHAv0u1tIBvT/q9BGD0o6w3x3s2K/ELcP+ARAtZJTy2wzQR1 xWRQV0OnmDUC/4J7B+623nFt3aLj6vhdWsh11YTEllApzgYb4zLHOcpIt87bH9jXtTsC 6YPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1wtxOXkgEIEKU8XQwNUeSlT4Y6Fve79jFtXE/YJnOWg=; b=ogRb9LLjSzwhrP/aKFVIbQ5n3cu0SfTFYqIzOZ8PDCbcCK69viP+RIVyTSZlGtv2by jtT3lLDL1JNBgwxyGFUNuQhsbYyR2yzgdCry1JHeZf7exc5KVuY6G7gegqdMVLiQwn3v CUE2Sv4C8sZ9Tn5riUFyS65NRla4RiBLa7XJf+3GG6CVsuCfmsKMUnFF2y4PXfv9PzGe fmG85r2VFm1oMvYVoppbXlEWFDp5Ig79reF90dmsZa5NZKgyQ/qyMdGa7OmGxDVVrU3U BKFgQ+XGc+yP1QUyyxMEIToihMDfwKFwaX76LcSvaM9+d/+ovCF/8JsQ/14FkNOEY5MZ bFeQ== X-Gm-Message-State: AOAM530+XlXLH0a3VzEVhabGb2S1I/pg7Kwwh+eKiOjdRWefZ/L4GRpE EyY5pz4As04GAHFNWf96RLfgn7SpwIqZuw== X-Google-Smtp-Source: ABdhPJxrzz0UJdTa7MomOqgCAkjBmc9qyiSV+kSS3oamXQ/SID17fLDoiyiJ6G9uMsFFoXpXBcS0MA== X-Received: by 2002:a65:50c8:: with SMTP id s8mr8221122pgp.68.1614468321499; Sat, 27 Feb 2021 15:25:21 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id ha8sm8187516pjb.6.2021.02.27.15.25.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Feb 2021 15:25:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/2] target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed Date: Sat, 27 Feb 2021 15:25:18 -0800 Message-Id: <20210227232519.222663-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210227232519.222663-1-richard.henderson@linaro.org> References: <20210227232519.222663-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, cfontana@suse.de Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add a flag to MIPSCPUClass in order to avoid needing to replace mips_tcg_ops.do_transaction_failed. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- target/mips/cpu-qom.h | 3 +++ hw/mips/jazz.c | 35 +++-------------------------------- target/mips/op_helper.c | 3 ++- 3 files changed, 8 insertions(+), 33 deletions(-) diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index 826ab13019..dda0c911fa 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -47,6 +47,9 @@ struct MIPSCPUClass { DeviceRealize parent_realize; DeviceReset parent_reset; const struct mips_def_t *cpu_def; + + /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */ + bool no_data_aborts; }; diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index 83c8086062..7b22a9b511 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -120,30 +120,6 @@ static const MemoryRegionOps dma_dummy_ops = { #define MAGNUM_BIOS_SIZE \ (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) -#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) -static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, - uintptr_t retaddr); - -static void mips_jazz_do_transaction_failed(CPUState *cs, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, - uintptr_t retaddr) -{ - if (access_type != MMU_INST_FETCH) { - /* ignore invalid access (ie do not raise exception) */ - return; - } - (*real_do_transaction_failed)(cs, physaddr, addr, size, access_type, - mmu_idx, attrs, response, retaddr); -} -#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ - static void mips_jazz_init(MachineState *machine, enum jazz_model_e jazz_model) { @@ -152,7 +128,7 @@ static void mips_jazz_init(MachineState *machine, int bios_size, n; Clock *cpuclk; MIPSCPU *cpu; - CPUClass *cc; + MIPSCPUClass *mcc; CPUMIPSState *env; qemu_irq *i8259; rc4030_dma *dmas; @@ -199,8 +175,6 @@ static void mips_jazz_init(MachineState *machine, * However, we can't simply add a global memory region to catch * everything, as this would make all accesses including instruction * accesses be ignored and not raise exceptions. - * So instead we hijack the do_transaction_failed method on the CPU, and - * do not raise exceptions for data access. * * NOTE: this behaviour of raising exceptions for bad instruction * fetches but not bad data accesses was added in commit 54e755588cf1e9 @@ -210,11 +184,8 @@ static void mips_jazz_init(MachineState *machine, * we could replace this hijacking of CPU methods with a simple global * memory region that catches all memory accesses, as we do on Malta. */ - cc = CPU_GET_CLASS(cpu); -#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) - real_do_transaction_failed = cc->tcg_ops->do_transaction_failed; - cc->tcg_ops->do_transaction_failed = mips_jazz_do_transaction_failed; -#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ + mcc = MIPS_CPU_GET_CLASS(cpu); + mcc->no_data_aborts = true; /* allocate RAM */ memory_region_add_subregion(address_space, 0, machine->ram); diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index b80e8f7540..7626fc5254 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1164,11 +1164,12 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, MemTxResult response, uintptr_t retaddr) { MIPSCPU *cpu = MIPS_CPU(cs); + MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); CPUMIPSState *env = &cpu->env; if (access_type == MMU_INST_FETCH) { do_raise_exception(env, EXCP_IBE, retaddr); - } else { + } else if (!mcc->no_data_aborts) { do_raise_exception(env, EXCP_DBE, retaddr); } } From patchwork Sat Feb 27 23:25:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 12107949 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F18D9C433DB for ; Sat, 27 Feb 2021 23:29:36 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 85F3F64E24 for ; Sat, 27 Feb 2021 23:29:36 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 85F3F64E24 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:49014 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lG91j-0004dS-LJ for qemu-devel@archiver.kernel.org; Sat, 27 Feb 2021 18:29:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52960) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lG8xj-0001fk-H5 for qemu-devel@nongnu.org; Sat, 27 Feb 2021 18:25:27 -0500 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:41583) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lG8xf-00037N-Kd for qemu-devel@nongnu.org; Sat, 27 Feb 2021 18:25:27 -0500 Received: by mail-pl1-x62f.google.com with SMTP id d11so7312127plo.8 for ; Sat, 27 Feb 2021 15:25:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+D2NUcw390W8QaRp4L4LE0gHLhEua6WESpznKzpIu9Y=; b=DOr8oEwGYqBfj1/J80DN/U9ESN30zgb4pfEFcEOQrz1/09AqK8N/rq+/ZB4/BYeiww 0/iCZ9iVBrRAbQRfwluN9XAFO+xGzYsIlAMYfb0HrFqL03mNtt9qwkxkEyrbBcItNenJ 6mtMBmhzQotSVWL1KU69GFX9ow9m1h5ND3xwqzpGQZfFWSWBvD8yrTBEKbEtYECt85AR cR3imjyok7PftJ7HIi7PvvQBihKIY9FgTExjX1oZfTShee1La7f4aGapgPCDYXXfHkI4 eVN0aZRWq/GEaNXSi4gCMufPzHNrDXnMadHnQy9/TWtspD/aqMNViO8jfT5b+3qGxwym qc+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+D2NUcw390W8QaRp4L4LE0gHLhEua6WESpznKzpIu9Y=; b=o9SnZ5UsSXi42HCD9NZYyZT/sRFDpmYlQLENHDKNV/3w+G0zpF49EsOCE/p2c0VbRK FymL+m+Cv3cSgZOqbUB/LDkK2ti887zi03O9VxTU2lxVnt+yxmBjSSp4C3A1n19wjfPF NNQmBxKlpapYAwEdxPxhTQziNnXLN4Ds9pe732RMt+5VewblU4fge2AtH1KOe1CmkzBg P6fqDUETn1ZdqCxR4b+esunX+7kQga0Meu4tGof/YHwZS7dKwBYnfSTpNHjTNdTKVsKl w2Bsj2526mJhw69xDDJYz8CWMtPtp56cP6ZCQKiA1Zb7OT+AXUqiwo/RPwuHBggIckx7 1kcA== X-Gm-Message-State: AOAM533v4/vRwvMERURIpg3KxZnYyvMzm7+pYc7K+DU+N2Q/vUpPrayT oMWuMd8l8a1rWsNU9UCYGbgTGSJ8Mh7Ogg== X-Google-Smtp-Source: ABdhPJwe7sGIfhdC7cWmT5vd9DmcQlhSzstG6iaDbJrPiUer1i2XO0aQSrK0UyHsLOJRqzvlyqCo3w== X-Received: by 2002:a17:90a:cc02:: with SMTP id b2mr9591060pju.115.1614468322203; Sat, 27 Feb 2021 15:25:22 -0800 (PST) Received: from localhost.localdomain (174-21-84-25.tukw.qwest.net. [174.21.84.25]) by smtp.gmail.com with ESMTPSA id ha8sm8187516pjb.6.2021.02.27.15.25.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Feb 2021 15:25:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/2] hw/core: Constify TCGCPUOps Date: Sat, 27 Feb 2021 15:25:19 -0800 Message-Id: <20210227232519.222663-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210227232519.222663-1-richard.henderson@linaro.org> References: <20210227232519.222663-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: f4bug@amsat.org, cfontana@suse.de Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We no longer have any runtime modifications to this struct, so declare them all const. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 2 +- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/arm/cpu_tcg.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 4 ++-- target/hexagon/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/lm32/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/moxie/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tilegx/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/unicore32/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 26 files changed, 27 insertions(+), 27 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c005d3dc2d..e3648338df 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -191,7 +191,7 @@ struct CPUClass { struct AccelCPUClass *accel_cpu; /* when TCG is not available, this pointer is NULL */ - struct TCGCPUOps *tcg_ops; + const struct TCGCPUOps *tcg_ops; }; /* diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 27192b62e2..e50ae7bef0 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -208,7 +208,7 @@ static void alpha_cpu_initfn(Object *obj) #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps alpha_tcg_ops = { +static const struct TCGCPUOps alpha_tcg_ops = { .initialize = alpha_translate_init, .cpu_exec_interrupt = alpha_cpu_exec_interrupt, .tlb_fill = alpha_cpu_tlb_fill, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b8bc89e71f..5e018b2a73 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2261,7 +2261,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) } #ifdef CONFIG_TCG -static struct TCGCPUOps arm_tcg_ops = { +static const struct TCGCPUOps arm_tcg_ops = { .initialize = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, .cpu_exec_interrupt = arm_cpu_exec_interrupt, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index c29b434c60..4fc02d06b6 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -664,7 +664,7 @@ static void pxa270c5_initfn(Object *obj) } #ifdef CONFIG_TCG -static struct TCGCPUOps arm_v7m_tcg_ops = { +static const struct TCGCPUOps arm_v7m_tcg_ops = { .initialize = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 0f4596932b..7d0ab606ae 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -186,7 +186,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags) #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps avr_tcg_ops = { +static const struct TCGCPUOps avr_tcg_ops = { .initialize = avr_cpu_tcg_init, .synchronize_from_tb = avr_cpu_synchronize_from_tb, .cpu_exec_interrupt = avr_cpu_exec_interrupt, diff --git a/target/cris/cpu.c b/target/cris/cpu.c index ed983380fc..4586302ba3 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -195,7 +195,7 @@ static void cris_cpu_initfn(Object *obj) #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps crisv10_tcg_ops = { +static const struct TCGCPUOps crisv10_tcg_ops = { .initialize = cris_initialize_crisv10_tcg, .cpu_exec_interrupt = cris_cpu_exec_interrupt, .tlb_fill = cris_cpu_tlb_fill, @@ -205,7 +205,7 @@ static struct TCGCPUOps crisv10_tcg_ops = { #endif /* !CONFIG_USER_ONLY */ }; -static struct TCGCPUOps crisv32_tcg_ops = { +static const struct TCGCPUOps crisv32_tcg_ops = { .initialize = cris_initialize_tcg, .cpu_exec_interrupt = cris_cpu_exec_interrupt, .tlb_fill = cris_cpu_tlb_fill, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index b0b3040dd1..a13a941ed5 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -266,7 +266,7 @@ static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size, #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps hexagon_tcg_ops = { +static const struct TCGCPUOps hexagon_tcg_ops = { .initialize = hexagon_translate_init, .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, .tlb_fill = hexagon_tlb_fill, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index d8fad52d1f..5f1822b5fe 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -133,7 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps hppa_tcg_ops = { +static const struct TCGCPUOps hppa_tcg_ops = { .initialize = hppa_translate_init, .synchronize_from_tb = hppa_cpu_synchronize_from_tb, .cpu_exec_interrupt = hppa_cpu_exec_interrupt, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 1e125d2175..6a35aa664d 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -59,7 +59,7 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps x86_tcg_ops = { +static const struct TCGCPUOps x86_tcg_ops = { .initialize = tcg_x86_init, .synchronize_from_tb = x86_cpu_synchronize_from_tb, .cpu_exec_enter = x86_cpu_exec_enter, diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index c23d72874c..4ad253a50e 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -212,7 +212,7 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model) #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps lm32_tcg_ops = { +static const struct TCGCPUOps lm32_tcg_ops = { .initialize = lm32_translate_init, .cpu_exec_interrupt = lm32_cpu_exec_interrupt, .tlb_fill = lm32_cpu_tlb_fill, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 37d2ed9dc7..9b2f651213 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -504,7 +504,7 @@ static const VMStateDescription vmstate_m68k_cpu = { #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps m68k_tcg_ops = { +static const struct TCGCPUOps m68k_tcg_ops = { .initialize = m68k_tcg_init, .cpu_exec_interrupt = m68k_cpu_exec_interrupt, .tlb_fill = m68k_cpu_tlb_fill, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 433ba20203..4e086ab546 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -354,7 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model) #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps mb_tcg_ops = { +static const struct TCGCPUOps mb_tcg_ops = { .initialize = mb_tcg_init, .synchronize_from_tb = mb_cpu_synchronize_from_tb, .cpu_exec_interrupt = mb_cpu_exec_interrupt, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index bf70c77295..81030c5c40 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -686,7 +686,7 @@ static Property mips_cpu_properties[] = { * NB: cannot be const, as some elements are changed for specific * mips hardware (see hw/mips/jazz.c). */ -static struct TCGCPUOps mips_tcg_ops = { +static const struct TCGCPUOps mips_tcg_ops = { .initialize = mips_tcg_init, .synchronize_from_tb = mips_cpu_synchronize_from_tb, .cpu_exec_interrupt = mips_cpu_exec_interrupt, diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 83bec34d36..c3de71b82f 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -96,7 +96,7 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model) #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps moxie_tcg_ops = { +static const struct TCGCPUOps moxie_tcg_ops = { .initialize = moxie_translate_init, .tlb_fill = moxie_cpu_tlb_fill, diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index e9c9fc3a38..0de93cdd98 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -209,7 +209,7 @@ static Property nios2_properties[] = { #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps nios2_tcg_ops = { +static const struct TCGCPUOps nios2_tcg_ops = { .initialize = nios2_tcg_init, .cpu_exec_interrupt = nios2_cpu_exec_interrupt, .tlb_fill = nios2_cpu_tlb_fill, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 2c64842f46..52aef27723 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -176,7 +176,7 @@ static void openrisc_any_initfn(Object *obj) #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps openrisc_tcg_ops = { +static const struct TCGCPUOps openrisc_tcg_ops = { .initialize = openrisc_translate_init, .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, .tlb_fill = openrisc_cpu_tlb_fill, diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 16f1a34238..6f9822bc0a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -582,7 +582,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps riscv_tcg_ops = { +static const struct TCGCPUOps riscv_tcg_ops = { .initialize = riscv_translate_init, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, .cpu_exec_interrupt = riscv_cpu_exec_interrupt, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 7ac6618b26..28d2becc32 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -175,7 +175,7 @@ static void rx_cpu_init(Object *obj) #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps rx_tcg_ops = { +static const struct TCGCPUOps rx_tcg_ops = { .initialize = rx_translate_init, .synchronize_from_tb = rx_cpu_synchronize_from_tb, .cpu_exec_interrupt = rx_cpu_exec_interrupt, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d35eb39a1b..feaf2a6d08 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -480,7 +480,7 @@ static void s390_cpu_reset_full(DeviceState *dev) #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps s390_tcg_ops = { +static const struct TCGCPUOps s390_tcg_ops = { .initialize = s390x_translate_init, .tlb_fill = s390_cpu_tlb_fill, diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index ac65c88f1f..9d77f9cfda 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -225,7 +225,7 @@ static const VMStateDescription vmstate_sh_cpu = { #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps superh_tcg_ops = { +static const struct TCGCPUOps superh_tcg_ops = { .initialize = sh4_translate_init, .synchronize_from_tb = superh_cpu_synchronize_from_tb, .cpu_exec_interrupt = superh_cpu_exec_interrupt, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index aece2c7dc8..ccabe189c4 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -851,7 +851,7 @@ static Property sparc_cpu_properties[] = { #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps sparc_tcg_ops = { +static const struct TCGCPUOps sparc_tcg_ops = { .initialize = sparc_tcg_init, .synchronize_from_tb = sparc_cpu_synchronize_from_tb, .cpu_exec_interrupt = sparc_cpu_exec_interrupt, diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index d969c2f133..c7f8a898ca 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -136,7 +136,7 @@ static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request) #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps tilegx_tcg_ops = { +static const struct TCGCPUOps tilegx_tcg_ops = { .initialize = tilegx_tcg_init, .cpu_exec_interrupt = tilegx_cpu_exec_interrupt, .tlb_fill = tilegx_cpu_tlb_fill, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 0b1e139bcb..5b500b575b 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -144,7 +144,7 @@ static void tc27x_initfn(Object *obj) #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps tricore_tcg_ops = { +static const struct TCGCPUOps tricore_tcg_ops = { .initialize = tricore_tcg_init, .synchronize_from_tb = tricore_cpu_synchronize_from_tb, .tlb_fill = tricore_cpu_tlb_fill, diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 0258884f84..a732b08748 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -122,7 +122,7 @@ static const VMStateDescription vmstate_uc32_cpu = { #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps uc32_tcg_ops = { +static const struct TCGCPUOps uc32_tcg_ops = { .initialize = uc32_translate_init, .cpu_exec_interrupt = uc32_cpu_exec_interrupt, .tlb_fill = uc32_cpu_tlb_fill, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index e2b2c7a71c..badc3a26aa 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -183,7 +183,7 @@ static const VMStateDescription vmstate_xtensa_cpu = { #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps xtensa_tcg_ops = { +static const struct TCGCPUOps xtensa_tcg_ops = { .initialize = xtensa_translate_init, .cpu_exec_interrupt = xtensa_cpu_exec_interrupt, .tlb_fill = xtensa_cpu_tlb_fill, diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc index e7324e85cd..80239077e0 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10846,7 +10846,7 @@ static Property ppc_cpu_properties[] = { #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps ppc_tcg_ops = { +static const struct TCGCPUOps ppc_tcg_ops = { .initialize = ppc_translate_init, .cpu_exec_interrupt = ppc_cpu_exec_interrupt, .tlb_fill = ppc_cpu_tlb_fill,