From patchwork Mon Mar 1 12:35:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 12109609 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 095A7C433E0 for ; Mon, 1 Mar 2021 12:36:20 +0000 (UTC) Received: by mail.kernel.org (Postfix) id BFCED64E31; Mon, 1 Mar 2021 12:36:19 +0000 (UTC) Received: from mail-pg1-f170.google.com (mail-pg1-f170.google.com [209.85.215.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2CE0164E75 for ; Mon, 1 Mar 2021 12:36:18 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2CE0164E75 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=daniel@0x0f.com Received: by mail-pg1-f170.google.com with SMTP id o10so11464892pgg.4 for ; Mon, 01 Mar 2021 04:36:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=C88FmiAqxDnJbB9m5EGVR/CJ40sQ0nT98Az9DhqgecU=; b=k25ODqx0AJ9FiPd1SEWkoupl4VkvfyH//7e4sw3S9SizNEvqDBmeG8PMTbrw8Wud2p jPT/5r8AUEOc+6GCoMClwE2m9U12dn/IyaSPGBhnWNegGzlei+RJ5Q0GhZ1do2ME2bob 0valpUCI4R32euZNZJguYY2Uh3+rSnvly1/gY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=C88FmiAqxDnJbB9m5EGVR/CJ40sQ0nT98Az9DhqgecU=; b=b1rV9knbbWRqwbFk8GCY6t/6UlkLUPy/22awVC0EurYssCI+aQj8r9yLBLShBHdw28 75+4681ZM+zWSGs7xs2e74JHEtChErD4NkrKQhpK9zth1c6Z4MMTvZI/2lMjU0Kk+LTj iVdwBUhY7lVH6FoBunrDtHafBDZ/20TnOIVMSB9cTx8X60NyX/TseeXwVUu8qCGxCkNM zXCNh6bT1v7vtR3xQbpHiSKv2X6x64oPGYkuAbEkZ3SOuyUtV3LpslCClDBwdgglrOlG 3W68+ammkT43NgqkfNXa0Rk8/1xRa4jFM2nrpwABbcOEQeBrqOBZZ7mBSD4JAenwR9a4 zzFQ== X-Gm-Message-State: AOAM532TiMW9xD+qhohrB4TYo0kcRogvNTVyUHzFwhIGIzG0FgVb52VC 9Zxamz86eiF2hqFqGJ7FOlYIt4Eg+dvF8A== X-Google-Smtp-Source: ABdhPJy4edf/KQypinIj/0pMZbp3pGG1yVFbUE7VPL2CwLLI5GWeL1N/ukAkzUJwOZk8lI2iMzCeTQ== X-Received: by 2002:a62:ed0b:0:b029:1ee:7568:5ab9 with SMTP id u11-20020a62ed0b0000b02901ee75685ab9mr7010492pfh.79.1614602178032; Mon, 01 Mar 2021 04:36:18 -0800 (PST) Received: from shiro.work (p345188-ipngn200408sizuokaden.shizuoka.ocn.ne.jp. [124.98.97.188]) by smtp.googlemail.com with ESMTPSA id 8sm18130928pfp.171.2021.03.01.04.36.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Mar 2021 04:36:17 -0800 (PST) From: Daniel Palmer List-Id: To: soc@kernel.org Cc: arnd@kernel.org, olof@lixom.net, w@1wt.eu, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Daniel Palmer Subject: [PATCH 1/3] ARM: mstar: Select MSTAR_MSC313_MPLL Date: Mon, 1 Mar 2021 21:35:40 +0900 Message-Id: <20210301123542.2800643-2-daniel@0x0f.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210301123542.2800643-1-daniel@0x0f.com> References: <20210301123542.2800643-1-daniel@0x0f.com> MIME-Version: 1.0 All of the ARCH_MSTARV7 chips have an MPLL as the source for peripheral clocks so select MSTAR_MSC313_MPLL. Signed-off-by: Daniel Palmer --- arch/arm/mach-mstar/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-mstar/Kconfig b/arch/arm/mach-mstar/Kconfig index 576d1ab293c8..cd300eeedc20 100644 --- a/arch/arm/mach-mstar/Kconfig +++ b/arch/arm/mach-mstar/Kconfig @@ -4,6 +4,7 @@ menuconfig ARCH_MSTARV7 select ARM_GIC select ARM_HEAVY_MB select MST_IRQ + select MSTAR_MSC313_MPLL help Support for newer MStar/Sigmastar SoC families that are based on Armv7 cores like the Cortex A7 and share the same From patchwork Mon Mar 1 12:35:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 12109611 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50ABCC433E6 for ; Mon, 1 Mar 2021 12:36:21 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 2691464E99; Mon, 1 Mar 2021 12:36:21 +0000 (UTC) Received: from mail-pf1-f172.google.com (mail-pf1-f172.google.com [209.85.210.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C5A2964E5C for ; Mon, 1 Mar 2021 12:36:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C5A2964E5C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=daniel@0x0f.com Received: by mail-pf1-f172.google.com with SMTP id e3so7418277pfj.6 for ; Mon, 01 Mar 2021 04:36:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+k4h3DmLpBdKDskL9GZ/5TFWOILyp4Yu88KprHaLQKE=; b=LXsgkHRudMusscZhb8tcXfF/UOSbdaiDWcQYPsD1X4Wq3fGQFyFSTcgYFNAa8NLPNq tTbnNz9qHrGUsGM9wVQ39viWKoq/ILyVTBh1LVGv/DhNUk/eOQCioNlhOHSm5JbM0DYN eANJzwaDFbvAKU1QILsouWS76VWxkq1hclLwI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+k4h3DmLpBdKDskL9GZ/5TFWOILyp4Yu88KprHaLQKE=; b=a2fz9yjdzWpAoQCePgjGEFTE8Kz5+fn3H+eqUy6UqRlhIMuTD3sOEzPqxEW7pPVRF4 RalUryN6cEXPXueMP8OMJPVUcLBGqInwDTPFosedgMWO977x5Hczf8iRXjh6zxJ8RJty lXG476YEVnDVxJHl+KMctWN3WULa+zlXrQowwm1nGvCbe4d6Aq9J6pTGSrrPUl3HN7h2 Obbs1VcHokDKW12EL9mCXIQpQQHGt3EzZWzJ1V6CWA3aj7LdNCTpUTdTwNM4JUnwFX1X RYzTv6SnVWZNVPcdfYAWnMuNrtQooeT6D97LY89fd3btZwhhT3X+0OImzLAyo/ICrKCZ nIaQ== X-Gm-Message-State: AOAM5325vShbSczlff2GbbJmFC0BXtvPpdT+/wcy/b2DRggyoTqqUUBg XQsWOYJgZ2Wx4vp9UpV6mslNOmTqcQisTg== X-Google-Smtp-Source: ABdhPJwTEPhmbXdM73IRV4qErcw1tHV6jN+BJBRpELMoKnNa4BLKg/pydkhpYosYCFC+tEFU67mx0g== X-Received: by 2002:a63:c1d:: with SMTP id b29mr13749890pgl.9.1614602180117; Mon, 01 Mar 2021 04:36:20 -0800 (PST) Received: from shiro.work (p345188-ipngn200408sizuokaden.shizuoka.ocn.ne.jp. [124.98.97.188]) by smtp.googlemail.com with ESMTPSA id 8sm18130928pfp.171.2021.03.01.04.36.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Mar 2021 04:36:19 -0800 (PST) From: Daniel Palmer List-Id: To: soc@kernel.org Cc: arnd@kernel.org, olof@lixom.net, w@1wt.eu, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Daniel Palmer Subject: [PATCH 2/3] ARM: mstar: Add the external clocks to the base dsti Date: Mon, 1 Mar 2021 21:35:41 +0900 Message-Id: <20210301123542.2800643-3-daniel@0x0f.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210301123542.2800643-1-daniel@0x0f.com> References: <20210301123542.2800643-1-daniel@0x0f.com> MIME-Version: 1.0 All of the currently known MStar/SigmaStar ARMv7 SoCs have an "xtal" clock input that is usually 24MHz and an "RTC xtal" that is usually 32KHz. The xtal input has to be connected to something so it's enabled by default. The MSC313 and MSC313E do not bring the RTC clock input out to the pins so it's impossible to connect it. The SSC8336 does bring the input out to the pins but it's not always actually connected to something. The RTC node needs to always be present because in the future the nodes for the clock muxes will refer to it even if it's not usable. The RTC node is disabled by default and should be enabled at the board level if the RTC input is wired up. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-v7.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index b0a21b0b731f..889c3804c251 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -46,6 +46,21 @@ pmu: pmu { interrupt-affinity = <&cpu0>; }; + clocks: clocks { + xtal: xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + rtc_xtal: rtc_xtal { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + status = "disabled"; + }; + }; + soc: soc { compatible = "simple-bus"; #address-cells = <1>; From patchwork Mon Mar 1 12:35:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Palmer X-Patchwork-Id: 12109613 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B86AC433DB for ; Mon, 1 Mar 2021 12:36:23 +0000 (UTC) Received: by mail.kernel.org (Postfix) id 21AB664E75; Mon, 1 Mar 2021 12:36:23 +0000 (UTC) Received: from mail-pj1-f50.google.com (mail-pj1-f50.google.com [209.85.216.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CEFD164EAE for ; Mon, 1 Mar 2021 12:36:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CEFD164EAE Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=0x0f.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=daniel@0x0f.com Received: by mail-pj1-f50.google.com with SMTP id e9so8408542pjs.2 for ; Mon, 01 Mar 2021 04:36:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=0x0f.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=536xRWNL7jknD9IRPbTVC2QcHZZ+m5eHrkYF4PRPpVs=; b=S8bV2V8DbZz51yB79NHw1Qy5wgklnsXO4bpxwk/7Yo8G5e9J+77QaPbiJbTcvc+dlt PMWdcbW2I+A1CUoKWv94xaPmPurGfHghp37tKPxyWJYu2jiT1maVOJXVjuit63g2TnO1 jcPvcbMs/uP1VXjWXhM7ZU/wuUToOBgqCOeM8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=536xRWNL7jknD9IRPbTVC2QcHZZ+m5eHrkYF4PRPpVs=; b=quepq1caP+gLn+UqUZ9eGW5YN9Ouf/tRAk8kgvT/khQIW14Ap9ZO7bC2P1U3XEX1uq hctRzhKtjXHTPU+TdW/ZV2vkdR2yWzohiaQCpNZ0/IrA5UK4VZlWTFih2/9T1A79x/eo hF8HdLa9xpxxnEoE0YgkycA6JGMFY0BzaibpYZb2Q9DVeoJBKxTnpjxOhsXperffdYkt uxGgG6IeMdBBJXXsnM8G+IGTFEVy1Jp36/+p+ivwSxaUHQzPqU6xARrWsFJgnehlAe+B R43maYdzBlVhIqp/TUI1al3/vyArsiJbXRazGWkJia6PogRYGLuBvmF/Gq7XqPrMX2aF Wqvw== X-Gm-Message-State: AOAM533hgMHoOyIzltRk6iXV9kuwYPT966T7k6mdnqw1U+EHlvQqFBTB e0T0HRwDW0hc3eZxhrMlXcoARGCrLU8o3Q== X-Google-Smtp-Source: ABdhPJxmG3O7GKhc9qGTw5SpHoWvJ1q6BkDMP4KXQkRz8Z1MS08I62eDj0MAiABHUQcXvEmu/Q8wlQ== X-Received: by 2002:a17:90a:6c22:: with SMTP id x31mr17844508pjj.213.1614602182273; Mon, 01 Mar 2021 04:36:22 -0800 (PST) Received: from shiro.work (p345188-ipngn200408sizuokaden.shizuoka.ocn.ne.jp. [124.98.97.188]) by smtp.googlemail.com with ESMTPSA id 8sm18130928pfp.171.2021.03.01.04.36.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Mar 2021 04:36:22 -0800 (PST) From: Daniel Palmer List-Id: To: soc@kernel.org Cc: arnd@kernel.org, olof@lixom.net, w@1wt.eu, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Daniel Palmer Subject: [PATCH 3/3] ARM: mstar: Add mpll to base dtsi Date: Mon, 1 Mar 2021 21:35:42 +0900 Message-Id: <20210301123542.2800643-4-daniel@0x0f.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210301123542.2800643-1-daniel@0x0f.com> References: <20210301123542.2800643-1-daniel@0x0f.com> MIME-Version: 1.0 All of the currently known MStar/SigmaStar ARMv7 SoCs have at least one MPLL and it seems to always be at the same place so add it to the base dtsi. Signed-off-by: Daniel Palmer --- arch/arm/boot/dts/mstar-v7.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 889c3804c251..075d583d6f40 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -6,6 +6,7 @@ #include #include +#include / { #address-cells = <1>; @@ -124,6 +125,13 @@ l3bridge: l3bridge@204400 { reg = <0x204400 0x200>; }; + mpll: mpll@206000 { + compatible = "mstar,msc313-mpll"; + #clock-cells = <1>; + reg = <0x206000 0x200>; + clocks = <&xtal>; + }; + gpio: gpio@207800 { #gpio-cells = <2>; reg = <0x207800 0x200>;