From patchwork Mon Mar 1 16:40:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Pinchart X-Patchwork-Id: 12110243 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95D57C433E0 for ; Mon, 1 Mar 2021 16:47:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 53A6B64F8F for ; Mon, 1 Mar 2021 16:47:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235130AbhCAQqs (ORCPT ); Mon, 1 Mar 2021 11:46:48 -0500 Received: from perceval.ideasonboard.com ([213.167.242.64]:44422 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233322AbhCAQld (ORCPT ); Mon, 1 Mar 2021 11:41:33 -0500 Received: from pendragon.lan (62-78-145-57.bb.dnainternet.fi [62.78.145.57]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 7540941; Mon, 1 Mar 2021 17:40:50 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1614616850; bh=kMfBkHDN7RFEJlDQXSSKlUfAQW+ErvHAIP4DY0y8wlc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=R2HsYgxy8wTX4KMB6CpcqZbj6YhFkSa1kl3Q6B2Q3NQ4e0fzn7ihhs3FqoB852gQz i0Lf1Uan46CbMqxPN+oNVqM2xpfES/JwaropHoMGGugRr9Wk0kAr/jBEcafJXMxHqQ vykFwrSNfjKmlXRe/LF/4yJZW61MjLBFnQ1+6Wfo= From: Laurent Pinchart To: linux-media@vger.kernel.org Cc: Rui Miguel Silva , Steve Longerbeam , Philipp Zabel , Ezequiel Garcia , Fabio Estevam Subject: [PATCH v2.1 70/77] media: imx: imx7_mipi_csis: Calculate Ths_settle from source lane rate Date: Mon, 1 Mar 2021 18:40:19 +0200 Message-Id: <20210301164019.13031-1-laurent.pinchart@ideasonboard.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20210215042741.28850-71-laurent.pinchart@ideasonboard.com> References: <20210215042741.28850-71-laurent.pinchart@ideasonboard.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The Ths_settle timing parameter depends solely on the lane data rate of the source. Calculate it at runtime instead of requiring it to be specified in the device tree. Signed-off-by: Laurent Pinchart --- Changes since v2: - Don't print hs_settle at probe time --- drivers/staging/media/imx/imx7-mipi-csis.c | 48 ++++++++++++++++++---- 1 file changed, 41 insertions(+), 7 deletions(-) diff --git a/drivers/staging/media/imx/imx7-mipi-csis.c b/drivers/staging/media/imx/imx7-mipi-csis.c index 333ab3966b5b..e1728240b494 100644 --- a/drivers/staging/media/imx/imx7-mipi-csis.c +++ b/drivers/staging/media/imx/imx7-mipi-csis.c @@ -24,6 +24,7 @@ #include #include +#include #include #include #include @@ -482,6 +483,39 @@ static void __mipi_csis_set_format(struct csi_state *state) mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH0, val); } +static int mipi_csis_calculate_params(struct csi_state *state) +{ + s64 link_freq; + u32 lane_rate; + + /* Calculate the line rate from the pixel rate. */ + link_freq = v4l2_get_link_freq(state->src_sd->ctrl_handler, + state->csis_fmt->width, + state->bus.num_data_lanes * 2); + if (link_freq < 0) { + dev_err(state->dev, "Unable to obtain link frequency: %d\n", + (int)link_freq); + return link_freq; + } + + lane_rate = link_freq * 2; + + if (lane_rate < 80000000 || lane_rate > 1500000000) { + dev_dbg(state->dev, "Out-of-bound lane rate %u\n", lane_rate); + return -EINVAL; + } + + /* + * The HSSETTLE counter value is document in a table, but can also + * easily be calculated. + */ + state->hs_settle = (lane_rate - 5000000) / 45000000; + dev_dbg(state->dev, "lane rate %u, Ths_settle %u\n", + lane_rate, state->hs_settle); + + return 0; +} + static void mipi_csis_set_params(struct csi_state *state) { int lanes = state->bus.num_data_lanes; @@ -608,9 +642,13 @@ static void mipi_csis_log_counters(struct csi_state *state, bool non_errors) static int mipi_csis_s_stream(struct v4l2_subdev *mipi_sd, int enable) { struct csi_state *state = mipi_sd_to_csis_state(mipi_sd); - int ret = 0; + int ret; if (enable) { + ret = mipi_csis_calculate_params(state); + if (ret < 0) + return ret; + mipi_csis_clear_counters(state); ret = pm_runtime_get_sync(&state->pdev->dev); if (ret < 0) { @@ -943,9 +981,6 @@ static int mipi_csis_parse_dt(struct platform_device *pdev, if (IS_ERR(state->mrst)) return PTR_ERR(state->mrst); - /* Get MIPI CSI-2 bus configuration from the endpoint node. */ - of_property_read_u32(node, "fsl,csis-hs-settle", &state->hs_settle); - return 0; } @@ -1143,9 +1178,8 @@ static int mipi_csis_probe(struct platform_device *pdev) goto unregister_all; } - dev_info(&pdev->dev, "lanes: %d, hs_settle: %d, freq: %u\n", - state->bus.num_data_lanes, state->hs_settle, - state->clk_frequency); + dev_info(&pdev->dev, "lanes: %d, freq: %u\n", + state->bus.num_data_lanes, state->clk_frequency); return 0; From patchwork Mon Mar 1 16:41:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Pinchart X-Patchwork-Id: 12110245 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EEADC433DB for ; Mon, 1 Mar 2021 16:47:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 367B465055 for ; Mon, 1 Mar 2021 16:47:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235203AbhCAQrD (ORCPT ); Mon, 1 Mar 2021 11:47:03 -0500 Received: from perceval.ideasonboard.com ([213.167.242.64]:44452 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234802AbhCAQmi (ORCPT ); Mon, 1 Mar 2021 11:42:38 -0500 Received: from pendragon.lan (62-78-145-57.bb.dnainternet.fi [62.78.145.57]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 7C725332; Mon, 1 Mar 2021 17:41:54 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1614616915; bh=NRxUQysokQ0kdDveb2reU8gNfxsXXdN2xmScRovTJqA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=wpbmcGIBTAX3TdMNvZHfrfQqiWg/Gl/h11TllxrquD2fhOc6cm3qEqMmB6EkWHE/h iQnZTcT10FGSjntQx95pkkcuos+OmSjWuO1YUlH3cZ609N78odltUpx9r10Eiu9HKq mbqlDn7m1YHG3w2FO/4bHpiis+ghxbGs6OKA6Juo= From: Laurent Pinchart To: linux-media@vger.kernel.org Cc: Rui Miguel Silva , Steve Longerbeam , Philipp Zabel , Ezequiel Garcia , Fabio Estevam Subject: [PATCH v2.1 75/77] media: imx: imx7_mipi_csis: Rename register macros to match datasheet Date: Mon, 1 Mar 2021 18:41:23 +0200 Message-Id: <20210301164123.13146-1-laurent.pinchart@ideasonboard.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20210215042741.28850-76-laurent.pinchart@ideasonboard.com> References: <20210215042741.28850-76-laurent.pinchart@ideasonboard.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Rename several register macros to match the names from the documentation. Signed-off-by: Laurent Pinchart Reviewed-by: Rui Miguel Silva --- Changes since v2: - Fix indentation - Address SCLKS_MASK and SCLKS_OFFSET --- drivers/staging/media/imx/imx7-mipi-csis.c | 172 ++++++++++----------- 1 file changed, 86 insertions(+), 86 deletions(-) diff --git a/drivers/staging/media/imx/imx7-mipi-csis.c b/drivers/staging/media/imx/imx7-mipi-csis.c index de1bc0146e59..f57268fad99c 100644 --- a/drivers/staging/media/imx/imx7-mipi-csis.c +++ b/drivers/staging/media/imx/imx7-mipi-csis.c @@ -63,61 +63,61 @@ #define MIPI_CSIS_CLK_CTRL_WCLK_SRC BIT(0) /* CSIS Interrupt mask */ -#define MIPI_CSIS_INTMSK 0x10 -#define MIPI_CSIS_INTMSK_EVEN_BEFORE BIT(31) -#define MIPI_CSIS_INTMSK_EVEN_AFTER BIT(30) -#define MIPI_CSIS_INTMSK_ODD_BEFORE BIT(29) -#define MIPI_CSIS_INTMSK_ODD_AFTER BIT(28) -#define MIPI_CSIS_INTMSK_FRAME_START BIT(24) -#define MIPI_CSIS_INTMSK_FRAME_END BIT(20) -#define MIPI_CSIS_INTMSK_ERR_SOT_HS BIT(16) -#define MIPI_CSIS_INTMSK_ERR_LOST_FS BIT(12) -#define MIPI_CSIS_INTMSK_ERR_LOST_FE BIT(8) -#define MIPI_CSIS_INTMSK_ERR_OVER BIT(4) -#define MIPI_CSIS_INTMSK_ERR_WRONG_CFG BIT(3) -#define MIPI_CSIS_INTMSK_ERR_ECC BIT(2) -#define MIPI_CSIS_INTMSK_ERR_CRC BIT(1) -#define MIPI_CSIS_INTMSK_ERR_UNKNOWN BIT(0) +#define MIPI_CSIS_INT_MSK 0x10 +#define MIPI_CSIS_INT_MSK_EVEN_BEFORE BIT(31) +#define MIPI_CSIS_INT_MSK_EVEN_AFTER BIT(30) +#define MIPI_CSIS_INT_MSK_ODD_BEFORE BIT(29) +#define MIPI_CSIS_INT_MSK_ODD_AFTER BIT(28) +#define MIPI_CSIS_INT_MSK_FRAME_START BIT(24) +#define MIPI_CSIS_INT_MSK_FRAME_END BIT(20) +#define MIPI_CSIS_INT_MSK_ERR_SOT_HS BIT(16) +#define MIPI_CSIS_INT_MSK_ERR_LOST_FS BIT(12) +#define MIPI_CSIS_INT_MSK_ERR_LOST_FE BIT(8) +#define MIPI_CSIS_INT_MSK_ERR_OVER BIT(4) +#define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG BIT(3) +#define MIPI_CSIS_INT_MSK_ERR_ECC BIT(2) +#define MIPI_CSIS_INT_MSK_ERR_CRC BIT(1) +#define MIPI_CSIS_INT_MSK_ERR_UNKNOWN BIT(0) /* CSIS Interrupt source */ -#define MIPI_CSIS_INTSRC 0x14 -#define MIPI_CSIS_INTSRC_EVEN_BEFORE BIT(31) -#define MIPI_CSIS_INTSRC_EVEN_AFTER BIT(30) -#define MIPI_CSIS_INTSRC_EVEN BIT(30) -#define MIPI_CSIS_INTSRC_ODD_BEFORE BIT(29) -#define MIPI_CSIS_INTSRC_ODD_AFTER BIT(28) -#define MIPI_CSIS_INTSRC_ODD (0x3 << 28) -#define MIPI_CSIS_INTSRC_NON_IMAGE_DATA (0xf << 28) -#define MIPI_CSIS_INTSRC_FRAME_START BIT(24) -#define MIPI_CSIS_INTSRC_FRAME_END BIT(20) -#define MIPI_CSIS_INTSRC_ERR_SOT_HS BIT(16) -#define MIPI_CSIS_INTSRC_ERR_LOST_FS BIT(12) -#define MIPI_CSIS_INTSRC_ERR_LOST_FE BIT(8) -#define MIPI_CSIS_INTSRC_ERR_OVER BIT(4) -#define MIPI_CSIS_INTSRC_ERR_WRONG_CFG BIT(3) -#define MIPI_CSIS_INTSRC_ERR_ECC BIT(2) -#define MIPI_CSIS_INTSRC_ERR_CRC BIT(1) -#define MIPI_CSIS_INTSRC_ERR_UNKNOWN BIT(0) -#define MIPI_CSIS_INTSRC_ERRORS 0xfffff +#define MIPI_CSIS_INT_SRC 0x14 +#define MIPI_CSIS_INT_SRC_EVEN_BEFORE BIT(31) +#define MIPI_CSIS_INT_SRC_EVEN_AFTER BIT(30) +#define MIPI_CSIS_INT_SRC_EVEN BIT(30) +#define MIPI_CSIS_INT_SRC_ODD_BEFORE BIT(29) +#define MIPI_CSIS_INT_SRC_ODD_AFTER BIT(28) +#define MIPI_CSIS_INT_SRC_ODD (0x3 << 28) +#define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA (0xf << 28) +#define MIPI_CSIS_INT_SRC_FRAME_START BIT(24) +#define MIPI_CSIS_INT_SRC_FRAME_END BIT(20) +#define MIPI_CSIS_INT_SRC_ERR_SOT_HS BIT(16) +#define MIPI_CSIS_INT_SRC_ERR_LOST_FS BIT(12) +#define MIPI_CSIS_INT_SRC_ERR_LOST_FE BIT(8) +#define MIPI_CSIS_INT_SRC_ERR_OVER BIT(4) +#define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG BIT(3) +#define MIPI_CSIS_INT_SRC_ERR_ECC BIT(2) +#define MIPI_CSIS_INT_SRC_ERR_CRC BIT(1) +#define MIPI_CSIS_INT_SRC_ERR_UNKNOWN BIT(0) +#define MIPI_CSIS_INT_SRC_ERRORS 0xfffff /* D-PHY status control */ -#define MIPI_CSIS_DPHYSTATUS 0x20 -#define MIPI_CSIS_DPHYSTATUS_ULPS_DAT BIT(8) -#define MIPI_CSIS_DPHYSTATUS_STOPSTATE_DAT BIT(4) -#define MIPI_CSIS_DPHYSTATUS_ULPS_CLK BIT(1) -#define MIPI_CSIS_DPHYSTATUS_STOPSTATE_CLK BIT(0) +#define MIPI_CSIS_DPHY_STATUS 0x20 +#define MIPI_CSIS_DPHY_STATUS_ULPS_DAT BIT(8) +#define MIPI_CSIS_DPHY_STATUS_STOPSTATE_DAT BIT(4) +#define MIPI_CSIS_DPHY_STATUS_ULPS_CLK BIT(1) +#define MIPI_CSIS_DPHY_STATUS_STOPSTATE_CLK BIT(0) /* D-PHY common control */ -#define MIPI_CSIS_DPHYCTRL 0x24 -#define MIPI_CSIS_DPHYCTRL_HSSETTLE(n) ((n) << 24) -#define MIPI_CSIS_DPHYCTRL_HSSETTLE_MASK GENMASK(31, 24) -#define MIPI_CSIS_DPHYCTRL_SCLKS_MASK (0x3 << 22) -#define MIPI_CSIS_DPHYCTRL_SCLKS_OFFSET 22 -#define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_CLK BIT(6) -#define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_DAT BIT(5) -#define MIPI_CSIS_DPHYCTRL_ENABLE_DAT BIT(1) -#define MIPI_CSIS_DPHYCTRL_ENABLE_CLK BIT(0) -#define MIPI_CSIS_DPHYCTRL_ENABLE (0x1f << 0) +#define MIPI_CSIS_DPHY_CMN_CTRL 0x24 +#define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(n) ((n) << 24) +#define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK GENMASK(31, 24) +#define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n) ((n) << 22) +#define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK GENMASK(23, 22) +#define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK BIT(6) +#define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT BIT(5) +#define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT BIT(1) +#define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK BIT(0) +#define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE (0x1f << 0) /* D-PHY Master and Slave Control register Low */ #define MIPI_CSIS_DPHY_BCTRL_L 0x30 @@ -163,7 +163,7 @@ #define MIPI_CSIS_DPHY_SCTRL_H 0x3c /* ISP Configuration register */ -#define MIPI_CSIS_ISPCONFIG_CH(n) (0x40 + (n) * 0x10) +#define MIPI_CSIS_ISP_CONFIG_CH(n) (0x40 + (n) * 0x10) #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK (0xff << 24) #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) ((x) << 24) #define MIPI_CSIS_ISPCFG_DOUBLE_CMPNT BIT(12) @@ -178,15 +178,15 @@ #define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2) /* ISP Image Resolution register */ -#define MIPI_CSIS_ISPRESOL_CH(n) (0x44 + (n) * 0x10) +#define MIPI_CSIS_ISP_RESOL_CH(n) (0x44 + (n) * 0x10) #define CSIS_MAX_PIX_WIDTH 0xffff #define CSIS_MAX_PIX_HEIGHT 0xffff /* ISP SYNC register */ -#define MIPI_CSIS_ISPSYNC_CH(n) (0x48 + (n) * 0x10) -#define MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET 18 -#define MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET 12 -#define MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET 0 +#define MIPI_CSIS_ISP_SYNC_CH(n) (0x48 + (n) * 0x10) +#define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET 18 +#define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET 12 +#define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET 0 /* Non-image packet data buffers */ #define MIPI_CSIS_PKTDATA_ODD 0x2000 @@ -209,22 +209,22 @@ struct mipi_csis_event { static const struct mipi_csis_event mipi_csis_events[] = { /* Errors */ - { MIPI_CSIS_INTSRC_ERR_SOT_HS, "SOT Error" }, - { MIPI_CSIS_INTSRC_ERR_LOST_FS, "Lost Frame Start Error" }, - { MIPI_CSIS_INTSRC_ERR_LOST_FE, "Lost Frame End Error" }, - { MIPI_CSIS_INTSRC_ERR_OVER, "FIFO Overflow Error" }, - { MIPI_CSIS_INTSRC_ERR_WRONG_CFG, "Wrong Configuration Error" }, - { MIPI_CSIS_INTSRC_ERR_ECC, "ECC Error" }, - { MIPI_CSIS_INTSRC_ERR_CRC, "CRC Error" }, - { MIPI_CSIS_INTSRC_ERR_UNKNOWN, "Unknown Error" }, + { MIPI_CSIS_INT_SRC_ERR_SOT_HS, "SOT Error" }, + { MIPI_CSIS_INT_SRC_ERR_LOST_FS, "Lost Frame Start Error" }, + { MIPI_CSIS_INT_SRC_ERR_LOST_FE, "Lost Frame End Error" }, + { MIPI_CSIS_INT_SRC_ERR_OVER, "FIFO Overflow Error" }, + { MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error" }, + { MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error" }, + { MIPI_CSIS_INT_SRC_ERR_CRC, "CRC Error" }, + { MIPI_CSIS_INT_SRC_ERR_UNKNOWN, "Unknown Error" }, /* Non-image data receive events */ - { MIPI_CSIS_INTSRC_EVEN_BEFORE, "Non-image data before even frame" }, - { MIPI_CSIS_INTSRC_EVEN_AFTER, "Non-image data after even frame" }, - { MIPI_CSIS_INTSRC_ODD_BEFORE, "Non-image data before odd frame" }, - { MIPI_CSIS_INTSRC_ODD_AFTER, "Non-image data after odd frame" }, + { MIPI_CSIS_INT_SRC_EVEN_BEFORE, "Non-image data before even frame" }, + { MIPI_CSIS_INT_SRC_EVEN_AFTER, "Non-image data after even frame" }, + { MIPI_CSIS_INT_SRC_ODD_BEFORE, "Non-image data before odd frame" }, + { MIPI_CSIS_INT_SRC_ODD_AFTER, "Non-image data after odd frame" }, /* Frame start/end */ - { MIPI_CSIS_INTSRC_FRAME_START, "Frame Start" }, - { MIPI_CSIS_INTSRC_FRAME_END, "Frame End" }, + { MIPI_CSIS_INT_SRC_FRAME_START, "Frame Start" }, + { MIPI_CSIS_INT_SRC_FRAME_END, "Frame End" }, }; #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events) @@ -444,7 +444,7 @@ static const struct csis_pix_format *find_csis_format(u32 code) static void mipi_csis_enable_interrupts(struct csi_state *state, bool on) { - mipi_csis_write(state, MIPI_CSIS_INTMSK, on ? 0xffffffff : 0); + mipi_csis_write(state, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0); } static void mipi_csis_sw_reset(struct csi_state *state) @@ -486,13 +486,13 @@ static void mipi_csis_system_enable(struct csi_state *state, int on) val &= ~MIPI_CSIS_CMN_CTRL_ENABLE; mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val); - val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL); - val &= ~MIPI_CSIS_DPHYCTRL_ENABLE; + val = mipi_csis_read(state, MIPI_CSIS_DPHY_CMN_CTRL); + val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE; if (on) { mask = (1 << (state->bus.num_data_lanes + 1)) - 1; - val |= (mask & MIPI_CSIS_DPHYCTRL_ENABLE); + val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE); } - mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val); + mipi_csis_write(state, MIPI_CSIS_DPHY_CMN_CTRL, val); } /* Called with the state.lock mutex held */ @@ -502,14 +502,14 @@ static void __mipi_csis_set_format(struct csi_state *state) u32 val; /* Color format */ - val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH(0)); + val = mipi_csis_read(state, MIPI_CSIS_ISP_CONFIG_CH(0)); val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK); val |= state->csis_fmt->fmt_reg; - mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH(0), val); + mipi_csis_write(state, MIPI_CSIS_ISP_CONFIG_CH(0), val); /* Pixel resolution */ val = mf->width | (mf->height << 16); - mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH(0), val); + mipi_csis_write(state, MIPI_CSIS_ISP_RESOL_CH(0), val); } static int mipi_csis_calculate_params(struct csi_state *state) @@ -558,13 +558,13 @@ static void mipi_csis_set_params(struct csi_state *state) __mipi_csis_set_format(state); - mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, - MIPI_CSIS_DPHYCTRL_HSSETTLE(state->hs_settle)); + mipi_csis_write(state, MIPI_CSIS_DPHY_CMN_CTRL, + MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(state->hs_settle)); - val = (0 << MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET) | - (0 << MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET) | - (0 << MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET); - mipi_csis_write(state, MIPI_CSIS_ISPSYNC_CH(0), val); + val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET) + | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET) + | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET); + mipi_csis_write(state, MIPI_CSIS_ISP_SYNC_CH(0), val); val = mipi_csis_read(state, MIPI_CSIS_CLK_CTRL); val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC; @@ -955,12 +955,12 @@ static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id) unsigned int i; u32 status; - status = mipi_csis_read(state, MIPI_CSIS_INTSRC); + status = mipi_csis_read(state, MIPI_CSIS_INT_SRC); spin_lock_irqsave(&state->slock, flags); /* Update the event/error counters */ - if ((status & MIPI_CSIS_INTSRC_ERRORS) || state->debug) { + if ((status & MIPI_CSIS_INT_SRC_ERRORS) || state->debug) { for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) { if (!(status & state->events[i].mask)) continue; @@ -969,7 +969,7 @@ static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id) } spin_unlock_irqrestore(&state->slock, flags); - mipi_csis_write(state, MIPI_CSIS_INTSRC, status); + mipi_csis_write(state, MIPI_CSIS_INT_SRC, status); return IRQ_HANDLED; }