From patchwork Tue Mar 2 11:51:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 12112845 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78AD5C4321A for ; Wed, 3 Mar 2021 04:25:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 45F4664E87 for ; Wed, 3 Mar 2021 04:25:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233257AbhCCEPC (ORCPT ); Tue, 2 Mar 2021 23:15:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1580308AbhCBSBl (ORCPT ); Tue, 2 Mar 2021 13:01:41 -0500 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 030FDC061793; Tue, 2 Mar 2021 03:51:43 -0800 (PST) Received: by mail-lj1-x233.google.com with SMTP id p15so14621375ljc.13; Tue, 02 Mar 2021 03:51:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S2GajrmIPPhVShSD9htWQH0c4G3php+jiJW9ohFhNDc=; b=a5NQi+dCliDqU3MZIq+HV1G7Hv02G5jQ0YFeFVSZ05AtJzCjeBzkUuynfOhQQrsZT1 +YSsRtVpekBd60kcBJL2wZWhFrnVdIdyrp3DSFSOWq1WzwaYFoydtpytUmoE0LGo+hdO PuGVU8a7n1MgPrQ7uD84HL4NdY0tcJJqyy/73Tn7geG0d8+OJ/L6G9tACVPZ2XiikmkB 8xUYvwGXLOeQaQ40VYUTwDc76BfOwVoEAC0TkyYDzy3gjltu1B9iZZB8P4rwmF/C7iJp 1WzbACU6/uQmiq7wUMQ9euWMHbDN13X8WKiyvtMHHG93/hAHrsj8syG3lMQgRgJZTn7i qwGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S2GajrmIPPhVShSD9htWQH0c4G3php+jiJW9ohFhNDc=; b=GQNboFbL8xcfNKc1TudNyrDTxPKpsrRoATSM39RhQliQU29yJlNr6bYWzUOhU9pD0G FPEhGW8VauBFSw/OqAbEaHhNh3JuUpFA6e6UhDCzwoE/H7morsz4i4hjgYoF4FvN8Jns 9SUeHEfXedd/ns3afH5EozuWQaI85p0Q/w5Y4imV64lEvjfxGgUwZG4U2DMuqBzEEcJF Kb1AQT59jFT3u1yWniNwPbq+uZcsOgzc/L4Ys3SLI6KGMAjo9wae3d1cIL7WJTae9NwV 81HNN7g4HnqKxEKQgCoyUZG+9aZQpOogmwyfA7/3nczzvfE/8kIv+nf8EczCL8/MAUE8 zdHQ== X-Gm-Message-State: AOAM53112BJoqeth2ol8GhddOLMPc/s2tbIZSNXQ6PqqPCIJ99NUXGNB +zXRI5jNN2umGXHdCZgCWiA= X-Google-Smtp-Source: ABdhPJyI63/HAHDw1/qnwJWecxidCq4Nihj3lXQGz7sFgGtD9auDUtWwRaK52RQSayhmGEumTOeeSw== X-Received: by 2002:a2e:b4c8:: with SMTP id r8mr6000300ljm.57.1614685901553; Tue, 02 Mar 2021 03:51:41 -0800 (PST) Received: from localhost.localdomain (109-252-193-52.dynamic.spd-mgts.ru. [109.252.193.52]) by smtp.gmail.com with ESMTPSA id f4sm2720151lja.69.2021.03.02.03.51.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Mar 2021 03:51:41 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/6] clk: tegra30: Use 300MHz for video decoder by default Date: Tue, 2 Mar 2021 14:51:12 +0300 Message-Id: <20210302115117.9375-2-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210302115117.9375-1-digetx@gmail.com> References: <20210302115117.9375-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The 600MHz is a too high clock rate for some SoC versions for the video decoder hardware and this may cause stability issues. Use 300MHz for the video decoder by default, which is supported by all hardware versions. Fixes: ed1a2459e20c ("clk: tegra: Add Tegra20/30 EMC clock implementation") Acked-by: Thierry Reding Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra30.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index 16dbf83d2f62..a33688b2359e 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1245,7 +1245,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 }, - { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 600000000, 0 }, + { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 300000000, 0 }, { TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, { TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 }, From patchwork Tue Mar 2 11:51:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 12112835 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BABEFC433E0 for ; Wed, 3 Mar 2021 04:25:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7285A64E84 for ; Wed, 3 Mar 2021 04:25:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236470AbhCCEME (ORCPT ); Tue, 2 Mar 2021 23:12:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1383900AbhCBMcS (ORCPT ); Tue, 2 Mar 2021 07:32:18 -0500 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD245C061794; Tue, 2 Mar 2021 03:51:43 -0800 (PST) Received: by mail-lj1-x22e.google.com with SMTP id r23so23541528ljh.1; Tue, 02 Mar 2021 03:51:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NgiEiyMoc7u/8Ng3SIz5oHTdRjhXUysxknviAcH7egQ=; b=UW3HlqC6QDEoPddiiI2KzzYcKDLA4dM/qS8t+kA7yWcSmbNAn//exk6p2jG3xrJq7R 5QPz7zbvaToxS39CLn8Mxh4EAq2aJ1coEWF+yVb1sc/uYGJx1nKZhuApXj5XKU7/y1DC 0TblblDF8YrbnHaNSu7fEb+j6n1aeSIpZqicwyFm+jV2wyJ1MGxTkh0MPPJDreWAONx7 KcXebtXqF//fHbHDGqB92h0H17SNNtk35c7niVHyN1y8DhVYKycKqjtYsMa6HC24qRRH lNAOW3o08KZPFEhMGo/bpOzxTp0tNSD1Oy/U/ZKrcBqeSlKEoVyCHQTLEr0GbHr/SWPO DgIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NgiEiyMoc7u/8Ng3SIz5oHTdRjhXUysxknviAcH7egQ=; b=oevW+BF/4jiB/9lFyDZ+wQPdOHHOY7L8pBTk4JKVvJhlCihNW2afdpITUkhvlR1qX4 ylfVWYvavLFMSVmttFUbHqg1vwf+GgGhkrDzXlU1Fk7X+EC9ihX4/1xI3dd8aSjZ7rp6 GKmBFYP6pPShfLANspHcjVPBzHH124I8FS24bQNCpmEH1LH+HHEc83WImg5gkWW8wmdx fUkUP/kz3aAoS3JewYDbEbkfRknUoXCcTArKncVNopKZZEYlqR6vgIvfru6VaQQFWkky hXpgXIK/rFo539QPFUz0kn0VQ5SQgYxBszht8JHAd+tjmL8EsYdDZKsF5jvAaE8K78Ek ZiQQ== X-Gm-Message-State: AOAM532TWcCmPQHYeWj1bovOKW3MhApWybZKP4f1v8W9JkM3cXt1sNBW QpUgaI6/vR0yMOyLq4r1zC0= X-Google-Smtp-Source: ABdhPJzVYoUbFmy+ERDy4vWMyjpMYklC/1O3ASfO1TGD8gMejiXgU76cMCR9EkinUSm/fQW58zOcZg== X-Received: by 2002:a05:651c:544:: with SMTP id q4mr11415260ljp.253.1614685902199; Tue, 02 Mar 2021 03:51:42 -0800 (PST) Received: from localhost.localdomain (109-252-193-52.dynamic.spd-mgts.ru. [109.252.193.52]) by smtp.gmail.com with ESMTPSA id f4sm2720151lja.69.2021.03.02.03.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Mar 2021 03:51:41 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/6] clk: tegra: Fix refcounting of gate clocks Date: Tue, 2 Mar 2021 14:51:13 +0300 Message-Id: <20210302115117.9375-3-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210302115117.9375-1-digetx@gmail.com> References: <20210302115117.9375-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The refcounting of the gate clocks has a bug causing the enable_refcnt to underflow when unused clocks are disabled. This happens because clk provider erroneously bumps the refcount if clock is enabled at a boot time, which it shouldn't be doing, and it does this only for the gate clocks, while peripheral clocks are using the same gate ops and the peripheral clocks are missing the initial bump. Hence the refcount of the peripheral clocks is 0 when unused clocks are disabled and then the counter is decremented further by the gate ops, causing the integer underflow. Fix this problem by removing the erroneous bump and by implementing the disable_unused() callback, which disables the unused gates properly. The visible effect of the bug is such that the unused clocks are never gated if a loaded kernel module grabs the unused clocks and starts to use them. In practice this shouldn't cause any real problems for the drivers and boards supported by the kernel today. Acked-by: Thierry Reding Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-periph-gate.c | 72 +++++++++++++++++++---------- drivers/clk/tegra/clk-periph.c | 11 +++++ 2 files changed, 58 insertions(+), 25 deletions(-) diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c index 4b31beefc9fc..3c4259fec82e 100644 --- a/drivers/clk/tegra/clk-periph-gate.c +++ b/drivers/clk/tegra/clk-periph-gate.c @@ -48,18 +48,9 @@ static int clk_periph_is_enabled(struct clk_hw *hw) return state; } -static int clk_periph_enable(struct clk_hw *hw) +static void clk_periph_enable_locked(struct clk_hw *hw) { struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); - unsigned long flags = 0; - - spin_lock_irqsave(&periph_ref_lock, flags); - - gate->enable_refcnt[gate->clk_num]++; - if (gate->enable_refcnt[gate->clk_num] > 1) { - spin_unlock_irqrestore(&periph_ref_lock, flags); - return 0; - } write_enb_set(periph_clk_to_bit(gate), gate); udelay(2); @@ -78,6 +69,32 @@ static int clk_periph_enable(struct clk_hw *hw) udelay(1); writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); } +} + +static void clk_periph_disable_locked(struct clk_hw *hw) +{ + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); + + /* + * If peripheral is in the APB bus then read the APB bus to + * flush the write operation in apb bus. This will avoid the + * peripheral access after disabling clock + */ + if (gate->flags & TEGRA_PERIPH_ON_APB) + tegra_read_chipid(); + + write_enb_clr(periph_clk_to_bit(gate), gate); +} + +static int clk_periph_enable(struct clk_hw *hw) +{ + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); + unsigned long flags = 0; + + spin_lock_irqsave(&periph_ref_lock, flags); + + if (!gate->enable_refcnt[gate->clk_num]++) + clk_periph_enable_locked(hw); spin_unlock_irqrestore(&periph_ref_lock, flags); @@ -91,21 +108,28 @@ static void clk_periph_disable(struct clk_hw *hw) spin_lock_irqsave(&periph_ref_lock, flags); - gate->enable_refcnt[gate->clk_num]--; - if (gate->enable_refcnt[gate->clk_num] > 0) { - spin_unlock_irqrestore(&periph_ref_lock, flags); - return; - } + WARN_ON(!gate->enable_refcnt[gate->clk_num]); + + if (gate->enable_refcnt[gate->clk_num]-- == 1) + clk_periph_disable_locked(hw); + + spin_unlock_irqrestore(&periph_ref_lock, flags); +} + +static void clk_periph_disable_unused(struct clk_hw *hw) +{ + struct tegra_clk_periph_gate *gate = to_clk_periph_gate(hw); + unsigned long flags = 0; + + spin_lock_irqsave(&periph_ref_lock, flags); /* - * If peripheral is in the APB bus then read the APB bus to - * flush the write operation in apb bus. This will avoid the - * peripheral access after disabling clock + * Some clocks are duplicated and some of them are marked as critical, + * like fuse and fuse_burn for example, thus the enable_refcnt will + * be non-zero here id the "unused" duplicate is disabled by CCF. */ - if (gate->flags & TEGRA_PERIPH_ON_APB) - tegra_read_chipid(); - - write_enb_clr(periph_clk_to_bit(gate), gate); + if (!gate->enable_refcnt[gate->clk_num]) + clk_periph_disable_locked(hw); spin_unlock_irqrestore(&periph_ref_lock, flags); } @@ -114,6 +138,7 @@ const struct clk_ops tegra_clk_periph_gate_ops = { .is_enabled = clk_periph_is_enabled, .enable = clk_periph_enable, .disable = clk_periph_disable, + .disable_unused = clk_periph_disable_unused, }; struct clk *tegra_clk_register_periph_gate(const char *name, @@ -148,9 +173,6 @@ struct clk *tegra_clk_register_periph_gate(const char *name, gate->enable_refcnt = enable_refcnt; gate->regs = pregs; - if (read_enb(gate) & periph_clk_to_bit(gate)) - enable_refcnt[clk_num]++; - /* Data in .init is copied by clk_register(), so stack variable OK */ gate->hw.init = &init; diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c index 67620c7ecd9e..79ca3aa072b7 100644 --- a/drivers/clk/tegra/clk-periph.c +++ b/drivers/clk/tegra/clk-periph.c @@ -100,6 +100,15 @@ static void clk_periph_disable(struct clk_hw *hw) gate_ops->disable(gate_hw); } +static void clk_periph_disable_unused(struct clk_hw *hw) +{ + struct tegra_clk_periph *periph = to_clk_periph(hw); + const struct clk_ops *gate_ops = periph->gate_ops; + struct clk_hw *gate_hw = &periph->gate.hw; + + gate_ops->disable_unused(gate_hw); +} + static void clk_periph_restore_context(struct clk_hw *hw) { struct tegra_clk_periph *periph = to_clk_periph(hw); @@ -126,6 +135,7 @@ const struct clk_ops tegra_clk_periph_ops = { .is_enabled = clk_periph_is_enabled, .enable = clk_periph_enable, .disable = clk_periph_disable, + .disable_unused = clk_periph_disable_unused, .restore_context = clk_periph_restore_context, }; @@ -135,6 +145,7 @@ static const struct clk_ops tegra_clk_periph_nodiv_ops = { .is_enabled = clk_periph_is_enabled, .enable = clk_periph_enable, .disable = clk_periph_disable, + .disable_unused = clk_periph_disable_unused, .restore_context = clk_periph_restore_context, }; From patchwork Tue Mar 2 11:51:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 12112849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A616C43333 for ; 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[109.252.193.52]) by smtp.gmail.com with ESMTPSA id f4sm2720151lja.69.2021.03.02.03.51.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Mar 2021 03:51:42 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/6] clk: tegra: Ensure that PLLU configuration is applied properly Date: Tue, 2 Mar 2021 14:51:14 +0300 Message-Id: <20210302115117.9375-4-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210302115117.9375-1-digetx@gmail.com> References: <20210302115117.9375-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org The PLLU (USB) consists of the PLL configuration itself and configuration of the PLLU outputs. The PLLU programming is inconsistent on T30 vs T114, where T114 immediately bails out if PLLU is enabled and T30 re-enables a potentially already enabled PLL (left after bootloader) and then fully reprograms it, which could be unsafe to do. The correct way should be to skip enabling of the PLL if it's already enabled and then apply configuration to the outputs. This patch doesn't fix any known problems, it's a minor improvement. Acked-by: Thierry Reding Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-pll.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index c5cc0a2dac6f..d709ecb7d8d7 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -1131,7 +1131,8 @@ static int clk_pllu_enable(struct clk_hw *hw) if (pll->lock) spin_lock_irqsave(pll->lock, flags); - _clk_pll_enable(hw); + if (!clk_pll_is_enabled(hw)) + _clk_pll_enable(hw); ret = clk_pll_wait_for_lock(pll); if (ret < 0) @@ -1748,15 +1749,13 @@ static int clk_pllu_tegra114_enable(struct clk_hw *hw) return -EINVAL; } - if (clk_pll_is_enabled(hw)) - return 0; - input_rate = clk_hw_get_rate(__clk_get_hw(osc)); if (pll->lock) spin_lock_irqsave(pll->lock, flags); - _clk_pll_enable(hw); + if (!clk_pll_is_enabled(hw)) + _clk_pll_enable(hw); ret = clk_pll_wait_for_lock(pll); if (ret < 0) From patchwork Tue Mar 2 11:51:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 12112837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3A8DC43331 for ; Wed, 3 Mar 2021 04:25:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B4C8D64E84 for ; Wed, 3 Mar 2021 04:25:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352764AbhCCENp (ORCPT ); Tue, 2 Mar 2021 23:13:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1448524AbhCBOVH (ORCPT ); Tue, 2 Mar 2021 09:21:07 -0500 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA15CC0617A7; Tue, 2 Mar 2021 03:51:44 -0800 (PST) Received: by mail-lj1-x22c.google.com with SMTP id e2so16368210ljo.7; Tue, 02 Mar 2021 03:51:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/OuucxeHi7PJrm8acOWag61CT7ykaXlnUVeZkx8Omt0=; b=ROQL/dhXDg5Y27qErAuirusjvCvGXignNERRBXjAv0CvJl83B9zCfXRk+vssCTQuSe sorWkpRTrXOmkIPwmMbNpZF+NEBBerllW4ulibhpy5PdNtBM0MOlt0I2BCWjdkAadQ/A R1M3PVLi0WEfGIx0koxvWyLITi4SdhnQBrWoW60ru2gla/9MT1xd2Z7fnxKO73v0xxXX Ye/PoeboWvjd4HDGeSV/BwwZqie/1iQPrX2+89U07uBAs2R5MCG36g+WnjWiFBYSrF2b jV6nPGhMxP12czpcGFYyy7+dc+kYxJRDK/E8C+0HVcLfhcHLs6x6f6Q1UFXxY2eoCEhy aI9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/OuucxeHi7PJrm8acOWag61CT7ykaXlnUVeZkx8Omt0=; b=sJHAMP8xXJhUkVK3QRKHaJYN/S4tBR+HWq06NJ3+Rl03ivHA5oOJ3vZyBEzP+/1PKO amcTx1Y/Nj+ciWfotsxgEk7AejJconftxRR3aXS/pS5KTmsVdk9GRf1Bymj5nyuvILJX oGlXdwiCr+gITRFaylKJrB94XIlJ1Gb0AJNS/li6D7fb9mSqjByx6ZM/GX5oBhfh9kKm U385V0D+go6Ay3TCFg9+MfC2XNIosQczlgcV8bkQM2jQVVpqgKb29dQuyzXhd+7m8OMF UVAa9BnNNuo2bDxV6ev8bdFxggv4HcGqLrjOkcA2VHQCY3keYn8gwP2yhgoIh1EP7I7e b62w== X-Gm-Message-State: AOAM5337QuLDZHm0owGfIeVGEU9HyQLhxmXZztELzRZSYCbMGsS6bEFH BYpYe4/PJzd20Y23RY/lTno= X-Google-Smtp-Source: ABdhPJxvAFpV5flsyCjZFesjEuXSRYhrqlM7qVyL8eMAxRrdkemgcDnXbx1+/wT2xtD5hatK14LZJg== X-Received: by 2002:a2e:a0d0:: with SMTP id f16mr12334231ljm.215.1614685903507; Tue, 02 Mar 2021 03:51:43 -0800 (PST) Received: from localhost.localdomain (109-252-193-52.dynamic.spd-mgts.ru. [109.252.193.52]) by smtp.gmail.com with ESMTPSA id f4sm2720151lja.69.2021.03.02.03.51.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Mar 2021 03:51:43 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/6] clk: tegra: Halve SCLK rate on Tegra20 Date: Tue, 2 Mar 2021 14:51:15 +0300 Message-Id: <20210302115117.9375-5-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210302115117.9375-1-digetx@gmail.com> References: <20210302115117.9375-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Higher SCLK rates on Tegra20 require high core voltage. The higher clock rate may have a positive performance effect only for AHB DMA transfers and AVP CPU, but both aren't used by upstream kernel at all. Halve SCLK rate on Tegra20 in order to remove the high core voltage requirement. Acked-by: Thierry Reding Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-tegra20.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 3efc651b42e3..3664593a5ba4 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1021,9 +1021,9 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 }, { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 }, { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 }, - { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 240000000, 0 }, - { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 240000000, 0 }, - { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 240000000, 0 }, + { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 0 }, + { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 120000000, 0 }, + { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 120000000, 0 }, { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 }, { TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 }, { TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 }, From patchwork Tue Mar 2 11:51:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 12112839 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FA17C4332E for ; Wed, 3 Mar 2021 04:25:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 583E564E87 for ; Wed, 3 Mar 2021 04:25:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236139AbhCCENJ (ORCPT ); Tue, 2 Mar 2021 23:13:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1446125AbhCBNQl (ORCPT ); Tue, 2 Mar 2021 08:16:41 -0500 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97312C0617A9; Tue, 2 Mar 2021 03:51:45 -0800 (PST) Received: by mail-lj1-x22c.google.com with SMTP id 2so19016042ljr.5; Tue, 02 Mar 2021 03:51:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hOjHRB69mCq2G+Xj/X2gbvje8jhvbBvQHq+6GJ2+Od8=; b=kcLAcYQYUkFawJCL3UQdTwwoffpy9C4olKM/nsMaJ15pv4BF8A3nmiGhx983dlVrPY 3eU9ZICtdyBRNQ1bjbYdOUluhW0rifLi6RXD8ovKPAgljHWYSH0S78RVj76XYgLKSyZA E58/F5ereotczp/CNlQzcYMmaePbsTavC7JHT1wIXJde2dGe7vFE/8Ueyk6w2bHo21VF Zdj39J+as46+9sakkas9FLWmQ5On9+NyAxFYc4VxgesRVpLgARrncyeSTmyHdrz4e2vT AngJ0ndqCiNIOHd59uGEVASysCnVnzGpHoOMqhlZARFzZcj9Jly6yWehhJu84VCtsHyH SOHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hOjHRB69mCq2G+Xj/X2gbvje8jhvbBvQHq+6GJ2+Od8=; b=hyzyBLd9qgVAaTm2NduOnlGTBcO1wXxbtFVU4WHZnYfolQjrAMnjlLI0wXhaq8Cvda dGNVSY0ufJAGHeyObPe4LMd1u9xkZ9sN5SpgxziOgDDzAPlFrnIX8rrkio9epWhEc+19 hBja1tuiNxw5YiUYyLGpzs3eH8BfroImGoZwiU3Z3ly6yClZY/FPrQi3hlBlZ3xCdJVh hHMJ0NnKyZFw9BPih+VWIB5JMiIghWdWL2A8w4LiVdRHhj8vGbS+b71MNV8+cTFVquJm Zz9rLWxt/jmEXH4Bk31gxO+MRbFVeFgEerCm9ehtg5ctwuQEXIxHTh/fi5QA7MXuzq3V z0vw== X-Gm-Message-State: AOAM531GACJTScH5bqaSCd72RhjXxuowdxx7URLCs9JkcOmJhD7Zf3a5 egvGzd0G9s4pDWSXR6PMvNk= X-Google-Smtp-Source: ABdhPJyhJaIQF0jtFjLD7MLoOjNv8qXxrEu88dNBKRzEqzdczwzNdDERuBYhvQfiHAU6Yt84ijJRyA== X-Received: by 2002:a2e:9145:: with SMTP id q5mr12533206ljg.54.1614685904153; Tue, 02 Mar 2021 03:51:44 -0800 (PST) Received: from localhost.localdomain (109-252-193-52.dynamic.spd-mgts.ru. [109.252.193.52]) by smtp.gmail.com with ESMTPSA id f4sm2720151lja.69.2021.03.02.03.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Mar 2021 03:51:43 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 5/6] MAINTAINERS: Hand Tegra clk driver to Jon and Thierry Date: Tue, 2 Mar 2021 14:51:16 +0300 Message-Id: <20210302115117.9375-6-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210302115117.9375-1-digetx@gmail.com> References: <20210302115117.9375-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Peter and Prashant aren't actively maintaining Tegra clock driver anymore. Jonathan and Thierry will pick up maintaining of the driver from now on. Acked-by: Thierry Reding Signed-off-by: Dmitry Osipenko --- CREDITS | 6 ++++++ MAINTAINERS | 4 ++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/CREDITS b/CREDITS index cef83b958cbe..e28724061f90 100644 --- a/CREDITS +++ b/CREDITS @@ -1250,6 +1250,10 @@ S: 29 Duchifat St. S: Ra'anana 4372029 S: Israel +N: Prashant Gaikwad +E: pgaikwad@nvidia.com +D: Maintained NVIDIA Tegra clock driver + N: Kumar Gala E: galak@kernel.crashing.org D: Embedded PowerPC 6xx/7xx/74xx/82xx/83xx/85xx support @@ -3387,7 +3391,9 @@ E: D: Macintosh IDE Driver N: Peter De Schrijver +E: pdeschrijver@nvidia.com E: stud11@cc4.kuleuven.ac.be +D: Maintained NVIDIA Tegra clock driver D: Mitsumi CD-ROM driver patches March version S: Molenbaan 29 S: B2240 Zandhoven diff --git a/MAINTAINERS b/MAINTAINERS index cac842923607..558c36f16680 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17587,8 +17587,8 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git N: [^a-z]tegra TEGRA CLOCK DRIVER -M: Peter De Schrijver -M: Prashant Gaikwad +M: Jonathan Hunter +M: Thierry Reding S: Supported F: drivers/clk/tegra/ From patchwork Tue Mar 2 11:51:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 12112841 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0229C432C3 for ; Wed, 3 Mar 2021 04:25:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6F91A64E84 for ; Wed, 3 Mar 2021 04:25:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1352740AbhCCEPL (ORCPT ); Tue, 2 Mar 2021 23:15:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1580311AbhCBSBl (ORCPT ); Tue, 2 Mar 2021 13:01:41 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45A1DC0617AA; Tue, 2 Mar 2021 03:51:46 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id k9so10901744lfo.12; Tue, 02 Mar 2021 03:51:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Aptp5NmMT0c2/gtpHM3jND6fOADz+c+cCW4tHwby9/0=; b=CX7XQ3GoFscwZMGxuAprdkK2a4Ju5XArGZ24+JTaHoSZbDUMIX3tylUM85HR+lIYwy 7EZLUdpKL34vby84vZXUo4i7EGGsd/Iq66dzQZNVvqPW3FTYpJFpRe3mrz+DKuSLzirC bEO+uBMbnnDiWPe42HL2721BLautywGKFN/DIqogn1BrjQmKG5VLYUXmEB7KKhkOhTeN Lp9n6BksMGi27Vei5UegQzsmt/OFS1A0gdbrarFEYhTm8jgAY5vTXf9Q6NpkeOlfs6RA umCVj6yOSH4emp6nwUDu4zrEJGXWWZXH1+I+AaBNY6JpYIHxTnRXj05wadUrjWLaAgnw ZgOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Aptp5NmMT0c2/gtpHM3jND6fOADz+c+cCW4tHwby9/0=; b=ZsMZHFr3yQhmPzdbxzHEJZvEWh7DB5CVF7bDmRaYllKxl852GX8pntlp+hm9nth9tH PzLdjOhLLlncflCAQC7UYbaOGvd0bGW94FSvhrSCuEcOl/4KhUhgb8efDdwxq4ocdKoC kPDsQJcBlWMcl7kKYaBzKl7HBRtsRUi5IxysC0i+FQQ1+y9ZjCe+CbTUgHvTuWcZ2Gum kqnFtSsMXEMS33GRoglMWfrXdArx2RhrNU+TCKC8MiE3UskK+4T6KlThzfXN9ED3uErk J2mvkzjGWKNtvchRPNuvpRHmLaQ1Op46sM6Y7p2Bq+Oe4ijtfwWjAa090V7gm6fFQasi pgJA== X-Gm-Message-State: AOAM53101k1kGkzj5Qbb65R2M0qZxwIg+Jxf0dw+TO8Rf/TaTJVMqb7q jj4Isoo9PdZs3tG8i7VvwIk= X-Google-Smtp-Source: ABdhPJwUa/fs69l5VobYIqUc2szq+QvQXNGsM9mxk1A52i95jEswLEFCVUXMJqqtPYq9V8LLFOrgFA== X-Received: by 2002:a19:c3c3:: with SMTP id t186mr11924940lff.596.1614685904824; Tue, 02 Mar 2021 03:51:44 -0800 (PST) Received: from localhost.localdomain (109-252-193-52.dynamic.spd-mgts.ru. [109.252.193.52]) by smtp.gmail.com with ESMTPSA id f4sm2720151lja.69.2021.03.02.03.51.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Mar 2021 03:51:44 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd Cc: linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 6/6] clk: tegra: Don't allow zero clock rate for PLLs Date: Tue, 2 Mar 2021 14:51:17 +0300 Message-Id: <20210302115117.9375-7-digetx@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210302115117.9375-1-digetx@gmail.com> References: <20210302115117.9375-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Zero clock rate doesn't make sense for PLLs and tegra-clk driver enters into infinite loop on trying to calculate PLL parameters for zero rate. Make code to error out if requested rate is zero. Originally this trouble was found by Robert Yang while he was trying to bring up upstream kernel on Samsung Galaxy Tab, which happened due to a bug in Tegra DRM driver that erroneously sets PLL rate to zero. This issues came over again recently during of kernel bring up on ASUS TF700T. Signed-off-by: Dmitry Osipenko --- drivers/clk/tegra/clk-pll.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index d709ecb7d8d7..af7d4941042e 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -558,6 +558,9 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, u32 p_div = 0; int ret; + if (!rate) + return -EINVAL; + switch (parent_rate) { case 12000000: case 26000000: