From patchwork Thu Mar 4 06:05:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 12115493 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8C5CC433E6 for ; Thu, 4 Mar 2021 06:07:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 98B0E64EF9 for ; Thu, 4 Mar 2021 06:07:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233606AbhCDGGR (ORCPT ); Thu, 4 Mar 2021 01:06:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39082 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233896AbhCDGGP (ORCPT ); Thu, 4 Mar 2021 01:06:15 -0500 Received: from mail-pg1-x52b.google.com (mail-pg1-x52b.google.com [IPv6:2607:f8b0:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 00BF3C061760 for ; Wed, 3 Mar 2021 22:05:34 -0800 (PST) Received: by mail-pg1-x52b.google.com with SMTP id p21so18190818pgl.12 for ; Wed, 03 Mar 2021 22:05:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Z8RUAsOxRMOpgK0k+D8Q9aGesIbnggJxLwFflwjLlcE=; b=it9UPNgFAIzPg4fVSgc7O0kA3WSkr3mcFUJUgL3CdAk9vcpuQS0aL4SNlGWFypGHmB Ndd3pKGbZiUntLVpDtHZ8A98VfzEw/Dg7E2yhsms5Cb9nNFYY6ygUAE5I3fhStVUNcdL d5RgQ/Ax9KBxnbPrnlXjh09DgithJCw9Ih4WIj3FVINHffzuNPejqTKmI2TJz6a/vIpB X54TwDc0LSp/PRXIlMYkVXfe+ygaiS3Vz4u/Pie0Sn+Ak8vishj1v/pCmA0wfirTSIlo xct19DLrL2Kk6yAUn7w5bo8a96KRz3iYoZizwrDSPltIfzA8jlYjzVMMpNe0SCpVG0iz cguQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Z8RUAsOxRMOpgK0k+D8Q9aGesIbnggJxLwFflwjLlcE=; b=ZnVnbIXSYUVF5WqNBlm5IBA9a0IRkpT8WnEQBrPrQGx2n+6u/AVPy1nckApmXi5srD ciSp9mtMMgRljyUCRcOnEk20680mbd4jqhEul+OObHJqflLMAK/qYCNVkbEXeHAglTOA 1fISd2Gxop2Fg/ryTZGzC6zVZNPspjNOFC4+nIDU48Tn73wIWVLNmviskptV7EgAflzV xlKbJUkvTIMn0csgTamjyu16snxorXT0a/YCFPvXtwi98gsEDQgu/3oLFW6JBYsf0EQ8 vK47Fqz6NuHxYB/h1eBHn7LZ3xI8WLfTS1rOzom9Rz66+2jQodNp433Jd+nZIuA4EHHR dThw== X-Gm-Message-State: AOAM531+09lXCadFtoa7lDR1+zkLeHYijj8wRCOk/xcxnwgVcmOQnVP8 5AjbJcTjCWIM7ydCdg+20VV0vjrrEBRY7g== X-Google-Smtp-Source: ABdhPJyreUBTtF030QQECYO3aAtKwXhfu5J12DNEA44oSodIQR88JnlIxhZOGWZV+zLQWLmgE4VvJw== X-Received: by 2002:aa7:808d:0:b029:1ed:993c:3922 with SMTP id v13-20020aa7808d0000b02901ed993c3922mr2522172pff.75.1614837934575; Wed, 03 Mar 2021 22:05:34 -0800 (PST) Received: from localhost.localdomain (80.251.214.228.16clouds.com. [80.251.214.228]) by smtp.gmail.com with ESMTPSA id j2sm776386pgh.39.2021.03.03.22.05.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 22:05:34 -0800 (PST) From: Shawn Guo To: Linus Walleij Cc: Bjorn Andersson , Andy Shevchenko , linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, Shawn Guo Subject: [PATCH v3 1/2] pinctrl: qcom: sc8180x: drop the use of tiles Date: Thu, 4 Mar 2021 14:05:19 +0800 Message-Id: <20210304060520.24975-2-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210304060520.24975-1-shawn.guo@linaro.org> References: <20210304060520.24975-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org To support both ACPI and DT, it makes more sense to not use tiles for pinctrl-sc8180x driver, as ACPI table describes TLMM block with one single memory resource. Since DTS of SC8180X hasn't landed, there is still chance to align DT description with ACPI. Signed-off-by: Shawn Guo --- drivers/pinctrl/qcom/pinctrl-sc8180x.c | 41 +++++++++----------------- 1 file changed, 14 insertions(+), 27 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-sc8180x.c b/drivers/pinctrl/qcom/pinctrl-sc8180x.c index b765bf667574..66f76ed22200 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8180x.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8180x.c @@ -11,17 +11,9 @@ #include "pinctrl-msm.h" -static const char * const sc8180x_tiles[] = { - "south", - "east", - "west" -}; - -enum { - SOUTH, - EAST, - WEST -}; +#define WEST 0x00100000 +#define EAST 0x00500000 +#define SOUTH 0x00d00000 #define FUNCTION(fname) \ [msm_mux_##fname] = { \ @@ -31,7 +23,7 @@ enum { } #define REG_SIZE 0x1000 -#define PINGROUP_OFFSET(id, _tile, offset, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ +#define PINGROUP_OFFSET(id, base, offset, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ { \ .name = "gpio" #id, \ .pins = gpio##id##_pins, \ @@ -49,12 +41,11 @@ enum { msm_mux_##f9 \ }, \ .nfuncs = 10, \ - .ctl_reg = REG_SIZE * id + offset, \ - .io_reg = REG_SIZE * id + 0x4 + offset, \ - .intr_cfg_reg = REG_SIZE * id + 0x8 + offset, \ - .intr_status_reg = REG_SIZE * id + 0xc + offset,\ - .intr_target_reg = REG_SIZE * id + 0x8 + offset,\ - .tile = _tile, \ + .ctl_reg = base + REG_SIZE * id + offset, \ + .io_reg = base + REG_SIZE * id + 0x4 + offset, \ + .intr_cfg_reg = base + REG_SIZE * id + 0x8 + offset, \ + .intr_status_reg = base + REG_SIZE * id + 0xc + offset, \ + .intr_target_reg = base + REG_SIZE * id + 0x8 + offset, \ .mux_bit = 2, \ .pull_bit = 0, \ .drv_bit = 6, \ @@ -71,20 +62,19 @@ enum { .intr_detection_width = 2, \ } -#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ - PINGROUP_OFFSET(id, _tile, 0x0, f1, f2, f3, f4, f5, f6, f7, f8, f9) +#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + PINGROUP_OFFSET(id, base, 0x0, f1, f2, f3, f4, f5, f6, f7, f8, f9) #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ { \ .name = #pg_name, \ .pins = pg_name##_pins, \ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ - .ctl_reg = ctl, \ + .ctl_reg = EAST + ctl, \ .io_reg = 0, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ .intr_target_reg = 0, \ - .tile = EAST, \ .mux_bit = -1, \ .pull_bit = pull, \ .drv_bit = drv, \ @@ -105,12 +95,11 @@ enum { .name = #pg_name, \ .pins = pg_name##_pins, \ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ - .ctl_reg = 0xb6000, \ - .io_reg = 0xb6004, \ + .ctl_reg = SOUTH + 0xb6000, \ + .io_reg = SOUTH + 0xb6004, \ .intr_cfg_reg = 0, \ .intr_status_reg = 0, \ .intr_target_reg = 0, \ - .tile = SOUTH, \ .mux_bit = -1, \ .pull_bit = 3, \ .drv_bit = 0, \ @@ -1575,8 +1564,6 @@ static const struct msm_gpio_wakeirq_map sc8180x_pdc_map[] = { }; static struct msm_pinctrl_soc_data sc8180x_pinctrl = { - .tiles = sc8180x_tiles, - .ntiles = ARRAY_SIZE(sc8180x_tiles), .pins = sc8180x_pins, .npins = ARRAY_SIZE(sc8180x_pins), .functions = sc8180x_functions, From patchwork Thu Mar 4 06:05:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 12115497 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D02BC433E0 for ; Thu, 4 Mar 2021 06:07:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 734D564EF4 for ; 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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id j2sm776386pgh.39.2021.03.03.22.05.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Mar 2021 22:05:36 -0800 (PST) From: Shawn Guo To: Linus Walleij Cc: Bjorn Andersson , Andy Shevchenko , linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, Shawn Guo Subject: [PATCH v3 2/2] pinctrl: qcom: sc8180x: add ACPI probe support Date: Thu, 4 Mar 2021 14:05:20 +0800 Message-Id: <20210304060520.24975-3-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210304060520.24975-1-shawn.guo@linaro.org> References: <20210304060520.24975-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org It adds ACPI probe support for pinctrl-sc8180x driver. Signed-off-by: Shawn Guo --- drivers/pinctrl/qcom/Kconfig | 2 +- drivers/pinctrl/qcom/pinctrl-sc8180x.c | 39 ++++++++++++++++++++++++-- 2 files changed, 38 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 6853a896c476..9f0218c4f9b3 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -222,7 +222,7 @@ config PINCTRL_SC7280 config PINCTRL_SC8180X tristate "Qualcomm Technologies Inc SC8180x pin controller driver" - depends on GPIOLIB && OF + depends on GPIOLIB && (OF || ACPI) select PINCTRL_MSM help This is the pinctrl, pinmux, pinconf and gpiolib driver for the diff --git a/drivers/pinctrl/qcom/pinctrl-sc8180x.c b/drivers/pinctrl/qcom/pinctrl-sc8180x.c index 66f76ed22200..45ecb4a022ca 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8180x.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8180x.c @@ -1546,6 +1546,13 @@ static const struct msm_pingroup sc8180x_groups[] = { [193] = SDC_QDSD_PINGROUP(sdc2_data, 0x4b2000, 9, 0), }; +static const int sc8180x_acpi_reserved_gpios[] = { + 0, 1, 2, 3, + 47, 48, 49, 50, + 126, 127, 128, 129, + -1 /* terminator */ +}; + static const struct msm_gpio_wakeirq_map sc8180x_pdc_map[] = { { 3, 31 }, { 5, 32 }, { 8, 33 }, { 9, 34 }, { 10, 100 }, { 12, 104 }, { 24, 37 }, { 26, 38 }, { 27, 41 }, { 28, 42 }, { 30, 39 }, { 36, 43 }, @@ -1575,13 +1582,40 @@ static struct msm_pinctrl_soc_data sc8180x_pinctrl = { .nwakeirq_map = ARRAY_SIZE(sc8180x_pdc_map), }; +static const struct msm_pinctrl_soc_data sc8180x_acpi_pinctrl = { + .pins = sc8180x_pins, + .npins = ARRAY_SIZE(sc8180x_pins), + .groups = sc8180x_groups, + .ngroups = ARRAY_SIZE(sc8180x_groups), + .reserved_gpios = sc8180x_acpi_reserved_gpios, + .ngpios = 191, +}; + static int sc8180x_pinctrl_probe(struct platform_device *pdev) { - return msm_pinctrl_probe(pdev, &sc8180x_pinctrl); + const struct msm_pinctrl_soc_data *soc_data; + + soc_data = device_get_match_data(&pdev->dev); + if (!soc_data) + return -EINVAL; + + return msm_pinctrl_probe(pdev, soc_data); } +static const struct acpi_device_id sc8180x_pinctrl_acpi_match[] = { + { + .id = "QCOM040D", + .driver_data = (kernel_ulong_t) &sc8180x_acpi_pinctrl, + }, + { } +}; +MODULE_DEVICE_TABLE(acpi, sc8180x_pinctrl_acpi_match); + static const struct of_device_id sc8180x_pinctrl_of_match[] = { - { .compatible = "qcom,sc8180x-tlmm", }, + { + .compatible = "qcom,sc8180x-tlmm", + .data = &sc8180x_pinctrl, + }, { }, }; MODULE_DEVICE_TABLE(of, sc8180x_pinctrl_of_match); @@ -1590,6 +1624,7 @@ static struct platform_driver sc8180x_pinctrl_driver = { .driver = { .name = "sc8180x-pinctrl", .of_match_table = sc8180x_pinctrl_of_match, + .acpi_match_table = sc8180x_pinctrl_acpi_match, }, .probe = sc8180x_pinctrl_probe, .remove = msm_pinctrl_remove,