From patchwork Mon Mar 8 23:38:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 12123527 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75B47C433DB for ; Mon, 8 Mar 2021 23:39:43 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 185966527D for ; Mon, 8 Mar 2021 23:39:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 185966527D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=7Q2mxbZnnckMjHGJPIaYXXqfJ9BQFaDd10IeQpXVgso=; b=hwPjrDTTR1icRyc8jqxDRiGQ+a HJ6u56uI60l/XjK/VW8tfRTxLVmh5hAJ/FHetT/ClH24VZN033LVt003DTPHUc9tSbc0qo5BFlIPT tU+Y2zb9mcekM3+2SnUlUF+5WR5i9KDhurBQbzoi4KFXBYjDlAVHBTkkL2gJ/8uFM7tMWYm9hQgDC W4NgVWTLKilpG23Zm+jGvVtu2m8IzFW0TL0w0hha9pH6R2Q53M/KSCRG6RPviongxyuAoJEmSVwY2 rDDJzLT9OLneWM4rMJTD0CiUttS2bYkw3K9jdsWvOb2PeFNi6KNoA1K+4pn8Z9YQRPoiuOdhrt1BW bw16uiyA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lJPTN-003OGr-Fq; Mon, 08 Mar 2021 23:39:37 +0000 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lJPT8-003ODZ-QT for linux-rockchip@lists.infradead.org; Mon, 08 Mar 2021 23:39:24 +0000 Received: by mail-wm1-x336.google.com with SMTP id b2-20020a7bc2420000b029010be1081172so4831500wmj.1 for ; Mon, 08 Mar 2021 15:39:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=eqyLkN28+VbZJ1BodN0k6GRf4WGaBBOV7lcLbkfiJBQ=; b=Xh+k5bGSptAyjUDGZQnXgFqbHzAG1QPvOAA81X4+86hLvLLPcBkxJp7PAp0mXyk8gI yAvz8MiX/7rbhLuhxHMMxcYXxEfCti/hBoXil6MGBKkmQ7gkro9wSdEKf2JNbhliCu0i VbGbqiqJfX8rUQjvkdQPoX6VJcl7sHNQuPGt309aH7ih1/9xWv+z297uaGFlfS+3Rijh del9/iXKRiBxWOGvTcprNCOUtJ6jMglS3lo8yhrgrim/WBjV+AUkG5L2AEQx8hro87Wr NRIbt0HqoqkQMZi1jxQpNbkKrBHGUatDDf4hPFqyXQIcIxSQ12Z2yRweL5U8hyLgpJ3+ +Eug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=eqyLkN28+VbZJ1BodN0k6GRf4WGaBBOV7lcLbkfiJBQ=; b=orFtDTS1QsvnaB9qT6xO199/U25pep/YNrxyFYviQ7oyYW9HhRYWIJfJVw9PSu2QlQ rUKILzueuSPMDpyLuWAMnnEvCszY4GuiKLGgqmtxwGquMddyZ/r6qbtgVfpktbS2jXsQ 2vlKxsfKRPVyto0SY0OIBlKuSGwfN3aIwtIJPVMeAmuSKE00JPqNdBjjYuBRo7Tso3oW vh97OtYEji9oAI8bMZpyRzz+WfK1OhpOU0bsPxOkpoTCKaljSbgwXUcGoAzuTdT6FxQB hkBLr/FxYvLGu2P1ehjkMtsVGqBKlGGnPA0odiy6/T59VUC0p8zX8MyFpmB3GA/Y6QV0 b3kQ== X-Gm-Message-State: AOAM5311QArsZQjCUvXfZTLv4yP2iwMj3EHkx/O/VbvwlGnNXAHS4ath 3u0NSKKD/nE8e7M1bapHOKuwtw== X-Google-Smtp-Source: ABdhPJx6PRCVhueYee+s5rTUuSEOQ5BGaZfr6qtVs+qF+7WlrvYJ8gsYqpzm7ZADmb/sCt4UW4mj3g== X-Received: by 2002:a1c:9849:: with SMTP id a70mr1108634wme.48.1615246761430; Mon, 08 Mar 2021 15:39:21 -0800 (PST) Received: from localhost.localdomain (lns-bzn-59-82-252-141-80.adsl.proxad.net. [82.252.141.80]) by smtp.gmail.com with ESMTPSA id b186sm1145408wmc.44.2021.03.08.15.39.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 15:39:21 -0800 (PST) From: Daniel Lezcano To: heiko@sntech.de Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Enric Balletbo i Serra , =?utf-8?q?Ga=C3=ABl_?= =?utf-8?q?PORTAY?= , Rob Herring , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , linux-pm@vger.kernel.org (open list:DEVICE FREQUENCY (DEVFREQ)), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [RESEND PATCH v5 1/4] dt-bindings: devfreq: rk3399_dmc: Add rockchip, pmu phandle. Date: Tue, 9 Mar 2021 00:38:55 +0100 Message-Id: <20210308233858.24741-1-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210308_233923_065092_D070092A X-CRM114-Status: GOOD ( 10.41 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From: Enric Balletbo i Serra The Rockchip DMC (Dynamic Memory Interface) needs to access to the PMU general register files to know the DRAM type, so add a phandle to the syscon that manages these registers. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Chanwoo Choi Acked-by: Rob Herring Signed-off-by: Gaël PORTAY Acked-by: MyungJoo Ham Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt index a10d1f6d85c6..a41bcfef95c8 100644 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt @@ -12,6 +12,8 @@ Required properties: for details. - center-supply: DMC supply node. - status: Marks the node enabled/disabled. +- rockchip,pmu: Phandle to the syscon managing the "PMU general register + files". Optional properties: - interrupts: The CPU interrupt number. The interrupt specifier From patchwork Mon Mar 8 23:38:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 12123529 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CE56C433DB for ; Mon, 8 Mar 2021 23:39:46 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D4F8664F96 for ; Mon, 8 Mar 2021 23:39:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D4F8664F96 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=4mAVb1bOT+L3+an+yEVCGtGRrq9JPjilM4wdqUjCuvk=; b=kCilqFM2MRoL99Wk8LOZ0LY3u Q29Bu9Im57/FHGvalzLH7pDid2ZAaALzLhB7fsKP/8oivUBo4DVR84XmqZ2VCYO9OUu/TzWgsk6wo qymJyqpQ8uFkYJopRk4d7WW1ib51kWrUeATY2vnXpQ9sn1S865xKC9dHOssJgjp6HJqFjqlxzezAx yTwlnkzx/93wDdkCyRiNKGJeBEJv/SvSsOKE2yUaIIKbdWoHQK5fjs/uzCEIbtknQ4WMqj5l000/P nYKEAjdsZ5a/uBDu8u0OnWVXE0amL8bwvCK3q8rvNCBV2AaSOoAUxuSL0zKafkjJi0sT5PjvDSlI1 Z19mO60Cg==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lJPTO-003OHO-Sg; Mon, 08 Mar 2021 23:39:39 +0000 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lJPTB-003OEP-Dz for linux-rockchip@lists.infradead.org; Mon, 08 Mar 2021 23:39:27 +0000 Received: by mail-wm1-x336.google.com with SMTP id d139-20020a1c1d910000b029010b895cb6f2so4827229wmd.5 for ; Mon, 08 Mar 2021 15:39:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cNI4lb320b0g3N9E/pXmEbLu1U21wMPwIZ392wgv3s0=; b=YcPsI338+uXPcczjZIr4QmN6Oyh6oeU8GRI3DSZWU3u/MWJjM8XgFa0Gb8xQ60FIuJ lzjDln7EN43CZ2axKiPiz31vDsxWjGmobql/eL7UYG7y3XCNXVZk5UCCwxpiaNGsupRK 0f05SH8UHs6G8D+vBiqFwlx6hjdrJfaT/0qeKJAv9gkTBqc18h9tmUqiebabPE7IIu1f iBRI34fSmAX3HLjR1L/DolojefjT/AiXjNQEwdPcFxTHxONrme0Op9ywkzOJgH1A0wf2 oXzx4B+03hMEdrUn3qIrj2ju5Y3+wdE0SIE2LEVe+KsvcpHeHGV3vgcvilfsF4BYcQML YStw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cNI4lb320b0g3N9E/pXmEbLu1U21wMPwIZ392wgv3s0=; b=WG4uu2Tf4gdPiYCXH+fBx1fKibivZ3MCHlHkcK7dxf65q3h3JRV5ABaiN6U9w3/T9R 5td+QA1UeAh4V3+NNHdsHMM4ms4gsH7AR+WwujOjeVNQERQoeFgDzkjkVzwjPvSGd7dm 6QdykNsd4o3SZsTVO+b3ewin1GJfjPpqEatf333yZqtAtL36vp3K7+B77ObyevCsgbs+ ojsX/Xr8sLURJpfbRhhzeHFSlUaCSzDrXRDGRljX78zVJFzfJQdvfs8TOVA6/7a7xGms IBYp/UaQCGmfmiZQoLn9vCyDElw9rMJJGMTsURTJaG8icQ3+ASk+M5kN2WyrkKphyZYZ qgDA== X-Gm-Message-State: AOAM531WP7uo4Xa0AH2LZ+LFMso93vbFELCbfRmnLo6lkOFBYfYifD8L xyYvxccfgMkkVnalMC2zqv+aKg== X-Google-Smtp-Source: ABdhPJzyFTtVk78UxQ9gsfuWPRMnCDwLJyL02l9xh21o6mqTHpXZXVEojYMD8BQd+qOCQw4hoQxpqA== X-Received: by 2002:a05:600c:289:: with SMTP id 9mr1023445wmk.135.1615246765017; Mon, 08 Mar 2021 15:39:25 -0800 (PST) Received: from localhost.localdomain (lns-bzn-59-82-252-141-80.adsl.proxad.net. [82.252.141.80]) by smtp.gmail.com with ESMTPSA id b186sm1145408wmc.44.2021.03.08.15.39.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 15:39:24 -0800 (PST) From: Daniel Lezcano To: heiko@sntech.de Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Lin Huang , Enric Balletbo i Serra , =?utf-8?q?Ga=C3=ABl_?= =?utf-8?q?PORTAY?= , Rob Herring , Johan Jonker , Helen Koike , Chen-Yu Tsai , Jacob Chen , Shunqian Zheng , Robin Murphy , Boris Brezillon , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [RESEND PATCH v5 2/4] arm64: dts: rk3399: Add dfi and dmc nodes. Date: Tue, 9 Mar 2021 00:38:56 +0100 Message-Id: <20210308233858.24741-2-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210308233858.24741-1-daniel.lezcano@linaro.org> References: <20210308233858.24741-1-daniel.lezcano@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210308_233925_620220_CB6FF04D X-CRM114-Status: UNSURE ( 9.78 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From: Lin Huang These are required to support DDR DVFS on rk3399 platform. Signed-off-by: Lin Huang Signed-off-by: Enric Balletbo i Serra Signed-off-by: Gaël PORTAY Signed-off-by: Daniel Lezcano --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index edbbf35fe19e..6f23d99236fe 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1937,6 +1937,25 @@ status = "disabled"; }; + dfi: dfi@ff630000 { + reg = <0x00 0xff630000 0x00 0x4000>; + compatible = "rockchip,rk3399-dfi"; + rockchip,pmu = <&pmugrf>; + interrupts = ; + clocks = <&cru PCLK_DDR_MON>; + clock-names = "pclk_ddr_mon"; + status = "disabled"; + }; + + dmc: dmc { + compatible = "rockchip,rk3399-dmc"; + rockchip,pmu = <&pmugrf>; + devfreq-events = <&dfi>; + clocks = <&cru SCLK_DDRC>; + clock-names = "dmc_clk"; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rk3399-pinctrl"; rockchip,grf = <&grf>; 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[82.252.141.80]) by smtp.gmail.com with ESMTPSA id b186sm1145408wmc.44.2021.03.08.15.39.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 15:39:32 -0800 (PST) From: Daniel Lezcano To: heiko@sntech.de Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Lin Huang , Enric Balletbo i Serra , =?utf-8?q?Ga=C3=ABl_?= =?utf-8?q?PORTAY?= , Rob Herring , Johan Jonker , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [RESEND PATCH v5 3/4] arm64: dts: rockchip: Enable dmc and dfi nodes on gru. Date: Tue, 9 Mar 2021 00:38:57 +0100 Message-Id: <20210308233858.24741-3-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210308233858.24741-1-daniel.lezcano@linaro.org> References: <20210308233858.24741-1-daniel.lezcano@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210308_233936_115684_8816DF44 X-CRM114-Status: GOOD ( 11.42 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From: Lin Huang Enable the DMC (Dynamic Memory Controller) and the DFI (DDR PHY Interface) nodes on gru boards so we can support DDR DVFS. Signed-off-by: Lin Huang Signed-off-by: Enric Balletbo i Serra Signed-off-by: Gaël PORTAY Signed-off-by: Daniel Lezcano --- .../dts/rockchip/rk3399-gru-chromebook.dtsi | 4 ++ arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 45 +++++++++++++++++++ .../boot/dts/rockchip/rk3399-op1-opp.dtsi | 29 ++++++++++++ 3 files changed, 78 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 1384dabbdf40..d32b015ad2cd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -398,3 +398,7 @@ ap_i2c_tp: &i2c5 { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + +&dmc { + center-supply = <&ppvar_centerlogic>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 32dcaf210085..fc3dc9a4b43c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -289,6 +289,12 @@ status = "okay"; }; +&dmc_opp_table { + opp04 { + opp-suspend; + }; +}; + /* * Set some suspend operating points to avoid OVP in suspend * @@ -489,6 +495,45 @@ ap_i2c_audio: &i2c8 { status = "okay"; }; +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + upthreshold = <25>; + downdifferential = <15>; + rockchip,ddr3_speed_bin = <21>; + rockchip,pd_idle = <0x40>; + rockchip,sr_idle = <0x2>; + rockchip,sr_mc_gate_idle = <0x3>; + rockchip,srpd_lite_idle = <0x4>; + rockchip,standby_idle = <0x2000>; + rockchip,dram_dll_dis_freq = <300000000>; + rockchip,phy_dll_dis_freq = <125000000>; + rockchip,auto_pd_dis_freq = <666000000>; + rockchip,ddr3_odt_dis_freq = <333000000>; + rockchip,ddr3_drv = <40>; + rockchip,ddr3_odt = <120>; + rockchip,phy_ddr3_ca_drv = <40>; + rockchip,phy_ddr3_dq_drv = <40>; + rockchip,phy_ddr3_odt = <240>; + rockchip,lpddr3_odt_dis_freq = <333000000>; + rockchip,lpddr3_drv = <34>; + rockchip,lpddr3_odt = <240>; + rockchip,phy_lpddr3_ca_drv = <40>; + rockchip,phy_lpddr3_dq_drv = <40>; + rockchip,phy_lpddr3_odt = <240>; + rockchip,lpddr4_odt_dis_freq = <333000000>; + rockchip,lpddr4_drv = <60>; + rockchip,lpddr4_dq_odt = <40>; + rockchip,lpddr4_ca_odt = <40>; + rockchip,phy_lpddr4_ca_drv = <40>; + rockchip,phy_lpddr4_ck_cs_drv = <80>; + rockchip,phy_lpddr4_dq_drv = <80>; + rockchip,phy_lpddr4_odt = <60>; +}; + &sdhci { /* * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the diff --git a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi index 69cc9b05baa5..c9e7032b01a8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi @@ -110,6 +110,31 @@ opp-microvolt = <1075000>; }; }; + + dmc_opp_table: dmc_opp_table { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <900000>; + }; + opp03 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000>; + }; + opp04 { + opp-hz = /bits/ 64 <928000000>; + opp-microvolt = <900000>; + }; + }; }; &cpu_l0 { @@ -139,3 +164,7 @@ &gpu { operating-points-v2 = <&gpu_opp_table>; }; + +&dmc { + operating-points-v2 = <&dmc_opp_table>; +}; From patchwork Mon Mar 8 23:38:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 12123533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CB9FC433E0 for ; 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[82.252.141.80]) by smtp.gmail.com with ESMTPSA id b186sm1145408wmc.44.2021.03.08.15.39.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Mar 2021 15:39:33 -0800 (PST) From: Daniel Lezcano To: heiko@sntech.de Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, =?utf-8?q?Ga=C3=ABl_PORTAY?= , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , linux-pm@vger.kernel.org (open list:DEVICE FREQUENCY (DEVFREQ)), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [RESEND PATCH v5 4/4] dt-bindings: devfreq: rk3399_dmc: Remove references of unexistant defines Date: Tue, 9 Mar 2021 00:38:58 +0100 Message-Id: <20210308233858.24741-4-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210308233858.24741-1-daniel.lezcano@linaro.org> References: <20210308233858.24741-1-daniel.lezcano@linaro.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210308_233936_128315_2CE1C7B3 X-CRM114-Status: GOOD ( 12.48 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org From: Gaël PORTAY Those DDR related defines do not exist. Replace their references with their numerical constant. Signed-off-by: Gaël PORTAY Reviewed-by: Rob Herring Signed-off-by: Daniel Lezcano --- .../bindings/devfreq/rk3399_dmc.txt | 73 +++++++++---------- 1 file changed, 34 insertions(+), 39 deletions(-) diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt index a41bcfef95c8..ddde2c4f97df 100644 --- a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt @@ -79,24 +79,23 @@ Following properties relate to DDR timing: - rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines the DRAM side driver strength in ohms. Default - value is DDR3_DS_40ohm. + value is 40. - rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines the DRAM side ODT strength in ohms. Default value - is DDR3_ODT_120ohm. + is 120. - rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines the phy side CA line (incluing command line, address line and clock line) driver strength. - Default value is PHY_DRV_ODT_40. + Default value is 40. - rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines the PHY side DQ line (including DQS/DQ/DM line) - driver strength. Default value is PHY_DRV_ODT_40. + driver strength. Default value is 40. - rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines - the PHY side ODT strength. Default value is - PHY_DRV_ODT_240. + the PHY side ODT strength. Default value is 240. - rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines then ODT disable frequency in MHz (Mega Hz). @@ -106,25 +105,23 @@ Following properties relate to DDR timing: - rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines the DRAM side driver strength in ohms. Default - value is LP3_DS_34ohm. + value is 34. - rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT strength in ohms. Default value - is LP3_ODT_240ohm. + is 240. - rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines the PHY side CA line (including command line, address line and clock line) driver strength. - Default value is PHY_DRV_ODT_40. + Default value is 40. - rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines the PHY side DQ line (including DQS/DQ/DM line) - driver strength. Default value is - PHY_DRV_ODT_40. + driver strength. Default value is 40. - rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define - the phy side odt strength, default value is - PHY_DRV_ODT_240. + the phy side odt strength, default value is 240. - rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter defines the ODT disable frequency in @@ -134,32 +131,30 @@ Following properties relate to DDR timing: - rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines the DRAM side driver strength in ohms. Default - value is LP4_PDDS_60ohm. + value is 60. - rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on DQS/DQ line strength in ohms. - Default value is LP4_DQ_ODT_40ohm. + Default value is 40. - rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on CA line strength in ohms. - Default value is LP4_CA_ODT_40ohm. + Default value is 40. - rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines the PHY side CA line (including command address - line) driver strength. Default value is - PHY_DRV_ODT_40. + line) driver strength. Default value is 40. - rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines the PHY side clock line and CS line driver - strength. Default value is PHY_DRV_ODT_80. + strength. Default value is 80. - rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line (including DQS/DQ/DM line) - driver strength. Default value is PHY_DRV_ODT_80. + driver strength. Default value is 80. - rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines - the PHY side ODT strength. Default value is - PHY_DRV_ODT_60. + the PHY side ODT strength. Default value is 60. Example: dmc_opp_table: dmc_opp_table { @@ -195,23 +190,23 @@ Example: rockchip,phy_dll_dis_freq = <125>; rockchip,auto_pd_dis_freq = <666>; rockchip,ddr3_odt_dis_freq = <333>; - rockchip,ddr3_drv = ; - rockchip,ddr3_odt = ; - rockchip,phy_ddr3_ca_drv = ; - rockchip,phy_ddr3_dq_drv = ; - rockchip,phy_ddr3_odt = ; + rockchip,ddr3_drv = <40>; + rockchip,ddr3_odt = <120>; + rockchip,phy_ddr3_ca_drv = <40>; + rockchip,phy_ddr3_dq_drv = <40>; + rockchip,phy_ddr3_odt = <240>; rockchip,lpddr3_odt_dis_freq = <333>; - rockchip,lpddr3_drv = ; - rockchip,lpddr3_odt = ; - rockchip,phy_lpddr3_ca_drv = ; - rockchip,phy_lpddr3_dq_drv = ; - rockchip,phy_lpddr3_odt = ; + rockchip,lpddr3_drv = <34>; + rockchip,lpddr3_odt = <240>; + rockchip,phy_lpddr3_ca_drv = <40>; + rockchip,phy_lpddr3_dq_drv = <40>; + rockchip,phy_lpddr3_odt = <240>; rockchip,lpddr4_odt_dis_freq = <333>; - rockchip,lpddr4_drv = ; - rockchip,lpddr4_dq_odt = ; - rockchip,lpddr4_ca_odt = ; - rockchip,phy_lpddr4_ca_drv = ; - rockchip,phy_lpddr4_ck_cs_drv = ; - rockchip,phy_lpddr4_dq_drv = ; - rockchip,phy_lpddr4_odt = ; + rockchip,lpddr4_drv = <60>; + rockchip,lpddr4_dq_odt = <40>; + rockchip,lpddr4_ca_odt = <40>; + rockchip,phy_lpddr4_ca_drv = <40>; + rockchip,phy_lpddr4_ck_cs_drv = <80>; + rockchip,phy_lpddr4_dq_drv = <80>; + rockchip,phy_lpddr4_odt = <60>; };