From patchwork Tue Mar 9 01:56:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Zhou X-Patchwork-Id: 12123845 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MIME_BASE64_TEXT,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 578F3C433E0 for ; Tue, 9 Mar 2021 02:04:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2859C65275 for ; Tue, 9 Mar 2021 02:04:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229764AbhCICDh (ORCPT ); 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Tue, 9 Mar 2021 10:03:07 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Mar 2021 10:03:07 +0800 From: Peng Zhou To: Eric Biggers , Ulf Hansson , Chaotian Jing , CC: , Adrian Hunter , Satya Tangirala , Wulin Li , Peng Zhou Subject: [PATCH v2 1/4] mmc: Mediatek: add Inline Crypto Engine support Date: Tue, 9 Mar 2021 09:56:31 +0800 Message-ID: <20210309015630.19545-1-peng.zhou@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-TM-SNTS-SMTP: 72253740D4C894CDB5A5941B85B082B1A76D6075D1C986720227B05D1B8E5AA52000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org 1. add crypto clock control and ungate it before CQHCI init 2. set MMC_CAP2_CRYPTO property of eMMC Signed-off-by: Peng Zhou --- drivers/mmc/host/mtk-sd.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 898ed1b023df..1c90360d6cf2 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -442,6 +442,7 @@ struct msdc_host { struct clk *src_clk_cg; /* msdc source clock control gate */ struct clk *sys_clk_cg; /* msdc subsys clock control gate */ struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; + struct clk *crypto_clk; /* msdc crypto clock */ u32 mclk; /* mmc subsystem clock frequency */ u32 src_clk_freq; /* source clock frequency */ unsigned char timing; @@ -802,6 +803,7 @@ static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) static void msdc_gate_clock(struct msdc_host *host) { + clk_disable_unprepare(host->crypto_clk); clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); clk_disable_unprepare(host->src_clk_cg); clk_disable_unprepare(host->src_clk); @@ -822,6 +824,7 @@ static void msdc_ungate_clock(struct msdc_host *host) dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); return; } + clk_prepare_enable(host->crypto_clk); while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) cpu_relax(); @@ -2512,6 +2515,15 @@ static int msdc_drv_probe(struct platform_device *pdev) goto host_free; } + /* only eMMC has crypto property */ + if ((mmc->caps2 & MMC_CAP2_NO_SD) && (mmc->caps2 & MMC_CAP2_NO_SDIO)) { + host->crypto_clk = devm_clk_get(&pdev->dev, "crypto"); + if (IS_ERR(host->crypto_clk)) + host->crypto_clk = NULL; + else + mmc->caps2 |= MMC_CAP2_CRYPTO; + } + host->irq = platform_get_irq(pdev, 0); if (host->irq < 0) { ret = -EINVAL; @@ -2582,6 +2594,8 @@ static int msdc_drv_probe(struct platform_device *pdev) host->dma_mask = DMA_BIT_MASK(32); mmc_dev(mmc)->dma_mask = &host->dma_mask; + /* here ungate due to cqhci init will access registers */ + msdc_ungate_clock(host); if (mmc->caps2 & MMC_CAP2_CQE) { host->cq_host = devm_kzalloc(mmc->parent, sizeof(*host->cq_host), @@ -2618,7 +2632,6 @@ static int msdc_drv_probe(struct platform_device *pdev) spin_lock_init(&host->lock); platform_set_drvdata(pdev, mmc); - msdc_ungate_clock(host); msdc_init_hw(host); ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, From patchwork Tue Mar 9 01:57:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Zhou X-Patchwork-Id: 12123847 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MIME_BASE64_TEXT,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4D97C433E0 for ; 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Tue, 09 Mar 2021 10:05:51 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by MTKMBS32N1.mediatek.inc (172.27.4.71) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 9 Mar 2021 10:05:47 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Mar 2021 10:05:46 +0800 From: Peng Zhou To: Eric Biggers , Ulf Hansson , Chaotian Jing , CC: , Adrian Hunter , Satya Tangirala , Wulin Li , Peng Zhou Subject: [PATCH v2 2/4] mmc: Mediatek: enable crypto hardware engine Date: Tue, 9 Mar 2021 09:57:51 +0800 Message-ID: <20210309015750.6283-1-peng.zhou@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-TM-SNTS-SMTP: 5ED153600B6D794E3DDF85777173329FED72E2B9C6542A1C7C67AE0CBB0AA6132000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Use SMC call enable hardware crypto engine due to it only be changed in ATF(EL3). Signed-off-by: Peng Zhou --- drivers/mmc/host/mtk-sd.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 1c90360d6cf2..225ef5519161 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -4,6 +4,7 @@ * Author: Chaotian.Jing */ +#include #include #include #include @@ -20,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -319,6 +321,12 @@ #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ #define PAD_DELAY_MAX 32 /* PAD delay cells */ + +/*--------------------------------------------------------------------------*/ +/* SiP commands which used for crypto */ +/*--------------------------------------------------------------------------*/ +#define MTK_SIP_MMC_CONTROL MTK_SIP_SMC_CMD(0x273) + /*--------------------------------------------------------------------------*/ /* Descriptor Structure */ /*--------------------------------------------------------------------------*/ @@ -2467,6 +2475,7 @@ static int msdc_of_clock_parse(struct platform_device *pdev, static int msdc_drv_probe(struct platform_device *pdev) { + struct arm_smccc_res smccc_res; struct mmc_host *mmc; struct msdc_host *host; struct resource *res; @@ -2616,6 +2625,15 @@ static int msdc_drv_probe(struct platform_device *pdev) mmc->max_seg_size = 64 * 1024; } + /* + * 1: MSDC_AES_CTL_INIT + * 4: cap_id, no-meaning now + * 1: cfg_id, we choose the second cfg group + */ + if (mmc->caps2 & MMC_CAP2_CRYPTO) + arm_smccc_smc(MTK_SIP_MMC_CONTROL, + 1, 4, 1, 0, 0, 0, 0, &smccc_res); + host->timeout_clks = 3 * 1048576; host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2 * sizeof(struct mt_gpdma_desc), @@ -2770,9 +2788,18 @@ static int __maybe_unused msdc_runtime_resume(struct device *dev) { struct mmc_host *mmc = dev_get_drvdata(dev); struct msdc_host *host = mmc_priv(mmc); + struct arm_smccc_res smccc_res; msdc_ungate_clock(host); msdc_restore_reg(host); + /* + * 1: MSDC_AES_CTL_INIT + * 4: cap_id, no-meaning now + * 1: cfg_id, we choose the second cfg group + */ + if (mmc->caps2 & MMC_CAP2_CRYPTO) + arm_smccc_smc(MTK_SIP_MMC_CONTROL, + 1, 4, 1, 0, 0, 0, 0, &smccc_res); return 0; } From patchwork Tue Mar 9 02:05:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Zhou X-Patchwork-Id: 12123849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MIME_BASE64_TEXT,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC4E3C433DB for ; Tue, 9 Mar 2021 02:13:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 91C0E6527B for ; Tue, 9 Mar 2021 02:13:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229797AbhCICMn (ORCPT ); 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Tue, 9 Mar 2021 10:12:16 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Mar 2021 10:12:16 +0800 From: Peng Zhou To: Eric Biggers , Ulf Hansson , Chaotian Jing , CC: , Adrian Hunter , Satya Tangirala , Wulin Li , Peng Zhou Subject: [PATCH v2 3/4] arm64: dts: Mediatek: MT6779: add mmc node with ICE setting Date: Tue, 9 Mar 2021 10:05:51 +0800 Message-ID: <20210309020550.18353-1-peng.zhou@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-TM-SNTS-SMTP: FAEBBAA6E0F71EECC9E685D6FB9A24C36222FC4F6905159FE2B6896E03F077602000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add mmc node with Inline Crypto Engine (ICE) for Mediatek eMMC controller on MT6779. Signed-off-by: Peng Zhou --- arch/arm64/boot/dts/mediatek/mt6779.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi index 9bdf5145966c..9246e59fa4a6 100644 --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi @@ -242,6 +242,20 @@ #clock-cells = <1>; }; + mmc0: mmc@11230000 { + compatible = "mediatek,mt6779-mmc"; + reg = <0 0x11230000 0 0x10000>, + <0 0x11f50000 0 0x10000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC50_0>, + <&infracfg_ao CLK_INFRA_MSDC0>, + <&infracfg_ao CLK_INFRA_MSDC0_SCK>, + <&infracfg_ao CLK_INFRA_AES_UFSFDE>; + clock-names = "source", "hclk", "source_cg", + "crypto"; + status = "disabled"; + }; + mfgcfg: clock-controller@13fbf000 { compatible = "mediatek,mt6779-mfgcfg", "syscon"; reg = <0 0x13fbf000 0 0x1000>; From patchwork Tue Mar 9 02:06:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Zhou X-Patchwork-Id: 12123851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MIME_BASE64_TEXT,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B80DDC433DB for ; Tue, 9 Mar 2021 02:13:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 77B6D6527B for ; Tue, 9 Mar 2021 02:13:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229688AbhCICNP (ORCPT ); Mon, 8 Mar 2021 21:13:15 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:2073 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229589AbhCICNP (ORCPT ); Mon, 8 Mar 2021 21:13:15 -0500 X-UUID: d55bf50da1714c48b98a191f0886a46e-20210309 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=HzSZXHmvNwYWi91TrlbB7npR6sCw+tpyWz5uepOikxY=; b=FMVq/xKtTjAst6TW9SzdBg1+JYETzqHfj4dkkTWnLTpi3nyCVf16WTr2u190jJY2PoXiLPpS8u5g7lJPks1UWyqnc3wKIoKeaBlZXX+dxsPfMKa/m48Fo/3s2wb4UCCD+GDmzngOkqCtQItlUc+1dJAReTh9TRKmhsRdkWKp15M=; X-UUID: d55bf50da1714c48b98a191f0886a46e-20210309 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2056281069; Tue, 09 Mar 2021 10:13:12 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by MTKMBS32N1.mediatek.inc (172.27.4.71) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 9 Mar 2021 10:13:09 +0800 Received: from localhost.localdomain (10.15.20.246) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 9 Mar 2021 10:13:02 +0800 From: Peng Zhou To: Eric Biggers , Ulf Hansson , Chaotian Jing , CC: , Adrian Hunter , Satya Tangirala , Wulin Li , Peng Zhou Subject: [PATCH v2 4/4] dt-bingdings: mmc: Mediatek: add ICE clock Date: Tue, 9 Mar 2021 10:06:50 +0800 Message-ID: <20210309020649.582-1-peng.zhou@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-TM-SNTS-SMTP: C7B9C1C986416529397245BF9289F010393F971BF14FF786B312334AFAD522B82000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Document the binding for crypto clock of the Inline Crypto Engine (ICE) on Mediatek SoCs. Signed-off-by: Peng Zhou Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index 01630b0ecea7..a81c14c88906 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -37,7 +37,7 @@ properties: description: Should contain phandle for the clock feeding the MMC controller. minItems: 2 - maxItems: 8 + maxItems: 9 items: - description: source clock (required). - description: HCLK which used for host (required). @@ -47,10 +47,11 @@ properties: - description: peripheral bus clock gate (required for MT8192). - description: AXI bus clock gate (required for MT8192). - description: AHB bus clock gate (required for MT8192). + - description: crypto clock used for data encrypt/decrypt (optional). clock-names: minItems: 2 - maxItems: 8 + maxItems: 9 items: - const: source - const: hclk @@ -60,6 +61,7 @@ properties: - const: pclk_cg - const: axi_cg - const: ahb_cg + - const: crypto pinctrl-names: items: