From patchwork Wed Mar 10 16:46:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Souradeep Chowdhury X-Patchwork-Id: 12128475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7C45C433E9 for ; Wed, 10 Mar 2021 16:48:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AF83064FD4 for ; Wed, 10 Mar 2021 16:48:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233255AbhCJQsZ (ORCPT ); Wed, 10 Mar 2021 11:48:25 -0500 Received: from m42-2.mailgun.net ([69.72.42.2]:60436 "EHLO m42-2.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233318AbhCJQsK (ORCPT ); Wed, 10 Mar 2021 11:48:10 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1615394890; h=References: In-Reply-To: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=r6TRjTpCRDb9yjUJxiphCJZipSbMlGWfC8pqUsCCPfA=; b=MGKeGzNzTlz2IqmQBAIo+Aocjzvk9oTGMXm3/i7vRl2dt3IuNVl+aBUc1fHqp6IvB5oNNXqg h38R/dlRC1yf0Mj7n1yi2wAnyb8i+l+xQfQlah5Ax52sDoPAzxgdNl5SJt8g87eHJ9ZaCdgI QDUs86Xsm7tKiaqmvf/gWtG+Qz8= X-Mailgun-Sending-Ip: 69.72.42.2 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n03.prod.us-west-2.postgun.com with SMTP id 6048f82f0c7cf0f56c7db6a9 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Wed, 10 Mar 2021 16:47:43 GMT Sender: schowdhu=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 0B0CEC43464; Wed, 10 Mar 2021 16:47:43 +0000 (UTC) Received: from blr-ubuntu-525.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: schowdhu) by smtp.codeaurora.org (Postfix) with ESMTPSA id 06F6FC433C6; Wed, 10 Mar 2021 16:47:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 06F6FC433C6 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=schowdhu@codeaurora.org From: Souradeep Chowdhury To: Rob Herring , Andy Gross , Bjorn Andersson Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, sibis@codeaurora.org, saiprakash.ranjan@codeaurora.org, Rajendra Nayak , vkoul@kernel.org, Souradeep Chowdhury Subject: [PATCH V1 1/6] dt-bindings: Added the yaml bindings for DCC Date: Wed, 10 Mar 2021 22:16:32 +0530 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Documentation for Data Capture and Compare(DCC) device tree bindings in yaml format. Signed-off-by: Souradeep Chowdhury --- .../devicetree/bindings/arm/msm/qcom,dcc.yaml | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml new file mode 100644 index 0000000..b8e9998 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/msm/qcom,dcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Data Capture and Compare + +maintainers: + - Souradeep Chowdhury + +description: | + DCC (Data Capture and Compare) is a DMA engine which is used to save + configuration data or system memory contents during catastrophic failure + or SW trigger. DCC is used to capture and store data for debugging purpose + + +properties: + compatible: + items: + - enum: + - qcom,sm8150-dcc + - const: qcom,dcc + + reg: + items: + - description: DCC base register region + - description: DCC RAM base register region + + reg-names: + items: + - const: dcc-base + - const: dcc-ram-base + +required: + - compatible + - reg + - reg-names + +additionalProperties: false + +examples: + - | + dcc@10a2000{ + compatible = "qcom,sm8150-dcc","qcom,dcc"; + reg = <0x010a2000 0x1000>, + <0x010ad000 0x2000>; + reg-names = "dcc-base", "dcc-ram-base"; + }; From patchwork Wed Mar 10 16:46:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Souradeep Chowdhury X-Patchwork-Id: 12128477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBF59C433E6 for ; Wed, 10 Mar 2021 16:48:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BDF9364FC3 for ; Wed, 10 Mar 2021 16:48:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233131AbhCJQsZ (ORCPT ); Wed, 10 Mar 2021 11:48:25 -0500 Received: from z11.mailgun.us ([104.130.96.11]:40899 "EHLO z11.mailgun.us" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233252AbhCJQsB (ORCPT ); Wed, 10 Mar 2021 11:48:01 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1615394881; h=References: In-Reply-To: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=ZcYHkAn24Jg6/fkEViWSKbPJn/xQGulQTgYx4syHdoE=; b=oTx9j0V/JvZP18hm59JSGlwSRI0n+8yLiW9OxN4vAtycF9wF6LprlfU/VU5s97ccCAXZ06OW 8FG2rnycutjnVOAP1DyDQL52J/chA/HDVrjwTAZfoqZ66YWJH213k5IHDNcvGjuL9+hfDao1 Yp/E7hqFYhhg7EcapE882kfYxUM= X-Mailgun-Sending-Ip: 104.130.96.11 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n05.prod.us-east-1.postgun.com with SMTP id 6048f838d3a53bc38f37661e (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Wed, 10 Mar 2021 16:47:52 GMT Sender: schowdhu=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 0DF01C433C6; Wed, 10 Mar 2021 16:47:52 +0000 (UTC) Received: from blr-ubuntu-525.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: schowdhu) by smtp.codeaurora.org (Postfix) with ESMTPSA id 476D1C433C6; Wed, 10 Mar 2021 16:47:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 476D1C433C6 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=schowdhu@codeaurora.org From: Souradeep Chowdhury To: Rob Herring , Andy Gross , Bjorn Andersson Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, sibis@codeaurora.org, saiprakash.ranjan@codeaurora.org, Rajendra Nayak , vkoul@kernel.org, Souradeep Chowdhury Subject: [PATCH V1 2/6] soc: qcom: dcc: Add driver support for Data Capture and Compare unit(DCC) Date: Wed, 10 Mar 2021 22:16:33 +0530 Message-Id: <48556129a02c9f7cd0b31b2e8ee0f168e6d211b7.1615393454.git.schowdhu@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The DCC is a DMA Engine designed to capture and store data during system crash or software triggers. The DCC operates based on link list entries which provides it with data and addresses and the function it needs to perform. These functions are read, write and loop. Added the basic driver in this patch which contains a probe method which instantiates the resources needed by the driver. DCC has it's own SRAM which needs to be instantiated at probe time as well. Signed-off-by: Souradeep Chowdhury --- drivers/soc/qcom/Kconfig | 8 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/dcc.c | 388 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 397 insertions(+) create mode 100644 drivers/soc/qcom/dcc.c diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 79b568f..8819e0b 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -69,6 +69,14 @@ config QCOM_LLCC SDM845. This provides interfaces to clients that use the LLCC. Say yes here to enable LLCC slice driver. +config QCOM_DCC + tristate "Qualcomm Technologies, Inc. Data Capture and Compare engine driver" + depends on ARCH_QCOM || COMPILE_TEST + help + This option enables driver for Data Capture and Compare engine. DCC + driver provides interface to configure DCC block and read back + captured data from DCC's internal SRAM. + config QCOM_KRYO_L2_ACCESSORS bool depends on ARCH_QCOM && ARM64 || COMPILE_TEST diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index ad675a6..1b00870 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -26,3 +26,4 @@ obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o +obj-$(CONFIG_QCOM_DCC) += dcc.o diff --git a/drivers/soc/qcom/dcc.c b/drivers/soc/qcom/dcc.c new file mode 100644 index 0000000..89816bf --- /dev/null +++ b/drivers/soc/qcom/dcc.c @@ -0,0 +1,388 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define dcc_readl(drvdata, off) \ + readl(drvdata->base + dcc_offset_conv(drvdata, off)) + +/* DCC registers */ +#define DCC_HW_INFO 0x04 +#define DCC_LL_NUM_INFO 0x10 + +#define DCC_MAP_LEVEL1 0x18 +#define DCC_MAP_LEVEL2 0x34 +#define DCC_MAP_LEVEL3 0x4C + +#define DCC_MAP_OFFSET1 0x10 +#define DCC_MAP_OFFSET2 0x18 +#define DCC_MAP_OFFSET3 0x1C +#define DCC_MAP_OFFSET4 0x8 + +#define DCC_FIX_LOOP_OFFSET 16 +#define DCC_VER_INFO_BIT 9 + +#define DCC_MAX_LINK_LIST 8 +#define DCC_INVALID_LINK_LIST GENMASK(7, 0) + +#define DCC_VER_MASK1 GENMASK(6, 0) +#define DCC_VER_MASK2 GENMASK(5, 0) + +#define DCC_RD_MOD_WR_ADDR 0xC105E + +struct qcom_dcc_config { + const int dcc_ram_offset; +}; + +enum dcc_mem_map_ver { + DCC_MEM_MAP_VER1, + DCC_MEM_MAP_VER2, + DCC_MEM_MAP_VER3 +}; + +enum dcc_descriptor_type { + DCC_ADDR_TYPE, + DCC_LOOP_TYPE, + DCC_READ_WRITE_TYPE, + DCC_WRITE_TYPE +}; + +struct dcc_config_entry { + u32 base; + u32 offset; + u32 len; + u32 index; + u32 loop_cnt; + u32 write_val; + u32 mask; + bool apb_bus; + enum dcc_descriptor_type desc_type; + struct list_head list; +}; + +struct dcc_drvdata { + void __iomem *base; + u32 reg_size; + struct device *dev; + struct mutex mutex; + void __iomem *ram_base; + u32 ram_size; + u32 ram_offset; + enum dcc_mem_map_ver mem_map_ver; + u32 ram_cfg; + u32 ram_start; + bool *enable; + bool *configured; + bool interrupt_disable; + char *sram_node; + struct cdev sram_dev; + struct class *sram_class; + struct list_head *cfg_head; + u32 *nr_config; + u32 nr_link_list; + u8 curr_list; + u8 loopoff; +}; + +static u32 dcc_offset_conv(struct dcc_drvdata *drvdata, u32 off) +{ + if (drvdata->mem_map_ver == DCC_MEM_MAP_VER1) { + if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL3) + return (off - DCC_MAP_OFFSET3); + if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL2) + return (off - DCC_MAP_OFFSET2); + else if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL1) + return (off - DCC_MAP_OFFSET1); + } else if (drvdata->mem_map_ver == DCC_MEM_MAP_VER2) { + if ((off & DCC_VER_MASK1) >= DCC_MAP_LEVEL2) + return (off - DCC_MAP_OFFSET4); + } + return off; +} + +static void dcc_config_reset(struct dcc_drvdata *drvdata) +{ + struct dcc_config_entry *entry, *temp; + int curr_list; + + mutex_lock(&drvdata->mutex); + + for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) { + + list_for_each_entry_safe(entry, temp, + &drvdata->cfg_head[curr_list], list) { + list_del(&entry->list); + devm_kfree(drvdata->dev, entry); + drvdata->nr_config[curr_list]--; + } + } + drvdata->ram_start = 0; + drvdata->ram_cfg = 0; + mutex_unlock(&drvdata->mutex); +} + +static int dcc_sram_open(struct inode *inode, struct file *file) +{ + struct dcc_drvdata *drvdata = container_of(inode->i_cdev, + struct dcc_drvdata, + sram_dev); + file->private_data = drvdata; + + return 0; +} + +static ssize_t dcc_sram_read(struct file *file, char __user *data, + size_t len, loff_t *ppos) +{ + unsigned char *buf; + struct dcc_drvdata *drvdata = file->private_data; + + /* EOF check */ + if (drvdata->ram_size <= *ppos) + return 0; + + if ((*ppos + len) > drvdata->ram_size) + len = (drvdata->ram_size - *ppos); + + buf = kzalloc(len, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + memcpy_fromio(buf, (drvdata->ram_base + *ppos), len); + + if (copy_to_user(data, buf, len)) { + dev_err(drvdata->dev, "DCC: Couldn't copy all data to user\n"); + kfree(buf); + return -EFAULT; + } + + *ppos += len; + + kfree(buf); + + return len; +} + +static const struct file_operations dcc_sram_fops = { + .owner = THIS_MODULE, + .open = dcc_sram_open, + .read = dcc_sram_read, + .llseek = no_llseek, +}; + +static int dcc_sram_dev_register(struct dcc_drvdata *drvdata) +{ + int ret; + struct device *device; + dev_t dev; + + ret = alloc_chrdev_region(&dev, 0, 1, drvdata->sram_node); + if (ret) + goto err_alloc; + + cdev_init(&drvdata->sram_dev, &dcc_sram_fops); + + drvdata->sram_dev.owner = THIS_MODULE; + ret = cdev_add(&drvdata->sram_dev, dev, 1); + if (ret) + goto err_cdev_add; + + drvdata->sram_class = class_create(THIS_MODULE, drvdata->sram_node); + if (IS_ERR(drvdata->sram_class)) { + ret = PTR_ERR(drvdata->sram_class); + goto err_class_create; + } + + device = device_create(drvdata->sram_class, NULL, + drvdata->sram_dev.dev, drvdata, + drvdata->sram_node); + if (IS_ERR(device)) { + ret = PTR_ERR(device); + goto err_dev_create; + } + + return 0; +err_dev_create: + class_destroy(drvdata->sram_class); +err_class_create: + cdev_del(&drvdata->sram_dev); +err_cdev_add: + unregister_chrdev_region(drvdata->sram_dev.dev, 1); +err_alloc: + return ret; +} + +static void dcc_sram_dev_deregister(struct dcc_drvdata *drvdata) +{ + device_destroy(drvdata->sram_class, drvdata->sram_dev.dev); + class_destroy(drvdata->sram_class); + cdev_del(&drvdata->sram_dev); + unregister_chrdev_region(drvdata->sram_dev.dev, 1); +} + +static int dcc_sram_dev_init(struct dcc_drvdata *drvdata) +{ + int ret = 0; + size_t node_size; + char *node_name = "dcc_sram"; + struct device *dev = drvdata->dev; + + node_size = strlen(node_name) + 1; + + drvdata->sram_node = devm_kzalloc(dev, node_size, GFP_KERNEL); + if (!drvdata->sram_node) + return -ENOMEM; + + strlcpy(drvdata->sram_node, node_name, node_size); + ret = dcc_sram_dev_register(drvdata); + if (ret) + dev_err(drvdata->dev, "DCC: sram node not registered.\n"); + + return ret; +} + +static void dcc_sram_dev_exit(struct dcc_drvdata *drvdata) +{ + dcc_sram_dev_deregister(drvdata); +} + +static int dcc_probe(struct platform_device *pdev) +{ + int ret = 0, i; + struct device *dev = &pdev->dev; + struct dcc_drvdata *drvdata; + struct resource *res; + const struct qcom_dcc_config *cfg; + + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->dev = &pdev->dev; + platform_set_drvdata(pdev, drvdata); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dcc-base"); + if (!res) + return -EINVAL; + + drvdata->reg_size = resource_size(res); + drvdata->base = devm_ioremap(dev, res->start, resource_size(res)); + if (!drvdata->base) + return -ENOMEM; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "dcc-ram-base"); + if (!res) + return -EINVAL; + + drvdata->ram_size = resource_size(res); + drvdata->ram_base = devm_ioremap(dev, res->start, resource_size(res)); + if (!drvdata->ram_base) + return -ENOMEM; + cfg = of_device_get_match_data(&pdev->dev); + drvdata->ram_offset = cfg->dcc_ram_offset; + + if (FIELD_GET(BIT(DCC_VER_INFO_BIT), dcc_readl(drvdata, DCC_HW_INFO))) { + drvdata->mem_map_ver = DCC_MEM_MAP_VER3; + drvdata->nr_link_list = dcc_readl(drvdata, DCC_LL_NUM_INFO); + if (drvdata->nr_link_list == 0) + return -EINVAL; + } else if ((dcc_readl(drvdata, DCC_HW_INFO) & DCC_VER_MASK2) == DCC_VER_MASK2) { + drvdata->mem_map_ver = DCC_MEM_MAP_VER2; + drvdata->nr_link_list = dcc_readl(drvdata, DCC_LL_NUM_INFO); + if (drvdata->nr_link_list == 0) + return -EINVAL; + } else { + drvdata->mem_map_ver = DCC_MEM_MAP_VER1; + drvdata->nr_link_list = DCC_MAX_LINK_LIST; + } + + if ((dcc_readl(drvdata, DCC_HW_INFO) & BIT(6)) == BIT(6)) + drvdata->loopoff = DCC_FIX_LOOP_OFFSET; + else + drvdata->loopoff = get_bitmask_order((drvdata->ram_size + + drvdata->ram_offset) / 4 - 1); + mutex_init(&drvdata->mutex); + + drvdata->enable = devm_kzalloc(dev, drvdata->nr_link_list * + sizeof(bool), GFP_KERNEL); + if (!drvdata->enable) + return -ENOMEM; + drvdata->configured = devm_kzalloc(dev, drvdata->nr_link_list * + sizeof(bool), GFP_KERNEL); + if (!drvdata->configured) + return -ENOMEM; + drvdata->nr_config = devm_kzalloc(dev, drvdata->nr_link_list * + sizeof(u32), GFP_KERNEL); + if (!drvdata->nr_config) + return -ENOMEM; + drvdata->cfg_head = devm_kzalloc(dev, drvdata->nr_link_list * + sizeof(struct list_head), GFP_KERNEL); + if (!drvdata->cfg_head) + return -ENOMEM; + + for (i = 0; i < drvdata->nr_link_list; i++) { + INIT_LIST_HEAD(&drvdata->cfg_head[i]); + drvdata->nr_config[i] = 0; + } + + memset_io(drvdata->ram_base, 0, drvdata->ram_size); + + drvdata->curr_list = DCC_INVALID_LINK_LIST; + + ret = dcc_sram_dev_init(drvdata); + if (ret) + goto err; + + return ret; +err: + return ret; +} + +static int dcc_remove(struct platform_device *pdev) +{ + struct dcc_drvdata *drvdata = platform_get_drvdata(pdev); + + dcc_sram_dev_exit(drvdata); + + dcc_config_reset(drvdata); + + return 0; +} + +static const struct qcom_dcc_config sm8150_cfg = { + .dcc_ram_offset = 0x5000, +}; + +static const struct of_device_id dcc_match_table[] = { + { .compatible = "qcom,sm8150-dcc", .data = &sm8150_cfg }, +}; + +static struct platform_driver dcc_driver = { + .probe = dcc_probe, + .remove = dcc_remove, + .driver = { + .name = "msm-dcc", + .of_match_table = dcc_match_table, + }, +}; + +module_platform_driver(dcc_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Qualcomm Technologies Inc. DCC driver"); + From patchwork Wed Mar 10 16:46:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Souradeep Chowdhury X-Patchwork-Id: 12128481 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6212CC4332E for ; Wed, 10 Mar 2021 16:48:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3A65B64FCA for ; Wed, 10 Mar 2021 16:48:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233300AbhCJQs0 (ORCPT ); Wed, 10 Mar 2021 11:48:26 -0500 Received: from m42-2.mailgun.net ([69.72.42.2]:42085 "EHLO m42-2.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233340AbhCJQsU (ORCPT ); Wed, 10 Mar 2021 11:48:20 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1615394899; h=References: In-Reply-To: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=7wMo81FgOLKNOqClQ2j9KiARVg8va9YtXI/yBCInQyI=; b=LLSPJesrLFKirIedxNjdRaeFcxVmR/eM23BjhCMaH6TlPuDZsgLxRzPDD/gBVGFnXiT4dcir 40QkvOHbvI7VkI58F1vQq1nmX1JGDr1VGoYc2TPPhK5VC1395Lu3frZduPG9F5DWWYTmbscr NH0Bf4Q3CtpZYLPPn1e7sPIZfE8= X-Mailgun-Sending-Ip: 69.72.42.2 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n06.prod.us-east-1.postgun.com with SMTP id 6048f843a6850484a6b49518 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Wed, 10 Mar 2021 16:48:03 GMT Sender: schowdhu=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 11A58C43467; Wed, 10 Mar 2021 16:48:03 +0000 (UTC) Received: from blr-ubuntu-525.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: schowdhu) by smtp.codeaurora.org (Postfix) with ESMTPSA id A7EFAC433ED; Wed, 10 Mar 2021 16:47:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org A7EFAC433ED Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=schowdhu@codeaurora.org From: Souradeep Chowdhury To: Rob Herring , Andy Gross , Bjorn Andersson Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, sibis@codeaurora.org, saiprakash.ranjan@codeaurora.org, Rajendra Nayak , vkoul@kernel.org, Souradeep Chowdhury Subject: [PATCH V1 3/6] soc: qcom: dcc: Add the sysfs variables to the Data Capture and Compare driver(DCC) Date: Wed, 10 Mar 2021 22:16:34 +0530 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the sysfs variables to expose the user space functionalities like DCC enable, disable, configure addresses and software triggers. Also add the necessary methods along with the same. Signed-off-by: Souradeep Chowdhury --- drivers/soc/qcom/dcc.c | 1179 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 1171 insertions(+), 8 deletions(-) diff --git a/drivers/soc/qcom/dcc.c b/drivers/soc/qcom/dcc.c index 89816bf..61e5225 100644 --- a/drivers/soc/qcom/dcc.c +++ b/drivers/soc/qcom/dcc.c @@ -17,12 +17,30 @@ #include #include + +#define TIMEOUT_US 100 + +#define dcc_writel(drvdata, val, off) \ + writel((val), drvdata->base + dcc_offset_conv(drvdata, off)) #define dcc_readl(drvdata, off) \ readl(drvdata->base + dcc_offset_conv(drvdata, off)) +#define dcc_sram_readl(drvdata, off) \ + readl(drvdata->ram_base + off) + /* DCC registers */ #define DCC_HW_INFO 0x04 #define DCC_LL_NUM_INFO 0x10 +#define DCC_STATUS 0x1C +#define DCC_LL_LOCK(m) (0x34 + 0x80 * m) +#define DCC_LL_CFG(m) (0x38 + 0x80 * m) +#define DCC_LL_BASE(m) (0x3c + 0x80 * m) +#define DCC_FD_BASE(m) (0x40 + 0x80 * m) +#define DCC_LL_TIMEOUT(m) (0x44 + 0x80 * m) +#define DCC_LL_INT_ENABLE(m) (0x4C + 0x80 * m) +#define DCC_LL_INT_STATUS(m) (0x50 + 0x80 * m) +#define DCC_LL_SW_TRIGGER(m) (0x60 + 0x80 * m) +#define DCC_LL_BUS_ACCESS_STATUS(m) (0x64 + 0x80 * m) #define DCC_MAP_LEVEL1 0x18 #define DCC_MAP_LEVEL2 0x34 @@ -36,24 +54,38 @@ #define DCC_FIX_LOOP_OFFSET 16 #define DCC_VER_INFO_BIT 9 +#define DCC_READ 0 +#define DCC_WRITE 1 +#define DCC_LOOP 2 +#define DCC_READ_WRITE 3 + +#define MAX_DCC_OFFSET GENMASK(9, 2) +#define MAX_DCC_LEN GENMASK(6, 0) +#define MAX_LOOP_CNT GENMASK(7, 0) + +#define DCC_ADDR_DESCRIPTOR 0x00 +#define DCC_LOOP_DESCRIPTOR BIT(30) +#define DCC_RD_MOD_WR_DESCRIPTOR BIT(31) +#define DCC_LINK_DESCRIPTOR GENMASK(31, 30) + +#define DCC_READ_IND 0x00 +#define DCC_WRITE_IND (BIT(28)) + +#define DCC_AHB_IND 0x00 +#define DCC_APB_IND BIT(29) + #define DCC_MAX_LINK_LIST 8 #define DCC_INVALID_LINK_LIST GENMASK(7, 0) #define DCC_VER_MASK1 GENMASK(6, 0) #define DCC_VER_MASK2 GENMASK(5, 0) -#define DCC_RD_MOD_WR_ADDR 0xC105E +#define DCC_RD_MOD_WR_ADDR 0xC105E struct qcom_dcc_config { const int dcc_ram_offset; }; -enum dcc_mem_map_ver { - DCC_MEM_MAP_VER1, - DCC_MEM_MAP_VER2, - DCC_MEM_MAP_VER3 -}; - enum dcc_descriptor_type { DCC_ADDR_TYPE, DCC_LOOP_TYPE, @@ -61,6 +93,12 @@ enum dcc_descriptor_type { DCC_WRITE_TYPE }; +enum dcc_mem_map_ver { + DCC_MEM_MAP_VER1, + DCC_MEM_MAP_VER2, + DCC_MEM_MAP_VER3 +}; + struct dcc_config_entry { u32 base; u32 offset; @@ -98,6 +136,22 @@ struct dcc_drvdata { u8 loopoff; }; +struct dcc_cfg_attr { + u32 addr; + u32 prev_addr; + u32 prev_off; + u32 link; + u32 sram_offset; +}; + +struct dcc_cfg_loop_attr { + u32 loop; + bool loop_start; + u32 loop_cnt; + u32 loop_len; + u32 loop_off; +}; + static u32 dcc_offset_conv(struct dcc_drvdata *drvdata, u32 off) { if (drvdata->mem_map_ver == DCC_MEM_MAP_VER1) { @@ -114,6 +168,832 @@ static u32 dcc_offset_conv(struct dcc_drvdata *drvdata, u32 off) return off; } +static int dcc_sram_writel(struct dcc_drvdata *drvdata, + u32 val, u32 off) +{ + if (unlikely(off > (drvdata->ram_size - 4))) + return -EINVAL; + + writel((val), drvdata->ram_base + off); + + return 0; +} + +static bool dcc_ready(struct dcc_drvdata *drvdata) +{ + u32 val; + + /* poll until DCC ready */ + if (!readl_poll_timeout((drvdata->base + DCC_STATUS), val, + (FIELD_GET(GENMASK(1, 0), val) == 0), 1, TIMEOUT_US)) + return true; + + return false; +} + +static int dcc_read_status(struct dcc_drvdata *drvdata) +{ + int curr_list; + u32 bus_status; + u32 ll_cfg = 0; + u32 tmp_ll_cfg = 0; + + for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) { + if (!drvdata->enable[curr_list]) + continue; + + bus_status = dcc_readl(drvdata, DCC_LL_BUS_ACCESS_STATUS(curr_list)); + + if (bus_status) { + dev_err(drvdata->dev, + "Read access error for list %d err: 0x%x.\n", + curr_list, bus_status); + + ll_cfg = dcc_readl(drvdata, DCC_LL_CFG(curr_list)); + tmp_ll_cfg = ll_cfg & ~BIT(9); + dcc_writel(drvdata, tmp_ll_cfg, DCC_LL_CFG(curr_list)); + dcc_writel(drvdata, 0x3, + DCC_LL_BUS_ACCESS_STATUS(curr_list)); + dcc_writel(drvdata, ll_cfg, DCC_LL_CFG(curr_list)); + return -ENODATA; + } + } + + return 0; +} + +static int dcc_sw_trigger(struct dcc_drvdata *drvdata) +{ + int ret = 0; + int curr_list; + u32 ll_cfg = 0; + u32 tmp_ll_cfg = 0; + + mutex_lock(&drvdata->mutex); + + for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) { + if (!drvdata->enable[curr_list]) + continue; + ll_cfg = dcc_readl(drvdata, DCC_LL_CFG(curr_list)); + tmp_ll_cfg = ll_cfg & ~BIT(9); + dcc_writel(drvdata, tmp_ll_cfg, DCC_LL_CFG(curr_list)); + dcc_writel(drvdata, 1, DCC_LL_SW_TRIGGER(curr_list)); + dcc_writel(drvdata, ll_cfg, DCC_LL_CFG(curr_list)); + } + + if (!dcc_ready(drvdata)) { + dev_err(drvdata->dev, + "DCC is busy after receiving sw tigger.\n"); + ret = -EBUSY; + goto err; + } + + ret = dcc_read_status(drvdata); + +err: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static void _dcc_ll_cfg_reset_link(struct dcc_cfg_attr *cfg) +{ + cfg->addr = 0; + cfg->link = 0; + cfg->prev_off = 0; + cfg->prev_addr = cfg->addr; +} + +static int _dcc_ll_cfg_read_write(struct dcc_drvdata *drvdata, + struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg) +{ + int ret; + + if (cfg->link) { + /* + * write new offset = 1 to continue + * processing the list + */ + + ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset); + if (ret) + return ret; + cfg->sram_offset += 4; + /* Reset link and prev_off */ + _dcc_ll_cfg_reset_link(cfg); + } + + cfg->addr = DCC_RD_MOD_WR_DESCRIPTOR; + ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset); + if (ret) + return ret; + + cfg->sram_offset += 4; + ret = dcc_sram_writel(drvdata, entry->mask, cfg->sram_offset); + if (ret) + return ret; + + cfg->sram_offset += 4; + ret = dcc_sram_writel(drvdata, entry->write_val, cfg->sram_offset); + if (ret) + return ret; + + cfg->sram_offset += 4; + cfg->addr = 0; + return ret; +} + +static int _dcc_ll_cfg_loop(struct dcc_drvdata *drvdata, struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg, + struct dcc_cfg_loop_attr *cfg_loop, + u32 *total_len) +{ + + int ret; + + /* Check if we need to write link of prev entry */ + if (cfg->link) { + ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset); + if (ret) + return ret; + cfg->sram_offset += 4; + } + + if (cfg_loop->loop_start) { + cfg_loop->loop = (cfg->sram_offset - cfg_loop->loop_off) / 4; + cfg_loop->loop |= (cfg_loop->loop_cnt << drvdata->loopoff) & + GENMASK(27, drvdata->loopoff); + cfg_loop->loop |= DCC_LOOP_DESCRIPTOR; + *total_len += (*total_len - cfg_loop->loop_len) * cfg_loop->loop_cnt; + + ret = dcc_sram_writel(drvdata, cfg_loop->loop, cfg->sram_offset); + + if (ret) + return ret; + cfg->sram_offset += 4; + + cfg_loop->loop_start = false; + cfg_loop->loop_len = 0; + cfg_loop->loop_off = 0; + } else { + cfg_loop->loop_start = true; + cfg_loop->loop_cnt = entry->loop_cnt - 1; + cfg_loop->loop_len = *total_len; + cfg_loop->loop_off = cfg->sram_offset; + } + + /* Reset link and prev_off */ + + _dcc_ll_cfg_reset_link(cfg); + + return ret; +} + +static int _dcc_ll_cfg_write(struct dcc_drvdata *drvdata, + struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg, + u32 *total_len) +{ + u32 off; + int ret; + + if (cfg->link) { + /* + * write new offset = 1 to continue + * processing the list + */ + ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset); + + if (ret) + return ret; + + cfg->sram_offset += 4; + /* Reset link and prev_off */ + cfg->addr = 0; + cfg->prev_off = 0; + cfg->prev_addr = cfg->addr; + } + + off = entry->offset/4; + /* write new offset-length pair to correct position */ + cfg->link |= ((off & GENMASK(7, 0)) | BIT(15) | ((entry->len << 8) & GENMASK(14, 8))); + cfg->link |= DCC_LINK_DESCRIPTOR; + + /* Address type */ + cfg->addr = (entry->base >> 4) & GENMASK(27, 0); + if (entry->apb_bus) + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_APB_IND; + else + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_WRITE_IND | DCC_AHB_IND; + ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset); + if (ret) + return ret; + + cfg->sram_offset += 4; + ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset); + if (ret) + return ret; + + cfg->sram_offset += 4; + ret = dcc_sram_writel(drvdata, entry->write_val, cfg->sram_offset); + if (ret) + return ret; + + cfg->sram_offset += 4; + cfg->addr = 0; + cfg->link = 0; + return ret; +} + +static int _dcc_ll_cfg_default(struct dcc_drvdata *drvdata, + struct dcc_config_entry *entry, + struct dcc_cfg_attr *cfg, + u32 *pos, u32 *total_len) +{ + int ret; + u32 off; + + cfg->addr = (entry->base >> 4) & GENMASK(27, 0); + + if (entry->apb_bus) + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_APB_IND; + else + cfg->addr |= DCC_ADDR_DESCRIPTOR | DCC_READ_IND | DCC_AHB_IND; + + off = entry->offset/4; + *total_len += entry->len * 4; + + if (!cfg->prev_addr || cfg->prev_addr != cfg->addr || cfg->prev_off > off) { + /* Check if we need to write prev link entry */ + if (cfg->link) { + ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset); + if (ret) + return ret; + cfg->sram_offset += 4; + } + dev_dbg(drvdata->dev, "DCC: sram address 0x%x\n", cfg->sram_offset); + + /* Write address */ + ret = dcc_sram_writel(drvdata, cfg->addr, cfg->sram_offset); + + if (ret) + return ret; + + cfg->sram_offset += 4; + + /* Reset link and prev_off */ + cfg->link = 0; + cfg->prev_off = 0; + } + + if ((off - cfg->prev_off) > 0xFF || entry->len > MAX_DCC_LEN) { + dev_err(drvdata->dev, "DCC: Programming error Base: 0x%x, offset 0x%x\n", + entry->base, entry->offset); + ret = -EINVAL; + return ret; + } + + if (cfg->link) { + /* + * link already has one offset-length so new + * offset-length needs to be placed at + * bits [29:15] + */ + *pos = 15; + + /* Clear bits [31:16] */ + cfg->link &= GENMASK(14, 0); + } else { + /* + * link is empty, so new offset-length needs + * to be placed at bits [15:0] + */ + *pos = 0; + cfg->link = 1 << 15; + } + + /* write new offset-length pair to correct position */ + cfg->link |= (((off-cfg->prev_off) & GENMASK(7, 0)) | + ((entry->len << 8) & GENMASK(14, 8))) << *pos; + cfg->link |= DCC_LINK_DESCRIPTOR; + + if (*pos) { + ret = dcc_sram_writel(drvdata, cfg->link, cfg->sram_offset); + if (ret) + return ret; + cfg->sram_offset += 4; + cfg->link = 0; + } + + cfg->prev_off = off + entry->len - 1; + cfg->prev_addr = cfg->addr; + return ret; +} + +static int __dcc_ll_cfg(struct dcc_drvdata *drvdata, int curr_list) +{ + int ret = 0; + u32 total_len, pos; + struct dcc_config_entry *entry; + struct dcc_cfg_attr cfg; + struct dcc_cfg_loop_attr cfg_loop; + + memset(&cfg, 0, sizeof(cfg)); + memset(&cfg_loop, 0, sizeof(cfg_loop)); + cfg.sram_offset = drvdata->ram_cfg * 4; + total_len = 0; + + list_for_each_entry(entry, &drvdata->cfg_head[curr_list], list) { + switch (entry->desc_type) { + case DCC_READ_WRITE_TYPE: + ret = _dcc_ll_cfg_read_write(drvdata, entry, &cfg); + if (ret) + goto overstep; + break; + + case DCC_LOOP_TYPE: + ret = _dcc_ll_cfg_loop(drvdata, entry, &cfg, &cfg_loop, &total_len); + if (ret) + goto overstep; + break; + + case DCC_WRITE_TYPE: + ret = _dcc_ll_cfg_write(drvdata, entry, &cfg, &total_len); + if (ret) + goto overstep; + break; + + default: + ret = _dcc_ll_cfg_default(drvdata, entry, &cfg, &pos, &total_len); + if (ret) + goto overstep; + break; + } + } + + if (cfg.link) { + ret = dcc_sram_writel(drvdata, cfg.link, cfg.sram_offset); + if (ret) + goto overstep; + cfg.sram_offset += 4; + } + + if (cfg_loop.loop_start) { + dev_err(drvdata->dev, "DCC: Programming error: Loop unterminated\n"); + ret = -EINVAL; + goto err; + } + + /* Handling special case of list ending with a rd_mod_wr */ + if (cfg.addr == DCC_RD_MOD_WR_DESCRIPTOR) { + cfg.addr = (DCC_RD_MOD_WR_ADDR) & GENMASK(27, 0); + cfg.addr |= DCC_ADDR_DESCRIPTOR; + ret = dcc_sram_writel(drvdata, cfg.addr, cfg.sram_offset); + if (ret) + goto overstep; + cfg.sram_offset += 4; + } + + /* Setting zero to indicate end of the list */ + cfg.link = DCC_LINK_DESCRIPTOR; + ret = dcc_sram_writel(drvdata, cfg.link, cfg.sram_offset); + if (ret) + goto overstep; + cfg.sram_offset += 4; + + /* Update ram_cfg and check if the data will overstep */ + drvdata->ram_cfg = (cfg.sram_offset + total_len) / 4; + if (cfg.sram_offset + total_len > drvdata->ram_size) { + cfg.sram_offset += total_len; + goto overstep; + } + + drvdata->ram_start = cfg.sram_offset/4; + return 0; +overstep: + ret = -EINVAL; + memset_io(drvdata->ram_base, 0, drvdata->ram_size); + dev_err(drvdata->dev, "DCC SRAM oversteps, 0x%x (0x%x)\n", + cfg.sram_offset, drvdata->ram_size); + +err: + return ret; +} + +static int dcc_valid_list(struct dcc_drvdata *drvdata, int curr_list) +{ + u32 lock_reg; + + if (list_empty(&drvdata->cfg_head[curr_list])) + return -EINVAL; + + if (drvdata->enable[curr_list]) { + dev_err(drvdata->dev, "List %d is already enabled\n", + curr_list); + return -EINVAL; + } + + lock_reg = dcc_readl(drvdata, DCC_LL_LOCK(curr_list)); + if (lock_reg & 0x1) { + dev_err(drvdata->dev, "List %d is already locked\n", + curr_list); + return -EINVAL; + } + + dev_err(drvdata->dev, "DCC list passed %d\n", curr_list); + return 0; +} + +static bool is_dcc_enabled(struct dcc_drvdata *drvdata) +{ + bool dcc_enable = false; + int list; + + for (list = 0; list < DCC_MAX_LINK_LIST; list++) { + if (drvdata->enable[list]) { + dcc_enable = true; + break; + } + } + + return dcc_enable; +} + +static int dcc_enable(struct dcc_drvdata *drvdata) +{ + int ret = 0; + int list; + u32 ram_cfg_base; + + mutex_lock(&drvdata->mutex); + + if (!is_dcc_enabled(drvdata)) { + memset_io(drvdata->ram_base, + 0xDE, drvdata->ram_size); + } + + for (list = 0; list < drvdata->nr_link_list; list++) { + + if (dcc_valid_list(drvdata, list)) + continue; + + /* 1. Take ownership of the list */ + dcc_writel(drvdata, BIT(0), DCC_LL_LOCK(list)); + + /* 2. Program linked-list in the SRAM */ + ram_cfg_base = drvdata->ram_cfg; + ret = __dcc_ll_cfg(drvdata, list); + if (ret) { + dcc_writel(drvdata, 0, DCC_LL_LOCK(list)); + dev_info(drvdata->dev, "DCC ram programming failed\n"); + goto err; + } + + /* 3. program DCC_RAM_CFG reg */ + dcc_writel(drvdata, ram_cfg_base + + drvdata->ram_offset/4, DCC_LL_BASE(list)); + dcc_writel(drvdata, drvdata->ram_start + + drvdata->ram_offset/4, DCC_FD_BASE(list)); + dcc_writel(drvdata, 0xFFF, DCC_LL_TIMEOUT(list)); + + /* 4. Clears interrupt status register */ + dcc_writel(drvdata, 0, DCC_LL_INT_ENABLE(list)); + dcc_writel(drvdata, (BIT(0) | BIT(1) | BIT(2)), + DCC_LL_INT_STATUS(list)); + + dev_info(drvdata->dev, "All values written to enable.\n"); + /* Make sure all config is written in sram */ + mb(); + + drvdata->enable[list] = true; + + /* 5. Configure trigger */ + dcc_writel(drvdata, BIT(9), DCC_LL_CFG(list)); + } + +err: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static void dcc_disable(struct dcc_drvdata *drvdata) +{ + int curr_list; + + mutex_lock(&drvdata->mutex); + + if (!dcc_ready(drvdata)) + dev_err(drvdata->dev, "DCC is not ready Disabling DCC...\n"); + + for (curr_list = 0; curr_list < drvdata->nr_link_list; curr_list++) { + if (!drvdata->enable[curr_list]) + continue; + dcc_writel(drvdata, 0, DCC_LL_CFG(curr_list)); + dcc_writel(drvdata, 0, DCC_LL_BASE(curr_list)); + dcc_writel(drvdata, 0, DCC_FD_BASE(curr_list)); + dcc_writel(drvdata, 0, DCC_LL_LOCK(curr_list)); + drvdata->enable[curr_list] = false; + } + memset_io(drvdata->ram_base, 0, drvdata->ram_size); + drvdata->ram_cfg = 0; + drvdata->ram_start = 0; + mutex_unlock(&drvdata->mutex); +} + +static ssize_t curr_list_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret; + struct dcc_drvdata *drvdata = dev_get_drvdata(dev); + + mutex_lock(&drvdata->mutex); + if (drvdata->curr_list == DCC_INVALID_LINK_LIST) { + dev_err(dev, "curr_list is not set.\n"); + ret = -EINVAL; + goto err; + } + + ret = scnprintf(buf, PAGE_SIZE, "%d\n", drvdata->curr_list); +err: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static ssize_t curr_list_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + struct dcc_drvdata *drvdata = dev_get_drvdata(dev); + unsigned long val; + u32 lock_reg; + bool dcc_enable = false; + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + if (val >= drvdata->nr_link_list) + return -EINVAL; + + mutex_lock(&drvdata->mutex); + + dcc_enable = is_dcc_enabled(drvdata); + if (drvdata->curr_list != DCC_INVALID_LINK_LIST && dcc_enable) { + dev_err(drvdata->dev, "DCC is enabled, please disable it first.\n"); + mutex_unlock(&drvdata->mutex); + return -EINVAL; + } + + lock_reg = dcc_readl(drvdata, DCC_LL_LOCK(val)); + if (lock_reg & 0x1) { + dev_err(drvdata->dev, "DCC linked list is already configured\n"); + mutex_unlock(&drvdata->mutex); + return -EINVAL; + } + drvdata->curr_list = val; + mutex_unlock(&drvdata->mutex); + + return size; +} + +static DEVICE_ATTR_RW(curr_list); + + +static ssize_t trigger_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int ret = 0; + unsigned long val; + struct dcc_drvdata *drvdata = dev_get_drvdata(dev); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + if (val != 1) + return -EINVAL; + + ret = dcc_sw_trigger(drvdata); + if (!ret) + ret = size; + + return ret; +} +static DEVICE_ATTR_WO(trigger); + +static ssize_t enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret; + bool dcc_enable = false; + struct dcc_drvdata *drvdata = dev_get_drvdata(dev); + + mutex_lock(&drvdata->mutex); + if (drvdata->curr_list >= drvdata->nr_link_list) { + dev_err(dev, "Select link list to program using curr_list\n"); + ret = -EINVAL; + goto err; + } + + dcc_enable = is_dcc_enabled(drvdata); + + ret = scnprintf(buf, PAGE_SIZE, "%u\n", + (unsigned int)dcc_enable); +err: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static ssize_t enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int ret = 0; + unsigned long val; + struct dcc_drvdata *drvdata = dev_get_drvdata(dev); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + if (val) + ret = dcc_enable(drvdata); + else + dcc_disable(drvdata); + + if (!ret) + ret = size; + + return ret; + +} + +static DEVICE_ATTR_RW(enable); + +static ssize_t config_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dcc_drvdata *drvdata = dev_get_drvdata(dev); + struct dcc_config_entry *entry; + char local_buf[64]; + int len = 0, count = 0; + + buf[0] = '\0'; + + mutex_lock(&drvdata->mutex); + if (drvdata->curr_list >= drvdata->nr_link_list) { + dev_err(dev, "Select link list to program using curr_list\n"); + count = -EINVAL; + goto err; + } + + list_for_each_entry(entry, + &drvdata->cfg_head[drvdata->curr_list], list) { + switch (entry->desc_type) { + case DCC_READ_WRITE_TYPE: + len = snprintf(local_buf, 64, "Index: 0x%x, mask: 0x%x, val: 0x%x\n", + entry->index, entry->mask, entry->write_val); + break; + case DCC_LOOP_TYPE: + len = snprintf(local_buf, 64, "Index: 0x%x, Loop: %d\n", + entry->index, entry->loop_cnt); + break; + case DCC_WRITE_TYPE: + len = snprintf(local_buf, 64, + "Write Index: 0x%x, Base: 0x%x, Offset: 0x%x, len: 0x%x APB: %d\n", + entry->index, entry->base, entry->offset, entry->len, + entry->apb_bus); + break; + default: + len = snprintf(local_buf, 64, + "Read Index: 0x%x, Base: 0x%x, Offset: 0x%x, len: 0x%x APB: %d\n", + entry->index, entry->base, entry->offset, + entry->len, entry->apb_bus); + } + + if ((count + len) > PAGE_SIZE) { + dev_err(dev, "DCC: Couldn't write complete config\n"); + break; + } + strlcat(buf, local_buf, PAGE_SIZE); + count += len; + } + +err: + mutex_unlock(&drvdata->mutex); + return count; +} + +static int dcc_config_add(struct dcc_drvdata *drvdata, unsigned int addr, + unsigned int len, int apb_bus) +{ + int ret; + struct dcc_config_entry *entry, *pentry; + unsigned int base, offset; + + mutex_lock(&drvdata->mutex); + + if (drvdata->curr_list >= drvdata->nr_link_list) { + dev_err(drvdata->dev, "Select link list to program using curr_list\n"); + ret = -EINVAL; + goto err; + } + + if (!len || len > (drvdata->ram_size / 8)) { + dev_err(drvdata->dev, "DCC: Invalid length\n"); + ret = -EINVAL; + goto err; + } + + base = addr & GENMASK(31, 4); + + if (!list_empty(&drvdata->cfg_head[drvdata->curr_list])) { + pentry = list_last_entry(&drvdata->cfg_head[drvdata->curr_list], + struct dcc_config_entry, list); + + if (pentry->desc_type == DCC_ADDR_TYPE && + addr >= (pentry->base + pentry->offset) && + addr <= (pentry->base + + pentry->offset + MAX_DCC_OFFSET)) { + + /* Re-use base address from last entry */ + base = pentry->base; + + if ((pentry->len * 4 + pentry->base + pentry->offset) + == addr) { + len += pentry->len; + + if (len > MAX_DCC_LEN) + pentry->len = MAX_DCC_LEN; + else + pentry->len = len; + + addr = pentry->base + pentry->offset + + pentry->len * 4; + len -= pentry->len; + } + } + } + + offset = addr - base; + + while (len) { + entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL); + if (!entry) { + ret = -ENOMEM; + goto err; + } + + entry->base = base; + entry->offset = offset; + entry->len = min_t(u32, len, MAX_DCC_LEN); + entry->index = drvdata->nr_config[drvdata->curr_list]++; + entry->desc_type = DCC_ADDR_TYPE; + entry->apb_bus = apb_bus; + INIT_LIST_HEAD(&entry->list); + list_add_tail(&entry->list, + &drvdata->cfg_head[drvdata->curr_list]); + + len -= entry->len; + offset += MAX_DCC_LEN * 4; + } + + mutex_unlock(&drvdata->mutex); + return 0; +err: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static ssize_t config_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int ret, len, apb_bus; + unsigned int base; + struct dcc_drvdata *drvdata = dev_get_drvdata(dev); + int nval; + + nval = sscanf(buf, "%x %i %d", &base, &len, &apb_bus); + if (nval <= 0 || nval > 3) + return -EINVAL; + + if (nval == 1) { + len = 1; + apb_bus = 0; + } else if (nval == 2) { + apb_bus = 0; + } else { + apb_bus = 1; + } + + ret = dcc_config_add(drvdata, base, len, apb_bus); + if (ret) + return ret; + + return size; + +} + +static DEVICE_ATTR_RW(config); + static void dcc_config_reset(struct dcc_drvdata *drvdata) { struct dcc_config_entry *entry, *temp; @@ -135,6 +1015,286 @@ static void dcc_config_reset(struct dcc_drvdata *drvdata) mutex_unlock(&drvdata->mutex); } + +static ssize_t config_reset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct dcc_drvdata *drvdata = dev_get_drvdata(dev); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + if (val) + dcc_config_reset(drvdata); + + return size; +} + +static DEVICE_ATTR_WO(config_reset); + +static ssize_t ready_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret; + struct dcc_drvdata *drvdata = dev_get_drvdata(dev); + + mutex_lock(&drvdata->mutex); + + if (drvdata->curr_list >= drvdata->nr_link_list) { + dev_err(dev, "Select link list to program using curr_list\n"); + ret = -EINVAL; + goto err; + } + + if (!drvdata->enable[drvdata->curr_list]) { + ret = -EINVAL; + goto err; + } + + ret = scnprintf(buf, PAGE_SIZE, "%u\n", + (unsigned int)FIELD_GET(BIT(1), dcc_readl(drvdata, DCC_STATUS))); +err: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static DEVICE_ATTR_RO(ready); + +static ssize_t interrupt_disable_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct dcc_drvdata *drvdata = dev_get_drvdata(dev); + + return scnprintf(buf, PAGE_SIZE, "%u\n", + (unsigned int)drvdata->interrupt_disable); +} + +static ssize_t interrupt_disable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + unsigned long val; + struct dcc_drvdata *drvdata = dev_get_drvdata(dev); + + if (kstrtoul(buf, 16, &val)) + return -EINVAL; + + mutex_lock(&drvdata->mutex); + drvdata->interrupt_disable = (val ? 1:0); + mutex_unlock(&drvdata->mutex); + return size; +} + +static DEVICE_ATTR_RW(interrupt_disable); + +static int dcc_add_loop(struct dcc_drvdata *drvdata, unsigned long loop_cnt) +{ + struct dcc_config_entry *entry; + + entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL); + if (!entry) + return -ENOMEM; + + entry->loop_cnt = min_t(u32, loop_cnt, MAX_LOOP_CNT); + entry->index = drvdata->nr_config[drvdata->curr_list]++; + entry->desc_type = DCC_LOOP_TYPE; + INIT_LIST_HEAD(&entry->list); + list_add_tail(&entry->list, &drvdata->cfg_head[drvdata->curr_list]); + + return 0; +} + +static ssize_t loop_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int ret; + unsigned long loop_cnt; + struct dcc_drvdata *drvdata = dev_get_drvdata(dev); + + mutex_lock(&drvdata->mutex); + + if (kstrtoul(buf, 16, &loop_cnt)) { + ret = -EINVAL; + goto err; + } + + if (drvdata->curr_list >= drvdata->nr_link_list) { + dev_err(dev, "Select link list to program using curr_list\n"); + ret = -EINVAL; + goto err; + } + + ret = dcc_add_loop(drvdata, loop_cnt); + if (ret) + goto err; + + mutex_unlock(&drvdata->mutex); + return size; +err: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static DEVICE_ATTR_WO(loop); + +static int dcc_rd_mod_wr_add(struct dcc_drvdata *drvdata, unsigned int mask, + unsigned int val) +{ + int ret = 0; + struct dcc_config_entry *entry; + + mutex_lock(&drvdata->mutex); + + if (drvdata->curr_list >= drvdata->nr_link_list) { + dev_err(drvdata->dev, "Select link list to program using curr_list\n"); + ret = -EINVAL; + goto err; + } + + if (list_empty(&drvdata->cfg_head[drvdata->curr_list])) { + dev_err(drvdata->dev, "DCC: No read address programmed\n"); + ret = -EPERM; + goto err; + } + + entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL); + if (!entry) { + ret = -ENOMEM; + goto err; + } + + entry->desc_type = DCC_READ_WRITE_TYPE; + entry->mask = mask; + entry->write_val = val; + entry->index = drvdata->nr_config[drvdata->curr_list]++; + INIT_LIST_HEAD(&entry->list); + list_add_tail(&entry->list, &drvdata->cfg_head[drvdata->curr_list]); +err: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static ssize_t rd_mod_wr_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int ret; + int nval; + unsigned int mask, val; + struct dcc_drvdata *drvdata = dev_get_drvdata(dev); + + nval = sscanf(buf, "%x %x", &mask, &val); + + if (nval <= 1 || nval > 2) + return -EINVAL; + + ret = dcc_rd_mod_wr_add(drvdata, mask, val); + if (ret) + return ret; + + return size; + +} + +static DEVICE_ATTR_WO(rd_mod_wr); + +static int dcc_add_write(struct dcc_drvdata *drvdata, unsigned int addr, + unsigned int write_val, int apb_bus) +{ + struct dcc_config_entry *entry; + + entry = devm_kzalloc(drvdata->dev, sizeof(*entry), GFP_KERNEL); + if (!entry) + return -ENOMEM; + + entry->desc_type = DCC_WRITE_TYPE; + entry->base = addr & GENMASK(31, 4); + entry->offset = addr - entry->base; + entry->write_val = write_val; + entry->index = drvdata->nr_config[drvdata->curr_list]++; + entry->len = 1; + entry->apb_bus = apb_bus; + INIT_LIST_HEAD(&entry->list); + list_add_tail(&entry->list, &drvdata->cfg_head[drvdata->curr_list]); + + return 0; +} + +static ssize_t config_write_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int ret; + int nval; + unsigned int addr, write_val; + int apb_bus = 0; + struct dcc_drvdata *drvdata = dev_get_drvdata(dev); + + mutex_lock(&drvdata->mutex); + + nval = sscanf(buf, "%x %x %d", &addr, &write_val, &apb_bus); + + if (nval <= 1 || nval > 3) { + ret = -EINVAL; + goto err; + } + + if (drvdata->curr_list >= drvdata->nr_link_list) { + dev_err(dev, "Select link list to program using curr_list\n"); + ret = -EINVAL; + goto err; + } + + if (nval == 3 && apb_bus != 0) + apb_bus = 1; + + ret = dcc_add_write(drvdata, addr, write_val, apb_bus); + if (ret) + goto err; + + mutex_unlock(&drvdata->mutex); + return size; +err: + mutex_unlock(&drvdata->mutex); + return ret; +} + +static DEVICE_ATTR_WO(config_write); + +static const struct device_attribute *dcc_attrs[] = { + &dev_attr_trigger, + &dev_attr_enable, + &dev_attr_config, + &dev_attr_config_reset, + &dev_attr_ready, + &dev_attr_interrupt_disable, + &dev_attr_loop, + &dev_attr_rd_mod_wr, + &dev_attr_curr_list, + &dev_attr_config_write, + NULL, +}; + +static int dcc_create_files(struct device *dev, + const struct device_attribute **attrs) +{ + int ret = 0, i; + + for (i = 0; attrs[i] != NULL; i++) { + ret = device_create_file(dev, attrs[i]); + if (ret) { + dev_err(dev, "DCC: Couldn't create sysfs attribute: %s\n", + attrs[i]->attr.name); + break; + } + } + return ret; +} + static int dcc_sram_open(struct inode *inode, struct file *file) { struct dcc_drvdata *drvdata = container_of(inode->i_cdev, @@ -347,6 +1507,9 @@ static int dcc_probe(struct platform_device *pdev) ret = dcc_sram_dev_init(drvdata); if (ret) goto err; + ret = dcc_create_files(dev, dcc_attrs); + if (ret) + goto err; return ret; err: @@ -365,7 +1528,7 @@ static int dcc_remove(struct platform_device *pdev) } static const struct qcom_dcc_config sm8150_cfg = { - .dcc_ram_offset = 0x5000, + .dcc_ram_offset = 0x5000, }; static const struct of_device_id dcc_match_table[] = { From patchwork Wed Mar 10 16:46:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Souradeep Chowdhury X-Patchwork-Id: 12128479 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D963C43332 for ; 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Wed, 10 Mar 2021 16:48:06 GMT Sender: schowdhu=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 3D89EC43463; Wed, 10 Mar 2021 16:48:06 +0000 (UTC) Received: from blr-ubuntu-525.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: schowdhu) by smtp.codeaurora.org (Postfix) with ESMTPSA id 9B0BBC43463; Wed, 10 Mar 2021 16:48:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 9B0BBC43463 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=schowdhu@codeaurora.org From: Souradeep Chowdhury To: Rob Herring , Andy Gross , Bjorn Andersson Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, sibis@codeaurora.org, saiprakash.ranjan@codeaurora.org, Rajendra Nayak , vkoul@kernel.org, Souradeep Chowdhury Subject: [PATCH V1 4/6] DCC: Added the sysfs entries for DCC(Data Capture and Compare) driver Date: Wed, 10 Mar 2021 22:16:35 +0530 Message-Id: <332477ea39088fca5879af1a5278c289e1602f6d.1615393454.git.schowdhu@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The DCC is a DMA engine designed to store register values either in case of a system crash or in case of software triggers manually done by the user. Using DCC hardware and the sysfs interface of the driver the user can exploit various functionalities of DCC. The user can specify the register addresses, the values of which is stored by DCC in it's dedicated SRAM. The register addresses can be used either to read from, write to, first read and store value and then write or to loop. All these options can be exploited using the sysfs interface given to the user. Following are the sysfs interfaces exposed in DCC driver which are documented 1)trigger 2)config 3)config_write 4)config_reset 5)enable 6)rd_mod_wr 7)loop Signed-off-by: Souradeep Chowdhury --- Documentation/ABI/testing/sysfs-driver-dcc | 74 ++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-driver-dcc diff --git a/Documentation/ABI/testing/sysfs-driver-dcc b/Documentation/ABI/testing/sysfs-driver-dcc new file mode 100644 index 0000000..7a855ca --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-dcc @@ -0,0 +1,74 @@ +What: /sys/bus/platform/devices/.../trigger +Date: February 2021 +Contact: Souradeep Chowdhury +Description: + This file allows the software trigger to be enabled + by the user through the sysfs interface.Through this + interface the user can manually start a software trigger + in dcc where by the dcc driver stores the current status + of the specified registers in dcc sram. + +What: /sys/bus/platform/devices/.../enable +Date: February 2021 +Contact: Souradeep Chowdhury +Description: + This file allows the user to manually enable or + disable dcc driver.The dcc hardware needs to be + enabled before use. + +What: /sys/bus/platform/devices/.../config +Date: February 2021 +Contact: Souradeep Chowdhury +Description: + This file allows user to configure the register values + along with addresses to the dcc driver.This register + addresses are used to read from,write or loop through. + To enable all these options separate sysfs files have + are created. + +What: /sys/bus/platform/devices/.../config_write +Date: February 2021 +Contact: Souradeep Chowdhury +Description: + This file allows user to write a value to the register + address given as argument.The values are entered in the + form of . + +What: /sys/bus/platform/devices/.../config_reset +Date: February 2021 +Contact: Souradeep Chowdhury +Description: + This file is used to reset the configuration of + a dcc driver to the default configuration. + +What: /sys/bus/platform/devices/.../loop +Date: February 2021 +Contact: Souradeep Chowdhury +Description: + This file is used to enter the loop count as dcc + driver gives the option to loop multiple times on + the same register and store the values for each + loop. + +What: /sys/bus/platform/devices/.../rd_mod_wr +Date: February 2021 +Contact: Souradeep Chowdhury +Description: + This file is used to read the value of the register + and then write the value given as an argument to the + register address in config.The address argument should + be given of the form . + +What: /sys/bus/platform/devices/.../ready +Date: February 2021 +Contact: Souradeep Chowdhury +Description: + This file is used to check the status of the dcc + hardware if it's ready to take the inputs. + +What: /sys/bus/platform/devices/.../curr_list +Date: February 2021 +Contact: Souradeep Chowdhury +Description: + This file is used to configure the linkedlist data + to be used while configuring addresses. From patchwork Wed Mar 10 16:46:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Souradeep Chowdhury X-Patchwork-Id: 12128483 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0BB2C43333 for ; Wed, 10 Mar 2021 16:48:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 864B064FCC for ; Wed, 10 Mar 2021 16:48:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233322AbhCJQs1 (ORCPT ); Wed, 10 Mar 2021 11:48:27 -0500 Received: from m42-2.mailgun.net ([69.72.42.2]:30735 "EHLO m42-2.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231941AbhCJQsY (ORCPT ); Wed, 10 Mar 2021 11:48:24 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1615394904; h=References: In-Reply-To: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=hEE3w8HTASHETEiuf9bTDObpKPT8w+L8zVEz6r58fms=; b=S6HlvvkQYkgfx8xnnsNfCfyYJS4RBuHcEk2gacBMG3f12bCXm0NE8h9MTj5tQBJ9IE2/rTSL 6SRpbrixjVoumBTSS8v8Rg7V881FLSndgVTEzhPmeGZVR8h89LYqJEn6kz310q2Nvrx0sK6K cjT4snJ4o+CMby3/DC5WmKS00VM= X-Mailgun-Sending-Ip: 69.72.42.2 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n02.prod.us-east-1.postgun.com with SMTP id 6048f84dd3a53bc38f37e989 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Wed, 10 Mar 2021 16:48:13 GMT Sender: schowdhu=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id C4DC4C43468; Wed, 10 Mar 2021 16:48:12 +0000 (UTC) Received: from blr-ubuntu-525.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: schowdhu) by smtp.codeaurora.org (Postfix) with ESMTPSA id BC81DC43466; Wed, 10 Mar 2021 16:48:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org BC81DC43466 Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=schowdhu@codeaurora.org From: Souradeep Chowdhury To: Rob Herring , Andy Gross , Bjorn Andersson Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, sibis@codeaurora.org, saiprakash.ranjan@codeaurora.org, Rajendra Nayak , vkoul@kernel.org, Souradeep Chowdhury Subject: [PATCH V1 5/6] MAINTAINERS: Add the entry for DCC(Data Capture and Compare) driver support Date: Wed, 10 Mar 2021 22:16:36 +0530 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Added the entries for all the files added as a part of driver support for DCC(Data Capture and Compare). Signed-off-by: Souradeep Chowdhury --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d92f85c..fb28218 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4969,6 +4969,14 @@ F: include/linux/tfrc.h F: include/uapi/linux/dccp.h F: net/dccp/ +QTI DCC DRIVER +M: Souradeep Chowdhury +L: linux-arm-msm@vger.kernel.org +S: Maintained +F: Documentation/ABI/testing/sysfs-driver-dcc +F: Documentation/devicetree/bindings/arm/msm/qcom,dcc.yaml +F: drivers/soc/qcom/dcc.c + DECnet NETWORK LAYER L: linux-decnet-user@lists.sourceforge.net S: Orphan From patchwork Wed Mar 10 16:46:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Souradeep Chowdhury X-Patchwork-Id: 12128485 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93283C433E0 for ; Wed, 10 Mar 2021 16:49:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6CDF664FCC for ; Wed, 10 Mar 2021 16:49:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232330AbhCJQs5 (ORCPT ); Wed, 10 Mar 2021 11:48:57 -0500 Received: from z11.mailgun.us ([104.130.96.11]:40899 "EHLO z11.mailgun.us" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231828AbhCJQso (ORCPT ); Wed, 10 Mar 2021 11:48:44 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1615394924; h=References: In-Reply-To: References: In-Reply-To: Message-Id: Date: Subject: Cc: To: From: Sender; bh=ccY+ZYJiL1Jn6kZNz3yh4uEzqvLAYwq+T9O1hnn3N6k=; b=gVc9rW+NowMzBR9tchUn+tacCYDEs7PQuX0NdLNPlU3407P9DTJzqlc/sCrw6HrH64eB2iXJ V2405DgErKPSeXmiU1vE3+Kf9PWMVVlMK/W4wjbiPN/Szw8JPXPEMRvxFSY9wSGlxm+Li+NL 3N2raTNDwUj19eKhI6HpUF+vW2k= X-Mailgun-Sending-Ip: 104.130.96.11 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n01.prod.us-east-1.postgun.com with SMTP id 6048f859b86af9bf235a8831 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Wed, 10 Mar 2021 16:48:25 GMT Sender: schowdhu=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 1BEA1C43461; Wed, 10 Mar 2021 16:48:25 +0000 (UTC) Received: from blr-ubuntu-525.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: schowdhu) by smtp.codeaurora.org (Postfix) with ESMTPSA id 77C62C433CA; Wed, 10 Mar 2021 16:48:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 77C62C433CA Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=fail smtp.mailfrom=schowdhu@codeaurora.org From: Souradeep Chowdhury To: Rob Herring , Andy Gross , Bjorn Andersson Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, sibis@codeaurora.org, saiprakash.ranjan@codeaurora.org, Rajendra Nayak , vkoul@kernel.org, Souradeep Chowdhury Subject: [PATCH V1 6/6] arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support node Date: Wed, 10 Mar 2021 22:16:37 +0530 Message-Id: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: In-Reply-To: References: Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the DCC(Data Capture and Compare) device tree node entry along with the addresses for register regions. Signed-off-by: Souradeep Chowdhury --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index e5bb17b..5c564b1 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -654,6 +654,13 @@ interrupts = ; }; + dcc@10a2000 { + compatible = "qcom,sm8150-dcc", "qcom,dcc"; + reg = <0x0 0x010a2000 0x0 0x1000>, + <0x0 0x010ad000 0x0 0x3000>; + reg-names = "dcc-base", "dcc-ram-base"; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0";