From patchwork Fri Mar 12 12:07:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gwan-gyeong Mun X-Patchwork-Id: 12134431 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0323C433E0 for ; Fri, 12 Mar 2021 12:07:37 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A84C664FD6 for ; Fri, 12 Mar 2021 12:07:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A84C664FD6 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 574BE6F5D7; Fri, 12 Mar 2021 12:07:37 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id EFABC6F5D7 for ; Fri, 12 Mar 2021 12:07:35 +0000 (UTC) IronPort-SDR: opODCwEInOh4zYDjgl5/x81aOKg8U3pzLazazgM8+AoRQHKbY8lzsq5zvfJiTL0XfRbz+CR1W1 3C7dRTCK2Smg== X-IronPort-AV: E=McAfee;i="6000,8403,9920"; a="208662670" X-IronPort-AV: E=Sophos;i="5.81,243,1610438400"; d="scan'208";a="208662670" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2021 04:07:34 -0800 IronPort-SDR: 0wMc8DZGpLwKrtCwImUS1q6EUEPAiJutEszgGJHe8lnzFPv6tJxKA3mV5Z+Ay8cYarHl3MyHBb 6l+ZxmFE2Lnw== X-IronPort-AV: E=Sophos;i="5.81,243,1610438400"; d="scan'208";a="510313040" Received: from joemurpx-mobl.ger.corp.intel.com (HELO helsinki.intel.com) ([10.213.209.246]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2021 04:07:33 -0800 From: Gwan-gyeong Mun To: intel-gfx@lists.freedesktop.org Date: Fri, 12 Mar 2021 14:07:22 +0200 Message-Id: <20210312120722.1450481-1-gwan-gyeong.mun@intel.com> X-Mailer: git-send-email 2.30.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915/psr: Configure and Program IO buffer Wake and Fast Wake X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" As per b.spec 49274, the IO buffer Wake lines and Fast Wake lines can be calculated based on the following formula. IO buffer wake lines = ROUNDUP(PSR2 IO wake time / total line time in microseconds) Fast wake lines = ROUNDUP(PSR2 aux transaction time / total line time in microseconds) For both fields limit the minimum to 7 lines and maximum to 12 lines PSR2 IO wake time = 50us, PSR2 aux transaction time = 32us. It calculates IO buffer Wake and Fast Wake based on b.spec 49274 and programs it. v2: Address Jose's review comment. - Do not overwrite the values. - Move calulating and validating of io_buffer_wake/fast_wake to intel_psr2_config_valid() from intel_psr_compute_config() - Add macros for hardcoded values. - Simplify and reuse the validating the io_buffer_wake/fast_wake. Cc: José Roberto de Souza Cc: Lee Shawn C Signed-off-by: Gwan-gyeong Mun --- .../drm/i915/display/intel_display_types.h | 2 + drivers/gpu/drm/i915/display/intel_psr.c | 65 +++++++++++++++---- drivers/gpu/drm/i915/i915_reg.h | 8 +++ 3 files changed, 63 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index f159dce0f744..0241f7eb0a1d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1469,6 +1469,8 @@ struct intel_psr { u16 su_x_granularity; bool dc3co_enabled; u32 dc3co_exit_delay; + u32 io_buffer_wake; + u32 fast_wake; struct delayed_work dc3co_work; struct drm_dp_vsc_sdp vsc; }; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index cd434285e3b7..faac023d05b2 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -531,19 +531,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) val |= intel_psr2_get_tp_time(intel_dp); if (INTEL_GEN(dev_priv) >= 12) { - /* - * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default - * values from BSpec. In order to setting an optimal power - * consumption, lower than 4k resoluition mode needs to decrese - * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution - * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE. - */ - val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; - val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7); - val |= TGL_EDP_PSR2_FAST_WAKE(7); + if (intel_dp->psr.io_buffer_wake < 9 || intel_dp->psr.fast_wake < 9) + val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; + else + val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3; + val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_buffer_wake); + val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake); } else if (INTEL_GEN(dev_priv) >= 9) { - val |= EDP_PSR2_IO_BUFFER_WAKE(7); - val |= EDP_PSR2_FAST_WAKE(7); + val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_buffer_wake); + val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake); } if (intel_dp->psr.psr2_sel_fetch_enabled) { @@ -722,6 +718,8 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; int psr_max_h = 0, psr_max_v = 0, max_bpp = 0; + u32 io_buffer_wake, io_buffer_wake_max, io_buffer_wake_min; + u32 fast_wake, fast_wake_max, fast_wake_min; if (!intel_dp->psr.sink_psr2_support) return false; @@ -765,14 +763,26 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, psr_max_h = 5120; psr_max_v = 3200; max_bpp = 30; + io_buffer_wake_max = TGL_EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES; + io_buffer_wake_min = TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES; + fast_wake_max = TGL_EDP_PSR2_FAST_WAKE_MAX_LINES; + fast_wake_min = TGL_EDP_PSR2_FAST_WAKE_MIN_LINES; } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { psr_max_h = 4096; psr_max_v = 2304; max_bpp = 24; + io_buffer_wake_max = EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES; + io_buffer_wake_min = EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES; + fast_wake_max = EDP_PSR2_FAST_WAKE_MAX_LINES; + fast_wake_min = EDP_PSR2_FAST_WAKE_MIN_LINES; } else if (IS_GEN(dev_priv, 9)) { psr_max_h = 3640; psr_max_v = 2304; max_bpp = 24; + io_buffer_wake_max = EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES; + io_buffer_wake_min = EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES; + fast_wake_max = EDP_PSR2_FAST_WAKE_MAX_LINES; + fast_wake_min = EDP_PSR2_FAST_WAKE_MIN_LINES; } if (crtc_state->pipe_bpp > max_bpp) { @@ -782,6 +792,37 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } + /* + * B.Spec 49274 + * IO buffer wake lines = ROUNDUP(PSR2 IO wake time / total line time in microseconds) + * Fast wake lines = ROUNDUP(PSR2 aux transaction time / total line time in microseconds) + * For both fields limit the minimum to 7 lines and maximum to 12 lines + * PSR2 IO wake time = 50us, PSR2 aux transaction time = 32us. + */ + io_buffer_wake = intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, + EDP_PSR2_IO_WAKE_TIME); + fast_wake = intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, + EDP_PSR2_AUX_TRANSACTION_TIME); + + if (io_buffer_wake < io_buffer_wake_min || io_buffer_wake > io_buffer_wake_max) { + drm_dbg_kms(&dev_priv->drm, + "PSR condition failed: Invalid PSR2 IO Buffer Wake lines (%d)\n", + io_buffer_wake); + return false; + } + + if (fast_wake < fast_wake_min || fast_wake > fast_wake_max) { + drm_dbg_kms(&dev_priv->drm, + "PSR condition failed: Invalid PSR2 FAST Wake lines (%d)\n", + fast_wake); + return false; + } + + intel_dp->psr.io_buffer_wake = + io_buffer_wake < EDP_PSR2_IO_BUFFER_WAKE_DEFAULT ? EDP_PSR2_IO_BUFFER_WAKE_DEFAULT : io_buffer_wake; + intel_dp->psr.fast_wake = + fast_wake < EDP_PSR2_FAST_WAKE_DEFAULT ? EDP_PSR2_FAST_WAKE_DEFAULT : fast_wake; + /* * HW sends SU blocks of size four scan lines, which means the starting * X coordinate and Y granularity requirements will always be met. We diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e5dd0203991b..4ae4cdbb9754 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4557,14 +4557,22 @@ enum { #define EDP_MAX_SU_DISABLE_TIME(t) ((t) << 20) #define EDP_MAX_SU_DISABLE_TIME_MASK (0x1f << 20) #define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8 +#define EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 +#define EDP_PSR2_IO_BUFFER_WAKE_DEFAULT 7 #define EDP_PSR2_IO_BUFFER_WAKE(lines) ((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13) #define EDP_PSR2_IO_BUFFER_WAKE_MASK (3 << 13) +#define EDP_PSR2_IO_WAKE_TIME 50 +#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 12 #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) (((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13) #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK (7 << 13) #define EDP_PSR2_FAST_WAKE_MAX_LINES 8 +#define EDP_PSR2_FAST_WAKE_MIN_LINES 5 +#define EDP_PSR2_FAST_WAKE_DEFAULT 7 #define EDP_PSR2_FAST_WAKE(lines) ((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11) #define EDP_PSR2_FAST_WAKE_MASK (3 << 11) +#define EDP_PSR2_AUX_TRANSACTION_TIME 32 +#define TGL_EDP_PSR2_FAST_WAKE_MAX_LINES 12 #define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5 #define TGL_EDP_PSR2_FAST_WAKE(lines) (((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10) #define TGL_EDP_PSR2_FAST_WAKE_MASK (7 << 10)