From patchwork Mon Nov 19 17:30:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergei Shtylyov X-Patchwork-Id: 10689155 X-Patchwork-Delegate: geert@linux-m68k.org Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0815C13B5 for ; Mon, 19 Nov 2018 17:30:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DF7132A002 for ; Mon, 19 Nov 2018 17:30:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D3BA52A0B6; Mon, 19 Nov 2018 17:30:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3695F2A002 for ; Mon, 19 Nov 2018 17:30:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404327AbeKTDyh (ORCPT ); Mon, 19 Nov 2018 22:54:37 -0500 Received: from mail-lf1-f67.google.com ([209.85.167.67]:38232 "EHLO mail-lf1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390868AbeKTDyf (ORCPT ); Mon, 19 Nov 2018 22:54:35 -0500 Received: by mail-lf1-f67.google.com with SMTP id p86so21931945lfg.5 for ; Mon, 19 Nov 2018 09:30:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cogentembedded-com.20150623.gappssmtp.com; s=20150623; h=from:subject:to:cc:references:organization:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=bS4lW/dKHup1oDaCjCFJxFBd11q65ZeGWV+PCMYS92k=; b=vfXmv49NOFchXp99osqOQlYgHnw93pkOR54OVIR2ItmsCSWd213hI0BSr+GB3MvkQ6 iXQXjuGXM/eQ8LJWPP/E5PYXQ2ekVtsBkWnBPm/EgulaU0eNoCUUiXquLjQuEBEPfwBT YPJ5nf95Pr/nKJEb3P5+PqmZSlarx7SHua3/Gnwt4wlhGrFNJiwgZyaxlYXnMqxiV37k 4gjo9C0ueBv03d2AZ0wz2iCd6v/+vRX7fTLUsfH8/dNv2j3UeYvc6pww/6B3ZdxN7P9v T7xAlwjHmiO/mRKligMmsSMn4tBD/yGX1d40V4Cq8YrUY2pWrVNrGctFY6ao9WV1LWew LUww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:subject:to:cc:references:organization :message-id:date:user-agent:mime-version:in-reply-to :content-language:content-transfer-encoding; bh=bS4lW/dKHup1oDaCjCFJxFBd11q65ZeGWV+PCMYS92k=; b=lQn2GjwtDgVi6UFEHuzJl0Jr1riI9+VxTfpYx5iGkHM5BdBy8TgWmR/UjdQkxOaf2O z0Giypbr4Sv77nqhWytGo7KNpKWBequ43L+TU/7XK30V8qd+2wQ+68uBRTqaQNb2RFyg QtM+gU1bfK7RkskMk2CFc9LTEkOhTbqyvGYTBjWpYJ87JGACksNRuQOT921z7HDfgb6t 7d3GRc1C2+Xb9EB88o2liaETAezpwWFdnwOBMoeVkiWYNHf7qle20NHiOzK5mkSKrGek uC1TYIstK+IaIccfqipkgvuB68GpDVVApFWFEkYg1NnDLCTaxecysfqp1U976MIRiBfw xVRQ== X-Gm-Message-State: AGRZ1gJpfHt6LT1EWbYnHrSEvJpPgBQ/b7/T+BBB+g0UnVdiowpE0uIh O4MjnWi9Nk7Hg9O2PTVqbSqITQ== X-Google-Smtp-Source: AJdET5chvDecqw84XiPJweQR8//BORSat+70iS/1D/Cxg1wiuS1JXqto4BG0SV9yupI3Mkoz1W2h0A== X-Received: by 2002:a19:6806:: with SMTP id d6mr10802036lfc.48.1542648608038; Mon, 19 Nov 2018 09:30:08 -0800 (PST) Received: from wasted.cogentembedded.com ([31.173.87.42]) by smtp.gmail.com with ESMTPSA id z7-v6sm1820472lji.42.2018.11.19.09.30.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 19 Nov 2018 09:30:07 -0800 (PST) From: Sergei Shtylyov Subject: [PATCH] pinctrl: sh-pfc: r8a77980: add QSPI pins, groups, and functions To: Linus Walleij , Geert Uytterhoeven , linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org Cc: Laurent Pinchart References: <21306a59-8f20-ad08-fdc1-bcc6333c01d4@cogentembedded.com> Organization: Cogent Embedded Message-ID: <0f421bfb-8d5b-1a28-e5e5-2cbccfc62479@cogentembedded.com> Date: Mon, 19 Nov 2018 20:30:06 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <21306a59-8f20-ad08-fdc1-bcc6333c01d4@cogentembedded.com> Content-Language: en-MW Sender: linux-renesas-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-renesas-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Dmitry Shifrin Add the QSPI{0|1} pins/groups/functions to the R8A77980 PFC driver. [Sergei: ported to the upstream driver, fixed up the swapped QSPI0 SPCLK/ SSL pins, fixed up the comments, moved the QSPI pins/groups/functions to be in the alphanumeric order, removed unneeded empty lines, renamed the patch.] Signed-off-by: Dmitry Shifrin Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven --- The patch is against the 'sh-pfc' branch of Geert's 'renesas-drivers.git' repo. drivers/pinctrl/sh-pfc/pfc-r8a77980.c | 70 ++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) Index: renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77980.c =================================================================== --- renesas-drivers.orig/drivers/pinctrl/sh-pfc/pfc-r8a77980.c +++ renesas-drivers/drivers/pinctrl/sh-pfc/pfc-r8a77980.c @@ -1660,6 +1660,56 @@ static const unsigned int pwm4_b_mux[] = PWM4_B_MARK, }; +/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5), +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +static const unsigned int qspi0_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), +}; +static const unsigned int qspi0_data2_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, +}; +static const unsigned int qspi0_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), + RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), +}; +static const unsigned int qspi0_data4_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK +}; + +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* SPCLK, SSL */ + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11), +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int qspi1_data2_pins[] = { + /* MOSI_IO0, MISO_IO1 */ + RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), +}; +static const unsigned int qspi1_data2_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +}; +static const unsigned int qspi1_data4_pins[] = { + /* MOSI_IO0, MISO_IO1, IO2, IO3 */ + RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), +}; +static const unsigned int qspi1_data4_mux[] = { + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX0, TX0 */ @@ -2092,6 +2142,12 @@ static const struct sh_pfc_pin_group pin SH_PFC_PIN_GROUP(pwm3_b), SH_PFC_PIN_GROUP(pwm4_a), SH_PFC_PIN_GROUP(pwm4_b), + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP(qspi0_data2), + SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP(qspi1_data2), + SH_PFC_PIN_GROUP(qspi1_data4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -2316,6 +2372,18 @@ static const char * const pwm4_groups[] "pwm4_b", }; +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -2412,6 +2480,8 @@ static const struct sh_pfc_function pinm SH_PFC_FUNCTION(pwm2), SH_PFC_FUNCTION(pwm3), SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif3),