From patchwork Mon Nov 19 23:47:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10689621 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0BF6813BB for ; Mon, 19 Nov 2018 23:47:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EF8512A3F0 for ; Mon, 19 Nov 2018 23:47:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E348F2A567; Mon, 19 Nov 2018 23:47:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8DED62A3F0 for ; Mon, 19 Nov 2018 23:47:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732146AbeKTKNV (ORCPT ); Tue, 20 Nov 2018 05:13:21 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:55002 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726431AbeKTKNV (ORCPT ); Tue, 20 Nov 2018 05:13:21 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 289C360B0D; Mon, 19 Nov 2018 23:47:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1542671233; bh=BXc30Oiq33agLJdtDiAxc9XUnBIPBPQDmrvakRMft6w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XX2qAb6NqByev74MbXuiaaQhE2WY0L2YVOe+PrvCpzxuUWMvupH60mE5ee1JCMfVj DQBJoaXeE0IOjwWglAdYv5zWZR1AF1eQT7DlRvN5dghK+6uWVNOGEVEkOJ6QrlMpSA erSwXWOXecJyCgovG122zDKPmwXibtFgPgS6qpbw= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 95DBF60767; Mon, 19 Nov 2018 23:47:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1542671232; bh=BXc30Oiq33agLJdtDiAxc9XUnBIPBPQDmrvakRMft6w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D7/DyzZw7Usvkv9kK/O8DT81kgv/YA9LZp5F8B9UqnW6MceJ6C/gDyf3CIgvrXtWC Haj1tC5/CgOI++4fwWxHYhc8MjliP41wEGrFeQRfylNgc2elwiPzJLvtDhi1dTqgrX fO9IV3t6Ii9fMwDM35zQYlZL/9qzZNU7bEBL2jKY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 95DBF60767 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: sboyd@kernel.org, mturquette@baylibre.com Cc: andy.gross@linaro.org, david.brown@linaro.org, rnayak@codeaurora.org, okukatla@codeaurora.org, tdas@codeaurora.org, linux-arm-msm@vger.kernel.orgi, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, robdclark@gmail.com, freedreno@lists.freedesktop.org Subject: [PATCH 1/4] drm/msm/a6xx: Remove unwanted regulator code Date: Mon, 19 Nov 2018 16:47:03 -0700 Message-Id: <20181119234706.5821-2-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181119234706.5821-1-jcrouse@codeaurora.org> References: <20181119234706.5821-1-jcrouse@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The GMU code currently has some misguided code to try to work around a hardware quirk that requires the power domains on the GPU be collapsed in a certain order. Upcoming patches will do this the right way so get rid of the unused and unwanted regulator code. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ---- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 -- 2 files changed, 6 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 546599a7ab05..51493f409358 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -646,9 +646,6 @@ int a6xx_gmu_reset(struct a6xx_gpu *a6xx_gpu) gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val, (val & 1), 100, 1000); - /* Force off the GX GSDC */ - regulator_force_disable(gmu->gx); - /* Disable the resources */ clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); pm_runtime_put_sync(gmu->dev); @@ -1173,7 +1170,6 @@ int a6xx_gmu_probe(struct a6xx_gpu *a6xx_gpu, struct device_node *node) gmu->idle_level = GMU_IDLE_STATE_ACTIVE; pm_runtime_enable(gmu->dev); - gmu->gx = devm_regulator_get(gmu->dev, "vdd"); /* Get the list of clocks */ ret = a6xx_gmu_clocks_probe(gmu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index 35f765afae45..a871cae2fc5e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -52,8 +52,6 @@ struct a6xx_gmu { int hfi_irq; int gmu_irq; - struct regulator *gx; - struct iommu_domain *domain; u64 uncached_iova_base; From patchwork Mon Nov 19 23:47:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10689623 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CF0BF13BB for ; Mon, 19 Nov 2018 23:47:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C15DD2A3F0 for ; Mon, 19 Nov 2018 23:47:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B56712A567; Mon, 19 Nov 2018 23:47:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 692C62A3F0 for ; Mon, 19 Nov 2018 23:47:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732148AbeKTKNW (ORCPT ); Tue, 20 Nov 2018 05:13:22 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:55138 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726431AbeKTKNW (ORCPT ); Tue, 20 Nov 2018 05:13:22 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 8C7D260F39; Mon, 19 Nov 2018 23:47:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1542671234; bh=wdqBCYihQ6Q6FwhJQZHjTJyK6hJPxkoDalFBTcPQ5TQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jW7rKHwtb1sqR10Cw/xAkgVDfewC6UCjA3iGSI7yNFBrLatyU8KU72kdUY5Eygq+X Jpa/FhkzCv3wc50SSh/T/3jhr7Z3XnpyG9AaeAD6soU2J1injMjN3jE9WV9dV0Fw83 Iz6eF3z+fD3ZU/oSY741rTS1IZFSGukXXbXfDJ1Y= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id C46D160BDE; Mon, 19 Nov 2018 23:47:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1542671233; bh=wdqBCYihQ6Q6FwhJQZHjTJyK6hJPxkoDalFBTcPQ5TQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mHyfvIu7WTxtJ9ATU2ZX7dHhuhVNwgBMjJx699zJ0SjWdkBxDzP2UGXNANigaZvA7 fPKvV25lftpWWWDB8JptapAVgP0Q2hPBTSMFO623/0xFTD8xnLOMk+orwcrrOkfCTE FVYjZFPtdTzFv02+EkChNpObVM4aZnNtS4W3GYm8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C46D160BDE Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: sboyd@kernel.org, mturquette@baylibre.com Cc: andy.gross@linaro.org, david.brown@linaro.org, rnayak@codeaurora.org, okukatla@codeaurora.org, tdas@codeaurora.org, linux-arm-msm@vger.kernel.orgi, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, robdclark@gmail.com, freedreno@lists.freedesktop.org Subject: [PATCH 2/4] clk: qcom: gdsc: Don't override existing gdsc pd functions Date: Mon, 19 Nov 2018 16:47:04 -0700 Message-Id: <20181119234706.5821-3-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181119234706.5821-1-jcrouse@codeaurora.org> References: <20181119234706.5821-1-jcrouse@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In very extreme cases an individual gdsc may wish to override the power domain enable or disable callback functions for their own purposes. Only set the generic gdsc callback if the function pointers are not already set. Signed-off-by: Jordan Crouse Acked-by: Rajendra Nayak --- drivers/clk/qcom/gdsc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index b6adca1f3918..7b55368b9a9c 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -394,8 +394,10 @@ static int gdsc_init(struct gdsc *sc) else gdsc_clear_mem_on(sc); - sc->pd.power_off = gdsc_disable; - sc->pd.power_on = gdsc_enable; + if (!sc->pd.power_off) + sc->pd.power_off = gdsc_disable; + if (!sc->pd.power_on) + sc->pd.power_on = gdsc_enable; pm_genpd_init(&sc->pd, NULL, !on); return 0; From patchwork Mon Nov 19 23:47:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10689625 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D94B513AD for ; Mon, 19 Nov 2018 23:47:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CB24E2A3F0 for ; Mon, 19 Nov 2018 23:47:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BF3DC2A567; Mon, 19 Nov 2018 23:47:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 507152A3F0 for ; Mon, 19 Nov 2018 23:47:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732155AbeKTKNY (ORCPT ); Tue, 20 Nov 2018 05:13:24 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:55334 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726431AbeKTKNY (ORCPT ); Tue, 20 Nov 2018 05:13:24 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 0AA1D612F2; Mon, 19 Nov 2018 23:47:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1542671236; bh=oYam9LxkR87XzgaWihdvEc7whQBRvvyQxOaxx+4DZ1U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ovbUL+mTe/G175h8/S4mCEuuOzQS+8PTNgeSQzqKmhmeJNK6Kbk80Ef5F4DHTSYiB lvRIr7xqgpByPrJMS7+WyyqA/OYHfnJzvZgV6SDYQ8UBu/vD2mK27YurQvrBRdmd3a MREEFcdZPZe5ZGnBjuZxl0QZETzvrcsb5+FJWNUI= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2329760C5F; Mon, 19 Nov 2018 23:47:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1542671235; bh=oYam9LxkR87XzgaWihdvEc7whQBRvvyQxOaxx+4DZ1U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KlISF6bz8eQX9waIRufS3DmOx68Bh4fCRIMyaTZj9vUPH7uQ2kcyzBpuOGlx0EUqk kzfZxEXMdzfYVAN2XkAseNhV6jBCkMTdQP/HaUYDNf9q52nR+MdvqYg/96ZDPw72LI XONem/giJjrmg/Cjt5rW23sCkjiDgoLonQRIuRIc= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 2329760C5F Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: sboyd@kernel.org, mturquette@baylibre.com Cc: andy.gross@linaro.org, david.brown@linaro.org, rnayak@codeaurora.org, okukatla@codeaurora.org, tdas@codeaurora.org, linux-arm-msm@vger.kernel.orgi, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, robdclark@gmail.com, freedreno@lists.freedesktop.org Subject: [PATCH 3/4] clk: qcom: Add a dummy enable function for GX gdsc Date: Mon, 19 Nov 2018 16:47:05 -0700 Message-Id: <20181119234706.5821-4-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181119234706.5821-1-jcrouse@codeaurora.org> References: <20181119234706.5821-1-jcrouse@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Most of the time the CPU should not be touching the GX domain on the GPU except for a very special use case when the CPU needs to force the GX headswitch off. Add a dummy enable function for the GX gdsc to simulate success so that the pm_runtime reference counting is correct. Signed-off-by: Jordan Crouse --- drivers/clk/qcom/gpucc-sdm845.c | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/gpucc-sdm845.c b/drivers/clk/qcom/gpucc-sdm845.c index 7a11b70b33f4..06254329ea33 100644 --- a/drivers/clk/qcom/gpucc-sdm845.c +++ b/drivers/clk/qcom/gpucc-sdm845.c @@ -319,16 +319,38 @@ static struct gdsc gpu_cx_gdsc = { .flags = VOTABLE, }; +/* + * On SDM845 the GPU GX domain is *almost* entirely controlled by the GMU + * running in the CX domain so the CPU doesn't need to know anything about the + * GX domain EXCEPT.... + * + * Hardware constraints dictate that the GX be powered down before the CX. If + * the GMU crashes it could leave the GX on. In order to successfully bring back + * the device the CPU needs to disable the GX headswitch. There being no sane + * way to reach in and touch that register from deep inside the GPU driver we + * need to set up the infrastructure to be able to ensure that the GPU can + * ensure that the GX is off during this super special case. We do this by + * defining a GX gdsc with a dummy enable function and a "default" disable + * function. + * + * This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU + * driver. During power up, nothing will happen from the CPU (and the GMU will + * power up normally but during power down this will ensure that the GX domain + * is *really* off - this gives us a semi standard way of doing what we need. + */ +static int gx_gdsc_enable(struct generic_pm_domain *domain) +{ + /* Do nothing but give genpd the impression that we were successful */ + return 0; +} + static struct gdsc gpu_gx_gdsc = { .gdscr = 0x100c, .clamp_io_ctrl = 0x1508, .pd = { .name = "gpu_gx_gdsc", + .power_on = gx_gdsc_enable, }, - .clk_hws = { - &gpu_cc_gx_gfx3d_clk_src.clkr.hw, - }, - .clk_count = 1, .pwrsts = PWRSTS_OFF_ON, .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR, }; From patchwork Mon Nov 19 23:47:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10689627 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6C08713AD for ; Mon, 19 Nov 2018 23:47:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 297BC2A3F0 for ; Mon, 19 Nov 2018 23:47:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1D6F92A569; Mon, 19 Nov 2018 23:47:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 919942A3F0 for ; Mon, 19 Nov 2018 23:47:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732158AbeKTKNZ (ORCPT ); Tue, 20 Nov 2018 05:13:25 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:55426 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726431AbeKTKNZ (ORCPT ); Tue, 20 Nov 2018 05:13:25 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 4A9D26130F; Mon, 19 Nov 2018 23:47:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1542671237; bh=WSojjFjwCU/SrSA4Fc3cNylaU5CFnaVeAzuD6In1/rc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P4wCql7aWDpYauVgyNCWuRgf+Gm57OqbsCacE3M28RKP6rn5P986zZ1P5MkxYB4CN 3G7TfAf+MPRtXKDdKPOvnGweW5xCVXZTMTDrFar27xVTBdu+Z7bGIV1f2Jn5QDqUVs dfHzinEEbE/IMZpMyOh8El69kFHiOak6HzqGf00E= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 552BC612F1; Mon, 19 Nov 2018 23:47:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1542671236; bh=WSojjFjwCU/SrSA4Fc3cNylaU5CFnaVeAzuD6In1/rc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iWV9u81M8vK0tzXVNJdYKBWN04HTxJSep1T4+vRXYBH/xun8RNizqirD3eeW6xcsP 4FuU68EVtxrW+acnl1+4Ob/asxPGVaTpWvjrTeEzWdEFLwU5mlwtoYEhYWXjC27sXx H77y0KACjob+k04bWRduP8rL5Q/d1JiKqwWZmN98= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 552BC612F1 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: sboyd@kernel.org, mturquette@baylibre.com Cc: andy.gross@linaro.org, david.brown@linaro.org, rnayak@codeaurora.org, okukatla@codeaurora.org, tdas@codeaurora.org, linux-arm-msm@vger.kernel.orgi, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, robdclark@gmail.com, freedreno@lists.freedesktop.org Subject: [PATCH 4/4] drm/msm/gpu: Attach to the GPU GX power domain Date: Mon, 19 Nov 2018 16:47:06 -0700 Message-Id: <20181119234706.5821-5-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20181119234706.5821-1-jcrouse@codeaurora.org> References: <20181119234706.5821-1-jcrouse@codeaurora.org> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP 99.999% of the time during normal operation the GMU is responsible for power and clock control on the GX domain and the CPU remains blissfully unaware. However, there is one situation where the CPU needs to get involved: The power sequencing rules dictate that the GX needs to be turned off before the CX so that the CX can be turned on before the GX during power up. During normal operation when the CPU is taking down the CX domain a stop command is sent to the GMU which turns off the GX domain and then the CPU handles the CX domain. But if the GMU happened to be unresponsive while the GX domain was left then the CPU will need to step in and turn off the GX domain before resetting the CX and rebooting the GMU. This unfortunately means that the CPU needs to be marginally aware of the GX domain even though it is expected to usually keep its hands off. To support this we create a semi-disabled GX power domain that does nothing to the hardware on power up but tries to shut it down normally on power down. In this method the reference counting is correct and we can step in with the pm_runtime_put() at the right time during the failure path. This patch sets up the connection to the GX power domain and does the magic to "enable" and disable it at the right points. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 41 ++++++++++++++++++++++++++- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 ++ 2 files changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 51493f409358..ca71709efc94 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -2,6 +2,7 @@ /* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. */ #include +#include #include #include @@ -646,6 +647,16 @@ int a6xx_gmu_reset(struct a6xx_gpu *a6xx_gpu) gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val, (val & 1), 100, 1000); + /* + * Depending on the state of the GMU at this point the GX domain might + * have been left on. Hardware sequencing rules state that the GX has to + * be turned off before the CX domain so this is that one time that + * that calling pm_runtime_put_sync() is expected to do something useful + * (turn off the headswitch) + */ + if (!IS_ERR(gmu->gxpd)) + pm_runtime_put_sync(gmu->gxpd); + /* Disable the resources */ clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); pm_runtime_put_sync(gmu->dev); @@ -707,6 +718,14 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) /* Set the GPU to the highest power frequency */ __a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1); + /* + * "enable" the GX power domain which won't actually do anything but it + * will make sure that the refcounting is correct in case we need to + * bring down the GX after a GMU failure + */ + if (!IS_ERR(gmu->gxpd)) + pm_runtime_get(gmu->gxpd); + out: /* Make sure to turn off the boot OOB request on error */ if (ret) @@ -778,6 +797,14 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) /* Tell RPMh to power off the GPU */ a6xx_rpmh_stop(gmu); + /* + * Mark the GPU power domain as off. During the shutdown process the GMU + * should actually turn off the power so this is really just a + * houskeeping step + */ + if (!IS_ERR(gmu->gxpd)) + pm_runtime_put_sync(gmu->gxpd); + clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); pm_runtime_put_sync(gmu->dev); @@ -1142,9 +1169,15 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) if (IS_ERR_OR_NULL(gmu->mmio)) return; - pm_runtime_disable(gmu->dev); a6xx_gmu_stop(a6xx_gpu); + pm_runtime_disable(gmu->dev); + + if (!IS_ERR(gmu->gxpd)) { + pm_runtime_disable(gmu->gxpd); + dev_pm_domain_detach(gmu->gxpd, false); + } + a6xx_gmu_irq_disable(gmu); a6xx_gmu_memory_free(gmu, gmu->hfi); @@ -1203,6 +1236,12 @@ int a6xx_gmu_probe(struct a6xx_gpu *a6xx_gpu, struct device_node *node) if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) goto err; + /* + * Get a link to the GX power domain to reset the GPU in case of GMU + * crash + */ + gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx"); + /* Get the power levels for the GMU and GPU */ a6xx_gmu_pwrlevels_probe(gmu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h index a871cae2fc5e..dcc172d55f49 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -55,6 +55,8 @@ struct a6xx_gmu { struct iommu_domain *domain; u64 uncached_iova_base; + struct device *gxpd; + int idle_level; struct a6xx_gmu_bo *hfi;