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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id k12sm235183ios.2.2021.03.17.16.33.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 16:33:07 -0700 (PDT) From: Rebecca Cran To: Peter Maydell , Richard Henderson , qemu-arm@nongnu.org Subject: [PATCH v5 1/4] accel/tcg: Add TLB invalidation support for ranges of addresses Date: Wed, 17 Mar 2021 17:32:58 -0600 Message-Id: <20210317233301.4130-2-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210317233301.4130-1-rebecca@nuviainc.com> References: <20210317233301.4130-1-rebecca@nuviainc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d30; envelope-from=rebecca@nuviainc.com; helo=mail-io1-xd30.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Add functions to support the FEAT_TLBIRANGE ARMv8.4 feature that adds TLB invalidation instructions to invalidate ranges of addresses. Signed-off-by: Rebecca Cran --- accel/tcg/cputlb.c | 130 +++++++++++++++++++- include/exec/exec-all.h | 45 +++++++ 2 files changed, 172 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 8a7b779270a4..dc44967dcf8e 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -709,7 +709,7 @@ void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr) tlb_flush_page_by_mmuidx_all_cpus_synced(src, addr, ALL_MMUIDX_BITS); } -static void tlb_flush_page_bits_locked(CPUArchState *env, int midx, +static bool tlb_flush_page_bits_locked(CPUArchState *env, int midx, target_ulong page, unsigned bits) { CPUTLBDesc *d = &env_tlb(env)->d[midx]; @@ -729,7 +729,7 @@ static void tlb_flush_page_bits_locked(CPUArchState *env, int midx, TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", midx, page, mask); tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime()); - return; + return true; } /* Check if we need to flush due to large pages. */ @@ -738,13 +738,14 @@ static void tlb_flush_page_bits_locked(CPUArchState *env, int midx, TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", midx, d->large_page_addr, d->large_page_mask); tlb_flush_one_mmuidx_locked(env, midx, get_clock_realtime()); - return; + return true; } if (tlb_flush_entry_mask_locked(tlb_entry(env, midx, page), page, mask)) { tlb_n_used_entries_dec(env, midx); } tlb_flush_vtlb_page_mask_locked(env, midx, page, mask); + return false; } typedef struct { @@ -943,6 +944,129 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, } } +typedef struct { + target_ulong addr; + target_ulong length; + uint16_t idxmap; + uint16_t bits; +} TLBFlushPageRangeBitsByMMUIdxData; + +static void +tlb_flush_page_range_bits_by_mmuidx_async_0(CPUState *cpu, + target_ulong addr, + target_ulong length, + uint16_t idxmap, + unsigned bits) +{ + CPUArchState *env = cpu->env_ptr; + int mmu_idx; + target_ulong l; + target_ulong page = addr; + bool full_flush; + + assert_cpu_is_self(cpu); + + tlb_debug("page addr:" TARGET_FMT_lx "/%u len: " TARGET_FMT_lx + " mmu_map:0x%x\n", + addr, bits, length, idxmap); + + qemu_spin_lock(&env_tlb(env)->c.lock); + for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { + if ((idxmap >> mmu_idx) & 1) { + for (l = 0; l < length; l += TARGET_PAGE_SIZE) { + page = addr + l; + full_flush = tlb_flush_page_bits_locked(env, mmu_idx, + page, bits); + if (full_flush) { + break; + } + } + } + } + qemu_spin_unlock(&env_tlb(env)->c.lock); + + for (l = 0; l < length; l += TARGET_PAGE_SIZE) { + tb_flush_jmp_cache(cpu, page); + } +} + +static void +tlb_flush_page_range_bits_by_mmuidx_async_1(CPUState *cpu, + run_on_cpu_data data) +{ + TLBFlushPageRangeBitsByMMUIdxData *d = data.host_ptr; + + tlb_flush_page_range_bits_by_mmuidx_async_0(cpu, d->addr, d->length, + d->idxmap, d->bits); + + g_free(d); +} + +void tlb_flush_page_range_bits_by_mmuidx(CPUState *cpu, + target_ulong addr, + target_ulong length, + uint16_t idxmap, + unsigned bits) +{ + TLBFlushPageRangeBitsByMMUIdxData d; + TLBFlushPageRangeBitsByMMUIdxData *p; + + /* This should already be page aligned */ + addr &= TARGET_PAGE_BITS; + + d.addr = addr & TARGET_PAGE_MASK; + d.idxmap = idxmap; + d.bits = bits; + d.length = length; + + if (qemu_cpu_is_self(cpu)) { + tlb_flush_page_range_bits_by_mmuidx_async_0(cpu, addr, length, + idxmap, bits); + } else { + p = g_new(TLBFlushPageRangeBitsByMMUIdxData, 1); + + /* Allocate a structure, freed by the worker. */ + *p = d; + async_run_on_cpu(cpu, tlb_flush_page_range_bits_by_mmuidx_async_1, + RUN_ON_CPU_HOST_PTR(p)); + } +} + +void tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, + target_ulong addr, + target_ulong length, + uint16_t idxmap, + unsigned bits) +{ + TLBFlushPageRangeBitsByMMUIdxData d; + TLBFlushPageRangeBitsByMMUIdxData *p; + CPUState *dst_cpu; + + /* This should already be page aligned */ + addr &= TARGET_PAGE_BITS; + + d.addr = addr; + d.idxmap = idxmap; + d.bits = bits; + d.length = length; + + /* Allocate a separate data block for each destination cpu. */ + CPU_FOREACH(dst_cpu) { + if (dst_cpu != src_cpu) { + p = g_new(TLBFlushPageRangeBitsByMMUIdxData, 1); + *p = d; + async_run_on_cpu(dst_cpu, + tlb_flush_page_range_bits_by_mmuidx_async_1, + RUN_ON_CPU_HOST_PTR(p)); + } + } + + p = g_new(TLBFlushPageRangeBitsByMMUIdxData, 1); + *p = d; + async_safe_run_on_cpu(src_cpu, tlb_flush_page_range_bits_by_mmuidx_async_1, + RUN_ON_CPU_HOST_PTR(p)); +} + /* update the TLBs so that writes to code in the virtual page 'addr' can be detected */ void tlb_protect_code(ram_addr_t ram_addr) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 6b036cae8f65..833e8d654a1c 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -212,6 +212,37 @@ void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr, */ void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr, uint16_t idxmap); +/** + * tlb_flush_page_range_by_mmuidx: + * @cpu: CPU whose TLB should be flushed + * @addr: virtual address of start of page range to be flushed + * @length: the number of bytes to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush a range of pages from the TLB of the specified CPU, for the specified + * MMU indexes. + */ +void tlb_flush_page_range_bits_by_mmuidx(CPUState *cpu, target_ulong addr, + target_ulong length, uint16_t idxmap, + unsigned bits); +/** + * tlb_flush_page_range_by_mmuidx_all_cpus_synced: + * @cpu: Originating CPU of the flush + * @addr: virtual address of start of page range to be flushed + * @length: the number of bytes to be flushed + * @idxmap: bitmap of MMU indexes to flush + * + * Flush a range of pages from the TLB of all CPUs, for the specified MMU + * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source + * vCPUs work is scheduled as safe work meaning all flushes will be + * complete once the source vCPUs safe work is complete. This will + * depend on when the guests translation ends the TB. + */ +void tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, + target_ulong addr, + target_ulong length, + uint16_t idxmap, + unsigned bits); /** * tlb_flush_by_mmuidx: * @cpu: CPU whose TLB should be flushed @@ -313,6 +344,20 @@ static inline void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr) { } +static inline void tlb_flush_page_range_bits_by_mmuidx(CPUState *cpu, + target_ulong addr, + target_ulong length, + uint16_t idxmap, + unsigned bits) +{ +} +static inline void tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, + target_ulong addr, + target_ulong length, + uint16_t idxmap, + unsigned bits) +{ +} static inline void tlb_flush(CPUState *cpu) { } From patchwork Wed Mar 17 23:32:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rebecca Cran X-Patchwork-Id: 12147109 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03D93C433DB for ; Wed, 17 Mar 2021 23:36:55 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4DD9C64F17 for ; Wed, 17 Mar 2021 23:36:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4DD9C64F17 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=nuviainc.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:42052 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lMfig-0007VF-Cw for qemu-devel@archiver.kernel.org; Wed, 17 Mar 2021 19:36:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48572) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lMff6-0004Jl-Pa for qemu-devel@nongnu.org; Wed, 17 Mar 2021 19:33:12 -0400 Received: from mail-io1-xd34.google.com ([2607:f8b0:4864:20::d34]:47000) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lMff3-0001tD-UQ for qemu-devel@nongnu.org; Wed, 17 Mar 2021 19:33:12 -0400 Received: by mail-io1-xd34.google.com with SMTP id j26so378586iog.13 for ; Wed, 17 Mar 2021 16:33:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S00jNqe5qwvG10WP/V0cTf/NyHRWwWBdToA8oYUTOt4=; b=xVKt5xcrCS/oSZairJCs3iA+6RH+KK83g0d8FmM+cyPuvVJg26TSkIWUpfUAP2wUf/ VttzsTTvlK4QerMV5uZewU7HE6QroUKnxXBOHxiwXbDAYcpEEQlLxPRsb6SuziheQ7UV piTj4/g7LJwSX5aMLYo1noGY68NX0H8k3SHOxH7XWjkDAxn+Pp1pKkrCuzQB0qKcBYlE OoXpOaSfSow670FlzeU/i5jO3761AE+lA/zTdipz6klj6fMZ7Xj3tVxlEa9xcRbO1NEs VW+hSIKqWfBy3WpQ9R+dOYj1CaWrPpmgE2ikuZ7QmO1pJsEEdCYVQ8mMC2OFIv0CIomn wifw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S00jNqe5qwvG10WP/V0cTf/NyHRWwWBdToA8oYUTOt4=; b=edXczuaJl82y2rpOFDucIi1+hmtElT8NKn7yLwNboi4TdBN4nGsZPNbitKvXKz4zf9 Q2azjjWAwA+3BmFeys4M0+JT/pJFJcGwPw70vF5urkmt6Cnwhg6OQXrTp5jFIIM0qVhU qQHDJVML8tlxoC1S3/XA66h2HwqjVSmdXTPqMJSU13oP7hinL/PF2zkbB8zAv+K8VKzx jYqQy2GBTI2q7FFBJD/ACLWTtYuE80dH86RBIbDlrHQaIsxVA1RcLUDt9xWP4IvzveKu IHDGq78C9d0ya4bpSK4XZ/AYsW3SUbwgwOwb4RLX9fbo4AjtkcK9QYnphp+w0EhJ6+YR tiPw== X-Gm-Message-State: AOAM530TgngBc5wptvGG/xEHH1+O2Hqp2hUtL5qhUdNXuzSu+ENPWbK2 Oths48ZGknMqQt8408yh5s0sZg== X-Google-Smtp-Source: ABdhPJw26HsneT2j5+5aTJCp+gbqLHKzS/PGXEMub5OvSQkC9NyI46xJq5CRX69J7fzM8lbuv3MFMA== X-Received: by 2002:a05:6638:3049:: with SMTP id u9mr4727834jak.57.1616023988904; Wed, 17 Mar 2021 16:33:08 -0700 (PDT) Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id k12sm235183ios.2.2021.03.17.16.33.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 16:33:08 -0700 (PDT) From: Rebecca Cran To: Peter Maydell , Richard Henderson , qemu-arm@nongnu.org Subject: [PATCH v5 2/4] target/arm: Add support for FEAT_TLBIRANGE Date: Wed, 17 Mar 2021 17:32:59 -0600 Message-Id: <20210317233301.4130-3-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210317233301.4130-1-rebecca@nuviainc.com> References: <20210317233301.4130-1-rebecca@nuviainc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d34; envelope-from=rebecca@nuviainc.com; helo=mail-io1-xd34.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" ARMv8.4 adds the mandatory FEAT_TLBIRANGE. It provides TLBI maintenance instructions that apply to a range of input addresses. Signed-off-by: Rebecca Cran --- target/arm/cpu.h | 5 + target/arm/helper.c | 294 ++++++++++++++++++++ 2 files changed, 299 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 193a49ec7fac..32b78a4ef587 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4038,6 +4038,11 @@ static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; } +static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; +} + static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index d9220be7c5a0..ce913deff490 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4759,6 +4759,217 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, ARMMMUIdxBit_SE3, bits); } +#ifdef TARGET_AARCH64 +static uint64_t tlbi_aa64_range_get_length(CPUARMState *env, + uint64_t value) +{ + unsigned int page_shift; + unsigned int page_size_granule; + uint64_t num; + uint64_t scale; + uint64_t exponent; + uint64_t length; + + num = extract64(value, 39, 4); + scale = extract64(value, 44, 2); + page_size_granule = extract64(value, 46, 2); + + page_shift = page_size_granule * 2 + 10; + + if (page_size_granule == 0) { + qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", + page_size_granule); + return 0; + } + + exponent = (5 * scale) + 1; + length = (num + 1) << (exponent + page_shift); + + return length; +} + +static void tlbi_aa64_rvae1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL1&0. + * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + ARMMMUIdx mask; + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs = env_cpu(env); + mask = vae1_tlbmask(env); + if (regime_has_2_ranges(ctz32(mask))) { + pageaddr = sextract64(value, 0, 37) << TARGET_PAGE_BITS; + } else { + pageaddr = extract64(value, 0, 37) << TARGET_PAGE_BITS; + } + length = tlbi_aa64_range_get_length(env, value); + bits = tlbbits_for_regime(env, mask, pageaddr); + + if (tlb_force_broadcast(env)) { + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, mask, + bits); + } else { + tlb_flush_page_range_bits_by_mmuidx(cs, pageaddr, length, mask, + bits); + } +} + +static void tlbi_aa64_rvae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, Inner/Outer Shareable EL1&0. + * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS, + * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support + * flush-for-specific-ASID-only, flush-last-level-only or inner/outer + * shareable specific flushes. + */ + ARMMMUIdx mask; + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs = env_cpu(env); + mask = vae1_tlbmask(env); + if (regime_has_2_ranges(ctz32(mask))) { + pageaddr = sextract64(value, 0, 37) << TARGET_PAGE_BITS; + } else { + pageaddr = extract64(value, 0, 37) << TARGET_PAGE_BITS; + } + length = tlbi_aa64_range_get_length(env, value); + bits = tlbbits_for_regime(env, mask, pageaddr); + + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, mask, + bits); +} + +static void tlbi_aa64_rvae2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL2. + * Currently handles all of RVAE2, RVAAE2, RVAALE2 and RVALE2, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + ARMMMUIdx mask; + bool secure; + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs = env_cpu(env); + secure = arm_is_secure_below_el3(env); + pageaddr = extract64(value, 0, 37) << TARGET_PAGE_BITS; + length = tlbi_aa64_range_get_length(env, value); + mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; + bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2, + pageaddr); + + if (tlb_force_broadcast(env)) { + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, mask, + bits); + } else { + tlb_flush_page_range_bits_by_mmuidx(cs, pageaddr, length, mask, + bits); + } +} + +static void tlbi_aa64_rvae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, Inner/Outer Shareable, EL2. + * Currently handles all of RVAE2IS, RVAE2OS, RVAAE2IS, RVAAE2OS, + * RVAALE2IS, RVAALE2OS, RVALE2IS and RVALE2OS, since we don't support + * flush-for-specific-ASID-only, flush-last-level-only or inner/outer + * shareable specific flushes. + */ + ARMMMUIdx mask; + bool secure; + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs = env_cpu(env); + secure = arm_is_secure_below_el3(env); + pageaddr = extract64(value, 0, 37) << TARGET_PAGE_BITS; + length = tlbi_aa64_range_get_length(env, value); + mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; + bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2, + pageaddr); + + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, mask, + bits); +} + +static void tlbi_aa64_rvae3_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL3. + * Currently handles all of RVAE3, RVAAE3, RVAALE3 and RVALE3, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs = env_cpu(env); + pageaddr = extract64(value, 0, 37) << TARGET_PAGE_BITS; + length = tlbi_aa64_range_get_length(env, value); + bits = tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr); + + if (tlb_force_broadcast(env)) { + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, + ARMMMUIdxBit_SE3, + bits); + } else { + tlb_flush_page_range_bits_by_mmuidx(cs, pageaddr, length, + ARMMMUIdxBit_SE3, + bits); + } +} + +static void tlbi_aa64_rvae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA range, EL3, Inner/Outer Shareable. + * Currently handles all of RVAE3IS, RVAE3OS, RVAAE3IS, RVAAE3OS, + * RVAALE3IS, RVAALE3OS, RVALE3IS, and RVALE3OS, since we don't support + * flush-for-specific-ASID-only, flush-last-level-only or inner/outer + * specific flushes. + */ + int bits; + uint64_t pageaddr; + uint64_t length; + + CPUState *cs = env_cpu(env); + pageaddr = extract64(value, 0, 37) << TARGET_PAGE_BITS; + length = tlbi_aa64_range_get_length(env, value); + bits = tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr); + + tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + length, + ARMMMUIdxBit_SE3, + bits); +} +#endif + static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { @@ -6920,6 +7131,86 @@ static const ARMCPRegInfo pauth_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo tlbirange_reginfo[] = { + { .name = "TLBI_RVAE1IS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 1, + .access = PL1_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae1is_write }, + { .name = "TLBI_RVAAE1IS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 3, + .access = PL1_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae1is_write }, + { .name = "TLBI_RVALE1IS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 5, + .access = PL1_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae1is_write }, + { .name = "TLBI_RVAALE1IS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 2, .opc2 = 7, + .access = PL1_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae1is_write }, + { .name = "TLBI_RVAE1", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1, + .access = PL1_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae1_write }, + { .name = "TLBI_RVAAE1", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 3, + .access = PL1_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae1_write }, + { .name = "TLBI_RVALE1", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 5, + .access = PL1_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae1_write }, + { .name = "TLBI_RVAALE1", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 7, + .access = PL1_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae1_write }, + { .name = "TLBI_RIPAS2E1IS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 2, + .access = PL2_W, .type = ARM_CP_NOP }, + { .name = "TLBI_RIPAS2LE1IS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 6, + .access = PL2_W, .type = ARM_CP_NOP }, + { .name = "TLBI_RVAE2IS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 1, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae2is_write }, + { .name = "TLBI_RVALE2IS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 2, .opc2 = 5, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae2is_write }, + { .name = "TLBI_RIPAS2E1", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 2, + .access = PL2_W, .type = ARM_CP_NOP }, + { .name = "TLBI_RIPAS2LE1", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 6, + .access = PL2_W, .type = ARM_CP_NOP }, + { .name = "TLBI_RVAE2", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 1, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae2_write }, + { .name = "TLBI_RVALE2", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 6, .opc2 = 5, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae2_write }, + { .name = "TLBI_RVAE3IS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 1, + .access = PL3_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae3is_write }, + { .name = "TLBI_RVALE3IS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 2, .opc2 = 5, + .access = PL3_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae3is_write }, + { .name = "TLBI_RVAE3", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 1, + .access = PL3_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae3_write }, + { .name = "TLBI_RVALE3", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 6, .opc2 = 5, + .access = PL3_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae3_write }, + REGINFO_SENTINEL +}; + static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) { Error *err = NULL; @@ -8289,6 +8580,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_rndr, cpu)) { define_arm_cp_regs(cpu, rndr_reginfo); } + if (cpu_isar_feature(aa64_tlbirange, cpu)) { + define_arm_cp_regs(cpu, tlbirange_reginfo); + } #ifndef CONFIG_USER_ONLY /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { From patchwork Wed Mar 17 23:33:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rebecca Cran X-Patchwork-Id: 12147113 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93EAFC433E0 for ; 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id k12sm235183ios.2.2021.03.17.16.33.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 16:33:09 -0700 (PDT) From: Rebecca Cran To: Peter Maydell , Richard Henderson , qemu-arm@nongnu.org Subject: [PATCH v5 3/4] target/arm: Add support for FEAT_TLBIOS Date: Wed, 17 Mar 2021 17:33:00 -0600 Message-Id: <20210317233301.4130-4-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210317233301.4130-1-rebecca@nuviainc.com> References: <20210317233301.4130-1-rebecca@nuviainc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d2e; envelope-from=rebecca@nuviainc.com; helo=mail-io1-xd2e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" ARMv8.4 adds the mandatory FEAT_TLBIOS. It provides TLBI maintenance instructions that extend to the Outer Shareable domain. Signed-off-by: Rebecca Cran --- target/arm/cpu.h | 5 ++ target/arm/helper.c | 75 ++++++++++++++++++++ 2 files changed, 80 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 32b78a4ef587..272fde83ca4e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4043,6 +4043,11 @@ static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; } +static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0; +} + static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index ce913deff490..5b10f179b761 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7211,6 +7211,78 @@ static const ARMCPRegInfo tlbirange_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo tlbios_reginfo[] = { + { .name = "TLBI_VMALLE1OS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 0, + .access = PL1_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_vmalle1is_write }, + { .name = "TLBI_ASIDE1OS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 1, .opc2 = 2, + .access = PL1_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_vmalle1is_write }, + { .name = "TLBI_RVAE1OS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1, + .access = PL1_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae1is_write }, + { .name = "TLBI_RVAAE1OS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 3, + .access = PL1_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae1is_write }, + { .name = "TLBI_RVALE1OS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 5, + .access = PL1_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae1is_write }, + { .name = "TLBI_RVAALE1OS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 7, + .access = PL1_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae1is_write }, + { .name = "TLBI_ALLE2OS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 0, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_alle2is_write }, + { .name = "TLBI_ALLE1OS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 4, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_alle1is_write }, + { .name = "TLBI_VMALLS12E1OS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 1, .opc2 = 6, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_alle1is_write }, + { .name = "TLBI_IPAS2E1OS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 0, + .access = PL2_W, .type = ARM_CP_NOP }, + { .name = "TLBI_RIPAS2E1OS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 3, + .access = PL2_W, .type = ARM_CP_NOP }, + { .name = "TLBI_IPAS2LE1OS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 4, + .access = PL2_W, .type = ARM_CP_NOP }, + { .name = "TLBI_RIPAS2LE1OS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 7, + .access = PL2_W, .type = ARM_CP_NOP }, + { .name = "TLBI_RVAE2OS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 1, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae2is_write }, + { .name = "TLBI_RVALE2OS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 5, .opc2 = 5, + .access = PL2_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae2is_write }, + { .name = "TLBI_ALLE3OS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 0, + .access = PL3_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_alle3is_write }, + { .name = "TLBI_RVAE3OS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 1, + .access = PL3_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae3is_write }, + { .name = "TLBI_RVALE3OS", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 5, .opc2 = 5, + .access = PL3_W, .type = ARM_CP_NO_RAW, + .writefn = tlbi_aa64_rvae3is_write }, + REGINFO_SENTINEL +}; + static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) { Error *err = NULL; @@ -8583,6 +8655,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_tlbirange, cpu)) { define_arm_cp_regs(cpu, tlbirange_reginfo); } + if (cpu_isar_feature(aa64_tlbios, cpu)) { + define_arm_cp_regs(cpu, tlbios_reginfo); + } #ifndef CONFIG_USER_ONLY /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { From patchwork Wed Mar 17 23:33:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rebecca Cran X-Patchwork-Id: 12147111 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D287C433DB for ; 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[174.52.16.57]) by smtp.gmail.com with ESMTPSA id k12sm235183ios.2.2021.03.17.16.33.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Mar 2021 16:33:10 -0700 (PDT) From: Rebecca Cran To: Peter Maydell , Richard Henderson , qemu-arm@nongnu.org Subject: [PATCH v5 4/4] target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type Date: Wed, 17 Mar 2021 17:33:01 -0600 Message-Id: <20210317233301.4130-5-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210317233301.4130-1-rebecca@nuviainc.com> References: <20210317233301.4130-1-rebecca@nuviainc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d2b; envelope-from=rebecca@nuviainc.com; helo=mail-io1-xd2b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rebecca Cran , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f0a9e968c9c1..f42803ecaf1d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -651,6 +651,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ + t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); cpu->isar.id_aa64isar0 = t;