From patchwork Tue Nov 20 15:31:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Merello X-Patchwork-Id: 10690509 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id F242A13BB for ; Tue, 20 Nov 2018 15:32:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DE33D2A9BC for ; Tue, 20 Nov 2018 15:32:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D25212A9C0; Tue, 20 Nov 2018 15:32:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 52FBC2A9BC for ; Tue, 20 Nov 2018 15:32:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726172AbeKUCBp (ORCPT ); Tue, 20 Nov 2018 21:01:45 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:54825 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725898AbeKUCBn (ORCPT ); Tue, 20 Nov 2018 21:01:43 -0500 Received: by mail-wm1-f67.google.com with SMTP id r63-v6so2541561wma.4; Tue, 20 Nov 2018 07:31:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=UAVjVxrHy7jY0LD8rLTX0Nt447suhUTP5t0nzIFbdzg=; b=E7L5B6lvChTyKw1pqzpd7T+z6RZMF/JG26xYCU0vavXvAqEJ0H194iP8eSryW8kaMw F5//T2FUXh8KsDyBQh+sR88PKkbAOYlXZVGGwGcsaAeord2Y1SoL54/X+qO+83IQphuM CpwRpFHkjTGnpQMkMS44NiQuM1lD8DxikH1AlT6EkXAPgUYtf7thjesy+srXQf15eNkm okm7O7msB3Fk9fj3WKOhXoGMH5+BXsGisqq2BAvtbczrCUBCfhupLZww+jhYL+v4Bpnd 7LCQ+ZU3Z1RYxWwEQgb7JkQNOwyAuhif1+5wAAAsiuN3yrF1TgkiLv6YxBYm/8ppKj1J qHwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=UAVjVxrHy7jY0LD8rLTX0Nt447suhUTP5t0nzIFbdzg=; b=C5RyY5+FZyHCrcE3XyNSzVeOJQfr0uIfbdQScgEfOMga/g4IovPsmkI3llxQiKWJYp Reb1mnFX2bgPxuHSLnMwwZlJn2vgcpcE4kjmOoSFkjM2E4RwE+LAclJGazOeUfjqrQ6Z urF1s7TxSPjh3vE1WHIVUhXL/SUkPEHx4x+kxIjdhfk1gLu+HtDtD7W+1ZxHqxiaClGU At47z+2Ed7P/Bnm33HS3Y6uMVrz0HX+jiivsDjOxCPV9j69xJ1QCCFlj+4hRonenSiBb SSrZrt9lUpNZBagxYnstUHpEUpBiyO78KIanX0hGlaOcJoWb3tRHgZBKE2lqHBH3WdJk jBmA== X-Gm-Message-State: AGRZ1gLU54FdH0648dr/Rv13fFCJmCSWcGDW71513gHuf2FKbU0ac5au Xwa8pD25bqJJ8QO4eQtAAS4= X-Google-Smtp-Source: AFSGD/VAH1OR78zL6To3VWVtf/8aiVkX5+7F81vDlu47T5yDS43QTemEe1SW3noUIRu33oiL6vhjJw== X-Received: by 2002:a1c:7ec9:: with SMTP id z192-v6mr2504093wmc.43.1542727919065; Tue, 20 Nov 2018 07:31:59 -0800 (PST) Received: from NewMoon.iit.local ([90.147.180.254]) by smtp.gmail.com with ESMTPSA id k73sm14677464wmd.36.2018.11.20.07.31.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Nov 2018 07:31:58 -0800 (PST) From: Andrea Merello To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello Subject: [PATCH v6 1/7] dmaengine: xilinx_dma: commonize DMA copy size calculation Date: Tue, 20 Nov 2018 16:31:45 +0100 Message-Id: <20181120153151.18024-1-andrea.merello@gmail.com> X-Mailer: git-send-email 2.17.1 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch removes a bit of duplicated code by introducing a new function that implements calculations for DMA copy size, and prepares for changes to the copy size calculation that will happen in following patches. Suggested-by: Vinod Koul Signed-off-by: Andrea Merello Reviewed-by: Radhey Shyam Pandey --- Changes in v4: - introduce this patch in the patch series Changes in v5: None Changes in v6: - 2/7 was basically redoing what done here. Anticipate here the introduction of a local temporary variable so that 2/7 just add stuff - add dma chan ptr argument to xilinx_calc_cma_copysize() to prepare for 2/7 - introduce max_buffer_len variable in advance, to prepare for 4/7 - reword for above changes --- drivers/dma/xilinx/xilinx_dma.c | 39 ++++++++++++++++++++++++++------- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index c12442312595..2c1db500284f 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -423,6 +423,7 @@ struct xilinx_dma_config { * @rxs_clk: DMA s2mm stream clock * @nr_channels: Number of channels DMA device supports * @chan_id: DMA channel identifier + * @max_buffer_len: Max buffer length */ struct xilinx_dma_device { void __iomem *regs; @@ -442,6 +443,7 @@ struct xilinx_dma_device { struct clk *rxs_clk; u32 nr_channels; u32 chan_id; + u32 max_buffer_len; }; /* Macros */ @@ -957,6 +959,25 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) return 0; } +/** + * xilinx_dma_calc_copysize - Calculate the amount of data to copy + * @chan: Driver specific DMA channel + * @size: Total data that needs to be copied + * @done: Amount of data that has been already copied + * + * Return: Amount of data that has to be copied + */ +static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan, + int size, int done) +{ + size_t copy; + + copy = min_t(size_t, size - done, + chan->xdev->max_buffer_len); + + return copy; +} + /** * xilinx_dma_tx_status - Get DMA transaction status * @dchan: DMA channel @@ -990,7 +1011,7 @@ static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan, list_for_each_entry(segment, &desc->segments, node) { hw = &segment->hw; residue += (hw->control - hw->status) & - XILINX_DMA_MAX_TRANS_LEN; + chan->xdev->max_buffer_len; } } spin_unlock_irqrestore(&chan->lock, flags); @@ -1250,7 +1271,7 @@ static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan) /* Start the transfer */ dma_ctrl_write(chan, XILINX_DMA_REG_BTT, - hw->control & XILINX_DMA_MAX_TRANS_LEN); + hw->control & chan->xdev->max_buffer_len); } list_splice_tail_init(&chan->pending_list, &chan->active_list); @@ -1353,7 +1374,7 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) /* Start the transfer */ dma_ctrl_write(chan, XILINX_DMA_REG_BTT, - hw->control & XILINX_DMA_MAX_TRANS_LEN); + hw->control & chan->xdev->max_buffer_len); } list_splice_tail_init(&chan->pending_list, &chan->active_list); @@ -1714,7 +1735,7 @@ xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst, struct xilinx_cdma_tx_segment *segment; struct xilinx_cdma_desc_hw *hw; - if (!len || len > XILINX_DMA_MAX_TRANS_LEN) + if (!len || len > chan->xdev->max_buffer_len) return NULL; desc = xilinx_dma_alloc_tx_descriptor(chan); @@ -1804,8 +1825,8 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( * Calculate the maximum number of bytes to transfer, * making sure it is less than the hw limit */ - copy = min_t(size_t, sg_dma_len(sg) - sg_used, - XILINX_DMA_MAX_TRANS_LEN); + copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg), + sg_used); hw = &segment->hw; /* Fill in the descriptor */ @@ -1909,8 +1930,8 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( * Calculate the maximum number of bytes to transfer, * making sure it is less than the hw limit */ - copy = min_t(size_t, period_len - sg_used, - XILINX_DMA_MAX_TRANS_LEN); + copy = xilinx_dma_calc_copysize(chan, period_len, + sg_used); hw = &segment->hw; xilinx_axidma_buf(chan, hw, buf_addr, sg_used, period_len * i); @@ -2624,6 +2645,8 @@ static int xilinx_dma_probe(struct platform_device *pdev) /* Retrieve the DMA engine properties from the device tree */ xdev->has_sg = of_property_read_bool(node, "xlnx,include-sg"); + xdev->max_buffer_len = XILINX_DMA_MAX_TRANS_LEN; + if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) xdev->mcdma = of_property_read_bool(node, "xlnx,mcdma"); From patchwork Tue Nov 20 15:31:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Merello X-Patchwork-Id: 10690507 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6850D5A4 for ; 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Tue, 20 Nov 2018 07:32:00 -0800 (PST) Received: from NewMoon.iit.local ([90.147.180.254]) by smtp.gmail.com with ESMTPSA id k73sm14677464wmd.36.2018.11.20.07.31.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Nov 2018 07:31:59 -0800 (PST) From: Andrea Merello To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello Subject: [PATCH v6 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cyclic mode align split descriptors Date: Tue, 20 Nov 2018 16:31:46 +0100 Message-Id: <20181120153151.18024-2-andrea.merello@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181120153151.18024-1-andrea.merello@gmail.com> References: <20181120153151.18024-1-andrea.merello@gmail.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Whenever a single or cyclic transaction is prepared, the driver could eventually split it over several SG descriptors in order to deal with the HW maximum transfer length. This could end up in DMA operations starting from a misaligned address. This seems fatal for the HW if DRE (Data Realignment Engine) is not enabled. This patch eventually adjusts the transfer size in order to make sure all operations start from an aligned address. Cc: Radhey Shyam Pandey Signed-off-by: Andrea Merello Reviewed-by: Radhey Shyam Pandey --- Changes in v2: - don't introduce copy_mask field, rather rely on already-esistent copy_align field. Suggested by Radhey Shyam Pandey - reword title Changes in v3: - fix bug introduced in v2: wrong copy size when DRE is enabled - use implementation suggested by Radhey Shyam Pandey Changes in v4: - rework on the top of 1/6 Changes in v5: - fix typo in commit title - add hint about "DRE" meaning in commit message Changes in v6: None --- drivers/dma/xilinx/xilinx_dma.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 2c1db500284f..cbf34dd5e966 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -975,6 +975,15 @@ static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan, copy = min_t(size_t, size - done, chan->xdev->max_buffer_len); + if ((copy + done < size) && + chan->xdev->common.copy_align) { + /* + * If this is not the last descriptor, make sure + * the next one will be properly aligned + */ + copy = rounddown(copy, + (1 << chan->xdev->common.copy_align)); + } return copy; } From patchwork Tue Nov 20 15:31:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Merello X-Patchwork-Id: 10690519 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 82BDF5A4 for ; Tue, 20 Nov 2018 15:32:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 728442A9BC for ; Tue, 20 Nov 2018 15:32:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 670D02A9C1; Tue, 20 Nov 2018 15:32:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F24B52A9BC for ; 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Tue, 20 Nov 2018 07:32:00 -0800 (PST) From: Andrea Merello To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello Subject: [PATCH v6 3/7] dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property Date: Tue, 20 Nov 2018 16:31:47 +0100 Message-Id: <20181120153151.18024-3-andrea.merello@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181120153151.18024-1-andrea.merello@gmail.com> References: <20181120153151.18024-1-andrea.merello@gmail.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The width of the "length register" cannot be autodetected, and it is now specified with a DT property. Add documentation for it. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Radhey Shyam Pandey Signed-off-by: Andrea Merello Reviewed-by: Radhey Shyam Pandey --- Changes in v2: - change property name - property is now optional - cc DT maintainer Changes in v3: - reword - cc DT maintainerS and ML Changes in v4: - specify the unit, the valid range and the default value Changes in v5: - commit message trivial fix - fix spaces before tab Changes in v6: None --- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index 174af2c45e77..2fce9fb4b270 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -41,6 +41,10 @@ Optional properties: - xlnx,include-sg: Tells configured for Scatter-mode in the hardware. Optional properties for AXI DMA: +- xlnx,sg-length-width: Should be set to the width in bits of the length + register as configured in h/w. Takes values {8...26}. If the property + is missing or invalid then the default value 23 is used. This is the + maximum value that is supported by all IP versions. - xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware. Optional properties for VDMA: - xlnx,flush-fsync: Tells which channel to Flush on Frame sync. From patchwork Tue Nov 20 15:31:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Merello X-Patchwork-Id: 10690515 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 69DD813BB for ; Tue, 20 Nov 2018 15:32:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 572AA2A9BC for ; Tue, 20 Nov 2018 15:32:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4B2E02A9C0; Tue, 20 Nov 2018 15:32:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D924A2A9BC for ; Tue, 20 Nov 2018 15:32:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729972AbeKUCBs (ORCPT ); Tue, 20 Nov 2018 21:01:48 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:34931 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727135AbeKUCBr (ORCPT ); Tue, 20 Nov 2018 21:01:47 -0500 Received: by mail-wr1-f68.google.com with SMTP id 96so2446966wrb.2; Tue, 20 Nov 2018 07:32:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=U3HtB1h2/lHtTg364lrXafsr/nzN6yNozC0bkfvryl0=; b=Jp6+I9UL6fZUPtWifOERCwRWNAfY/Ap/iNphhSwsVZimOFSCCdkczHJLN77MyNy1wV BSiwmQpeZmgGs4iDuu2V3U5NUoFBEZbEt/RkVSFMPY5kxPFDNNyDqIAed7/aVPeh/Kbf xXJPsJe5GXwfueOUP+MaL97MsZmDgDGKS5P7ZhRMFHzrrS6xDcfZ0l/A9izHkEoDyArM PhZSaeZQzOqlJx+cugUNSN/IPGLUh8DlOJC9xDAI0MvKcEAWrwucQVcQC9mKxjoFM7Ms bXLFbdP0ePYc8tRnwj/NdKHwdbGDK3aHFMdoA65SqX0KiN2kC1O+ZGZjq9Z9BZU7D+kV //fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=U3HtB1h2/lHtTg364lrXafsr/nzN6yNozC0bkfvryl0=; b=c4LLmdctqEX3jifzB3lG1RPHh16loHBIm28p7TuGAK91COXuwHZJrrcH0no8aqXiVX Dn3w/XZi6hZOgy10JuwhvAHkY5ZQfVIV/f49JsyLikI/CzGf26wuR+/Z7ZiNrEqhhcvj vBK1xe4/7dcU9xnIP6gyIsXd+xP3Z5F0RrMb6fuaO2ioJNmNKeabFWpSjAWWjmPSCTPQ ktWmcoI7lmsuuNYU7kPbfiMrQqJyhppSIo024c2BQuxRRQQuzpCN+CXmMX3dy7MNELfF Z4t8AJhvNUzmwDaFaf2qeLhfyiiUN4lQAMIQIZxpE8GfExDqGTb3dvotEAW1cSVIyXQ+ P6TQ== X-Gm-Message-State: AA+aEWY5E/OsNz1at50hELTHc/iMFvYguxuU3KQKEW9vhyC4l/FIJZnd Q9mXKYC6dCp0YU8juEOG+JY= X-Google-Smtp-Source: AFSGD/U5qoC92UUHdd/fRWqc0u8ijQVJRFvvOSjTWugbhWVf+Gr9OU2wnD7B7e6Iz3IcfeVuZN8yBQ== X-Received: by 2002:adf:c189:: with SMTP id x9-v6mr2475813wre.233.1542727923400; Tue, 20 Nov 2018 07:32:03 -0800 (PST) Received: from NewMoon.iit.local ([90.147.180.254]) by smtp.gmail.com with ESMTPSA id k73sm14677464wmd.36.2018.11.20.07.32.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Nov 2018 07:32:02 -0800 (PST) From: Andrea Merello To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello Subject: [PATCH v6 4/7] dmaengine: xilinx_dma: program hardware supported buffer length Date: Tue, 20 Nov 2018 16:31:48 +0100 Message-Id: <20181120153151.18024-4-andrea.merello@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181120153151.18024-1-andrea.merello@gmail.com> References: <20181120153151.18024-1-andrea.merello@gmail.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Radhey Shyam Pandey AXI-DMA IP supports configurable (c_sg_length_width) buffer length register width, hence read buffer length (xlnx,sg-length-width) DT property and ensure that driver doesn't program buffer length exceeding the supported limit. For VDMA and CDMA there is no change. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Radhey Shyam Pandey Signed-off-by: Michal Simek Signed-off-by: Andrea Merello [rebase, reword] --- Changes in v2: - drop original patch and replace with the one in Xilinx tree Changes in v3: - cc DT maintainers/ML Changes in v4: - upper bound for the property should be 26, not 23 - add warn for width > 23 as per xilinx original patch - rework due to changes introduced in 1/6 Changes in v5: None Changes in v6: None --- drivers/dma/xilinx/xilinx_dma.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index cbf34dd5e966..0716db61f1d0 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -161,7 +161,9 @@ #define XILINX_DMA_REG_BTT 0x28 /* AXI DMA Specific Masks/Bit fields */ -#define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0) +#define XILINX_DMA_MAX_TRANS_LEN_MIN 8 +#define XILINX_DMA_MAX_TRANS_LEN_MAX 23 +#define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26 #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16) #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4) #define XILINX_DMA_CR_COALESCE_SHIFT 16 @@ -2622,7 +2624,7 @@ static int xilinx_dma_probe(struct platform_device *pdev) struct xilinx_dma_device *xdev; struct device_node *child, *np = pdev->dev.of_node; struct resource *io; - u32 num_frames, addr_width; + u32 num_frames, addr_width, len_width; int i, err; /* Allocate and initialize the DMA engine structure */ @@ -2654,10 +2656,24 @@ static int xilinx_dma_probe(struct platform_device *pdev) /* Retrieve the DMA engine properties from the device tree */ xdev->has_sg = of_property_read_bool(node, "xlnx,include-sg"); - xdev->max_buffer_len = XILINX_DMA_MAX_TRANS_LEN; + xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0); - if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) + if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { xdev->mcdma = of_property_read_bool(node, "xlnx,mcdma"); + if (!of_property_read_u32(node, "xlnx,sg-length-width", + &len_width)) { + if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN || + len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) { + dev_warn(xdev->dev, + "invalid xlnx,sg-length-width property value. Using default width\n"); + } else { + if (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX) + dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n"); + xdev->max_buffer_len = + GENMASK(len_width - 1, 0); + } + } + } if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { err = of_property_read_u32(node, "xlnx,num-fstores", From patchwork Tue Nov 20 15:31:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Merello X-Patchwork-Id: 10690517 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A02405A4 for ; Tue, 20 Nov 2018 15:32:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8E5862A9BE for ; Tue, 20 Nov 2018 15:32:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 828962A9BC; Tue, 20 Nov 2018 15:32:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 040222A9BC for ; Tue, 20 Nov 2018 15:32:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726208AbeKUCCF (ORCPT ); Tue, 20 Nov 2018 21:02:05 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:41273 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725898AbeKUCBr (ORCPT ); Tue, 20 Nov 2018 21:01:47 -0500 Received: by mail-wr1-f68.google.com with SMTP id x10so2421587wrs.8; Tue, 20 Nov 2018 07:32:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=E4uDeGcHjS28m8Y3GVEAHI2k3FFYlV0squiBOxB4Zjo=; b=AsPYakNhleTtSFGYfr0/v67a68rWA3Vc+aszgL11cX7RURvBlC98QyB8M1ZBql69ik 6DgOp7SOUXSIuk5DvA4XP1IlogC4PgiJ8kL7alI9ZDayEMSIYGDfXfa2ASQJg8B2QLEs tBUIft3AYZo/BsVa3qXT1BeETsqUgQEJ4HZk/7sMWfihPBlQ9ul3q10wnOJlO+INh3S8 xc5zG/xV2WyOTkhXw+XMzo6HoA26hkLey40WbqQboha0ohsbYvSLuW4XYR0XmGfs5R9d RNK7Q0hGwb+vkC4IMUQi8x8sDc2AxmalHNk3N9lod/QaDIxBuzaVwod2ASQloeyGZq+0 Mu0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=E4uDeGcHjS28m8Y3GVEAHI2k3FFYlV0squiBOxB4Zjo=; b=EaJOWQFcXDQjkWxwRqjC2UNBu1vmqNRjkaayg32xdU/7x18Wnxhfpc6P0xhMhiXlOq XX0s+XD1+i/JST2tCweaELrVkoFEVwEZ/pgNxB7ROLhX1sDkB0m4T5e/0GKTR3680uFc qbZZ2kPu7EMoDpDC1jq2ffSiBVpxUMo3xuXGhek4GV9qMEtP+hcH4flON2mZDzFUOX6x +PgtJUlUEY3Gio4xkzlb8XmAPUfrPBWY4vFImnnohqpoIA0mwgtO0qzhKwj3Ccr9Dfqd 4MnErG9sPR5bN/P4myZsWIdCt8WfPFtX278og39KOEYYwzXO0cEXEEr8FfRhNSRO2qhf 1j3g== X-Gm-Message-State: AA+aEWYCRAgs/JENWsfCGIxC8AltfGo5rgzCdTH7IWjh0eGwlqXV7W+9 ZysjT8upRC4GzCb8N7JC1FrUiGN8/ro= X-Google-Smtp-Source: AFSGD/XsZx4gvLXbkKc1j/8nTLN3FH77y46lBJnwpByol4szNCvTAAlgvgFsSi1VnH5oiExqfFDQrQ== X-Received: by 2002:a5d:66c1:: with SMTP id k1mr2354209wrw.132.1542727924627; Tue, 20 Nov 2018 07:32:04 -0800 (PST) Received: from NewMoon.iit.local ([90.147.180.254]) by smtp.gmail.com with ESMTPSA id k73sm14677464wmd.36.2018.11.20.07.32.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Nov 2018 07:32:04 -0800 (PST) From: Andrea Merello To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello Subject: [PATCH v6 5/7] dmaengine: xilinx_dma: autodetect whether the HW supports scatter-gather Date: Tue, 20 Nov 2018 16:31:49 +0100 Message-Id: <20181120153151.18024-5-andrea.merello@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181120153151.18024-1-andrea.merello@gmail.com> References: <20181120153151.18024-1-andrea.merello@gmail.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The AXIDMA and CDMA HW can be either direct-access or scatter-gather version. These are SW incompatible. The driver can handle both versions: a DT property was used to tell the driver whether to assume the HW is in scatter-gather mode. This patch makes the driver to autodetect this information. The DT property is not required anymore. No changes for VDMA. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Radhey Shyam Pandey Signed-off-by: Andrea Merello Reviewed-by: Radhey Shyam Pandey --- Changes in v2: - autodetect only in !VDMA case Changes in v3: - cc DT maintainers/ML Changes in v4: - fix typos in commit message Changes in v5: None Changes in v6: None --- drivers/dma/xilinx/xilinx_dma.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 0716db61f1d0..41bd8caca09e 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -86,6 +86,7 @@ #define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6) #define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5) #define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4) +#define XILINX_DMA_DMASR_SG_MASK BIT(3) #define XILINX_DMA_DMASR_IDLE BIT(1) #define XILINX_DMA_DMASR_HALTED BIT(0) #define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24) @@ -412,7 +413,6 @@ struct xilinx_dma_config { * @dev: Device Structure * @common: DMA device structure * @chan: Driver specific DMA channel - * @has_sg: Specifies whether Scatter-Gather is present or not * @mcdma: Specifies whether Multi-Channel is present or not * @flush_on_fsync: Flush on frame sync * @ext_addr: Indicates 64 bit addressing is supported by dma device @@ -432,7 +432,6 @@ struct xilinx_dma_device { struct device *dev; struct dma_device common; struct xilinx_dma_chan *chan[XILINX_DMA_MAX_CHANS_PER_DEVICE]; - bool has_sg; bool mcdma; u32 flush_on_fsync; bool ext_addr; @@ -2417,7 +2416,6 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, chan->dev = xdev->dev; chan->xdev = xdev; - chan->has_sg = xdev->has_sg; chan->desc_pendingcount = 0x0; chan->ext_addr = xdev->ext_addr; /* This variable ensures that descriptors are not @@ -2517,6 +2515,15 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, chan->stop_transfer = xilinx_dma_stop_transfer; } + /* check if SG is enabled (only for AXIDMA and CDMA) */ + if (xdev->dma_config->dmatype != XDMA_TYPE_VDMA) { + if (dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) & + XILINX_DMA_DMASR_SG_MASK) + chan->has_sg = true; + dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id, + chan->has_sg ? "enabled" : "disabled"); + } + /* Initialize the tasklet */ tasklet_init(&chan->tasklet, xilinx_dma_do_tasklet, (unsigned long)chan); @@ -2655,7 +2662,6 @@ static int xilinx_dma_probe(struct platform_device *pdev) return PTR_ERR(xdev->regs); /* Retrieve the DMA engine properties from the device tree */ - xdev->has_sg = of_property_read_bool(node, "xlnx,include-sg"); xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0); if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { From patchwork Tue Nov 20 15:31:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Merello X-Patchwork-Id: 10690511 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DE5FA13BB for ; Tue, 20 Nov 2018 15:32:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CCE332A9BC for ; Tue, 20 Nov 2018 15:32:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BE2DE2A9C0; Tue, 20 Nov 2018 15:32:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B675F2A9BC for ; Tue, 20 Nov 2018 15:32:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730063AbeKUCBt (ORCPT ); Tue, 20 Nov 2018 21:01:49 -0500 Received: from mail-wr1-f65.google.com ([209.85.221.65]:39017 "EHLO mail-wr1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726291AbeKUCBt (ORCPT ); Tue, 20 Nov 2018 21:01:49 -0500 Received: by mail-wr1-f65.google.com with SMTP id b13so2434049wrx.6; Tue, 20 Nov 2018 07:32:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jsZEbtzXddStkl/unoxEn2IHJkwc1Or+BPoxoA+8H3A=; b=Wa8G6QhjCgbGTqH2W8tarvEcnjGMz5zbWAFsdzQGX5fnTdm4nIhf5FsyiyGzWTmyiM 7102qjHPi8R5PqUAfcELqNSXgXNTVIB2qZqnItiwkzl2/KmTtqBhNuMHXVGfFNplqjWk hHc40pebYbkGFAX57D7lAndSxA2gUnmHv+5Ft1ytF9p7CZ5vCGFzDgkTsinF8NnFWlHM pnBDFnMOtaE69VqO7SYu0rKsgcuDKa8fMoo5fb98E2TnGSOXOSGr5wP4l7nuZWWaBbp8 9Xs85xKK3tZyrLRtZ1/S0JRA5S2U0SVuUzI++Ph/Dtgh+3yGYkThX+8k2lPchmu0uRL6 ha6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jsZEbtzXddStkl/unoxEn2IHJkwc1Or+BPoxoA+8H3A=; b=IURFR/ETOQJqedyfsMp0RhsX/2pbxL8YSYI41Se64UtIJQWEMMfzISZHep9vZez+gS GKuJKX5Qdnji9+sLqGitOUSGmv/cllFkxu5oabM5nbDQSgMpGN+KrrNqufiDj2zYKHJE lqanTk5BLp1P5oXixE9f6UMhXh+mpO/gNz0R95k4oa/9q7LaZhFfc8adV1ru+4D7dzqQ zH4vi6iUjMyEGmhUYH0A/jrsyA5S62bHuvS/kG0i21dscXY9Lr1jQPR0rm8GNT5b41A6 UtRXnVYF06ehGwMdyEtvzo08BSH5fUZBTLWQ9JzD/dcuftzEuz7dK1zQqLOt808+MYiQ bX0g== X-Gm-Message-State: AA+aEWYXA5N04Bsh0droowUivHv/I3KQucC0GsGIIt88IRAyN4ivOZLa YTncZjTmzE8xoDVLyxPz5P+GOHBkO+U= X-Google-Smtp-Source: AFSGD/UXkJZ9njMmidYgkjklo6d1AqHtmcoTv7xG13KlDc/a0/+VAH/tOVSP7n2CT4BOdTQH2wWLBg== X-Received: by 2002:adf:ed92:: with SMTP id c18mr2435677wro.194.1542727925804; Tue, 20 Nov 2018 07:32:05 -0800 (PST) Received: from NewMoon.iit.local ([90.147.180.254]) by smtp.gmail.com with ESMTPSA id k73sm14677464wmd.36.2018.11.20.07.32.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Nov 2018 07:32:05 -0800 (PST) From: Andrea Merello To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello Subject: [PATCH v6 6/7] dt-bindings: dmaengine: xilinx_dma: drop include-sg property Date: Tue, 20 Nov 2018 16:31:50 +0100 Message-Id: <20181120153151.18024-6-andrea.merello@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181120153151.18024-1-andrea.merello@gmail.com> References: <20181120153151.18024-1-andrea.merello@gmail.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This property is not needed anymore, because the driver now autodetects it. Delete references in documentation. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Radhey Shyam Pandey Signed-off-by: Andrea Merello Reviewed-by: Radhey Shyam Pandey Reviewed-by: Rob Herring --- Changes in v2: - cc DT maintainer Changes in v3: - cc DT maintainerS/ML Changes in v4: None Changes in v5: None Changes in v6: Fix wrong property name in commit title --- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 3 --- 1 file changed, 3 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index 2fce9fb4b270..93b6d961dd4f 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -37,9 +37,6 @@ Required properties: Required properties for VDMA: - xlnx,num-fstores: Should be the number of framebuffers as configured in h/w. -Optional properties: -- xlnx,include-sg: Tells configured for Scatter-mode in - the hardware. Optional properties for AXI DMA: - xlnx,sg-length-width: Should be set to the width in bits of the length register as configured in h/w. Takes values {8...26}. If the property From patchwork Tue Nov 20 15:31:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Merello X-Patchwork-Id: 10690513 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 03E235A4 for ; Tue, 20 Nov 2018 15:32:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E4C792A9BC for ; Tue, 20 Nov 2018 15:32:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D6F972A9C0; Tue, 20 Nov 2018 15:32:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B0CEF2A9BC for ; Tue, 20 Nov 2018 15:32:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726291AbeKUCBv (ORCPT ); Tue, 20 Nov 2018 21:01:51 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:36129 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727135AbeKUCBu (ORCPT ); Tue, 20 Nov 2018 21:01:50 -0500 Received: by mail-wr1-f67.google.com with SMTP id t3so2438827wrr.3; Tue, 20 Nov 2018 07:32:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4+qTUQgVrsH5WGyEnsnG2mHJoSQ0/3Ge4pcP7YNht8U=; b=ogB5lTFm7ZuZs4T50gjUg2yDDGIPay8vvwV4v8zHR8hLzsIjlFfzY684jd2+fDPIlN F6cC1RahcN/1utSO8sA6OwXEkpDJMhrLQqOK/ZejNh6jBtaqgwfJln5h39qk79BBw/IR mKOQXspeOWZRs+g4CwCZAroV7+ZrFvCZ4Pxaqfls6S6wQZbD6b0blGaatKxch0UgE5G3 TFf4BE6swiFxeX/hCrpNkMiDnK9lH4BK9jVzH+kAokmSO0gPVhY14XH4SWRm13EJEyRU j8e41l/AbH4jZIjK4m/+ABI2Z/GezqHGeOh7w1kMXJx0zjV53e25rPmDHraWFrJl4j9t Sp0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4+qTUQgVrsH5WGyEnsnG2mHJoSQ0/3Ge4pcP7YNht8U=; b=RH6EEQecYFyfXS8iyzeanD+WcwPKPWNhyWn5lXujBoG8/zVWv1v2D6udwuv7SJ2u++ spGJRQB3okfKx09qTxOEhZwaWpnsQeWJnL9eJwBQfIEow71zIDYzOfDjNSQ7aNXlOjia dSDZNOel9WhwvaRC+Q1mP8thX1PrFIiQxZhAMpQFQ4SVVOAiQ23+nVScIUOi564B2Beu FMGk4/yy44zVKwLr+ibC++mq0/ZsyHWyUG9BzGrFG48iGIZHqKncI40Rp9x18uKueKDv LOCCZz3lb/5dKZYNebjk6FuhHBZ4J7javRy1mlB8dikNjNzozYEMUZQJm5+ffz1NTWvI Tieg== X-Gm-Message-State: AA+aEWZYc04r429ojswiy7ZKi+d8WcINtK19IlvlEJksvkJ7oZmAEFbq jJhFay5nAfbbEJQVVMv83z8= X-Google-Smtp-Source: AFSGD/Wgwqu4mZOeo6gWd7BZixfMYcxFMWc9tWShv/oee9CWwCkPYGUBgcnI3b5OjnzuVxoG4r1i0A== X-Received: by 2002:adf:9cc2:: with SMTP id h2-v6mr2536834wre.322.1542727927050; Tue, 20 Nov 2018 07:32:07 -0800 (PST) Received: from NewMoon.iit.local ([90.147.180.254]) by smtp.gmail.com with ESMTPSA id k73sm14677464wmd.36.2018.11.20.07.32.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Nov 2018 07:32:06 -0800 (PST) From: Andrea Merello To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello Subject: [PATCH v6 7/7] dmaengine: xilinx_dma: Drop SG support for VDMA IP Date: Tue, 20 Nov 2018 16:31:51 +0100 Message-Id: <20181120153151.18024-7-andrea.merello@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181120153151.18024-1-andrea.merello@gmail.com> References: <20181120153151.18024-1-andrea.merello@gmail.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP xilinx_vdma_start_transfer() is used only for VDMA IP, still it contains conditional code on has_sg variable. has_sg is set only whenever the HW does support SG mode, that is never true for VDMA IP. This patch drops the never-taken branches. Signed-off-by: Andrea Merello Reviewed-by: Radhey Shyam Pandey --- Changes in V4: introduced this patch in series Changes in v5: None Changes in v6: None --- drivers/dma/xilinx/xilinx_dma.c | 84 +++++++++++++-------------------- 1 file changed, 32 insertions(+), 52 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 41bd8caca09e..a37e28a43885 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1100,6 +1100,8 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) struct xilinx_dma_tx_descriptor *desc, *tail_desc; u32 reg, j; struct xilinx_vdma_tx_segment *tail_segment; + struct xilinx_vdma_tx_segment *segment, *last = NULL; + int i = 0; /* This function was invoked with lock held */ if (chan->err) @@ -1119,14 +1121,6 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) tail_segment = list_last_entry(&tail_desc->segments, struct xilinx_vdma_tx_segment, node); - /* - * If hardware is idle, then all descriptors on the running lists are - * done, start new transfers - */ - if (chan->has_sg) - dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC, - desc->async_tx.phys); - /* Configure the hardware using info in the config structure */ if (chan->has_vflip) { reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP); @@ -1143,15 +1137,11 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) else reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN; - /* - * With SG, start with circular mode, so that BDs can be fetched. - * In direct register mode, if not parking, enable circular mode - */ - if (chan->has_sg || !config->park) - reg |= XILINX_DMA_DMACR_CIRC_EN; - + /* If not parking, enable circular mode */ if (config->park) reg &= ~XILINX_DMA_DMACR_CIRC_EN; + else + reg |= XILINX_DMA_DMACR_CIRC_EN; dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); @@ -1173,48 +1163,38 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) return; /* Start the transfer */ - if (chan->has_sg) { - dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC, - tail_segment->phys); - list_splice_tail_init(&chan->pending_list, &chan->active_list); - chan->desc_pendingcount = 0; - } else { - struct xilinx_vdma_tx_segment *segment, *last = NULL; - int i = 0; - - if (chan->desc_submitcount < chan->num_frms) - i = chan->desc_submitcount; - - list_for_each_entry(segment, &desc->segments, node) { - if (chan->ext_addr) - vdma_desc_write_64(chan, - XILINX_VDMA_REG_START_ADDRESS_64(i++), - segment->hw.buf_addr, - segment->hw.buf_addr_msb); - else - vdma_desc_write(chan, + if (chan->desc_submitcount < chan->num_frms) + i = chan->desc_submitcount; + + list_for_each_entry(segment, &desc->segments, node) { + if (chan->ext_addr) + vdma_desc_write_64(chan, + XILINX_VDMA_REG_START_ADDRESS_64(i++), + segment->hw.buf_addr, + segment->hw.buf_addr_msb); + else + vdma_desc_write(chan, XILINX_VDMA_REG_START_ADDRESS(i++), segment->hw.buf_addr); - last = segment; - } - - if (!last) - return; + last = segment; + } - /* HW expects these parameters to be same for one transaction */ - vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); - vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, - last->hw.stride); - vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); + if (!last) + return; - chan->desc_submitcount++; - chan->desc_pendingcount--; - list_del(&desc->node); - list_add_tail(&desc->node, &chan->active_list); - if (chan->desc_submitcount == chan->num_frms) - chan->desc_submitcount = 0; - } + /* HW expects these parameters to be same for one transaction */ + vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); + vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, + last->hw.stride); + vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); + + chan->desc_submitcount++; + chan->desc_pendingcount--; + list_del(&desc->node); + list_add_tail(&desc->node, &chan->active_list); + if (chan->desc_submitcount == chan->num_frms) + chan->desc_submitcount = 0; chan->idle = false; }