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Wysocki" , Viresh Kumar , Nishanth Menon , "Stephen Boyd" , Liam Girdwood , Mark Brown CC: , , , , , , "Saravana Kannan" , Sibi Sankar , Andrew-sh.Cheng Subject: [PATCH V8 1/8] PM / devfreq: Add cpu based scaling support to passive_governor Date: Tue, 23 Mar 2021 19:33:54 +0800 Message-ID: <1616499241-4906-2-git-send-email-andrew-sh.cheng@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1616499241-4906-1-git-send-email-andrew-sh.cheng@mediatek.com> References: <1616499241-4906-1-git-send-email-andrew-sh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210323_113417_972894_5CB5F216 X-CRM114-Status: GOOD ( 30.05 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: Saravana Kannan Many CPU architectures have caches that can scale independent of the CPUs. Frequency scaling of the caches is necessary to make sure that the cache is not a performance bottleneck that leads to poor performance and power. The same idea applies for RAM/DDR. To achieve this, this patch adds support for cpu based scaling to the passive governor. This is accomplished by taking the current frequency of each CPU frequency domain and then adjust the frequency of the cache (or any devfreq device) based on the frequency of the CPUs. It listens to CPU frequency transition notifiers to keep itself up to date on the current CPU frequency. To decide the frequency of the device, the governor does one of the following: * Derives the optimal devfreq device opp from required-opps property of the parent cpu opp_table. * Scales the device frequency in proportion to the CPU frequency. So, if the CPUs are running at their max frequency, the device runs at its max frequency. If the CPUs are running at their min frequency, the device runs at its min frequency. It is interpolated for frequencies in between. Andrew-sh.Cheng change dev_pm_opp_xlate_opp to dev_pm_opp_xlate_required_opp devfreq->max_freq to devfreq->user_min_freq_req.data.freq.qos->min_freq.target_value after kernel-5.7 Don't return -EINVAL in devfreq_passive_event_handler() since it doesn't handle DEVFREQ_GOV_SUSPEND DEVFREQ_GOV_RESUME cases. Signed-off-by: Saravana Kannan [Sibi: Integrated cpu-freqmap governor into passive_governor] Signed-off-by: Sibi Sankar Signed-off-by: Andrew-sh.Cheng --- drivers/devfreq/Kconfig | 2 + drivers/devfreq/governor_passive.c | 329 +++++++++++++++++++++++++++++++++++-- include/linux/devfreq.h | 29 +++- 3 files changed, 342 insertions(+), 18 deletions(-) diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index 00704efe6398..f56132b0ae64 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -73,6 +73,8 @@ config DEVFREQ_GOV_PASSIVE device. This governor does not change the frequency by itself through sysfs entries. The passive governor recommends that devfreq device uses the OPP table to get the frequency/voltage. + Alternatively the governor can also be chosen to scale based on + the online CPUs current frequency. comment "DEVFREQ Drivers" diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_passive.c index b094132bd20b..9cc57b083839 100644 --- a/drivers/devfreq/governor_passive.c +++ b/drivers/devfreq/governor_passive.c @@ -8,11 +8,103 @@ */ #include +#include +#include +#include #include #include +#include #include "governor.h" -static int devfreq_passive_get_target_freq(struct devfreq *devfreq, +struct devfreq_cpu_state { + unsigned int curr_freq; + unsigned int min_freq; + unsigned int max_freq; + unsigned int first_cpu; + struct device *cpu_dev; + struct opp_table *opp_table; +}; + +static unsigned long xlate_cpufreq_to_devfreq(struct devfreq_passive_data *data, + unsigned int cpu) +{ + unsigned int cpu_min_freq, cpu_max_freq, cpu_curr_freq_khz, cpu_percent; + unsigned long dev_min_freq, dev_max_freq, dev_max_state; + + struct devfreq_cpu_state *cpu_state = data->cpu_state[cpu]; + struct devfreq *devfreq = (struct devfreq *)data->this; + unsigned long *dev_freq_table = devfreq->profile->freq_table; + struct dev_pm_opp *opp = NULL, *p_opp = NULL; + unsigned long cpu_curr_freq, freq; + + if (!cpu_state || cpu_state->first_cpu != cpu || + !cpu_state->opp_table || !devfreq->opp_table) + return 0; + + cpu_curr_freq = cpu_state->curr_freq * 1000; + p_opp = devfreq_recommended_opp(cpu_state->cpu_dev, &cpu_curr_freq, 0); + if (IS_ERR(p_opp)) + return 0; + + opp = dev_pm_opp_xlate_required_opp(cpu_state->opp_table, + devfreq->opp_table, p_opp); + dev_pm_opp_put(p_opp); + + if (!IS_ERR(opp)) { + freq = dev_pm_opp_get_freq(opp); + dev_pm_opp_put(opp); + goto out; + } + + /* Use Interpolation if required opps is not available */ + cpu_min_freq = cpu_state->min_freq; + cpu_max_freq = cpu_state->max_freq; + cpu_curr_freq_khz = cpu_state->curr_freq; + + if (dev_freq_table) { + /* Get minimum frequency according to sorting order */ + dev_max_state = dev_freq_table[devfreq->profile->max_state - 1]; + if (dev_freq_table[0] < dev_max_state) { + dev_min_freq = dev_freq_table[0]; + dev_max_freq = dev_max_state; + } else { + dev_min_freq = dev_max_state; + dev_max_freq = dev_freq_table[0]; + } + } else { + dev_min_freq = dev_pm_qos_read_value(devfreq->dev.parent, + DEV_PM_QOS_MIN_FREQUENCY); + dev_max_freq = dev_pm_qos_read_value(devfreq->dev.parent, + DEV_PM_QOS_MAX_FREQUENCY); + + if (dev_max_freq <= dev_min_freq) + return 0; + } + cpu_percent = ((cpu_curr_freq_khz - cpu_min_freq) * 100) / cpu_max_freq - cpu_min_freq; + freq = dev_min_freq + mult_frac(dev_max_freq - dev_min_freq, cpu_percent, 100); + +out: + return freq; +} + +static int get_target_freq_with_cpufreq(struct devfreq *devfreq, + unsigned long *freq) +{ + struct devfreq_passive_data *p_data = + (struct devfreq_passive_data *)devfreq->data; + unsigned int cpu; + unsigned long target_freq = 0; + + for_each_online_cpu(cpu) + target_freq = max(target_freq, + xlate_cpufreq_to_devfreq(p_data, cpu)); + + *freq = target_freq; + + return 0; +} + +static int get_target_freq_with_devfreq(struct devfreq *devfreq, unsigned long *freq) { struct devfreq_passive_data *p_data @@ -23,14 +115,6 @@ static int devfreq_passive_get_target_freq(struct devfreq *devfreq, int i, count; /* - * If the devfreq device with passive governor has the specific method - * to determine the next frequency, should use the get_target_freq() - * of struct devfreq_passive_data. - */ - if (p_data->get_target_freq) - return p_data->get_target_freq(devfreq, freq); - - /* * If the parent and passive devfreq device uses the OPP table, * get the next frequency by using the OPP table. */ @@ -98,6 +182,37 @@ static int devfreq_passive_get_target_freq(struct devfreq *devfreq, return 0; } +static int devfreq_passive_get_target_freq(struct devfreq *devfreq, + unsigned long *freq) +{ + struct devfreq_passive_data *p_data = + (struct devfreq_passive_data *)devfreq->data; + int ret; + + /* + * If the devfreq device with passive governor has the specific method + * to determine the next frequency, should use the get_target_freq() + * of struct devfreq_passive_data. + */ + if (p_data->get_target_freq) + return p_data->get_target_freq(devfreq, freq); + + switch (p_data->parent_type) { + case DEVFREQ_PARENT_DEV: + ret = get_target_freq_with_devfreq(devfreq, freq); + break; + case CPUFREQ_PARENT_DEV: + ret = get_target_freq_with_cpufreq(devfreq, freq); + break; + default: + ret = -EINVAL; + dev_err(&devfreq->dev, "Invalid parent type\n"); + break; + } + + return ret; +} + static int devfreq_passive_notifier_call(struct notifier_block *nb, unsigned long event, void *ptr) { @@ -130,16 +245,200 @@ static int devfreq_passive_notifier_call(struct notifier_block *nb, return NOTIFY_DONE; } +static int cpufreq_passive_notifier_call(struct notifier_block *nb, + unsigned long event, void *ptr) +{ + struct devfreq_passive_data *data = + container_of(nb, struct devfreq_passive_data, nb); + struct devfreq *devfreq = (struct devfreq *)data->this; + struct devfreq_cpu_state *cpu_state; + struct cpufreq_freqs *cpu_freq = ptr; + unsigned int curr_freq; + int ret; + + if (event != CPUFREQ_POSTCHANGE || !cpu_freq || + !data->cpu_state[cpu_freq->policy->cpu]) + return 0; + + cpu_state = data->cpu_state[cpu_freq->policy->cpu]; + if (cpu_state->curr_freq == cpu_freq->new) + return 0; + + /* Backup current freq and pre-update cpu state freq*/ + curr_freq = cpu_state->curr_freq; + cpu_state->curr_freq = cpu_freq->new; + + mutex_lock(&devfreq->lock); + ret = update_devfreq(devfreq); + mutex_unlock(&devfreq->lock); + if (ret) { + cpu_state->curr_freq = curr_freq; + dev_err(&devfreq->dev, "Couldn't update the frequency.\n"); + return ret; + } + + return 0; +} + +static int cpufreq_passive_register(struct devfreq_passive_data **p_data) +{ + struct devfreq_passive_data *data = *p_data; + struct devfreq *devfreq = (struct devfreq *)data->this; + struct device *dev = devfreq->dev.parent; + struct opp_table *opp_table = NULL; + struct devfreq_cpu_state *cpu_state; + struct cpufreq_policy *policy; + struct device *cpu_dev; + unsigned int cpu; + int ret; + + get_online_cpus(); + + data->nb.notifier_call = cpufreq_passive_notifier_call; + ret = cpufreq_register_notifier(&data->nb, + CPUFREQ_TRANSITION_NOTIFIER); + if (ret) { + dev_err(dev, "Couldn't register cpufreq notifier.\n"); + data->nb.notifier_call = NULL; + goto out; + } + + /* Populate devfreq_cpu_state */ + for_each_online_cpu(cpu) { + if (data->cpu_state[cpu]) + continue; + + policy = cpufreq_cpu_get(cpu); + if (!policy) { + ret = -EINVAL; + goto out; + } else if (PTR_ERR(policy) == -EPROBE_DEFER) { + ret = -EPROBE_DEFER; + goto out; + } else if (IS_ERR(policy)) { + ret = PTR_ERR(policy); + dev_err(dev, "Couldn't get the cpufreq_poliy.\n"); + goto out; + } + + cpu_state = kzalloc(sizeof(*cpu_state), GFP_KERNEL); + if (!cpu_state) { + ret = -ENOMEM; + goto out; + } + + cpu_dev = get_cpu_device(cpu); + if (!cpu_dev) { + dev_err(dev, "Couldn't get cpu device.\n"); + ret = -ENODEV; + goto out; + } + + opp_table = dev_pm_opp_get_opp_table(cpu_dev); + if (IS_ERR(devfreq->opp_table)) { + ret = PTR_ERR(opp_table); + goto out; + } + + cpu_state->cpu_dev = cpu_dev; + cpu_state->opp_table = opp_table; + cpu_state->first_cpu = cpumask_first(policy->related_cpus); + cpu_state->curr_freq = policy->cur; + cpu_state->min_freq = policy->cpuinfo.min_freq; + cpu_state->max_freq = policy->cpuinfo.max_freq; + data->cpu_state[cpu] = cpu_state; + + cpufreq_cpu_put(policy); + } + +out: + put_online_cpus(); + if (ret) + return ret; + + /* Update devfreq */ + mutex_lock(&devfreq->lock); + ret = update_devfreq(devfreq); + mutex_unlock(&devfreq->lock); + if (ret) + dev_err(dev, "Couldn't update the frequency.\n"); + + return ret; +} + +static int cpufreq_passive_unregister(struct devfreq_passive_data **p_data) +{ + struct devfreq_passive_data *data = *p_data; + struct devfreq_cpu_state *cpu_state; + int cpu; + + if (data->nb.notifier_call) + cpufreq_unregister_notifier(&data->nb, + CPUFREQ_TRANSITION_NOTIFIER); + + for_each_possible_cpu(cpu) { + cpu_state = data->cpu_state[cpu]; + if (cpu_state) { + if (cpu_state->opp_table) + dev_pm_opp_put_opp_table(cpu_state->opp_table); + kfree(cpu_state); + cpu_state = NULL; + } + } + + return 0; +} + +int register_parent_dev_notifier(struct devfreq_passive_data **p_data) +{ + struct notifier_block *nb = &(*p_data)->nb; + int ret = 0; + + switch ((*p_data)->parent_type) { + case DEVFREQ_PARENT_DEV: + nb->notifier_call = devfreq_passive_notifier_call; + ret = devfreq_register_notifier((struct devfreq *)(*p_data)->parent, nb, + DEVFREQ_TRANSITION_NOTIFIER); + break; + case CPUFREQ_PARENT_DEV: + ret = cpufreq_passive_register(p_data); + break; + default: + ret = -EINVAL; + break; + } + return ret; +} + +int unregister_parent_dev_notifier(struct devfreq_passive_data **p_data) +{ + int ret = 0; + + switch ((*p_data)->parent_type) { + case DEVFREQ_PARENT_DEV: + WARN_ON(devfreq_unregister_notifier((struct devfreq *)(*p_data)->parent, + &(*p_data)->nb, + DEVFREQ_TRANSITION_NOTIFIER)); + break; + case CPUFREQ_PARENT_DEV: + cpufreq_passive_unregister(p_data); + break; + default: + ret = -EINVAL; + break; + } + return ret; +} + static int devfreq_passive_event_handler(struct devfreq *devfreq, unsigned int event, void *data) { struct devfreq_passive_data *p_data = (struct devfreq_passive_data *)devfreq->data; struct devfreq *parent = (struct devfreq *)p_data->parent; - struct notifier_block *nb = &p_data->nb; int ret = 0; - if (!parent) + if (p_data->parent_type == DEVFREQ_PARENT_DEV && !parent) return -EPROBE_DEFER; switch (event) { @@ -147,13 +446,11 @@ static int devfreq_passive_event_handler(struct devfreq *devfreq, if (!p_data->this) p_data->this = devfreq; - nb->notifier_call = devfreq_passive_notifier_call; - ret = devfreq_register_notifier(parent, nb, - DEVFREQ_TRANSITION_NOTIFIER); + ret = register_parent_dev_notifier(&p_data); break; + case DEVFREQ_GOV_STOP: - WARN_ON(devfreq_unregister_notifier(parent, nb, - DEVFREQ_TRANSITION_NOTIFIER)); + ret = unregister_parent_dev_notifier(&p_data); break; default: break; diff --git a/include/linux/devfreq.h b/include/linux/devfreq.h index 26ea0850be9b..e0093b7c805c 100644 --- a/include/linux/devfreq.h +++ b/include/linux/devfreq.h @@ -280,6 +280,25 @@ struct devfreq_simple_ondemand_data { #if IS_ENABLED(CONFIG_DEVFREQ_GOV_PASSIVE) /** + * struct devfreq_cpu_state - holds the per-cpu state + * @freq: the current frequency of the cpu. + * @min_freq: the min frequency of the cpu. + * @max_freq: the max frequency of the cpu. + * @first_cpu: the cpumask of the first cpu of a policy. + * @dev: reference to cpu device. + * @opp_table: reference to cpu opp table. + * + * This structure stores the required cpu_state of a cpu. + * This is auto-populated by the governor. + */ +struct devfreq_cpu_state; + +enum devfreq_parent_dev_type { + DEVFREQ_PARENT_DEV, + CPUFREQ_PARENT_DEV, +}; + +/** * struct devfreq_passive_data - ``void *data`` fed to struct devfreq * and devfreq_add_device * @parent: the devfreq instance of parent device. @@ -290,13 +309,15 @@ struct devfreq_simple_ondemand_data { * using governors except for passive governor. * If the devfreq device has the specific method to decide * the next frequency, should use this callback. + * @parent_type: parent type of the device * @this: the devfreq instance of own device. * @nb: the notifier block for DEVFREQ_TRANSITION_NOTIFIER list + * @cpu_state: the state min/max/current frequency of all online cpu's * * The devfreq_passive_data have to set the devfreq instance of parent * device with governors except for the passive governor. But, don't need to - * initialize the 'this' and 'nb' field because the devfreq core will handle - * them. + * initialize the 'this', 'nb' and 'cpu_state' field because the devfreq core + * will handle them. */ struct devfreq_passive_data { /* Should set the devfreq instance of parent device */ @@ -305,9 +326,13 @@ struct devfreq_passive_data { /* Optional callback to decide the next frequency of passvice device */ int (*get_target_freq)(struct devfreq *this, unsigned long *freq); + /* Should set the type of parent device */ + enum devfreq_parent_dev_type parent_type; + /* For passive governor's internal use. Don't need to set them */ struct devfreq *this; struct notifier_block nb; + struct devfreq_cpu_state *cpu_state[NR_CPUS]; }; #endif From patchwork Tue Mar 23 11:33:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "andrew-sh.cheng" X-Patchwork-Id: 12157421 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6145DC433C1 for ; Tue, 23 Mar 2021 11:34:42 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CA1C0619A9 for ; Tue, 23 Mar 2021 11:34:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CA1C0619A9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=JRL3oj8xYUV0bk3tKr+vAHjjj89M4dpLMgps5K1GVX4=; b=qBcetosiJpEFDQPbP5DsgnqLF exDEpgyBwUlIwEYB/mro70+G2QfnxoErCcchLGXxIWFhFc+7SEjlY0CKma7Qst7jdwvjI0KlnG+y9 1fj09Bn5RacRrgoMLFMWKK51FrHKRwxDcpsDbXxprg0dbP+rtazs79afxv6ax69BdpoyQ8JsV9qrf cndVcauL3r0Awe/CKzI7bFd1S4d1bReAx+ZbPXezKz9h/fbSg6D3Vtj4sV4rqtyzVJ5zsypcPWXl3 qe7wtKKIWl+YEqo0uOihrrCcTKnkF+t5xdYeo+gxicZcjigiuz2yVe0rZa9GG/5W57mu6axlbbZhf qJVrnTtYQ==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lOfIl-00Eiau-MQ; Tue, 23 Mar 2021 11:34:23 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lOfId-00EiXm-Kr; Tue, 23 Mar 2021 11:34:19 +0000 X-UUID: 8648e9a103ae4d65a854e06d24fcf66d-20210323 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=VUjEKEUOSLh//gC0dXPpk/7IKS2KMuv+5PyRzSyK4Ts=; b=fnOc3fWb6EWxa5XEtJEU/rJ1ugh4hAn51fxnkjrOzUAN4NPx23exci147WWJ6ZQ0DwiP9FTDRnjMjfX2AuRlyusXQQWGhbmig/FhLyyjQyXIkx1fvFRhKqeHo7fNTlWCgvT/+3zeaBoLoZbJLkIR7flG+XyNW2/xCdVmEjgSAZw=; X-UUID: 8648e9a103ae4d65a854e06d24fcf66d-20210323 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 804033606; Tue, 23 Mar 2021 03:34:07 -0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Mar 2021 04:34:06 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Mar 2021 19:34:04 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 23 Mar 2021 19:34:04 +0800 From: Andrew-sh.Cheng To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , "Rob Herring" , Mark Rutland , "Matthias Brugger" , "Rafael J. Wysocki" , Viresh Kumar , Nishanth Menon , "Stephen Boyd" , Liam Girdwood , Mark Brown CC: , , , , , , Andrew-sh.Cheng Subject: [PATCH V8 2/8] cpufreq: mediatek: Enable clock and regulator Date: Tue, 23 Mar 2021 19:33:55 +0800 Message-ID: <1616499241-4906-3-git-send-email-andrew-sh.cheng@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1616499241-4906-1-git-send-email-andrew-sh.cheng@mediatek.com> References: <1616499241-4906-1-git-send-email-andrew-sh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210323_113416_229909_8DA97D61 X-CRM114-Status: GOOD ( 14.05 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: "Andrew-sh.Cheng" Need to enable regulator, so that the max/min requested value will be recorded even it is not applied right away. Intermediate clock is not always enabled by ccf in different projects, so cpufreq should enable it by itself. Signed-off-by: Andrew-sh.Cheng --- drivers/cpufreq/mediatek-cpufreq.c | 33 +++++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index f2e491b25b07..432368707ea6 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -350,6 +350,11 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) ret = PTR_ERR(proc_reg); goto out_free_resources; } + ret = regulator_enable(proc_reg); + if (ret) { + pr_warn("enable vproc for cpu%d fail\n", cpu); + goto out_free_resources; + } /* Both presence and absence of sram regulator are valid cases. */ sram_reg = regulator_get_exclusive(cpu_dev, "sram"); @@ -368,13 +373,21 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) goto out_free_resources; } + ret = clk_prepare_enable(cpu_clk); + if (ret) + goto out_free_opp_table; + + ret = clk_prepare_enable(inter_clk); + if (ret) + goto out_disable_mux_clock; + /* Search a safe voltage for intermediate frequency. */ rate = clk_get_rate(inter_clk); opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); if (IS_ERR(opp)) { pr_err("failed to get intermediate opp for cpu%d\n", cpu); ret = PTR_ERR(opp); - goto out_free_opp_table; + goto out_disable_inter_clock; } info->intermediate_voltage = dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); @@ -393,6 +406,12 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) return 0; +out_disable_inter_clock: + clk_disable_unprepare(inter_clk); + +out_disable_mux_clock: + clk_disable_unprepare(cpu_clk); + out_free_opp_table: dev_pm_opp_of_cpumask_remove_table(&info->cpus); @@ -411,14 +430,20 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info) { - if (!IS_ERR(info->proc_reg)) + if (!IS_ERR(info->proc_reg)) { + regulator_disable(info->proc_reg); regulator_put(info->proc_reg); + } if (!IS_ERR(info->sram_reg)) regulator_put(info->sram_reg); - if (!IS_ERR(info->cpu_clk)) + if (!IS_ERR(info->cpu_clk)) { + clk_disable_unprepare(info->cpu_clk); clk_put(info->cpu_clk); - if (!IS_ERR(info->inter_clk)) + } + if (!IS_ERR(info->inter_clk)) { + clk_disable_unprepare(info->inter_clk); clk_put(info->inter_clk); + } dev_pm_opp_of_cpumask_remove_table(&info->cpus); } From patchwork Tue Mar 23 11:33:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "andrew-sh.cheng" X-Patchwork-Id: 12157423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB1A7C433C1 for ; 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Tue, 23 Mar 2021 19:34:05 +0800 From: Andrew-sh.Cheng To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , "Rob Herring" , Mark Rutland , "Matthias Brugger" , "Rafael J. Wysocki" , Viresh Kumar , Nishanth Menon , "Stephen Boyd" , Liam Girdwood , Mark Brown CC: , , , , , , Andrew-sh.Cheng Subject: [PATCH V8 3/8] dt-bindings: devfreq: add compatible for mt8183 cci devfreq Date: Tue, 23 Mar 2021 19:33:56 +0800 Message-ID: <1616499241-4906-4-git-send-email-andrew-sh.cheng@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1616499241-4906-1-git-send-email-andrew-sh.cheng@mediatek.com> References: <1616499241-4906-1-git-send-email-andrew-sh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210323_113417_246169_89E38DDF X-CRM114-Status: GOOD ( 14.30 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: "Andrew-sh.Cheng" This adds dt-binding documentation of cci devfreq for Mediatek MT8183 SoC platform. Signed-off-by: Andrew-sh.Cheng --- .../devicetree/bindings/devfreq/mt8183-cci.yaml | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/devfreq/mt8183-cci.yaml diff --git a/Documentation/devicetree/bindings/devfreq/mt8183-cci.yaml b/Documentation/devicetree/bindings/devfreq/mt8183-cci.yaml new file mode 100644 index 000000000000..a7341fd94097 --- /dev/null +++ b/Documentation/devicetree/bindings/devfreq/mt8183-cci.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/devfreq/mt8183-cci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CCI_DEVFREQ driver for MT8183. + +maintainers: + - Andrew-sh.Cheng + +description: | + This module is used to create CCI DEVFREQ. + The performance will depend on both CCI frequency and CPU frequency. + For MT8183, CCI co-buck with Little core. + Contain CCI opp table for voltage and frequency scaling. + +properties: + compatible: + const: "mediatek,mt8183-cci" + + clocks: + maxItems: 1 + + clock-names: + const: "cci" + + operating-points-v2: true + opp-table: true + + proc-supply: + description: + Phandle of the regulator that provides the supply voltage. + +required: + - compatible + - clocks + - clock-names + - proc-supply + +examples: + - | + #include + cci: cci { + compatible = "mediatek,mt8183-cci"; + clocks = <&apmixedsys CLK_APMIXED_CCIPLL>; + clock-names = "cci"; + operating-points-v2 = <&cci_opp>; + proc-supply = <&mt6358_vproc12_reg>; + }; + From patchwork Tue Mar 23 11:33:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "andrew-sh.cheng" X-Patchwork-Id: 12157435 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 848C2C433C1 for ; Tue, 23 Mar 2021 11:35:53 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 14FCB619A9 for ; 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Tue, 23 Mar 2021 03:34:08 -0800 Received: from mtkmbs05n1.mediatek.inc (172.21.101.15) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Mar 2021 04:34:08 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Mar 2021 19:34:06 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 23 Mar 2021 19:34:06 +0800 From: Andrew-sh.Cheng To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , "Rob Herring" , Mark Rutland , "Matthias Brugger" , "Rafael J. Wysocki" , Viresh Kumar , Nishanth Menon , "Stephen Boyd" , Liam Girdwood , Mark Brown CC: , , , , , , Andrew-sh.Cheng Subject: [PATCH V8 4/8] devfreq: add mediatek cci devfreq Date: Tue, 23 Mar 2021 19:33:57 +0800 Message-ID: <1616499241-4906-5-git-send-email-andrew-sh.cheng@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1616499241-4906-1-git-send-email-andrew-sh.cheng@mediatek.com> References: <1616499241-4906-1-git-send-email-andrew-sh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210323_113423_832794_E4A72818 X-CRM114-Status: GOOD ( 26.23 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: "Andrew-sh.Cheng" This adds a devfreq driver for the Cache Coherent Interconnect (CCI) of the Mediatek MT8183. On the MT8183 the CCI is supplied by the same regulator as the LITTLE cores. The driver is notified when the regulator voltage changes (driven by cpufreq) and adjusts the CCI frequency to the maximum possible value. Signed-off-by: Andrew-sh.Cheng --- drivers/devfreq/Kconfig | 10 ++ drivers/devfreq/Makefile | 1 + drivers/devfreq/mt8183-cci-devfreq.c | 198 +++++++++++++++++++++++++++++++++++ 3 files changed, 209 insertions(+) create mode 100644 drivers/devfreq/mt8183-cci-devfreq.c diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index f56132b0ae64..2538255ac2c1 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -111,6 +111,16 @@ config ARM_IMX8M_DDRC_DEVFREQ This adds the DEVFREQ driver for the i.MX8M DDR Controller. It allows adjusting DRAM frequency. +config ARM_MT8183_CCI_DEVFREQ + tristate "MT8183 CCI DEVFREQ Driver" + depends on ARM_MEDIATEK_CPUFREQ + help + This adds a devfreq driver for Cache Coherent Interconnect + of Mediatek MT8183, which is shared the same regulator + with cpu cluster. + It can track buck voltage and update a proper CCI frequency. + Use notification to get regulator status. + config ARM_TEGRA_DEVFREQ tristate "NVIDIA Tegra30/114/124/210 DEVFREQ Driver" depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_114_SOC || \ diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index a16333ea7034..991ef7740759 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o +obj-$(CONFIG_ARM_MT8183_CCI_DEVFREQ) += mt8183-cci-devfreq.o obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o diff --git a/drivers/devfreq/mt8183-cci-devfreq.c b/drivers/devfreq/mt8183-cci-devfreq.c new file mode 100644 index 000000000000..018543db7bae --- /dev/null +++ b/drivers/devfreq/mt8183-cci-devfreq.c @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 MediaTek Inc. + + * Author: Andrew-sh.Cheng + */ + +#include +#include +#include +#include +#include +#include +#include + +#define MAX_VOLT_LIMIT (1150000) + +struct cci_devfreq { + struct devfreq *devfreq; + struct regulator *cpu_reg; + struct clk *cci_clk; + int old_vproc; + unsigned long old_freq; +}; + +static int mtk_cci_set_voltage(struct cci_devfreq *cci_df, int vproc) +{ + int ret; + + ret = regulator_set_voltage(cci_df->cpu_reg, vproc, + MAX_VOLT_LIMIT); + if (!ret) + cci_df->old_vproc = vproc; + return ret; +} + +static int mtk_cci_devfreq_target(struct device *dev, unsigned long *freq, + u32 flags) +{ + int ret; + struct cci_devfreq *cci_df = dev_get_drvdata(dev); + struct dev_pm_opp *opp; + unsigned long opp_rate, opp_voltage, old_voltage; + + if (!cci_df) + return -EINVAL; + + if (cci_df->old_freq == *freq) + return 0; + + opp_rate = *freq; + opp = devfreq_recommended_opp(dev, &opp_rate, 1); + opp_voltage = dev_pm_opp_get_voltage(opp); + dev_pm_opp_put(opp); + + old_voltage = cci_df->old_vproc; + if (old_voltage == 0) + old_voltage = regulator_get_voltage(cci_df->cpu_reg); + + // scale up: set voltage first then freq + if (opp_voltage > old_voltage) { + ret = mtk_cci_set_voltage(cci_df, opp_voltage); + if (ret) { + pr_err("cci: failed to scale up voltage\n"); + return ret; + } + } + + ret = clk_set_rate(cci_df->cci_clk, *freq); + if (ret) { + pr_err("%s: failed cci to set rate: %d\n", __func__, + ret); + mtk_cci_set_voltage(cci_df, old_voltage); + return ret; + } + + // scale down: set freq first then voltage + if (opp_voltage < old_voltage) { + ret = mtk_cci_set_voltage(cci_df, opp_voltage); + if (ret) { + pr_err("cci: failed to scale down voltage\n"); + clk_set_rate(cci_df->cci_clk, cci_df->old_freq); + return ret; + } + } + + cci_df->old_freq = *freq; + + return 0; +} + +static struct devfreq_dev_profile cci_devfreq_profile = { + .target = mtk_cci_devfreq_target, +}; + +static int mtk_cci_devfreq_probe(struct platform_device *pdev) +{ + struct device *cci_dev = &pdev->dev; + struct cci_devfreq *cci_df; + struct devfreq_passive_data *passive_data; + int ret; + + cci_df = devm_kzalloc(cci_dev, sizeof(*cci_df), GFP_KERNEL); + if (!cci_df) + return -ENOMEM; + + cci_df->cci_clk = devm_clk_get(cci_dev, "cci_clock"); + ret = PTR_ERR_OR_ZERO(cci_df->cci_clk); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(cci_dev, "failed to get clock for CCI: %d\n", + ret); + return ret; + } + cci_df->cpu_reg = devm_regulator_get_optional(cci_dev, "proc"); + ret = PTR_ERR_OR_ZERO(cci_df->cpu_reg); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(cci_dev, "failed to get regulator for CCI: %d\n", + ret); + return ret; + } + ret = regulator_enable(cci_df->cpu_reg); + if (ret) { + dev_err(cci_dev, "enable buck for cci fail\n"); + return ret; + } + + ret = dev_pm_opp_of_add_table(cci_dev); + if (ret) { + dev_err(cci_dev, "Fail to get OPP table for CCI: %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, cci_df); + + passive_data = devm_kzalloc(cci_dev, sizeof(*passive_data), GFP_KERNEL); + if (!passive_data) { + ret = -ENOMEM; + goto err_opp; + } + + passive_data->parent_type = CPUFREQ_PARENT_DEV; + + cci_df->devfreq = devm_devfreq_add_device(cci_dev, + &cci_devfreq_profile, + DEVFREQ_GOV_PASSIVE, + passive_data); + if (IS_ERR(cci_df->devfreq)) { + ret = PTR_ERR(cci_df->devfreq); + dev_err(cci_dev, "cannot create cci devfreq device:%d\n", ret); + goto err_opp; + } + + return 0; + +err_opp: + dev_pm_opp_of_remove_table(cci_dev); + return ret; +} + +static int mtk_cci_devfreq_remove(struct platform_device *pdev) +{ + struct device *cci_dev = &pdev->dev; + struct cci_devfreq *cci_df; + struct notifier_block *opp_nb; + + cci_df = platform_get_drvdata(pdev); + opp_nb = &cci_df->opp_nb; + + dev_pm_opp_unregister_notifier(cci_dev, opp_nb); + dev_pm_opp_of_remove_table(cci_dev); + regulator_disable(cci_df->cpu_reg); + + return 0; +} + +static const __maybe_unused struct of_device_id + mediatek_cci_of_match[] = { + { .compatible = "mediatek,mt8183-cci" }, + { }, +}; +MODULE_DEVICE_TABLE(of, mediatek_cci_of_match); + +static struct platform_driver cci_devfreq_driver = { + .probe = mtk_cci_devfreq_probe, + .remove = mtk_cci_devfreq_remove, + .driver = { + .name = "mediatek-cci-devfreq", + .of_match_table = of_match_ptr(mediatek_cci_of_match), + }, +}; + +module_platform_driver(cci_devfreq_driver); + +MODULE_DESCRIPTION("Mediatek CCI devfreq driver"); +MODULE_AUTHOR("Andrew-sh.Cheng "); +MODULE_LICENSE("GPL v2"); From patchwork Tue Mar 23 11:33:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "andrew-sh.cheng" X-Patchwork-Id: 12157425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2633C433DB for ; Tue, 23 Mar 2021 11:35:12 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 337B7619B1 for ; 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Tue, 23 Mar 2021 03:34:10 -0800 Received: from mtkmbs05n2.mediatek.inc (172.21.101.140) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Mar 2021 04:34:07 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Mar 2021 19:34:07 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 23 Mar 2021 19:34:07 +0800 From: Andrew-sh.Cheng To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , "Rob Herring" , Mark Rutland , "Matthias Brugger" , "Rafael J. Wysocki" , Viresh Kumar , Nishanth Menon , "Stephen Boyd" , Liam Girdwood , Mark Brown CC: , , , , , , Andrew-sh.Cheng Subject: [PATCH V8 5/8] cpufreq: mediatek: Add record of previous desired vproc value Date: Tue, 23 Mar 2021 19:33:58 +0800 Message-ID: <1616499241-4906-6-git-send-email-andrew-sh.cheng@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1616499241-4906-1-git-send-email-andrew-sh.cheng@mediatek.com> References: <1616499241-4906-1-git-send-email-andrew-sh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210323_113420_583762_BAAFA069 X-CRM114-Status: GOOD ( 14.65 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: "Andrew-sh.Cheng" For case of share buck with other module, the result buck voltage may not exactly the same with what we set. Need to record the previous desired value instead of read from regulator. Signed-off-by: Andrew-sh.Cheng --- drivers/cpufreq/mediatek-cpufreq.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 432368707ea6..2a82c36aec21 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -42,6 +42,7 @@ struct mtk_cpu_dvfs_info { struct list_head list_head; int intermediate_voltage; bool need_voltage_tracking; + int old_vproc; }; static LIST_HEAD(dvfs_info_list); @@ -192,11 +193,16 @@ static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc) { + int ret; + if (info->need_voltage_tracking) - return mtk_cpufreq_voltage_tracking(info, vproc); + ret = mtk_cpufreq_voltage_tracking(info, vproc); else - return regulator_set_voltage(info->proc_reg, vproc, - vproc + VOLT_TOL); + ret = regulator_set_voltage(info->proc_reg, vproc, + MAX_VOLT_LIMIT); + if (!ret) + info->old_vproc = vproc; + return ret; } static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, @@ -214,7 +220,9 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, inter_vproc = info->intermediate_voltage; old_freq_hz = clk_get_rate(cpu_clk); - old_vproc = regulator_get_voltage(info->proc_reg); + old_vproc = info->old_vproc; + if (old_vproc == 0) + old_vproc = regulator_get_voltage(info->proc_reg); if (old_vproc < 0) { pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc); return old_vproc; From patchwork Tue Mar 23 11:33:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "andrew-sh.cheng" X-Patchwork-Id: 12157431 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FE35C433DB for ; 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Tue, 23 Mar 2021 19:34:07 +0800 From: Andrew-sh.Cheng To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , "Rob Herring" , Mark Rutland , "Matthias Brugger" , "Rafael J. Wysocki" , Viresh Kumar , Nishanth Menon , "Stephen Boyd" , Liam Girdwood , Mark Brown CC: , , , , , , Andrew-sh.Cheng Subject: [PATCH V8 6/8] cpufreq: mediatek: add opp notification for SVS support Date: Tue, 23 Mar 2021 19:33:59 +0800 Message-ID: <1616499241-4906-7-git-send-email-andrew-sh.cheng@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1616499241-4906-1-git-send-email-andrew-sh.cheng@mediatek.com> References: <1616499241-4906-1-git-send-email-andrew-sh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210323_113422_866557_7CEE15D6 X-CRM114-Status: GOOD ( 18.35 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: "Andrew-sh.Cheng" cpufreq should listen opp notification and do proper actions when receiving disable and voltage adjustment events, which are triggered when SVS is enabled. Signed-off-by: Andrew-sh.Cheng --- drivers/cpufreq/mediatek-cpufreq.c | 73 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c index 2a82c36aec21..1747b03e3059 100644 --- a/drivers/cpufreq/mediatek-cpufreq.c +++ b/drivers/cpufreq/mediatek-cpufreq.c @@ -43,6 +43,10 @@ struct mtk_cpu_dvfs_info { int intermediate_voltage; bool need_voltage_tracking; int old_vproc; + struct mutex lock; /* avoid notify and policy race condition */ + struct notifier_block opp_nb; + int opp_cpu; + unsigned long opp_freq; }; static LIST_HEAD(dvfs_info_list); @@ -239,6 +243,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, vproc = dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); + mutex_lock(&info->lock); /* * If the new voltage or the intermediate voltage is higher than the * current voltage, scale up voltage first. @@ -250,6 +255,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, pr_err("cpu%d: failed to scale up voltage!\n", policy->cpu); mtk_cpufreq_set_voltage(info, old_vproc); + mutex_unlock(&info->lock); return ret; } } @@ -261,6 +267,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, policy->cpu); mtk_cpufreq_set_voltage(info, old_vproc); WARN_ON(1); + mutex_unlock(&info->lock); return ret; } @@ -271,6 +278,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, policy->cpu); clk_set_parent(cpu_clk, armpll); mtk_cpufreq_set_voltage(info, old_vproc); + mutex_unlock(&info->lock); return ret; } @@ -281,6 +289,7 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, policy->cpu); mtk_cpufreq_set_voltage(info, inter_vproc); WARN_ON(1); + mutex_unlock(&info->lock); return ret; } @@ -296,15 +305,69 @@ static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, clk_set_parent(cpu_clk, info->inter_clk); clk_set_rate(armpll, old_freq_hz); clk_set_parent(cpu_clk, armpll); + mutex_unlock(&info->lock); return ret; } } + info->opp_freq = freq_hz; + mutex_unlock(&info->lock); + return 0; } #define DYNAMIC_POWER "dynamic-power-coefficient" +static int mtk_cpufreq_opp_notifier(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct dev_pm_opp *opp = data; + struct dev_pm_opp *new_opp; + struct mtk_cpu_dvfs_info *info; + unsigned long freq, volt; + struct cpufreq_policy *policy; + int ret = 0; + + info = container_of(nb, struct mtk_cpu_dvfs_info, opp_nb); + + if (event == OPP_EVENT_ADJUST_VOLTAGE) { + freq = dev_pm_opp_get_freq(opp); + + mutex_lock(&info->lock); + if (info->opp_freq == freq) { + volt = dev_pm_opp_get_voltage(opp); + ret = mtk_cpufreq_set_voltage(info, volt); + if (ret) + dev_err(info->cpu_dev, "failed to scale voltage: %d\n", + ret); + } + mutex_unlock(&info->lock); + } else if (event == OPP_EVENT_DISABLE) { + freq = dev_pm_opp_get_freq(opp); + /* case of current opp item is disabled */ + if (info->opp_freq == freq) { + freq = 1; + new_opp = dev_pm_opp_find_freq_ceil(info->cpu_dev, + &freq); + if (!IS_ERR(new_opp)) { + dev_pm_opp_put(new_opp); + policy = cpufreq_cpu_get(info->opp_cpu); + if (policy) { + cpufreq_driver_target(policy, + freq / 1000, + CPUFREQ_RELATION_L); + cpufreq_cpu_put(policy); + } + } else { + pr_err("%s: all opp items are disabled\n", + __func__); + } + } + } + + return notifier_from_errno(ret); +} + static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) { struct device *cpu_dev; @@ -400,11 +463,21 @@ static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) info->intermediate_voltage = dev_pm_opp_get_voltage(opp); dev_pm_opp_put(opp); + info->opp_cpu = cpu; + info->opp_nb.notifier_call = mtk_cpufreq_opp_notifier; + ret = dev_pm_opp_register_notifier(cpu_dev, &info->opp_nb); + if (ret) { + pr_warn("cannot register opp notification\n"); + goto out_disable_inter_clock; + } + + mutex_init(&info->lock); info->cpu_dev = cpu_dev; info->proc_reg = proc_reg; info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg; info->cpu_clk = cpu_clk; info->inter_clk = inter_clk; + info->opp_freq = clk_get_rate(cpu_clk); /* * If SRAM regulator is present, software "voltage tracking" is needed From patchwork Tue Mar 23 11:34:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "andrew-sh.cheng" X-Patchwork-Id: 12157429 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C3A3C433E0 for ; Tue, 23 Mar 2021 11:35:14 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 008BD619B1 for ; Tue, 23 Mar 2021 11:35:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 008BD619B1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=eTHs/dc0awfkc0z3NUoVqysM3GwftHB4eUHoLD+bHTc=; b=KnhhpI+w24iU+0Io+UuM2E2sB o1w6XQRdsxv4t+hi8jkTllhht7juRmOtjTFH8luHvqUbhJIy6MrEVzFjE7QpUP7HRrnob1oZoI9s3 JX7S+htkbhtBT+gMMakeq3YXCY+MGpEurG04NJhnXYOZyDF2oaQRGUBSS1ZlJWvikHcoVHDXGWrna 8vGoEv+ZEJBK7IDM/Fm6aTGi6G7Pz+Ltidv2tjLLy8QbHTpuMXpDBx4bd9GXVOidXIGUCIzUnr6n7 +LLtCfExhsSKAUHIcQaU6p1X69qdydIYT1BoLNQG66Y2Lu08oiKrjfafFpN9uCbG0Q7quzk4cpnV7 gSrqGMOkQ==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lOfJN-00Eifs-3t; Tue, 23 Mar 2021 11:35:01 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lOfIi-00EiXm-0w; Tue, 23 Mar 2021 11:34:22 +0000 X-UUID: bc67ec36ae3c405e8d533df3c46bc544-20210323 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=GtLlEQtFVYUJ6SnCVkNxU4lDx19Jh6fSbFyIZAPS6/Y=; b=QudIqlr01C/gg+42Q29aqh1aKYDqG4hP4JjU5Ne3CAQYQ0TsxaeaocVdj8z7F2R/3XRF1RcD5Ho+kTqr0IFLcjLY57vRIxorJvOGpMxE1PFsoUJy6vqAMdBEY/BF057Y826yLZuTi9rblTWOLXlkjR0uuGyAnmbU0Q2+P0KcwHU=; X-UUID: bc67ec36ae3c405e8d533df3c46bc544-20210323 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 949321265; Tue, 23 Mar 2021 03:34:11 -0800 Received: from mtkmbs05n1.mediatek.inc (172.21.101.15) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Mar 2021 04:34:10 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 23 Mar 2021 19:34:08 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 23 Mar 2021 19:34:08 +0800 From: Andrew-sh.Cheng To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , "Rob Herring" , Mark Rutland , "Matthias Brugger" , "Rafael J. Wysocki" , Viresh Kumar , Nishanth Menon , "Stephen Boyd" , Liam Girdwood , Mark Brown CC: , , , , , , Andrew-sh.Cheng Subject: [PATCH V8 7/8] devfreq: mediatek: cci devfreq register opp notification for SVS support Date: Tue, 23 Mar 2021 19:34:00 +0800 Message-ID: <1616499241-4906-8-git-send-email-andrew-sh.cheng@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1616499241-4906-1-git-send-email-andrew-sh.cheng@mediatek.com> References: <1616499241-4906-1-git-send-email-andrew-sh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210323_113420_531823_588C59D3 X-CRM114-Status: GOOD ( 16.10 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: "Andrew-sh.Cheng" SVS will change the voltage of opp item. CCI devfreq need to react to change frequency. Signed-off-by: Andrew-sh.Cheng --- drivers/devfreq/mt8183-cci-devfreq.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/devfreq/mt8183-cci-devfreq.c b/drivers/devfreq/mt8183-cci-devfreq.c index 018543db7bae..6942a48f3f4f 100644 --- a/drivers/devfreq/mt8183-cci-devfreq.c +++ b/drivers/devfreq/mt8183-cci-devfreq.c @@ -21,6 +21,7 @@ struct cci_devfreq { struct clk *cci_clk; int old_vproc; unsigned long old_freq; + struct notifier_block opp_nb; }; static int mtk_cci_set_voltage(struct cci_devfreq *cci_df, int vproc) @@ -89,6 +90,26 @@ static int mtk_cci_devfreq_target(struct device *dev, unsigned long *freq, return 0; } +static int ccidevfreq_opp_notifier(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct dev_pm_opp *opp = data; + struct cci_devfreq *cci_df = container_of(nb, struct cci_devfreq, + opp_nb); + unsigned long freq, volt; + + if (event == OPP_EVENT_ADJUST_VOLTAGE) { + freq = dev_pm_opp_get_freq(opp); + /* current opp item is changed */ + if (freq == cci_df->old_freq) { + volt = dev_pm_opp_get_voltage(opp); + mtk_cci_set_voltage(cci_df, volt); + } + } + + return 0; +} + static struct devfreq_dev_profile cci_devfreq_profile = { .target = mtk_cci_devfreq_target, }; @@ -98,12 +119,15 @@ static int mtk_cci_devfreq_probe(struct platform_device *pdev) struct device *cci_dev = &pdev->dev; struct cci_devfreq *cci_df; struct devfreq_passive_data *passive_data; + struct notifier_block *opp_nb; int ret; cci_df = devm_kzalloc(cci_dev, sizeof(*cci_df), GFP_KERNEL); if (!cci_df) return -ENOMEM; + opp_nb = &cci_df->opp_nb; + cci_df->cci_clk = devm_clk_get(cci_dev, "cci_clock"); ret = PTR_ERR_OR_ZERO(cci_df->cci_clk); if (ret) { @@ -152,6 +176,9 @@ static int mtk_cci_devfreq_probe(struct platform_device *pdev) goto err_opp; } + opp_nb->notifier_call = ccidevfreq_opp_notifier; + dev_pm_opp_register_notifier(cci_dev, opp_nb); + return 0; err_opp: From patchwork Tue Mar 23 11:34:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "andrew-sh.cheng" X-Patchwork-Id: 12157433 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 044E7C433E8 for ; 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Tue, 23 Mar 2021 19:34:09 +0800 From: Andrew-sh.Cheng To: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , "Rob Herring" , Mark Rutland , "Matthias Brugger" , "Rafael J. Wysocki" , Viresh Kumar , Nishanth Menon , "Stephen Boyd" , Liam Girdwood , Mark Brown CC: , , , , , , Andrew-sh.Cheng Subject: [PATCH V8 8/8] arm64: dts: mediatek: add cpufreq and cci devfreq nodes for mt8183 Date: Tue, 23 Mar 2021 19:34:01 +0800 Message-ID: <1616499241-4906-9-git-send-email-andrew-sh.cheng@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1616499241-4906-1-git-send-email-andrew-sh.cheng@mediatek.com> References: <1616499241-4906-1-git-send-email-andrew-sh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210323_113422_805825_E7B224F9 X-CRM114-Status: GOOD ( 10.19 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org From: "Andrew-sh.Cheng" add cpufreq and cci devfreq nodes for mt8183 base on regulator node https://patchwork.kernel.org/patch/11500339/ Now queued for v5.7-next/dts64 Signed-off-by: Andrew-sh.Cheng --- arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 36 ++++ arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 4 + arch/arm64/boot/dts/mediatek/mt8183.dtsi | 277 +++++++++++++++++++++++++ 3 files changed, 317 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index 3249c959f76f..77a591cc09a6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -395,6 +395,42 @@ }; +&cci { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu0 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu1 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu2 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu3 { + proc-supply = <&mt6358_vproc12_reg>; +}; + +&cpu4 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu5 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu6 { + proc-supply = <&mt6358_vproc11_reg>; +}; + +&cpu7 { + proc-supply = <&mt6358_vproc11_reg>; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index ff56bcfa3370..b1c3b88c4ac4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -217,6 +217,10 @@ status = "okay"; }; +&cci { + proc-supply = <&mt6358_vproc12_reg>; +}; + &cpu0 { proc-supply = <&mt6358_vproc12_reg>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 80519a145f13..c3dc87b01067 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -41,6 +41,251 @@ rdma1 = &rdma1; }; + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + opp0_00 { + opp-hz = /bits/ 64 <793000000>; + opp-microvolt = <650000>; + required-opps = <&opp2_00>; + }; + opp0_01 { + opp-hz = /bits/ 64 <910000000>; + opp-microvolt = <687500>; + required-opps = <&opp2_01>; + }; + opp0_02 { + opp-hz = /bits/ 64 <1014000000>; + opp-microvolt = <718750>; + required-opps = <&opp2_02>; + }; + opp0_03 { + opp-hz = /bits/ 64 <1131000000>; + opp-microvolt = <756250>; + required-opps = <&opp2_03>; + }; + opp0_04 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <800000>; + required-opps = <&opp2_04>; + }; + opp0_05 { + opp-hz = /bits/ 64 <1326000000>; + opp-microvolt = <818750>; + required-opps = <&opp2_05>; + }; + opp0_06 { + opp-hz = /bits/ 64 <1417000000>; + opp-microvolt = <850000>; + required-opps = <&opp2_06>; + }; + opp0_07 { + opp-hz = /bits/ 64 <1508000000>; + opp-microvolt = <868750>; + required-opps = <&opp2_07>; + }; + opp0_08 { + opp-hz = /bits/ 64 <1586000000>; + opp-microvolt = <893750>; + required-opps = <&opp2_08>; + }; + opp0_09 { + opp-hz = /bits/ 64 <1625000000>; + opp-microvolt = <906250>; + required-opps = <&opp2_09>; + }; + opp0_10 { + opp-hz = /bits/ 64 <1677000000>; + opp-microvolt = <931250>; + required-opps = <&opp2_10>; + }; + opp0_11 { + opp-hz = /bits/ 64 <1716000000>; + opp-microvolt = <943750>; + required-opps = <&opp2_11>; + }; + opp0_12 { + opp-hz = /bits/ 64 <1781000000>; + opp-microvolt = <975000>; + required-opps = <&opp2_12>; + }; + opp0_13 { + opp-hz = /bits/ 64 <1846000000>; + opp-microvolt = <1000000>; + required-opps = <&opp2_13>; + }; + opp0_14 { + opp-hz = /bits/ 64 <1924000000>; + opp-microvolt = <1025000>; + required-opps = <&opp2_14>; + }; + opp0_15 { + opp-hz = /bits/ 64 <1989000000>; + opp-microvolt = <1050000>; + required-opps = <&opp2_15>; + }; }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + opp1_00 { + opp-hz = /bits/ 64 <793000000>; + opp-microvolt = <700000>; + required-opps = <&opp2_00>; + }; + opp1_01 { + opp-hz = /bits/ 64 <910000000>; + opp-microvolt = <725000>; + required-opps = <&opp2_01>; + }; + opp1_02 { + opp-hz = /bits/ 64 <1014000000>; + opp-microvolt = <750000>; + required-opps = <&opp2_02>; + }; + opp1_03 { + opp-hz = /bits/ 64 <1131000000>; + opp-microvolt = <775000>; + required-opps = <&opp2_03>; + }; + opp1_04 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <800000>; + required-opps = <&opp2_04>; + }; + opp1_05 { + opp-hz = /bits/ 64 <1326000000>; + opp-microvolt = <825000>; + required-opps = <&opp2_05>; + }; + opp1_06 { + opp-hz = /bits/ 64 <1417000000>; + opp-microvolt = <850000>; + required-opps = <&opp2_06>; + }; + opp1_07 { + opp-hz = /bits/ 64 <1508000000>; + opp-microvolt = <875000>; + required-opps = <&opp2_07>; + }; + opp1_08 { + opp-hz = /bits/ 64 <1586000000>; + opp-microvolt = <900000>; + required-opps = <&opp2_08>; + }; + opp1_09 { + opp-hz = /bits/ 64 <1625000000>; + opp-microvolt = <912500>; + required-opps = <&opp2_09>; + }; + opp1_10 { + opp-hz = /bits/ 64 <1677000000>; + opp-microvolt = <931250>; + required-opps = <&opp2_10>; + }; + opp1_11 { + opp-hz = /bits/ 64 <1716000000>; + opp-microvolt = <950000>; + required-opps = <&opp2_11>; + }; + opp1_12 { + opp-hz = /bits/ 64 <1781000000>; + opp-microvolt = <975000>; + required-opps = <&opp2_12>; + }; + opp1_13 { + opp-hz = /bits/ 64 <1846000000>; + opp-microvolt = <1000000>; + required-opps = <&opp2_13>; + }; + opp1_14 { + opp-hz = /bits/ 64 <1924000000>; + opp-microvolt = <1025000>; + required-opps = <&opp2_14>; + }; + opp1_15 { + opp-hz = /bits/ 64 <1989000000>; + opp-microvolt = <1050000>; + required-opps = <&opp2_15>; + }; + }; + + cci_opp: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + opp2_00: opp-273000000 { + opp-hz = /bits/ 64 <273000000>; + opp-microvolt = <650000>; + }; + opp2_01: opp-338000000 { + opp-hz = /bits/ 64 <338000000>; + opp-microvolt = <687500>; + }; + opp2_02: opp-403000000 { + opp-hz = /bits/ 64 <403000000>; + opp-microvolt = <718750>; + }; + opp2_03: opp-463000000 { + opp-hz = /bits/ 64 <463000000>; + opp-microvolt = <756250>; + }; + opp2_04: opp-546000000 { + opp-hz = /bits/ 64 <546000000>; + opp-microvolt = <800000>; + }; + opp2_05: opp-624000000 { + opp-hz = /bits/ 64 <624000000>; + opp-microvolt = <818750>; + }; + opp2_06: opp-689000000 { + opp-hz = /bits/ 64 <689000000>; + opp-microvolt = <850000>; + }; + opp2_07: opp-767000000 { + opp-hz = /bits/ 64 <767000000>; + opp-microvolt = <868750>; + }; + opp2_08: opp-845000000 { + opp-hz = /bits/ 64 <845000000>; + opp-microvolt = <893750>; + }; + opp2_09: opp-871000000 { + opp-hz = /bits/ 64 <871000000>; + opp-microvolt = <906250>; + }; + opp2_10: opp-923000000 { + opp-hz = /bits/ 64 <923000000>; + opp-microvolt = <931250>; + }; + opp2_11: opp-962000000 { + opp-hz = /bits/ 64 <962000000>; + opp-microvolt = <943750>; + }; + opp2_12: opp-1027000000 { + opp-hz = /bits/ 64 <1027000000>; + opp-microvolt = <975000>; + }; + opp2_13: opp-1092000000 { + opp-hz = /bits/ 64 <1092000000>; + opp-microvolt = <1000000>; + }; + opp2_14: opp-1144000000 { + opp-hz = /bits/ 64 <1144000000>; + opp-microvolt = <1025000>; + }; + opp2_15: opp-1196000000 { + opp-hz = /bits/ 64 <1196000000>; + opp-microvolt = <1050000>; + }; + }; + + cci: cci { + compatible = "mediatek,mt8183-cci"; + clocks = <&apmixedsys CLK_APMIXED_CCIPLL>; + clock-names = "cci_clock"; + operating-points-v2 = <&cci_opp>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -84,6 +329,10 @@ enable-method = "psci"; capacity-dmips-mhz = <741>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; }; @@ -95,6 +344,10 @@ enable-method = "psci"; capacity-dmips-mhz = <741>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; }; @@ -106,6 +359,10 @@ enable-method = "psci"; capacity-dmips-mhz = <741>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; }; @@ -117,6 +374,10 @@ enable-method = "psci"; capacity-dmips-mhz = <741>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; + clocks = <&mcucfg CLK_MCU_MP0_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <84>; #cooling-cells = <2>; }; @@ -128,6 +389,10 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; }; @@ -139,6 +404,10 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; }; @@ -150,6 +419,10 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; }; @@ -161,6 +434,10 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; + clocks = <&mcucfg CLK_MCU_MP2_SEL>, + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; + clock-names = "cpu", "intermediate"; + operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <211>; #cooling-cells = <2>; };