From patchwork Wed Mar 24 06:37:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aswath Govindraju X-Patchwork-Id: 12160309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A34EEC433C1 for ; Wed, 24 Mar 2021 06:40:08 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3FBAF6191A for ; Wed, 24 Mar 2021 06:40:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3FBAF6191A Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=iu2+nMH9BZruEwDriuvgiO/dkg2MZhacbTwZdRkmIog=; b=S49B56xDbuOP9S7H6KqL+m+/S cWIs7LMbquzvAN88y/FkVR8Z+3xI1Oa+aJHzXqhnoKnSqHfCBlcGSz4qVKFKkV7segIkXXFFeqWLT e5Ot6XqsFZ85fUgQTzSJDHLa18sIgOM1TNpcYMuR/Si6U528gkWs+Fz3RNpYC0orH6KLJLTZ6d9Cq DZIkTRjxLgpPGIKNyYqEbKy09dQxgG0CUauDHY/ysx6TQrCqVBq2YwOdoUIzGVn5EdZ9ZE/UIiNgZ uuFxBJ/qnyRDDVOySgR4B6UbIak0Rns5DtmgFxjfpfYoFE3qbkqKjSt7EtrGI2aowIohrBhMQ2O2T q2wu9/VLg==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lOx9n-00GP2h-F7; Wed, 24 Mar 2021 06:38:19 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lOx9h-00GP1g-G5 for linux-arm-kernel@lists.infradead.org; Wed, 24 Mar 2021 06:38:17 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12O6cACP069623; Wed, 24 Mar 2021 01:38:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1616567890; bh=Dr4LHoqOWSsZAcnpqcfoAztyJbkQnZL0/LcVqWiFSTk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RtURsFpdcPIW6/mvW2nIPpxxpFzstrrLFc+Lkb8uZKUv287N+8mibb1sE75buKbaA PGgtqosqxJbCfwP3h4mQ/tESkKDHlQyTKLeqMpkBeDKcA/BeXpRzd3sr0K8Rj0XeJD BuzkdOA5aw+E5kRyU+VM4s8d4h7huK0e8B+j95/g= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12O6cA2d005399 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 24 Mar 2021 01:38:10 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 24 Mar 2021 01:38:09 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 24 Mar 2021 01:38:09 -0500 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12O6c2c7014513; Wed, 24 Mar 2021 01:38:06 -0500 From: Aswath Govindraju To: CC: Vignesh Raghavendra , Lokesh Vutla , Kishon Vijay Abraham I , Aswath Govindraju , Faiz Abbas , Sekhar Nori , Nishanth Menon , Tero Kristo , Rob Herring , , , Subject: [PATCH v8 1/3] arm64: dts: ti: k3-j7200: Add gpio nodes Date: Wed, 24 Mar 2021 12:07:57 +0530 Message-ID: <20210324063759.5837-2-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210324063759.5837-1-a-govindraju@ti.com> References: <20210324063759.5837-1-a-govindraju@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210324_063813_965719_158B925E X-CRM114-Status: GOOD ( 10.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Faiz Abbas There are 4 instances of gpio modules in main domain: gpio0, gpio2, gpio4 and gpio6 Groups are created to provide protection between different processor virtual worlds. Each of these modules I/O pins are muxed within the group. Exactly one module can be selected to control the corresponding pin by selecting it in the pad mux configuration registers. This group in main domain pins out 69 lines (5 banks). Add DT modes for each module instance in the main domain. Similar to the gpio groups in main domain, there is one gpio group in wakeup domain with 2 module instances in it. The gpio group pins out 72 pins (6 banks) of the first 85 gpio lines. Add DT nodes for each module instance in the wakeup domain. Signed-off-by: Faiz Abbas Signed-off-by: Sekhar Nori Signed-off-by: Aswath Govindraju Reviewed-by: Grygorii Strashko --- arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 72 +++++++++++++++++++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 34 +++++++++ 2 files changed, 106 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index 17477ab0fd8e..e60650a62b14 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -672,6 +672,78 @@ }; }; + main_gpio0: gpio@600000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00600000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <145>, <146>, <147>, <148>, + <149>; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <0>; + ti,ngpio = <69>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 105 0>; + clock-names = "gpio"; + }; + + main_gpio2: gpio@610000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00610000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <154>, <155>, <156>, <157>, + <158>; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <0>; + ti,ngpio = <69>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 107 0>; + clock-names = "gpio"; + }; + + main_gpio4: gpio@620000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00620000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <163>, <164>, <165>, <166>, + <167>; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <0>; + ti,ngpio = <69>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 109 0>; + clock-names = "gpio"; + }; + + main_gpio6: gpio@630000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x00630000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&main_gpio_intr>; + interrupts = <172>, <173>, <174>, <175>, + <176>; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <0>; + ti,ngpio = <69>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 111 0>; + clock-names = "gpio"; + }; + main_r5fss0: r5fss@5c00000 { compatible = "ti,j7200-r5fss"; ti,cluster-mode = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 5408ec815d58..4e4ea7655fe2 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -107,6 +107,40 @@ ti,interrupt-ranges = <16 960 16>; }; + wkup_gpio0: gpio@42110000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x42110000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&wkup_gpio_intr>; + interrupts = <103>, <104>, <105>, <106>, <107>, <108>; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <0>; + ti,ngpio = <85>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 113 0>; + clock-names = "gpio"; + }; + + wkup_gpio1: gpio@42100000 { + compatible = "ti,j721e-gpio", "ti,keystone-gpio"; + reg = <0x00 0x42100000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&wkup_gpio_intr>; + interrupts = <112>, <113>, <114>, <115>, <116>, <117>; + interrupt-controller; + #interrupt-cells = <2>; + #address-cells = <0>; + ti,ngpio = <85>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; + clock-names = "gpio"; + }; + mcu_navss: bus@28380000 { compatible = "simple-mfd"; #address-cells = <2>; From patchwork Wed Mar 24 06:37:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aswath Govindraju X-Patchwork-Id: 12160307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B5F4C433E0 for ; Wed, 24 Mar 2021 06:40:09 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0178A619E5 for ; Wed, 24 Mar 2021 06:40:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0178A619E5 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=cyEq/uSCu4FXs8w1IpFrEvKncWA5W2vFkfQjvO+qu5M=; b=QTmGVx4zSSLPQAXpJrb/UHujP lU8q0vpFzF6pXhgEj7kEEK6BtI3wBAm/ZVKLjCM6W1BIFwyJ4la1sCwhxZWYW8p95UaT0K0SNYGQQ PGKaHcUxb7Bl5jiUUGk9jgDABSA/Ndtig1nMLuVYslJmhVOyNYapqPjcq7l9YMIva2oiPqgv1WMDe g+x1eqPrb/JblYtQRD5rhI3NRJOAG52W13GV/QSxw3rkNEGCNiJXtsy4EyFTt9OOEJxBMgr0K838Z klJD+tFxT1G8rpj0xE3rPYR5NXH9VL/s14NQNpGhYh7+ICbBtuGMeD8Zn28fpCqZsN6/gh8ZIQGed kSzWemMng==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lOxA2-00GP3p-VJ; Wed, 24 Mar 2021 06:38:35 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lOx9k-00GP2B-I3 for linux-arm-kernel@lists.infradead.org; Wed, 24 Mar 2021 06:38:19 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12O6cEO1069655; Wed, 24 Mar 2021 01:38:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1616567894; bh=530e36igGodybBnc5gwlB/hSoWE3yMji47/Zyiw64Yk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NKnIYPgN0B4fbMm5yoJnBHgGt38qeSlOP3Yf8Jaar6S47hYYMZPkQOlt4KTOAO4kS gEn+0yVJqfaCaqRnQZuBKN9tzLyt5veuZ6sA5RtOYuJz+oGq0FtmYKiYVO+VJH5ytd l3GUlhCzqsKPlrGgI/4CxkyrbF/wbINL46hqZTTI= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12O6cEHf023514 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 24 Mar 2021 01:38:14 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 24 Mar 2021 01:38:14 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 24 Mar 2021 01:38:14 -0500 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12O6c2c8014513; Wed, 24 Mar 2021 01:38:11 -0500 From: Aswath Govindraju To: CC: Vignesh Raghavendra , Lokesh Vutla , Kishon Vijay Abraham I , Aswath Govindraju , Faiz Abbas , Sekhar Nori , Nishanth Menon , Tero Kristo , Rob Herring , , , Subject: [PATCH v8 2/3] arm64: dts: ti: k3-j7200-common-proc-board: Disable unused gpio modules Date: Wed, 24 Mar 2021 12:07:58 +0530 Message-ID: <20210324063759.5837-3-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210324063759.5837-1-a-govindraju@ti.com> References: <20210324063759.5837-1-a-govindraju@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210324_063816_928781_A67F31E0 X-CRM114-Status: GOOD ( 10.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Faiz Abbas There are 6 gpio instances inside SoC with 2 groups as show below: Group one: wkup_gpio0, wkup_gpio1 Group two: main_gpio0, main_gpio2, main_gpio4, main_gpio6 Only one instance from each group can be used at a time. So use main_gpio0 and wkup_gpio0 in current linux context and disable the rest of the nodes. Signed-off-by: Faiz Abbas Signed-off-by: Sekhar Nori Signed-off-by: Aswath Govindraju Reviewed-by: Grygorii Strashko --- .../boot/dts/ti/k3-j7200-common-proc-board.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 4a7182abccf5..b493f939b09a 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -122,6 +122,22 @@ status = "disabled"; }; +&main_gpio2 { + status = "disabled"; +}; + +&main_gpio4 { + status = "disabled"; +}; + +&main_gpio6 { + status = "disabled"; +}; + +&wkup_gpio1 { + status = "disabled"; +}; + &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; From patchwork Wed Mar 24 06:37:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aswath Govindraju X-Patchwork-Id: 12160311 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D077C433C1 for ; Wed, 24 Mar 2021 06:40:14 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A2312619B8 for ; Wed, 24 Mar 2021 06:40:13 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A2312619B8 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=eB1flMDmXGPa73YefmldSSjZ/zKKBfRGCdNjFKAJoF8=; b=fi+lnKgreWA9yZWRDtGaqN486 AeYSWqWHDl9FOvU/gE8KHHIbLfxD/x4lv5s8vx3aWkIoadCPBcdiUSEWihsBe0YrPZweOzdVyx/kE 1H2Bt/kpq+WU3HQDX/YL/YGv8pq3V9ovPmDF72hX0o167vuL9JccegmSOtl6Gnn/+6F4DdC/rNmt3 5BYYJwEe66IHkifXztSK1f0Ph23SSihRu0EIXu3c4FGUx8VweGEzGsIAVNanxpXTmCvXFxI1MXMZE ILfJ/OzsbP2X2jP4Lv9ImyhTcP8l2LJDc4Md0p37LlO/2vTA6kI5Ou1D4BE79vkCFvLhJyx3Fvhfd u95F2LLPA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lOxA9-00GP4Z-IJ; Wed, 24 Mar 2021 06:38:41 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lOx9p-00GP2o-EW for linux-arm-kernel@lists.infradead.org; Wed, 24 Mar 2021 06:38:26 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12O6cIpf007690; Wed, 24 Mar 2021 01:38:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1616567899; bh=nxFmLhVQMONHPfn7nZ4wk/3iWT9W3rYaCFlJKVE7r2o=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=v9roeEb6XkwdepChb7FPS8UFtLdecpTvIjrKFYsCiIeVCmE8TdojcY4IG3iSmQpUM hECDa2+Z/BW/cVq++vTgGZFdmKIQ2bFlzam/c7JY2gpugLd7EuVraM5CuZElKfxmkw +FnR3d/btUlomsL5cGS/ze+6WgBbYLyU/CzfbJWw= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12O6cIWh005740 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 24 Mar 2021 01:38:18 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Wed, 24 Mar 2021 01:38:18 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Wed, 24 Mar 2021 01:38:18 -0500 Received: from gsaswath-HP-ProBook-640-G5.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12O6c2c9014513; Wed, 24 Mar 2021 01:38:15 -0500 From: Aswath Govindraju To: CC: Vignesh Raghavendra , Lokesh Vutla , Kishon Vijay Abraham I , Aswath Govindraju , Nishanth Menon , Tero Kristo , Rob Herring , , , Subject: [PATCH v8 3/3] arm64: dts: ti: k3-j7200: Add support for higher speed modes and update delay select values for MMCSD subsystems Date: Wed, 24 Mar 2021 12:07:59 +0530 Message-ID: <20210324063759.5837-4-a-govindraju@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210324063759.5837-1-a-govindraju@ti.com> References: <20210324063759.5837-1-a-govindraju@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210324_063821_939562_25A47348 X-CRM114-Status: GOOD ( 13.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The following speed modes are now supported in J7200 SoC, - HS200 and HS400 modes at 1.8 V card voltage, in MMCSD0 subsystem [1]. - UHS-I speed modes in MMCSD1 subsystem [1]. Add support for UHS-I modes by adding voltage regulator device tree nodes and corresponding pinmux details, to power cycle and voltage switch cards. Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1 device tree nodes. Also update the delay values for various speed modes supported, based on the revised january 2021 J7200 datasheet[2]. [1] - section 12.3.6.1.1 MMCSD Features, in https://www.ti.com/lit/ug/spruiu1a/spruiu1a.pdf, (SPRUIU1A – JULY 2020 – REVISED JANUARY 2021) [2] - https://www.ti.com/lit/ds/symlink/dra821u.pdf, (SPRSP57B – APRIL 2020 – REVISED JANUARY 2021) Signed-off-by: Aswath Govindraju Reviewed-by: Kishon Vijay Abraham I --- .../dts/ti/k3-j7200-common-proc-board.dts | 78 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 14 +++- 2 files changed, 90 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index b493f939b09a..a069787e1783 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -16,6 +16,65 @@ stdout-path = "serial2:115200n8"; bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; + + evm_12v0: fixedregulator-evm12v0 { + /* main supply */ + compatible = "regulator-fixed"; + regulator-name = "evm_12v0"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: fixedregulator-vsys3v3 { + /* Output of LMS140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_5v0: fixedregulator-vsys5v0 { + /* Output of LM5140 */ + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&evm_12v0>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: fixedregulator-sd { + /* Output of TPS22918 */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vsys_3v3>; + gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: gpio-regulator-vdd-sd-dv { + /* Output of TLV71033 */ + compatible = "regulator-gpio"; + regulator-name = "vdd_sd_dv"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vsys_5v0>; + gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; }; &wkup_pmx0 { @@ -45,6 +104,13 @@ }; &main_pmx0 { + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ + J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ + >; + }; + main_i2c1_pins_default: main-i2c1-pins-default { pinctrl-single,pins = < J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ @@ -70,6 +136,12 @@ J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ >; }; + + vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0xd0, PIN_INPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ + >; + }; }; &wkup_uart0 { @@ -157,6 +229,10 @@ }; &main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins_default>; + clock-frequency = <400000>; + exp1: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; @@ -206,6 +282,8 @@ /* SD card */ pinctrl-0 = <&main_mmc1_pins_default>; pinctrl-names = "default"; + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; ti,driver-strength-ohm = <50>; disable-wp; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index e60650a62b14..f86c493a44f1 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -512,11 +512,16 @@ ti,otap-del-sel-mmc-hs = <0x0>; ti,otap-del-sel-ddr52 = <0x6>; ti,otap-del-sel-hs200 = <0x8>; - ti,otap-del-sel-hs400 = <0x0>; + ti,otap-del-sel-hs400 = <0x5>; + ti,itap-del-sel-legacy = <0x10>; + ti,itap-del-sel-mmc-hs = <0xa>; ti,strobe-sel = <0x77>; + ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; bus-width = <8>; mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; dma-coherent; }; @@ -534,7 +539,12 @@ ti,otap-del-sel-sdr50 = <0xc>; ti,otap-del-sel-sdr104 = <0x5>; ti,otap-del-sel-ddr50 = <0xc>; - no-1-8-v; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + ti,clkbuf-sel = <0x7>; + ti,trm-icp = <0x8>; dma-coherent; };