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bh=PNclna4r96z+ADs9Z6sKNU7TGol0SXSB3VYQsdRhSU4=; b=sZf7/H4z1KXQsEQ38Cn+uj5QdRRET8r78/gEsu5TNLi65dIveo4Zq6D7bL1ThrUbCg mN15BstQMFaPuT8xckCWmmoQzEI+Xbiwpt2vfqJ92LPtBgLvOLjwiJsg8dQYGGEdm7P8 8tcdfdlUw2by8x71APQu7X4Z/8s6Z1s7nlt/4kwogGJ6rCADya83aQCOizhmUrzL8fX9 DBiJ0cpuuNffKl77mJeWJCu5pSzVob2mgWGYUyKYHPVIPlXndi96rnZHlY336wTKP0gV Qz11HnUuN5eeaUqUp7l/2ZHJsh12qYwPCL/l7YHcSnkEprLoVYWIoXKOrCbT4fsjZ7nV ukaw== X-Gm-Message-State: AOAM532hecYo6JSCZfZqVflZXiSto7EDo+k9eafDQaO3tX+5FE6OwF7Y VflmecQnhBLUsyKTcVN01HnNjg== X-Google-Smtp-Source: ABdhPJyaMBulk3s1mm/SNbnsxJGB+1AhFTA5Tqmuc39h8ixwGUrWDFzcvYQdzesbAeUlzQjkr6jIXA== X-Received: by 2002:a17:902:7c94:b029:e6:e1d7:62b7 with SMTP id y20-20020a1709027c94b02900e6e1d762b7mr6522874pll.29.1616636141541; Wed, 24 Mar 2021 18:35:41 -0700 (PDT) Received: from evanbenn1.syd.corp.google.com ([2401:fa00:9:15:5d74:fcca:830d:3b2f]) by smtp.gmail.com with ESMTPSA id w203sm3645602pfc.188.2021.03.24.18.35.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Mar 2021 18:35:41 -0700 (PDT) From: Evan Benn To: Matthias Brugger Cc: Stanley Chu , Alexey Klimov , Julia Lawall , Yingjoe Chen , Thomas Gleixner , linux-mediatek@lists.infradead.org, Daniel Lezcano , linux-arm-kernel@lists.infradead.org, Evan Benn , Viresh Kumar , LKML , Fabien Parent Subject: [PATCH v2] drivers/clocksource/mediatek: Ack and disable interrupts on shutdown Date: Thu, 25 Mar 2021 12:35:00 +1100 Message-Id: <20210325123446.v2.1.I1d9917047de06715da16e1620759f703fcfdcbcb@changeid> X-Mailer: git-send-email 2.31.0.291.g576ba9dcdaf-goog MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210325_013543_973204_B9E16ACE X-CRM114-Status: GOOD ( 15.91 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org set_state_shutdown is called during system suspend after interrupts have been disabled. If the timer has fired in the meantime, there will be a pending IRQ. So we ack that now and disable the timer. Without this ARM trusted firmware will abort the suspend due to the pending interrupt. Now always disable the IRQ in state transitions, and re-enable in set_periodic and next_event. Signed-off-by: Evan Benn --- Changes in v2: Remove the patch that splits the drivers into 2 files. drivers/clocksource/timer-mediatek.c | 49 +++++++++++++++++----------- 1 file changed, 30 insertions(+), 19 deletions(-) diff --git a/drivers/clocksource/timer-mediatek.c b/drivers/clocksource/timer-mediatek.c index 9318edcd8963..fba2f9494d90 100644 --- a/drivers/clocksource/timer-mediatek.c +++ b/drivers/clocksource/timer-mediatek.c @@ -132,13 +132,33 @@ static u64 notrace mtk_gpt_read_sched_clock(void) return readl_relaxed(gpt_sched_reg); } +static void mtk_gpt_disable_ack_interrupts(struct timer_of *to, u8 timer) +{ + u32 val; + + /* Disable interrupts */ + val = readl(timer_of_base(to) + GPT_IRQ_EN_REG); + writel(val & ~GPT_IRQ_ENABLE(timer), timer_of_base(to) + + GPT_IRQ_EN_REG); + + /* Ack interrupts */ + writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG); +} + static void mtk_gpt_clkevt_time_stop(struct timer_of *to, u8 timer) { u32 val; + /* Disable timer */ val = readl(timer_of_base(to) + GPT_CTRL_REG(timer)); writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) + GPT_CTRL_REG(timer)); + + /* This may be called with interrupts disabled, + * so we need to ack any interrupt that is pending + * Or for example ATF will prevent a suspend from completing. + */ + mtk_gpt_disable_ack_interrupts(to, timer); } static void mtk_gpt_clkevt_time_setup(struct timer_of *to, @@ -152,8 +172,10 @@ static void mtk_gpt_clkevt_time_start(struct timer_of *to, { u32 val; - /* Acknowledge interrupt */ - writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG); + /* Enable interrupts */ + val = readl(timer_of_base(to) + GPT_IRQ_EN_REG); + writel(val | GPT_IRQ_ENABLE(timer), + timer_of_base(to) + GPT_IRQ_EN_REG); val = readl(timer_of_base(to) + GPT_CTRL_REG(timer)); @@ -226,21 +248,6 @@ __init mtk_gpt_setup(struct timer_of *to, u8 timer, u8 option) timer_of_base(to) + GPT_CTRL_REG(timer)); } -static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer) -{ - u32 val; - - /* Disable all interrupts */ - writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG); - - /* Acknowledge all spurious pending interrupts */ - writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG); - - val = readl(timer_of_base(to) + GPT_IRQ_EN_REG); - writel(val | GPT_IRQ_ENABLE(timer), - timer_of_base(to) + GPT_IRQ_EN_REG); -} - static struct timer_of to = { .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK, @@ -292,6 +299,12 @@ static int __init mtk_gpt_init(struct device_node *node) if (ret) return ret; + /* In case the firmware left the interrupts enabled + * disable and ack those now + */ + mtk_gpt_disable_ack_interrupts(&to, TIMER_CLK_SRC); + mtk_gpt_disable_ack_interrupts(&to, TIMER_CLK_EVT); + /* Configure clock source */ mtk_gpt_setup(&to, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN); clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC), @@ -305,8 +318,6 @@ static int __init mtk_gpt_init(struct device_node *node) clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), TIMER_SYNC_TICKS, 0xffffffff); - mtk_gpt_enable_irq(&to, TIMER_CLK_EVT); - return 0; } TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init);