From patchwork Thu Mar 25 05:52:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dylan Jhong X-Patchwork-Id: 12162979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC503C433C1 for ; Thu, 25 Mar 2021 05:54:03 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 035BB61A1D for ; Thu, 25 Mar 2021 05:54:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 035BB61A1D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=andestech.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:56200 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lPIwT-0000mU-TF for qemu-devel@archiver.kernel.org; Thu, 25 Mar 2021 01:54:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38574) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lPIve-0000J8-Te; Thu, 25 Mar 2021 01:53:10 -0400 Received: from exmail.andestech.com ([60.248.187.195]:17814 helo=ATCSQR.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lPIva-0001jS-M9; Thu, 25 Mar 2021 01:53:09 -0400 Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id 12P5qMjR086974; Thu, 25 Mar 2021 13:52:22 +0800 (GMT-8) (envelope-from dylan@andestech.com) Received: from atcfdc88.andestech.com (10.0.15.120) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Thu, 25 Mar 2021 13:52:23 +0800 From: Dylan Jhong To: , , , , , Subject: [PATCH V2] target/riscv: Align the data type of reset vector address Date: Thu, 25 Mar 2021 13:52:13 +0800 Message-ID: <20210325055213.13464-1-dylan@andestech.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [10.0.15.120] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 12P5qMjR086974 Received-SPF: pass client-ip=60.248.187.195; envelope-from=dylan@andestech.com; helo=ATCSQR.andestech.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ruinland@andestech.com, bmeng.cn@gmail.com, x5710999x@gmail.com, alankao@andestech.com, Dylan Jhong Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Dylan Jhong Signed-off-by: Ruinland ChuanTzu Tsai --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7d6ed80f6b..4ac901245a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -137,7 +137,7 @@ static void set_feature(CPURISCVState *env, int feature) env->features |= (1ULL << feature); } -static void set_resetvec(CPURISCVState *env, int resetvec) +static void set_resetvec(CPURISCVState *env, target_ulong resetvec) { #ifndef CONFIG_USER_ONLY env->resetvec = resetvec; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0a33d387ba..d9d7891666 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -303,7 +303,7 @@ struct RISCVCPU { uint16_t elen; bool mmu; bool pmp; - uint64_t resetvec; + target_ulong resetvec; } cfg; };