From patchwork Fri Mar 26 13:21:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 12166619 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40C06C433C1 for ; Fri, 26 Mar 2021 13:21:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D98EB61A18 for ; Fri, 26 Mar 2021 13:21:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D98EB61A18 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 655906F3CF; Fri, 26 Mar 2021 13:21:53 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 155006F3CF for ; Fri, 26 Mar 2021 13:21:52 +0000 (UTC) IronPort-SDR: 0EhWE3WcaNz0h/6EaJUhIhl1VltAdpdH74aZB+LY3FFReI/l4oaBr9jxP3DSVEMWyQ0TwOJ0GK SIt05UoxYSCw== X-IronPort-AV: E=McAfee;i="6000,8403,9934"; a="191239643" X-IronPort-AV: E=Sophos;i="5.81,280,1610438400"; d="scan'208";a="191239643" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2021 06:21:51 -0700 IronPort-SDR: UBEux/JYJsDgyTIEHT0RMoAasowygYpQRlPyLtL/0VrnreeGg8doXFfxhkmfl0CgwIx5aK2TNn hBs15cE4KusA== X-IronPort-AV: E=Sophos;i="5.81,280,1610438400"; d="scan'208";a="416532579" Received: from mpaulits-mobl1.ger.corp.intel.com (HELO localhost) ([10.252.55.191]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2021 06:21:49 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Fri, 26 Mar 2021 15:21:32 +0200 Message-Id: X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 1/7] drm/i915: split out stepping info to a new file X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, Lucas De Marchi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" gt/intel_workarounds.c is decidedly the wrong place for handling stepping info. Add new intel_step.[ch] for the data, and move the stepping arrays there. No functional changes. v2: Rename stepping->step Reviewed-by: Lucas De Marchi Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 39 ----------------- drivers/gpu/drm/i915/i915_drv.h | 19 +-------- drivers/gpu/drm/i915/intel_step.c | 46 +++++++++++++++++++++ drivers/gpu/drm/i915/intel_step.h | 25 +++++++++++ 5 files changed, 74 insertions(+), 56 deletions(-) create mode 100644 drivers/gpu/drm/i915/intel_step.c create mode 100644 drivers/gpu/drm/i915/intel_step.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 14f1ab399ad0..390badf1ad0e 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -52,6 +52,7 @@ i915-y += i915_drv.o \ intel_pm.o \ intel_runtime_pm.o \ intel_sideband.o \ + intel_step.o \ intel_uncore.o \ intel_wakeref.o \ vlv_suspend.o diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index bb2357119792..0eebb9eb7d3c 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -52,45 +52,6 @@ * - Public functions to init or apply the given workaround type. */ -/* - * KBL revision ID ordering is bizarre; higher revision ID's map to lower - * steppings in some cases. So rather than test against the revision ID - * directly, let's map that into our own range of increasing ID's that we - * can test against in a regular manner. - */ - -const struct i915_rev_steppings kbl_revids[] = { - [0] = { .gt_stepping = KBL_REVID_A0, .disp_stepping = KBL_REVID_A0 }, - [1] = { .gt_stepping = KBL_REVID_B0, .disp_stepping = KBL_REVID_B0 }, - [2] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B0 }, - [3] = { .gt_stepping = KBL_REVID_D0, .disp_stepping = KBL_REVID_B0 }, - [4] = { .gt_stepping = KBL_REVID_F0, .disp_stepping = KBL_REVID_C0 }, - [5] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B1 }, - [6] = { .gt_stepping = KBL_REVID_D1, .disp_stepping = KBL_REVID_B1 }, - [7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 }, -}; - -const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = { - [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 }, - [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 }, - [2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 }, - [3] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_D0 }, -}; - -/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */ -const struct i915_rev_steppings tgl_revid_step_tbl[] = { - [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 }, - [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 }, -}; - -const struct i915_rev_steppings adls_revid_step_tbl[] = { - [0x0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 }, - [0x1] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A2 }, - [0x4] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 }, - [0x8] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 }, - [0xC] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_C0 }, -}; - static void wa_init_start(struct i915_wa_list *wal, const char *name, const char *engine_name) { wal->name = name; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index fa596dace490..3fcba7d93db7 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -86,9 +86,10 @@ #include "gt/uc/intel_uc.h" #include "intel_device_info.h" +#include "intel_memory_region.h" #include "intel_pch.h" #include "intel_runtime_pm.h" -#include "intel_memory_region.h" +#include "intel_step.h" #include "intel_uncore.h" #include "intel_wakeref.h" #include "intel_wopcm.h" @@ -1466,14 +1467,6 @@ enum { KBL_REVID_G0, }; -struct i915_rev_steppings { - u8 gt_stepping; - u8 disp_stepping; -}; - -/* Defined in intel_workarounds.c */ -extern const struct i915_rev_steppings kbl_revids[]; - #define IS_KBL_GT_REVID(dev_priv, since, until) \ (IS_KABYLAKE(dev_priv) && \ kbl_revids[INTEL_REVID(dev_priv)].gt_stepping >= since && \ @@ -1522,14 +1515,6 @@ enum { STEP_D0, }; -#define TGL_UY_REVID_STEP_TBL_SIZE 4 -#define TGL_REVID_STEP_TBL_SIZE 2 -#define ADLS_REVID_STEP_TBL_SIZE 13 - -extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE]; -extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE]; -extern const struct i915_rev_steppings adls_revid_step_tbl[ADLS_REVID_STEP_TBL_SIZE]; - static inline const struct i915_rev_steppings * tgl_stepping_get(struct drm_i915_private *dev_priv) { diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c new file mode 100644 index 000000000000..e19820cbe8e3 --- /dev/null +++ b/drivers/gpu/drm/i915/intel_step.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2020,2021 Intel Corporation + */ + +#include "i915_drv.h" +#include "intel_step.h" + +/* + * KBL revision ID ordering is bizarre; higher revision ID's map to lower + * steppings in some cases. So rather than test against the revision ID + * directly, let's map that into our own range of increasing ID's that we + * can test against in a regular manner. + */ + +const struct i915_rev_steppings kbl_revids[] = { + [0] = { .gt_stepping = KBL_REVID_A0, .disp_stepping = KBL_REVID_A0 }, + [1] = { .gt_stepping = KBL_REVID_B0, .disp_stepping = KBL_REVID_B0 }, + [2] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B0 }, + [3] = { .gt_stepping = KBL_REVID_D0, .disp_stepping = KBL_REVID_B0 }, + [4] = { .gt_stepping = KBL_REVID_F0, .disp_stepping = KBL_REVID_C0 }, + [5] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B1 }, + [6] = { .gt_stepping = KBL_REVID_D1, .disp_stepping = KBL_REVID_B1 }, + [7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 }, +}; + +const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = { + [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 }, + [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 }, + [2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 }, + [3] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_D0 }, +}; + +/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */ +const struct i915_rev_steppings tgl_revid_step_tbl[] = { + [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 }, + [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 }, +}; + +const struct i915_rev_steppings adls_revid_step_tbl[] = { + [0x0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 }, + [0x1] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A2 }, + [0x4] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 }, + [0x8] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 }, + [0xC] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_C0 }, +}; diff --git a/drivers/gpu/drm/i915/intel_step.h b/drivers/gpu/drm/i915/intel_step.h new file mode 100644 index 000000000000..af922ae3bb4e --- /dev/null +++ b/drivers/gpu/drm/i915/intel_step.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2020,2021 Intel Corporation + */ + +#ifndef __INTEL_STEP_H__ +#define __INTEL_STEP_H__ + +#include + +struct i915_rev_steppings { + u8 gt_stepping; + u8 disp_stepping; +}; + +#define TGL_UY_REVID_STEP_TBL_SIZE 4 +#define TGL_REVID_STEP_TBL_SIZE 2 +#define ADLS_REVID_STEP_TBL_SIZE 13 + +extern const struct i915_rev_steppings kbl_revids[]; +extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE]; +extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE]; +extern const struct i915_rev_steppings adls_revid_step_tbl[ADLS_REVID_STEP_TBL_SIZE]; + +#endif /* __INTEL_STEP_H__ */ From patchwork Fri Mar 26 13:21:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 12166621 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A479C433C1 for ; Fri, 26 Mar 2021 13:21:58 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3A7AD61A06 for ; Fri, 26 Mar 2021 13:21:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3A7AD61A06 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BCB866F3D0; Fri, 26 Mar 2021 13:21:57 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0F3F76F3D0 for ; Fri, 26 Mar 2021 13:21:57 +0000 (UTC) IronPort-SDR: OelCu17690g9JmNZz2JFTc7k5VNMfdH7WbDc1sXLTnzFMsfJuCYxHjhYPU0txXhydcrGqo/KDw 1cPYQKcdQSVg== X-IronPort-AV: E=McAfee;i="6000,8403,9934"; a="187858190" X-IronPort-AV: E=Sophos;i="5.81,280,1610438400"; d="scan'208";a="187858190" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2021 06:21:56 -0700 IronPort-SDR: mfsjvbrsJXC3ThLPFUzhQkpRPdyuTNd6AG15sjbvAlRdTVQBqZ0qDr9q0sHedSHvDRYqEbgQ0M tMb4F3x8aGdA== X-IronPort-AV: E=Sophos;i="5.81,280,1610438400"; d="scan'208";a="409896408" Received: from mpaulits-mobl1.ger.corp.intel.com (HELO localhost) ([10.252.55.191]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2021 06:21:54 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Fri, 26 Mar 2021 15:21:33 +0200 Message-Id: X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 2/7] drm/i915: add new helpers for accessing stepping info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add new runtime info field for stepping. Add new helpers for accessing them. As we'll be switching platforms over to the new scheme incrementally, check for non-initialized steppings. In case a platform does not have separate display and gt steppings, it's okay to use a common shorthand. However, in this case the display stepping must not be initialized, and gt stepping is the single point of truth. v3: Remove IS_STEP() (José) v2: Rename stepping->step Reviewed-by: José Roberto de Souza Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 20 +++++++++++--------- drivers/gpu/drm/i915/intel_device_info.h | 4 ++++ drivers/gpu/drm/i915/intel_step.h | 14 ++++++++++++++ 3 files changed, 29 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3fcba7d93db7..380088fd6dcf 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1268,6 +1268,17 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) #define IS_REVID(p, since, until) \ (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) +#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.disp_stepping) +#define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_stepping) + +#define IS_DISPLAY_STEP(__i915, since, until) \ + (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \ + INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) <= (until)) + +#define IS_GT_STEP(__i915, since, until) \ + (drm_WARN_ON(&(__i915)->drm, INTEL_GT_STEP(__i915) == STEP_NONE), \ + INTEL_GT_STEP(__i915) >= (since) && INTEL_GT_STEP(__i915) <= (until)) + static __always_inline unsigned int __platform_mask_index(const struct intel_runtime_info *info, enum intel_platform p) @@ -1506,15 +1517,6 @@ enum { #define IS_JSL_EHL_REVID(p, since, until) \ (IS_JSL_EHL(p) && IS_REVID(p, since, until)) -enum { - STEP_A0, - STEP_A2, - STEP_B0, - STEP_B1, - STEP_C0, - STEP_D0, -}; - static inline const struct i915_rev_steppings * tgl_stepping_get(struct drm_i915_private *dev_priv) { diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 90acbaf800d5..e410635cb4ea 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -27,6 +27,8 @@ #include +#include "intel_step.h" + #include "display/intel_display.h" #include "gt/intel_engine_types.h" @@ -227,6 +229,8 @@ struct intel_runtime_info { u8 num_scalers[I915_MAX_PIPES]; u32 rawclk_freq; + + struct i915_rev_steppings step; }; struct intel_driver_caps { diff --git a/drivers/gpu/drm/i915/intel_step.h b/drivers/gpu/drm/i915/intel_step.h index af922ae3bb4e..8b3ef19d935b 100644 --- a/drivers/gpu/drm/i915/intel_step.h +++ b/drivers/gpu/drm/i915/intel_step.h @@ -22,4 +22,18 @@ extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_T extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE]; extern const struct i915_rev_steppings adls_revid_step_tbl[ADLS_REVID_STEP_TBL_SIZE]; +/* + * Symbolic steppings that do not match the hardware. These are valid both as gt + * and display steppings as symbolic names. + */ +enum intel_step { + STEP_NONE = 0, + STEP_A0, + STEP_A2, + STEP_B0, + STEP_B1, + STEP_C0, + STEP_D0, +}; + #endif /* __INTEL_STEP_H__ */ From patchwork Fri Mar 26 13:21:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 12166623 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7722FC433C1 for ; Fri, 26 Mar 2021 13:22:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1C3E861A18 for ; Fri, 26 Mar 2021 13:22:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1C3E861A18 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 880916F3D1; Fri, 26 Mar 2021 13:22:03 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id CBC786F3D1 for ; Fri, 26 Mar 2021 13:22:02 +0000 (UTC) IronPort-SDR: byFG/NBOtmgrLq0J+kFeSXY8zWFDAfZkEDkVO8QCp7T2RU5ld+4KDMrnjbiEfXoirK1W0ZBOlE ZnYD5cmKq5iw== X-IronPort-AV: E=McAfee;i="6000,8403,9934"; a="190584873" X-IronPort-AV: E=Sophos;i="5.81,280,1610438400"; d="scan'208";a="190584873" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2021 06:22:01 -0700 IronPort-SDR: 4wlUso6ZFxLlSDWt6qxLKhh6syRiaLqjZY9NGsmbjluwbbVbJUsnBm/rbVNLe7QfCD81e1s3wO 2bcOeTNdoMUw== X-IronPort-AV: E=Sophos;i="5.81,280,1610438400"; d="scan'208";a="416532615" Received: from mpaulits-mobl1.ger.corp.intel.com (HELO localhost) ([10.252.55.191]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2021 06:21:59 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Fri, 26 Mar 2021 15:21:34 +0200 Message-Id: <79b6c48211c6b214165391d350d556bad748f747.1616764798.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 3/7] drm/i915: switch KBL to the new stepping scheme X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add new symbolic names for revision ids, and convert KBL revids to use them via the new stepping check macros. This also fixes theoretical out of bounds access to kbl_revids array. v3: upgrade dbg to warn on unknown revid (José) v2: Rename stepping->step Reviewed-by: José Roberto de Souza Signed-off-by: Jani Nikula --- The initialization sounds like an early part of intel_device_info_runtime_init(), and indeed touches runtime info. --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +- drivers/gpu/drm/i915/i915_drv.c | 3 +- drivers/gpu/drm/i915/i915_drv.h | 24 ++----- drivers/gpu/drm/i915/intel_pm.c | 4 +- drivers/gpu/drm/i915/intel_step.c | 69 ++++++++++++++++++--- drivers/gpu/drm/i915/intel_step.h | 11 +++- 7 files changed, 82 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index 4b69ede3485d..732c2ed1d933 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c @@ -42,7 +42,7 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode) vf_flush_wa = true; /* WaForGAMHang:kbl */ - if (IS_KBL_GT_REVID(rq->engine->i915, 0, KBL_REVID_B0)) + if (IS_KBL_GT_STEP(rq->engine->i915, 0, STEP_B0)) dc_flush_wa = true; } diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 0eebb9eb7d3c..9af01277e51f 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -481,7 +481,7 @@ static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine, gen9_ctx_workarounds_init(engine, wal); /* WaToEnableHwFixForPushConstHWBug:kbl */ - if (IS_KBL_GT_REVID(i915, KBL_REVID_C0, REVID_FOREVER)) + if (IS_KBL_GT_STEP(i915, STEP_C0, STEP_FOREVER)) wa_masked_en(wal, COMMON_SLICE_CHICKEN2, GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); @@ -899,7 +899,7 @@ kbl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) gen9_gt_workarounds_init(i915, wal); /* WaDisableDynamicCreditSharing:kbl */ - if (IS_KBL_GT_REVID(i915, 0, KBL_REVID_B0)) + if (IS_KBL_GT_STEP(i915, 0, STEP_B0)) wa_write_or(wal, GAMT_CHKN_BIT_REG, GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); @@ -2020,7 +2020,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) struct drm_i915_private *i915 = engine->i915; /* WaKBLVECSSemaphoreWaitPoll:kbl */ - if (IS_KBL_GT_REVID(i915, KBL_REVID_A0, KBL_REVID_E0)) { + if (IS_KBL_GT_STEP(i915, STEP_A0, STEP_E0)) { wa_write(wal, RING_SEMA_WAIT_POLL(engine->mmio_base), 1); diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index b2018e85afc2..c2329bc44f55 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -272,7 +272,7 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv) pre |= IS_HSW_EARLY_SDV(dev_priv); pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0); pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST); - pre |= IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_A0); + pre |= IS_KBL_GT_STEP(dev_priv, 0, STEP_A0); pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2); if (pre) { @@ -306,6 +306,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv) return -ENODEV; intel_device_info_subplatform_init(dev_priv); + intel_step_init(dev_priv); intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug); intel_uncore_init_early(&dev_priv->uncore, dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 380088fd6dcf..ff392f7c8507 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1466,26 +1466,10 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_BXT_REVID(dev_priv, since, until) \ (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) -enum { - KBL_REVID_A0, - KBL_REVID_B0, - KBL_REVID_B1, - KBL_REVID_C0, - KBL_REVID_D0, - KBL_REVID_D1, - KBL_REVID_E0, - KBL_REVID_F0, - KBL_REVID_G0, -}; - -#define IS_KBL_GT_REVID(dev_priv, since, until) \ - (IS_KABYLAKE(dev_priv) && \ - kbl_revids[INTEL_REVID(dev_priv)].gt_stepping >= since && \ - kbl_revids[INTEL_REVID(dev_priv)].gt_stepping <= until) -#define IS_KBL_DISP_REVID(dev_priv, since, until) \ - (IS_KABYLAKE(dev_priv) && \ - kbl_revids[INTEL_REVID(dev_priv)].disp_stepping >= since && \ - kbl_revids[INTEL_REVID(dev_priv)].disp_stepping <= until) +#define IS_KBL_GT_STEP(dev_priv, since, until) \ + (IS_KABYLAKE(dev_priv) && IS_GT_STEP(dev_priv, since, until)) +#define IS_KBL_DISPLAY_STEP(dev_priv, since, until) \ + (IS_KABYLAKE(dev_priv) && IS_DISPLAY_STEP(dev_priv, since, until)) #define GLK_REVID_A0 0x0 #define GLK_REVID_A1 0x1 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b2aede2be89d..e2dd3140eb0b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7233,12 +7233,12 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv) FBC_LLC_FULLY_OPEN); /* WaDisableSDEUnitClockGating:kbl */ - if (IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_B0)) + if (IS_KBL_GT_STEP(dev_priv, 0, STEP_B0)) intel_uncore_write(&dev_priv->uncore, GEN8_UCGCTL6, intel_uncore_read(&dev_priv->uncore, GEN8_UCGCTL6) | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); /* WaDisableGamClockGating:kbl */ - if (IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_B0)) + if (IS_KBL_GT_STEP(dev_priv, 0, STEP_B0)) intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1, intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) | GEN6_GAMUNIT_CLOCK_GATE_DISABLE); diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c index e19820cbe8e3..e9ff481b2eda 100644 --- a/drivers/gpu/drm/i915/intel_step.c +++ b/drivers/gpu/drm/i915/intel_step.c @@ -13,15 +13,17 @@ * can test against in a regular manner. */ -const struct i915_rev_steppings kbl_revids[] = { - [0] = { .gt_stepping = KBL_REVID_A0, .disp_stepping = KBL_REVID_A0 }, - [1] = { .gt_stepping = KBL_REVID_B0, .disp_stepping = KBL_REVID_B0 }, - [2] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B0 }, - [3] = { .gt_stepping = KBL_REVID_D0, .disp_stepping = KBL_REVID_B0 }, - [4] = { .gt_stepping = KBL_REVID_F0, .disp_stepping = KBL_REVID_C0 }, - [5] = { .gt_stepping = KBL_REVID_C0, .disp_stepping = KBL_REVID_B1 }, - [6] = { .gt_stepping = KBL_REVID_D1, .disp_stepping = KBL_REVID_B1 }, - [7] = { .gt_stepping = KBL_REVID_G0, .disp_stepping = KBL_REVID_C0 }, + +/* FIXME: what about REVID_E0 */ +static const struct i915_rev_steppings kbl_revids[] = { + [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 }, + [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 }, + [2] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 }, + [3] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_B0 }, + [4] = { .gt_stepping = STEP_F0, .disp_stepping = STEP_C0 }, + [5] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B1 }, + [6] = { .gt_stepping = STEP_D1, .disp_stepping = STEP_B1 }, + [7] = { .gt_stepping = STEP_G0, .disp_stepping = STEP_C0 }, }; const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = { @@ -44,3 +46,52 @@ const struct i915_rev_steppings adls_revid_step_tbl[] = { [0x8] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 }, [0xC] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_C0 }, }; + +void intel_step_init(struct drm_i915_private *i915) +{ + const struct i915_rev_steppings *revids = NULL; + int size = 0; + int revid = INTEL_REVID(i915); + struct i915_rev_steppings step = {}; + + if (IS_KABYLAKE(i915)) { + revids = kbl_revids; + size = ARRAY_SIZE(kbl_revids); + } + + /* Not using the stepping scheme for the platform yet. */ + if (!revids) + return; + + if (revid < size && revids[revid].gt_stepping != STEP_NONE) { + step = revids[revid]; + } else { + drm_warn(&i915->drm, "Unknown revid 0x%02x\n", revid); + + /* + * If we hit a gap in the revid array, use the information for + * the next revid. + * + * This may be wrong in all sorts of ways, especially if the + * steppings in the array are not monotonically increasing, but + * it's better than defaulting to 0. + */ + while (revid < size && revids[revid].gt_stepping == STEP_NONE) + revid++; + + if (revid < size) { + drm_dbg(&i915->drm, "Using steppings for revid 0x%02x\n", + revid); + step = revids[revid]; + } else { + drm_dbg(&i915->drm, "Using future steppings\n"); + step.gt_stepping = STEP_FUTURE; + step.disp_stepping = STEP_FUTURE; + } + } + + if (drm_WARN_ON(&i915->drm, step.gt_stepping == STEP_NONE)) + return; + + RUNTIME_INFO(i915)->step = step; +} diff --git a/drivers/gpu/drm/i915/intel_step.h b/drivers/gpu/drm/i915/intel_step.h index 8b3ef19d935b..b29e15f71214 100644 --- a/drivers/gpu/drm/i915/intel_step.h +++ b/drivers/gpu/drm/i915/intel_step.h @@ -8,6 +8,8 @@ #include +struct drm_i915_private; + struct i915_rev_steppings { u8 gt_stepping; u8 disp_stepping; @@ -17,7 +19,6 @@ struct i915_rev_steppings { #define TGL_REVID_STEP_TBL_SIZE 2 #define ADLS_REVID_STEP_TBL_SIZE 13 -extern const struct i915_rev_steppings kbl_revids[]; extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE]; extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE]; extern const struct i915_rev_steppings adls_revid_step_tbl[ADLS_REVID_STEP_TBL_SIZE]; @@ -34,6 +35,14 @@ enum intel_step { STEP_B1, STEP_C0, STEP_D0, + STEP_D1, + STEP_E0, + STEP_F0, + STEP_G0, + STEP_FUTURE, + STEP_FOREVER, }; +void intel_step_init(struct drm_i915_private *i915); + #endif /* __INTEL_STEP_H__ */ From patchwork Fri Mar 26 13:21:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 12166625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2FF0C433DB for ; Fri, 26 Mar 2021 13:22:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 66B9761A06 for ; Fri, 26 Mar 2021 13:22:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 66B9761A06 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E68D36F3D8; Fri, 26 Mar 2021 13:22:07 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 828706F3D5 for ; Fri, 26 Mar 2021 13:22:06 +0000 (UTC) IronPort-SDR: x+eB/IARdHHin951fa3pG2nEb3rax29MpSyEg0UCGWkTwdtZnwtaxMNAn+Kb6fhICWOnC62SJm Yc1sKRf/i9Yg== X-IronPort-AV: E=McAfee;i="6000,8403,9934"; a="188870128" X-IronPort-AV: E=Sophos;i="5.81,280,1610438400"; d="scan'208";a="188870128" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2021 06:22:06 -0700 IronPort-SDR: 1oWMCM1qhRax9a31iZLqAOj/12Wl1CRZyJ25eIG0Rqsc4jpwdnbBgRYcRg2Hzaeae7UbCl42Rl vru6fN8ARqJg== X-IronPort-AV: E=Sophos;i="5.81,280,1610438400"; d="scan'208";a="409896437" Received: from mpaulits-mobl1.ger.corp.intel.com (HELO localhost) ([10.252.55.191]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2021 06:22:04 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Fri, 26 Mar 2021 15:21:35 +0200 Message-Id: <756fe3d75b1e91ef812fc1fd3f70337e9c571d91.1616764798.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 4/7] drm/i915: switch TGL and ADL to the new stepping scheme X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" This changes the way revids not present in the array are handled: - For gaps in the array, the next present revid is used. - For revids beyond the array, the new STEP_FUTURE is used instead of the last revid in the array. In both cases, we'll get debug logging of what's going on. v2: Rename stepping->step Reviewed-by: José Roberto de Souza Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 59 ++++++++----------------------- drivers/gpu/drm/i915/intel_step.c | 17 ++++++--- drivers/gpu/drm/i915/intel_step.h | 8 ----- 3 files changed, 28 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ff392f7c8507..d1d253f7132d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1501,44 +1501,17 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_JSL_EHL_REVID(p, since, until) \ (IS_JSL_EHL(p) && IS_REVID(p, since, until)) -static inline const struct i915_rev_steppings * -tgl_stepping_get(struct drm_i915_private *dev_priv) -{ - u8 revid = INTEL_REVID(dev_priv); - u8 size; - const struct i915_rev_steppings *revid_step_tbl; - - if (IS_ALDERLAKE_S(dev_priv)) { - revid_step_tbl = adls_revid_step_tbl; - size = ARRAY_SIZE(adls_revid_step_tbl); - } else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) { - revid_step_tbl = tgl_uy_revid_step_tbl; - size = ARRAY_SIZE(tgl_uy_revid_step_tbl); - } else { - revid_step_tbl = tgl_revid_step_tbl; - size = ARRAY_SIZE(tgl_revid_step_tbl); - } - - revid = min_t(u8, revid, size - 1); - - return &revid_step_tbl[revid]; -} - -#define IS_TGL_DISP_STEPPING(p, since, until) \ - (IS_TIGERLAKE(p) && \ - tgl_stepping_get(p)->disp_stepping >= (since) && \ - tgl_stepping_get(p)->disp_stepping <= (until)) +#define IS_TGL_DISP_STEPPING(__i915, since, until) \ + (IS_TIGERLAKE(__i915) && \ + IS_DISPLAY_STEP(__i915, since, until)) -#define IS_TGL_UY_GT_STEPPING(p, since, until) \ - ((IS_TGL_U(p) || IS_TGL_Y(p)) && \ - tgl_stepping_get(p)->gt_stepping >= (since) && \ - tgl_stepping_get(p)->gt_stepping <= (until)) +#define IS_TGL_UY_GT_STEPPING(__i915, since, until) \ + ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ + IS_GT_STEP(__i915, since, until)) -#define IS_TGL_GT_STEPPING(p, since, until) \ - (IS_TIGERLAKE(p) && \ - !(IS_TGL_U(p) || IS_TGL_Y(p)) && \ - tgl_stepping_get(p)->gt_stepping >= (since) && \ - tgl_stepping_get(p)->gt_stepping <= (until)) +#define IS_TGL_GT_STEPPING(__i915, since, until) \ + (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ + IS_GT_STEP(__i915, since, until)) #define RKL_REVID_A0 0x0 #define RKL_REVID_B0 0x1 @@ -1553,15 +1526,13 @@ tgl_stepping_get(struct drm_i915_private *dev_priv) #define IS_DG1_REVID(p, since, until) \ (IS_DG1(p) && IS_REVID(p, since, until)) -#define IS_ADLS_DISP_STEPPING(p, since, until) \ - (IS_ALDERLAKE_S(p) && \ - tgl_stepping_get(p)->disp_stepping >= (since) && \ - tgl_stepping_get(p)->disp_stepping <= (until)) +#define IS_ADLS_DISP_STEPPING(__i915, since, until) \ + (IS_ALDERLAKE_S(__i915) && \ + IS_DISPLAY_STEP(__i915, since, until)) -#define IS_ADLS_GT_STEPPING(p, since, until) \ - (IS_ALDERLAKE_S(p) && \ - tgl_stepping_get(p)->gt_stepping >= (since) && \ - tgl_stepping_get(p)->gt_stepping <= (until)) +#define IS_ADLS_GT_STEPPING(__i915, since, until) \ + (IS_ALDERLAKE_S(__i915) && \ + IS_GT_STEP(__i915, since, until)) #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv)) diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c index e9ff481b2eda..f6298622c53e 100644 --- a/drivers/gpu/drm/i915/intel_step.c +++ b/drivers/gpu/drm/i915/intel_step.c @@ -26,7 +26,7 @@ static const struct i915_rev_steppings kbl_revids[] = { [7] = { .gt_stepping = STEP_G0, .disp_stepping = STEP_C0 }, }; -const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = { +static const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = { [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 }, [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 }, [2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 }, @@ -34,12 +34,12 @@ const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = { }; /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */ -const struct i915_rev_steppings tgl_revid_step_tbl[] = { +static const struct i915_rev_steppings tgl_revid_step_tbl[] = { [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 }, [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 }, }; -const struct i915_rev_steppings adls_revid_step_tbl[] = { +static const struct i915_rev_steppings adls_revid_step_tbl[] = { [0x0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 }, [0x1] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A2 }, [0x4] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 }, @@ -54,7 +54,16 @@ void intel_step_init(struct drm_i915_private *i915) int revid = INTEL_REVID(i915); struct i915_rev_steppings step = {}; - if (IS_KABYLAKE(i915)) { + if (IS_ALDERLAKE_S(i915)) { + revids = adls_revid_step_tbl; + size = ARRAY_SIZE(adls_revid_step_tbl); + } else if (IS_TGL_U(i915) || IS_TGL_Y(i915)) { + revids = tgl_uy_revid_step_tbl; + size = ARRAY_SIZE(tgl_uy_revid_step_tbl); + } else if (IS_TIGERLAKE(i915)) { + revids = tgl_revid_step_tbl; + size = ARRAY_SIZE(tgl_revid_step_tbl); + } else if (IS_KABYLAKE(i915)) { revids = kbl_revids; size = ARRAY_SIZE(kbl_revids); } diff --git a/drivers/gpu/drm/i915/intel_step.h b/drivers/gpu/drm/i915/intel_step.h index b29e15f71214..5cc5601794f0 100644 --- a/drivers/gpu/drm/i915/intel_step.h +++ b/drivers/gpu/drm/i915/intel_step.h @@ -15,14 +15,6 @@ struct i915_rev_steppings { u8 disp_stepping; }; -#define TGL_UY_REVID_STEP_TBL_SIZE 4 -#define TGL_REVID_STEP_TBL_SIZE 2 -#define ADLS_REVID_STEP_TBL_SIZE 13 - -extern const struct i915_rev_steppings tgl_uy_revid_step_tbl[TGL_UY_REVID_STEP_TBL_SIZE]; -extern const struct i915_rev_steppings tgl_revid_step_tbl[TGL_REVID_STEP_TBL_SIZE]; -extern const struct i915_rev_steppings adls_revid_step_tbl[ADLS_REVID_STEP_TBL_SIZE]; - /* * Symbolic steppings that do not match the hardware. These are valid both as gt * and display steppings as symbolic names. From patchwork Fri Mar 26 13:21:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 12166627 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE279C433DB for ; Fri, 26 Mar 2021 13:22:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7CF1361A06 for ; Fri, 26 Mar 2021 13:22:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7CF1361A06 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 090C26F3DA; Fri, 26 Mar 2021 13:22:15 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 485066F3DD for ; Fri, 26 Mar 2021 13:22:13 +0000 (UTC) IronPort-SDR: n05mTiOJx4L5J7hBSzQJzZFVgn5H3dRRqXtfNfw+qhVoU3fMDadNV94+L3lcHqpjH7iSTq640K BnPjcLrbhLWA== X-IronPort-AV: E=McAfee;i="6000,8403,9934"; a="190584891" X-IronPort-AV: E=Sophos;i="5.81,280,1610438400"; d="scan'208";a="190584891" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2021 06:22:12 -0700 IronPort-SDR: oVX/pgmhxskq2Xy9g7FbiPl5aPOOsnfq4KqqBBmaNcTIVPECtNFOjTh2XkxPJGvcf1ebiNoB8R 1xE0L4l4TDQQ== X-IronPort-AV: E=Sophos;i="5.81,280,1610438400"; d="scan'208";a="453508678" Received: from mpaulits-mobl1.ger.corp.intel.com (HELO localhost) ([10.252.55.191]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2021 06:22:09 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Fri, 26 Mar 2021 15:21:36 +0200 Message-Id: X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 5/7] drm/i915: rename DISP_STEPPING->DISPLAY_STEP and GT_STEPPING->GT_STEP X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Matter of taste. STEP matches the enums. Reviewed-by: José Roberto de Souza Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 4 ++-- drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +- drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++----- drivers/gpu/drm/i915/i915_drv.h | 10 +++++----- drivers/gpu/drm/i915/intel_device_info.c | 2 +- drivers/gpu/drm/i915/intel_pm.c | 2 +- 7 files changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index cef177208e68..99126caf5747 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -5333,7 +5333,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) if (IS_ALDERLAKE_S(dev_priv) || IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) || - IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B0)) + IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) /* Wa_1409767108:tgl,dg1,adl-s */ table = wa_1409767108_buddy_page_masks; else diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index d05f9aaa8c06..1d561812fcad 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -548,7 +548,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) if (intel_dp->psr.psr2_sel_fetch_enabled) { /* WA 1408330847 */ - if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) || + if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) || IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)) intel_de_rmw(dev_priv, CHICKEN_PAR1_1, DIS_RAM_BYPASS_PSR2_MAN_TRACK, @@ -1109,7 +1109,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) /* WA 1408330847 */ if (intel_dp->psr.psr2_sel_fetch_enabled && - (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0) || + (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0) || IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))) intel_de_rmw(dev_priv, CHICKEN_PAR1_1, DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0); diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index c6d7b6c054b5..245c10221538 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1858,7 +1858,7 @@ static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv, { /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */ if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) || - IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_C0)) + IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) return false; return plane_id < PLANE_SPRITE4; diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 9af01277e51f..2c6f7217469f 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1091,19 +1091,19 @@ tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) gen12_gt_workarounds_init(i915, wal); /* Wa_1409420604:tgl */ - if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) + if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) wa_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS); /* Wa_1607087056:tgl also know as BUG:1409180338 */ - if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) + if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) wa_write_or(wal, SLICE_UNIT_LEVEL_CLKGATE, L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS); /* Wa_1408615072:tgl[a0] */ - if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) + if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL); } @@ -1581,7 +1581,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) struct drm_i915_private *i915 = engine->i915; if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) || - IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) { + IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) { /* * Wa_1607138336:tgl[a0],dg1[a0] * Wa_1607063988:tgl[a0],dg1[a0] @@ -1591,7 +1591,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN12_DISABLE_POSH_BUSY_FF_DOP_CG); } - if (IS_TGL_UY_GT_STEPPING(i915, STEP_A0, STEP_A0)) { + if (IS_TGL_UY_GT_STEP(i915, STEP_A0, STEP_A0)) { /* * Wa_1606679103:tgl * (see also Wa_1606682166:icl) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d1d253f7132d..7520e5fd8cff 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1501,15 +1501,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_JSL_EHL_REVID(p, since, until) \ (IS_JSL_EHL(p) && IS_REVID(p, since, until)) -#define IS_TGL_DISP_STEPPING(__i915, since, until) \ +#define IS_TGL_DISPLAY_STEP(__i915, since, until) \ (IS_TIGERLAKE(__i915) && \ IS_DISPLAY_STEP(__i915, since, until)) -#define IS_TGL_UY_GT_STEPPING(__i915, since, until) \ +#define IS_TGL_UY_GT_STEP(__i915, since, until) \ ((IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ IS_GT_STEP(__i915, since, until)) -#define IS_TGL_GT_STEPPING(__i915, since, until) \ +#define IS_TGL_GT_STEP(__i915, since, until) \ (IS_TIGERLAKE(__i915) && !(IS_TGL_U(__i915) || IS_TGL_Y(__i915)) && \ IS_GT_STEP(__i915, since, until)) @@ -1526,11 +1526,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_DG1_REVID(p, since, until) \ (IS_DG1(p) && IS_REVID(p, since, until)) -#define IS_ADLS_DISP_STEPPING(__i915, since, until) \ +#define IS_ADLS_DISPLAY_STEP(__i915, since, until) \ (IS_ALDERLAKE_S(__i915) && \ IS_DISPLAY_STEP(__i915, since, until)) -#define IS_ADLS_GT_STEPPING(__i915, since, until) \ +#define IS_ADLS_GT_STEP(__i915, since, until) \ (IS_ALDERLAKE_S(__i915) && \ IS_GT_STEP(__i915, since, until)) diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index aeb28d589b2b..de02207f6ec6 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -251,7 +251,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) enum pipe pipe; /* Wa_14011765242: adl-s A0 */ - if (IS_ADLS_DISP_STEPPING(dev_priv, STEP_A0, STEP_A0)) + if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A0)) for_each_pipe(dev_priv, pipe) runtime->num_scalers[pipe] = 0; else if (INTEL_GEN(dev_priv) >= 10) { diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e2dd3140eb0b..066abaa73a06 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7134,7 +7134,7 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL); /* Wa_1409825376:tgl (pre-prod)*/ - if (IS_TGL_DISP_STEPPING(dev_priv, STEP_A0, STEP_B1)) + if (IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B1)) intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) | TGL_VRH_GATING_DIS); From patchwork Fri Mar 26 13:21:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 12166629 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58C77C433DB for ; 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a="276287740" X-IronPort-AV: E=Sophos;i="5.81,280,1610438400"; d="scan'208";a="276287740" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2021 06:22:17 -0700 IronPort-SDR: 2y5vTv5B6iyRg2Mvah2iL0uup5E07OMw0PaR1exzSbzf1jhzg9I7tmUQdepk3C+j9GZRO0yjmy /E/qn4b3rg5g== X-IronPort-AV: E=Sophos;i="5.81,280,1610438400"; d="scan'208";a="515063643" Received: from mpaulits-mobl1.ger.corp.intel.com (HELO localhost) ([10.252.55.191]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2021 06:22:15 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Fri, 26 Mar 2021 15:21:37 +0200 Message-Id: <1724c8bde0e0f596240437d72ace60b9c34ae9db.1616764798.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 6/7] drm/i915: rename disp_stepping->display_step and gt_stepping->gt_step X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Matter of taste. Step matches the enums. Reviewed-by: José Roberto de Souza Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.h | 4 +-- drivers/gpu/drm/i915/intel_step.c | 48 +++++++++++++++---------------- drivers/gpu/drm/i915/intel_step.h | 4 +-- 3 files changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 7520e5fd8cff..69e43bf91a15 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1268,8 +1268,8 @@ static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) #define IS_REVID(p, since, until) \ (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) -#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.disp_stepping) -#define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_stepping) +#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step) +#define INTEL_GT_STEP(__i915) (RUNTIME_INFO(__i915)->step.gt_step) #define IS_DISPLAY_STEP(__i915, since, until) \ (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \ diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c index f6298622c53e..7ad3acc80564 100644 --- a/drivers/gpu/drm/i915/intel_step.c +++ b/drivers/gpu/drm/i915/intel_step.c @@ -16,35 +16,35 @@ /* FIXME: what about REVID_E0 */ static const struct i915_rev_steppings kbl_revids[] = { - [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 }, - [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 }, - [2] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 }, - [3] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_B0 }, - [4] = { .gt_stepping = STEP_F0, .disp_stepping = STEP_C0 }, - [5] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B1 }, - [6] = { .gt_stepping = STEP_D1, .disp_stepping = STEP_B1 }, - [7] = { .gt_stepping = STEP_G0, .disp_stepping = STEP_C0 }, + [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 }, + [1] = { .gt_step = STEP_B0, .display_step = STEP_B0 }, + [2] = { .gt_step = STEP_C0, .display_step = STEP_B0 }, + [3] = { .gt_step = STEP_D0, .display_step = STEP_B0 }, + [4] = { .gt_step = STEP_F0, .display_step = STEP_C0 }, + [5] = { .gt_step = STEP_C0, .display_step = STEP_B1 }, + [6] = { .gt_step = STEP_D1, .display_step = STEP_B1 }, + [7] = { .gt_step = STEP_G0, .display_step = STEP_C0 }, }; static const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = { - [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 }, - [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_C0 }, - [2] = { .gt_stepping = STEP_B1, .disp_stepping = STEP_C0 }, - [3] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_D0 }, + [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 }, + [1] = { .gt_step = STEP_B0, .display_step = STEP_C0 }, + [2] = { .gt_step = STEP_B1, .display_step = STEP_C0 }, + [3] = { .gt_step = STEP_C0, .display_step = STEP_D0 }, }; /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */ static const struct i915_rev_steppings tgl_revid_step_tbl[] = { - [0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_B0 }, - [1] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_D0 }, + [0] = { .gt_step = STEP_A0, .display_step = STEP_B0 }, + [1] = { .gt_step = STEP_B0, .display_step = STEP_D0 }, }; static const struct i915_rev_steppings adls_revid_step_tbl[] = { - [0x0] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A0 }, - [0x1] = { .gt_stepping = STEP_A0, .disp_stepping = STEP_A2 }, - [0x4] = { .gt_stepping = STEP_B0, .disp_stepping = STEP_B0 }, - [0x8] = { .gt_stepping = STEP_C0, .disp_stepping = STEP_B0 }, - [0xC] = { .gt_stepping = STEP_D0, .disp_stepping = STEP_C0 }, + [0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 }, + [0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 }, + [0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0 }, + [0x8] = { .gt_step = STEP_C0, .display_step = STEP_B0 }, + [0xC] = { .gt_step = STEP_D0, .display_step = STEP_C0 }, }; void intel_step_init(struct drm_i915_private *i915) @@ -72,7 +72,7 @@ void intel_step_init(struct drm_i915_private *i915) if (!revids) return; - if (revid < size && revids[revid].gt_stepping != STEP_NONE) { + if (revid < size && revids[revid].gt_step != STEP_NONE) { step = revids[revid]; } else { drm_warn(&i915->drm, "Unknown revid 0x%02x\n", revid); @@ -85,7 +85,7 @@ void intel_step_init(struct drm_i915_private *i915) * steppings in the array are not monotonically increasing, but * it's better than defaulting to 0. */ - while (revid < size && revids[revid].gt_stepping == STEP_NONE) + while (revid < size && revids[revid].gt_step == STEP_NONE) revid++; if (revid < size) { @@ -94,12 +94,12 @@ void intel_step_init(struct drm_i915_private *i915) step = revids[revid]; } else { drm_dbg(&i915->drm, "Using future steppings\n"); - step.gt_stepping = STEP_FUTURE; - step.disp_stepping = STEP_FUTURE; + step.gt_step = STEP_FUTURE; + step.display_step = STEP_FUTURE; } } - if (drm_WARN_ON(&i915->drm, step.gt_stepping == STEP_NONE)) + if (drm_WARN_ON(&i915->drm, step.gt_step == STEP_NONE)) return; RUNTIME_INFO(i915)->step = step; diff --git a/drivers/gpu/drm/i915/intel_step.h b/drivers/gpu/drm/i915/intel_step.h index 5cc5601794f0..102fd6a26893 100644 --- a/drivers/gpu/drm/i915/intel_step.h +++ b/drivers/gpu/drm/i915/intel_step.h @@ -11,8 +11,8 @@ struct drm_i915_private; struct i915_rev_steppings { - u8 gt_stepping; - u8 disp_stepping; + u8 gt_step; + u8 display_step; }; /* From patchwork Fri Mar 26 13:21:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jani Nikula X-Patchwork-Id: 12166631 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CE27C433C1 for ; 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a="178263376" X-IronPort-AV: E=Sophos;i="5.81,280,1610438400"; d="scan'208";a="178263376" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2021 06:22:25 -0700 IronPort-SDR: D2QzZhOcFbLLEvd/VLmU8pP1aF4EMBND6USrWemyhD+Fo5FBQFDL7H1vIWh2dA4Oqvks1Fv7NL 16jZKUmImYxQ== X-IronPort-AV: E=Sophos;i="5.81,280,1610438400"; d="scan'208";a="392209642" Received: from mpaulits-mobl1.ger.corp.intel.com (HELO localhost) ([10.252.55.191]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Mar 2021 06:22:20 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org Date: Fri, 26 Mar 2021 15:21:38 +0200 Message-Id: X-Mailer: git-send-email 2.20.1 In-Reply-To: References: MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v4 7/7] drm/i915: rename i915_rev_steppings->intel_step_info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Matter of taste. Match the prefix for everything else related to steppings. No functional changes. Reviewed-by: José Roberto de Souza Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_device_info.h | 2 +- drivers/gpu/drm/i915/intel_step.c | 12 ++++++------ drivers/gpu/drm/i915/intel_step.h | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index e410635cb4ea..2f442d418a15 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -230,7 +230,7 @@ struct intel_runtime_info { u32 rawclk_freq; - struct i915_rev_steppings step; + struct intel_step_info step; }; struct intel_driver_caps { diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c index 7ad3acc80564..4d71547a5b83 100644 --- a/drivers/gpu/drm/i915/intel_step.c +++ b/drivers/gpu/drm/i915/intel_step.c @@ -15,7 +15,7 @@ /* FIXME: what about REVID_E0 */ -static const struct i915_rev_steppings kbl_revids[] = { +static const struct intel_step_info kbl_revids[] = { [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 }, [1] = { .gt_step = STEP_B0, .display_step = STEP_B0 }, [2] = { .gt_step = STEP_C0, .display_step = STEP_B0 }, @@ -26,7 +26,7 @@ static const struct i915_rev_steppings kbl_revids[] = { [7] = { .gt_step = STEP_G0, .display_step = STEP_C0 }, }; -static const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = { +static const struct intel_step_info tgl_uy_revid_step_tbl[] = { [0] = { .gt_step = STEP_A0, .display_step = STEP_A0 }, [1] = { .gt_step = STEP_B0, .display_step = STEP_C0 }, [2] = { .gt_step = STEP_B1, .display_step = STEP_C0 }, @@ -34,12 +34,12 @@ static const struct i915_rev_steppings tgl_uy_revid_step_tbl[] = { }; /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */ -static const struct i915_rev_steppings tgl_revid_step_tbl[] = { +static const struct intel_step_info tgl_revid_step_tbl[] = { [0] = { .gt_step = STEP_A0, .display_step = STEP_B0 }, [1] = { .gt_step = STEP_B0, .display_step = STEP_D0 }, }; -static const struct i915_rev_steppings adls_revid_step_tbl[] = { +static const struct intel_step_info adls_revid_step_tbl[] = { [0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 }, [0x1] = { .gt_step = STEP_A0, .display_step = STEP_A2 }, [0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0 }, @@ -49,10 +49,10 @@ static const struct i915_rev_steppings adls_revid_step_tbl[] = { void intel_step_init(struct drm_i915_private *i915) { - const struct i915_rev_steppings *revids = NULL; + const struct intel_step_info *revids = NULL; int size = 0; int revid = INTEL_REVID(i915); - struct i915_rev_steppings step = {}; + struct intel_step_info step = {}; if (IS_ALDERLAKE_S(i915)) { revids = adls_revid_step_tbl; diff --git a/drivers/gpu/drm/i915/intel_step.h b/drivers/gpu/drm/i915/intel_step.h index 102fd6a26893..958a8bb5d677 100644 --- a/drivers/gpu/drm/i915/intel_step.h +++ b/drivers/gpu/drm/i915/intel_step.h @@ -10,7 +10,7 @@ struct drm_i915_private; -struct i915_rev_steppings { +struct intel_step_info { u8 gt_step; u8 display_step; };