From patchwork Tue Mar 30 10:06:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lecopzer Chen X-Patchwork-Id: 12172187 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AF04C433DB for ; Tue, 30 Mar 2021 10:08:38 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CC3EB60231 for ; Tue, 30 Mar 2021 10:08:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CC3EB60231 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=bss9AhoD2RCvJtP26mzdzY8Goy89VQJzY4Dbl+IBgtg=; b=IdHPzXa3m2sBo6NMZbnLipmt+Y 1OK078lQYRJzIhARwqNwhLD7BqHpDyl9wxA4k1TivTwDzXcaZfFbPsUL95j4RH2BPNLA2RstzPlmr UHzkoFkr90yen58TIzI6GE10LlHsJek+12cPRQcutWafHFEZ5gNpN2/H0Tm7g2MnTEsRxKd7m9Qdy vB1buISA1O6gYsIs+HM24UMfmgNP5MR4ltOAJVTimP/0RxPUy2MlvXODJh6utQAJHE9hrNOizLut7 zDB5j5NhHRFKbx/JYqQRd6ntTjNTbrnPIXOGXnv6LvVST3B4+ByapYgbKWD7shFsJ/rIEiQSjvk3u eg44oU+Q==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lRBGj-003Lba-1A; Tue, 30 Mar 2021 10:06:41 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lRBGc-003LZF-R7 for linux-arm-kernel@lists.infradead.org; Tue, 30 Mar 2021 10:06:37 +0000 X-UUID: ea10f845760448b499c4a51366ddb94f-20210330 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=/b2EgdxoitxnKqLyXoHYkilw8mdHK5KQF1Qepya0HEQ=; b=ZbNoREg8rybGLJngWN9/zWSIVPVBVz4LtvfzZHZv+JmlC7w2FyueLWL3PKSIsd/lBxK+qSeXwOHuMcaOEUltm2B8eQ8tukJcEN2keOStyvdeZ6w7KFhlB0Zf1ypWBLHnapC2qxuniU/bR3qy8lnCbr0augFeM8lwQffsv5S5NL4=; X-UUID: ea10f845760448b499c4a51366ddb94f-20210330 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1919374094; Tue, 30 Mar 2021 02:06:29 -0800 Received: from mtkmbs08n1.mediatek.inc (172.21.101.55) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 30 Mar 2021 03:06:28 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 30 Mar 2021 18:06:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 30 Mar 2021 18:06:26 +0800 From: Lecopzer Chen To: , , , CC: , , , Lecopzer Chen Subject: [PATCH] irqchip/gic-v3: Fix IPRIORITYR can't perform byte operations in GIC-600 Date: Tue, 30 Mar 2021 18:06:19 +0800 Message-ID: <20210330100619.24747-1-lecopzer.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210330_110635_408615_1AA2B594 X-CRM114-Status: GOOD ( 14.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When pseudo-NMI enabled, register_nmi() set priority of specific IRQ by byte ops, and this doesn't work in GIC-600. We have asked ARM Support [1]: > Please refer to following description in > "2.1.2 Distributor ACE-Lite slave interface" of GIC-600 TRM for > the GIC600 ACE-lite slave interface supported sizes: > "The GIC-600 only accepts single beat accesses of the sizes for > each register that are shown in the Programmers model, > see Chapter 4 Programmer's model on page 4-102. > All other accesses are rejected and given either an > OKAY or SLVERR response that is based on the GICT_ERR0CTLR.UE bit.". Thus the register needs to be written by double word operation and the step will be: read 32bit, set byte and write it back. [1] https://services.arm.com/support/s/case/5003t00001L4Pba Signed-off-by: Lecopzer Chen --- drivers/irqchip/irq-gic-v3.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index eb0ee356a629..cfc5a6ad30dc 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -440,10 +440,21 @@ static void gic_irq_set_prio(struct irq_data *d, u8 prio) { void __iomem *base = gic_dist_base(d); u32 offset, index; + u32 val, prio_offset_mask, prio_offset_shift; offset = convert_offset_index(d, GICD_IPRIORITYR, &index); - writeb_relaxed(prio, base + offset + index); + /* + * GIC-600 memory mapping register doesn't support byte opteration, + * thus read 32-bits from register, set bytes and wtire back to it. + */ + prio_offset_shift = (index & 0x3) * 8; + prio_offset_mask = GENMASK(prio_offset_shift + 7, prio_offset_shift); + index &= ~0x3; + val = readl_relaxed(base + offset + index); + val &= ~prio_offset_mask; + val |= prio << prio_offset_shift; + writel_relaxed(val, base + offset + index); } static u32 gic_get_ppi_index(struct irq_data *d)