From patchwork Tue Mar 30 17:33:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12173297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F62BC433DB for ; Tue, 30 Mar 2021 17:35:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0672F619CF for ; Tue, 30 Mar 2021 17:35:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232001AbhC3Rek (ORCPT ); Tue, 30 Mar 2021 13:34:40 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:53056 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232298AbhC3Re2 (ORCPT ); Tue, 30 Mar 2021 13:34:28 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12UHY27G080685; Tue, 30 Mar 2021 12:34:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1617125642; bh=bOoAsGAFt4jk/rid5QKQyQcMiWPMKnzEbnCMJ1Uie3U=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=D7owOXb0KpBrZ0eP/FWeqeYbhDTzvBtSCRPY843Hx9WWHBn4R8/NOUb3c+Avs/l7G 7fUsk5Dm1zKqkOG53TNWrhCjXMgcCgX9DL7h2n1MxdSwaPM8HnMdc1x1s3cblH8TMt 5QkPe4UF5tnKanDaEwjCKgDMVFfqqE/KI7k4XByQ= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12UHY229024850 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Mar 2021 12:34:02 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 30 Mar 2021 12:34:02 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 30 Mar 2021 12:34:01 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12UHXmgi125244; Tue, 30 Mar 2021 12:33:56 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab , Rob Herring , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Maxime Ripard , Benoit Parrot , Hans Verkuil , Alexandre Courbot , Laurent Pinchart , Stanimir Varbanov , Helen Koike , Michael Tretter , Peter Chen , Chunfeng Yun , , , , , CC: Pratyush Yadav , Vignesh Raghavendra , Tomi Valkeinen Subject: [PATCH 01/16] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes Date: Tue, 30 Mar 2021 23:03:33 +0530 Message-ID: <20210330173348.30135-2-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210330173348.30135-1-p.yadav@ti.com> References: <20210330173348.30135-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org From: Paul Kocialkowski As some D-PHY controllers support both Rx and Tx mode, we need a way for users to explicitly request one or the other. For instance, Rx mode can be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI. Introduce new MIPI D-PHY PHY submodes to use with PHY_MODE_MIPI_DPHY. The default (zero value) is kept to Tx so only the rkisp1 driver, which uses D-PHY in Rx mode, needs to be adapted. Signed-off-by: Paul Kocialkowski Signed-off-by: Pratyush Yadav --- include/linux/phy/phy-mipi-dphy.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/linux/phy/phy-mipi-dphy.h b/include/linux/phy/phy-mipi-dphy.h index a877ffee845d..0f57ef46a8b5 100644 --- a/include/linux/phy/phy-mipi-dphy.h +++ b/include/linux/phy/phy-mipi-dphy.h @@ -6,6 +6,19 @@ #ifndef __PHY_MIPI_DPHY_H_ #define __PHY_MIPI_DPHY_H_ +/** + * enum phy_mipi_dphy_submode - MIPI D-PHY sub-mode + * + * A MIPI D-PHY can be used to transmit or receive data. + * Since some controllers can support both, the direction to enable is specified + * with the PHY sub-mode. Transmit is assumed by default with phy_set_mode. + */ + +enum phy_mipi_dphy_submode { + PHY_MIPI_DPHY_SUBMODE_TX = 0, + PHY_MIPI_DPHY_SUBMODE_RX, +}; + /** * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set * From patchwork Tue Mar 30 17:33:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12173301 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC2C0C433E6 for ; Tue, 30 Mar 2021 17:35:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C3E8E619D4 for ; Tue, 30 Mar 2021 17:35:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232403AbhC3Rel (ORCPT ); Tue, 30 Mar 2021 13:34:41 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59550 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232307AbhC3Re2 (ORCPT ); Tue, 30 Mar 2021 13:34:28 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12UHY80Y057005; Tue, 30 Mar 2021 12:34:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1617125648; bh=al0qmsNw4qGGrS+IvvHucR10n/i1H5Cqvddimz3Fllo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hRH4ppKTtspbs7IgkAuV20kiT3OtQ9wAACBZ01sx0r37zYB25zbpiFKrjtg+aZESH qx6n6E/L9xhi4JRLVi5HXGnf7yBtrJNY3L2w23vSP/iQXfu0oztu3EFMBp9zir/5+B k0RvzX57vE2tmhw+X5CT/UQrO8x9cyjmBcqEt4rU= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12UHY8lc067690 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Mar 2021 12:34:08 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 30 Mar 2021 12:34:08 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 30 Mar 2021 12:34:08 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12UHXmgj125244; Tue, 30 Mar 2021 12:34:02 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab , Rob Herring , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Maxime Ripard , Benoit Parrot , Hans Verkuil , Alexandre Courbot , Laurent Pinchart , Stanimir Varbanov , Helen Koike , Michael Tretter , Peter Chen , Chunfeng Yun , , , , , CC: Pratyush Yadav , Vignesh Raghavendra , Tomi Valkeinen Subject: [PATCH 02/16] phy: cdns-dphy: Prepare for Rx support Date: Tue, 30 Mar 2021 23:03:34 +0530 Message-ID: <20210330173348.30135-3-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210330173348.30135-1-p.yadav@ti.com> References: <20210330173348.30135-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The Rx programming sequence differs from the Tx programming sequence. Currently only Tx mode is supported. Move all the Tx related parts into a set of Tx-specific hooks that are then called by the main PHY framework hooks. This way when Rx support is added all that is needed to be done is to plug in the Rx hooks. The clocks "psm" and "pll_ref" are not used by the Rx path so make them optional in the probe and then check if they exist in the power_on() hook. Signed-off-by: Pratyush Yadav --- drivers/phy/cadence/cdns-dphy.c | 140 ++++++++++++++++++++++++-------- 1 file changed, 104 insertions(+), 36 deletions(-) diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c index ba042e39cfaf..8656f2102a91 100644 --- a/drivers/phy/cadence/cdns-dphy.c +++ b/drivers/phy/cadence/cdns-dphy.c @@ -75,6 +75,11 @@ struct cdns_dphy; struct cdns_dphy_ops { int (*probe)(struct cdns_dphy *dphy); void (*remove)(struct cdns_dphy *dphy); + int (*power_on)(struct cdns_dphy *dphy); + int (*power_off)(struct cdns_dphy *dphy); + int (*validate)(struct cdns_dphy *dphy, enum phy_mode mode, int submode, + union phy_configure_opts *opts); + int (*configure)(struct cdns_dphy *dphy, union phy_configure_opts *opts); void (*set_psm_div)(struct cdns_dphy *dphy, u8 div); void (*set_clk_lane_cfg)(struct cdns_dphy *dphy, enum cdns_dphy_clk_lane_cfg cfg); @@ -86,12 +91,18 @@ struct cdns_dphy_ops { struct cdns_dphy { struct cdns_dphy_cfg cfg; void __iomem *regs; + struct device *dev; struct clk *psm_clk; struct clk *pll_ref_clk; const struct cdns_dphy_ops *ops; struct phy *phy; }; +struct cdns_dphy_driver_data { + const struct cdns_dphy_ops *tx; + const struct cdns_dphy_ops *rx; +}; + static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy, struct cdns_dphy_cfg *cfg, struct phy_configure_opts_mipi_dphy *opts, @@ -199,20 +210,9 @@ static void cdns_dphy_ref_set_psm_div(struct cdns_dphy *dphy, u8 div) dphy->regs + DPHY_PSM_CFG); } -/* - * This is the reference implementation of DPHY hooks. Specific integration of - * this IP may have to re-implement some of them depending on how they decided - * to wire things in the SoC. - */ -static const struct cdns_dphy_ops ref_dphy_ops = { - .get_wakeup_time_ns = cdns_dphy_ref_get_wakeup_time_ns, - .set_pll_cfg = cdns_dphy_ref_set_pll_cfg, - .set_psm_div = cdns_dphy_ref_set_psm_div, -}; - -static int cdns_dphy_config_from_opts(struct phy *phy, - struct phy_configure_opts_mipi_dphy *opts, - struct cdns_dphy_cfg *cfg) +static int cdns_dphy_tx_config_from_opts(struct phy *phy, + struct phy_configure_opts_mipi_dphy *opts, + struct cdns_dphy_cfg *cfg) { struct cdns_dphy *dphy = phy_get_drvdata(phy); unsigned int dsi_hfp_ext = 0; @@ -232,24 +232,13 @@ static int cdns_dphy_config_from_opts(struct phy *phy, return 0; } -static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode, - union phy_configure_opts *opts) +static int cdns_dphy_tx_configure(struct cdns_dphy *dphy, + union phy_configure_opts *opts) { struct cdns_dphy_cfg cfg = { 0 }; - - if (mode != PHY_MODE_MIPI_DPHY) - return -EINVAL; - - return cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg); -} - -static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) -{ - struct cdns_dphy *dphy = phy_get_drvdata(phy); - struct cdns_dphy_cfg cfg = { 0 }; int ret; - ret = cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg); + ret = cdns_dphy_tx_config_from_opts(dphy->phy, &opts->mipi_dphy, &cfg); if (ret) return ret; @@ -279,9 +268,21 @@ static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) return 0; } -static int cdns_dphy_power_on(struct phy *phy) +static int cdns_dphy_tx_validate(struct cdns_dphy *dphy, enum phy_mode mode, + int submode, union phy_configure_opts *opts) { - struct cdns_dphy *dphy = phy_get_drvdata(phy); + struct cdns_dphy_cfg cfg = { 0 }; + + if (submode != PHY_MIPI_DPHY_SUBMODE_TX) + return -EINVAL; + + return cdns_dphy_tx_config_from_opts(dphy->phy, &opts->mipi_dphy, &cfg); +} + +static int cdns_dphy_tx_power_on(struct cdns_dphy *dphy) +{ + if (!dphy->psm_clk || !dphy->pll_ref_clk) + return -EINVAL; clk_prepare_enable(dphy->psm_clk); clk_prepare_enable(dphy->pll_ref_clk); @@ -293,16 +294,77 @@ static int cdns_dphy_power_on(struct phy *phy) return 0; } -static int cdns_dphy_power_off(struct phy *phy) +static int cdns_dphy_tx_power_off(struct cdns_dphy *dphy) { - struct cdns_dphy *dphy = phy_get_drvdata(phy); - clk_disable_unprepare(dphy->pll_ref_clk); clk_disable_unprepare(dphy->psm_clk); return 0; } +static const struct cdns_dphy_ops tx_ref_dphy_ops = { + .power_on = cdns_dphy_tx_power_on, + .power_off = cdns_dphy_tx_power_off, + .validate = cdns_dphy_tx_validate, + .configure = cdns_dphy_tx_configure, + .get_wakeup_time_ns = cdns_dphy_ref_get_wakeup_time_ns, + .set_pll_cfg = cdns_dphy_ref_set_pll_cfg, + .set_psm_div = cdns_dphy_ref_set_psm_div, +}; + +/* + * This is the reference implementation of DPHY hooks. Specific integration of + * this IP may have to re-implement some of them depending on how they decided + * to wire things in the SoC. + */ +static const struct cdns_dphy_driver_data ref_dphy_ops = { + .tx = &tx_ref_dphy_ops, +}; + +static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode, + union phy_configure_opts *opts) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + + if (mode != PHY_MODE_MIPI_DPHY) + return -EINVAL; + + if (dphy->ops->validate) + return dphy->ops->validate(dphy, mode, submode, opts); + + return 0; +} + +static int cdns_dphy_power_on(struct phy *phy) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + + if (dphy->ops->power_on) + return dphy->ops->power_on(dphy); + + return 0; +} + +static int cdns_dphy_power_off(struct phy *phy) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + + if (dphy->ops->power_off) + return dphy->ops->power_off(dphy); + + return 0; +} + +static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + + if (dphy->ops->configure) + return dphy->ops->configure(dphy, opts); + + return 0; +} + static const struct phy_ops cdns_dphy_ops = { .configure = cdns_dphy_configure, .validate = cdns_dphy_validate, @@ -314,14 +376,20 @@ static int cdns_dphy_probe(struct platform_device *pdev) { struct phy_provider *phy_provider; struct cdns_dphy *dphy; + const struct cdns_dphy_driver_data *ddata; int ret; dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL); if (!dphy) return -ENOMEM; dev_set_drvdata(&pdev->dev, dphy); + dphy->dev = &pdev->dev; - dphy->ops = of_device_get_match_data(&pdev->dev); + ddata = of_device_get_match_data(&pdev->dev); + if (!ddata) + return -EINVAL; + + dphy->ops = ddata->tx; if (!dphy->ops) return -EINVAL; @@ -329,11 +397,11 @@ static int cdns_dphy_probe(struct platform_device *pdev) if (IS_ERR(dphy->regs)) return PTR_ERR(dphy->regs); - dphy->psm_clk = devm_clk_get(&pdev->dev, "psm"); + dphy->psm_clk = devm_clk_get_optional(dphy->dev, "psm"); if (IS_ERR(dphy->psm_clk)) return PTR_ERR(dphy->psm_clk); - dphy->pll_ref_clk = devm_clk_get(&pdev->dev, "pll_ref"); + dphy->pll_ref_clk = devm_clk_get_optional(dphy->dev, "pll_ref"); if (IS_ERR(dphy->pll_ref_clk)) return PTR_ERR(dphy->pll_ref_clk); From patchwork Tue Mar 30 17:33:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12173305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 168DBC433E8 for ; Tue, 30 Mar 2021 17:35:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E7985619D3 for ; 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Tue, 30 Mar 2021 12:34:14 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 30 Mar 2021 12:34:14 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 30 Mar 2021 12:34:14 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12UHXmgk125244; Tue, 30 Mar 2021 12:34:08 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab , Rob Herring , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Maxime Ripard , Benoit Parrot , Hans Verkuil , Alexandre Courbot , Laurent Pinchart , Stanimir Varbanov , Helen Koike , Michael Tretter , Peter Chen , Chunfeng Yun , , , , , CC: Pratyush Yadav , Vignesh Raghavendra , Tomi Valkeinen Subject: [PATCH 03/16] phy: cdns-dphy: Allow setting mode Date: Tue, 30 Mar 2021 23:03:35 +0530 Message-ID: <20210330173348.30135-4-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210330173348.30135-1-p.yadav@ti.com> References: <20210330173348.30135-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Allow callers to set the PHY mode. The main mode should always be PHY_MODE_MIPI_DPHY but the submode can either be PHY_MIPI_DPHY_SUBMODE_RX or PHY_MIPI_DPHY_SUBMODE_TX. Update the ops based on the requested submode. Signed-off-by: Pratyush Yadav --- drivers/phy/cadence/cdns-dphy.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c index 8656f2102a91..7d5f7b333893 100644 --- a/drivers/phy/cadence/cdns-dphy.c +++ b/drivers/phy/cadence/cdns-dphy.c @@ -365,11 +365,41 @@ static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts) return 0; } +static int cdns_dphy_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct cdns_dphy *dphy = phy_get_drvdata(phy); + const struct cdns_dphy_driver_data *ddata; + + ddata = of_device_get_match_data(dphy->dev); + if (!ddata) + return -EINVAL; + + if (mode != PHY_MODE_MIPI_DPHY) + return -EINVAL; + + if (submode == PHY_MIPI_DPHY_SUBMODE_TX) { + if (!ddata->tx) + return -EOPNOTSUPP; + + dphy->ops = ddata->tx; + } else if (submode == PHY_MIPI_DPHY_SUBMODE_RX) { + if (!ddata->rx) + return -EOPNOTSUPP; + + dphy->ops = ddata->rx; + } else { + return -EOPNOTSUPP; + } + + return 0; +} + static const struct phy_ops cdns_dphy_ops = { .configure = cdns_dphy_configure, .validate = cdns_dphy_validate, .power_on = cdns_dphy_power_on, .power_off = cdns_dphy_power_off, + .set_mode = cdns_dphy_set_mode, }; static int cdns_dphy_probe(struct platform_device *pdev) From patchwork Tue Mar 30 17:33:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12173303 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06603C433E5 for ; Tue, 30 Mar 2021 17:35:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D4D4F60235 for ; Tue, 30 Mar 2021 17:35:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232466AbhC3Ren (ORCPT ); Tue, 30 Mar 2021 13:34:43 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:53140 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232333AbhC3Rei (ORCPT ); Tue, 30 Mar 2021 13:34:38 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12UHYLdJ080764; Tue, 30 Mar 2021 12:34:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1617125661; bh=1Fypw72Nte2J+9GlPnAZdJjpruajqd+6kEaRZTmljYk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=x9ydMyTqsRjZi8Wnj+rdsIZqBPRlhKcMhqp60ms4dcQ87g2UJEHbo/u6+EAasMk3s qO+C4JmsSOSZFeJ0nDbOwzzanfSIgXd0bU/tO/zGKtikUEdKRFLh/mbr6Jf6RbUhDG ObLw2Y2gZtmPx02aayaDAm5GQIoxhkTIsdqw6YG4= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12UHYLhr025636 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Mar 2021 12:34:21 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 30 Mar 2021 12:34:20 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 30 Mar 2021 12:34:20 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12UHXmgl125244; Tue, 30 Mar 2021 12:34:15 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab , Rob Herring , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Maxime Ripard , Benoit Parrot , Hans Verkuil , Alexandre Courbot , Laurent Pinchart , Stanimir Varbanov , Helen Koike , Michael Tretter , Peter Chen , Chunfeng Yun , , , , , CC: Pratyush Yadav , Vignesh Raghavendra , Tomi Valkeinen Subject: [PATCH 04/16] phy: cdns-dphy: Add Rx support Date: Tue, 30 Mar 2021 23:03:36 +0530 Message-ID: <20210330173348.30135-5-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210330173348.30135-1-p.yadav@ti.com> References: <20210330173348.30135-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The Cadence DPHY can be used to receive image data over the CSI-2 protocol. Add support for Rx mode. The programming sequence differs from the Tx mode so it is added as a separate set of hooks to isolate the two paths. The PHY is in Tx mode by default and it needs to be set in Rx mode by setting the submode to PHY_MIPI_DPHY_SUBMODE_RX in the set_mode() callback. Signed-off-by: Pratyush Yadav --- drivers/phy/cadence/cdns-dphy.c | 237 ++++++++++++++++++++++++++++++++ 1 file changed, 237 insertions(+) diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c index 7d5f7b333893..7bbca679e2bb 100644 --- a/drivers/phy/cadence/cdns-dphy.c +++ b/drivers/phy/cadence/cdns-dphy.c @@ -1,11 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright: 2017-2018 Cadence Design Systems, Inc. + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ */ #include +#include #include #include +#include #include #include #include @@ -25,10 +28,14 @@ #define DPHY_PMA_RCLK(reg) (0x600 + (reg)) #define DPHY_PMA_RDATA(lane, reg) (0x700 + ((lane) * 0x100) + (reg)) #define DPHY_PCS(reg) (0xb00 + (reg)) +#define DPHY_ISO(reg) (0xc00 + (reg)) #define DPHY_CMN_SSM DPHY_PMA_CMN(0x20) #define DPHY_CMN_SSM_EN BIT(0) +#define DPHY_CMN_RX_BANDGAP_TIMER_MASK GENMASK(8, 1) #define DPHY_CMN_TX_MODE_EN BIT(9) +#define DPHY_CMN_RX_MODE_EN BIT(10) +#define DPHY_CMN_RX_BANDGAP_TIMER 0x14 #define DPHY_CMN_PWM DPHY_PMA_CMN(0x40) #define DPHY_CMN_PWM_DIV(x) ((x) << 20) @@ -45,10 +52,27 @@ #define DPHY_CMN_OPDIV_FROM_REG BIT(6) #define DPHY_CMN_OPDIV(x) ((x) << 7) +#define DPHY_BAND_CFG DPHY_PCS(0x0) +#define DPHY_BAND_CFG_LEFT_BAND GENMASK(4, 0) +#define DPHY_BAND_CFG_RIGHT_BAND GENMASK(9, 5) + #define DPHY_PSM_CFG DPHY_PCS(0x4) #define DPHY_PSM_CFG_FROM_REG BIT(0) #define DPHY_PSM_CLK_DIV(x) ((x) << 1) +#define DPHY_POWER_ISLAND_EN_DATA DPHY_PCS(0x8) +#define DPHY_POWER_ISLAND_EN_DATA_VAL 0xaaaaaaaa +#define DPHY_POWER_ISLAND_EN_CLK DPHY_PCS(0xc) +#define DPHY_POWER_ISLAND_EN_CLK_VAL 0xaa + +#define DPHY_ISO_CL_CTRL_L DPHY_ISO(0x10) +#define DPHY_ISO_DL_CTRL_L0 DPHY_ISO(0x14) +#define DPHY_ISO_DL_CTRL_L1 DPHY_ISO(0x20) +#define DPHY_ISO_DL_CTRL_L2 DPHY_ISO(0x30) +#define DPHY_ISO_DL_CTRL_L3 DPHY_ISO(0x3c) +#define DPHY_ISO_LANE_READY_BIT 0 +#define DPHY_ISO_LANE_READY_TIMEOUT_MS 100UL + #define DSI_HBP_FRAME_OVERHEAD 12 #define DSI_HSA_FRAME_OVERHEAD 14 #define DSI_HFP_FRAME_OVERHEAD 6 @@ -57,6 +81,9 @@ #define DSI_NULL_FRAME_OVERHEAD 6 #define DSI_EOT_PKT_SIZE 4 +#define DPHY_LANES_MIN 1 +#define DPHY_LANES_MAX 4 + struct cdns_dphy_cfg { u8 pll_ipdiv; u8 pll_opdiv; @@ -312,6 +339,214 @@ static const struct cdns_dphy_ops tx_ref_dphy_ops = { .set_psm_div = cdns_dphy_ref_set_psm_div, }; +static int cdns_dphy_rx_power_on(struct cdns_dphy *dphy) +{ + /* Start RX state machine. */ + writel(DPHY_CMN_SSM_EN | DPHY_CMN_RX_MODE_EN | + FIELD_PREP(DPHY_CMN_RX_BANDGAP_TIMER_MASK, + DPHY_CMN_RX_BANDGAP_TIMER), + dphy->regs + DPHY_CMN_SSM); + + return 0; +} + +static int cdns_dphy_rx_power_off(struct cdns_dphy *dphy) +{ + writel(0, dphy->regs + DPHY_CMN_SSM); + + return 0; +} + +static int cdns_dphy_rx_get_band_ctrl(unsigned long hs_clk_rate) +{ + unsigned int rate = hs_clk_rate / 1000000UL; + + if (rate < 80 || rate >= 2500) + return -EOPNOTSUPP; + + if (rate >= 80 && rate < 100) + return 0; + + if (rate >= 100 && rate < 120) + return 1; + + if (rate >= 120 && rate < 160) + return 2; + + if (rate >= 160 && rate < 200) + return 3; + + if (rate >= 200 && rate < 240) + return 4; + + if (rate >= 240 && rate < 280) + return 5; + + if (rate >= 280 && rate < 320) + return 6; + + if (rate >= 320 && rate < 360) + return 7; + + if (rate >= 360 && rate < 400) + return 8; + + if (rate >= 400 && rate < 480) + return 9; + + if (rate >= 480 && rate < 560) + return 10; + + if (rate >= 560 && rate < 640) + return 11; + + if (rate >= 640 && rate < 720) + return 12; + + if (rate >= 720 && rate < 800) + return 13; + + if (rate >= 800 && rate < 880) + return 14; + + if (rate >= 880 && rate < 1040) + return 15; + + if (rate >= 1040 && rate < 1200) + return 16; + + if (rate >= 1200 && rate < 1350) + return 17; + + if (rate >= 1350 && rate < 1500) + return 18; + + if (rate >= 1500 && rate < 1750) + return 19; + + if (rate >= 1750 && rate < 2000) + return 20; + + if (rate >= 2000 && rate < 2250) + return 21; + + if (rate >= 2250 && rate < 2500) + return 22; + + /* Unreachable. */ + WARN(1, "Reached unreachable code."); + return -EINVAL; +} + +static int cdns_dphy_rx_wait_for_bit(void __iomem *addr, unsigned int bit) +{ + u32 val; + + return readl_relaxed_poll_timeout(addr, val, val & BIT(bit), 10, + DPHY_ISO_LANE_READY_TIMEOUT_MS * 1000); +} + +static int cdns_dphy_rx_wait_lane_ready(struct cdns_dphy *dphy, int lanes) +{ + void __iomem *reg = dphy->regs; + int ret; + + if (lanes < DPHY_LANES_MIN || lanes > DPHY_LANES_MAX) + return -EINVAL; + + /* Clock lane */ + ret = cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_CL_CTRL_L, + DPHY_ISO_LANE_READY_BIT); + if (ret) + return ret; + + /* Data lanes. Minimum one lane is mandatory. */ + ret = cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_DL_CTRL_L0, + DPHY_ISO_LANE_READY_BIT); + if (ret) + return ret; + + if (lanes < 2) + return 0; + + ret = cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_DL_CTRL_L1, + DPHY_ISO_LANE_READY_BIT); + if (ret) + return ret; + + if (lanes < 3) + return 0; + + ret = cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_DL_CTRL_L2, + DPHY_ISO_LANE_READY_BIT); + if (ret) + return ret; + + if (lanes < 4) + return 0; + + ret = cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_DL_CTRL_L3, + DPHY_ISO_LANE_READY_BIT); + if (ret) + return ret; + + return 0; +} + +static int cdns_dphy_rx_configure(struct cdns_dphy *dphy, + union phy_configure_opts *opts) +{ + unsigned int reg; + int band_ctrl, ret; + + band_ctrl = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); + if (band_ctrl < 0) + return band_ctrl; + + reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) | + FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl); + writel(reg, dphy->regs + DPHY_BAND_CFG); + + /* + * Set the required power island phase 2 time. This is mandated by DPHY + * specs. + */ + reg = DPHY_POWER_ISLAND_EN_DATA_VAL; + writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_DATA); + reg = DPHY_POWER_ISLAND_EN_CLK_VAL; + writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_CLK); + + ret = cdns_dphy_rx_wait_lane_ready(dphy, opts->mipi_dphy.lanes); + if (ret) { + dev_err(dphy->dev, "DPHY wait for lane ready timeout\n"); + return ret; + } + + return 0; +} + +static int cdns_dphy_rx_validate(struct cdns_dphy *dphy, enum phy_mode mode, + int submode, union phy_configure_opts *opts) +{ + int ret; + + if (submode != PHY_MIPI_DPHY_SUBMODE_RX) + return -EINVAL; + + ret = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate); + if (ret < 0) + return ret; + + return phy_mipi_dphy_config_validate(&opts->mipi_dphy); +} + +static const struct cdns_dphy_ops rx_ref_dphy_ops = { + .power_on = cdns_dphy_rx_power_on, + .power_off = cdns_dphy_rx_power_off, + .configure = cdns_dphy_rx_configure, + .validate = cdns_dphy_rx_validate, +}; + /* * This is the reference implementation of DPHY hooks. Specific integration of * this IP may have to re-implement some of them depending on how they decided @@ -319,6 +554,7 @@ static const struct cdns_dphy_ops tx_ref_dphy_ops = { */ static const struct cdns_dphy_driver_data ref_dphy_ops = { .tx = &tx_ref_dphy_ops, + .rx = &rx_ref_dphy_ops, }; static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode, @@ -483,5 +719,6 @@ static struct platform_driver cdns_dphy_platform_driver = { module_platform_driver(cdns_dphy_platform_driver); MODULE_AUTHOR("Maxime Ripard "); +MODULE_AUTHOR("Pratyush Yadav "); MODULE_DESCRIPTION("Cadence MIPI D-PHY Driver"); MODULE_LICENSE("GPL"); From patchwork Tue Mar 30 17:33:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12173307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0D4FC433E0 for ; Tue, 30 Mar 2021 17:35:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BDF5F60235 for ; Tue, 30 Mar 2021 17:35:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232543AbhC3RfN (ORCPT ); Tue, 30 Mar 2021 13:35:13 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:53156 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232484AbhC3Rep (ORCPT ); Tue, 30 Mar 2021 13:34:45 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12UHYRHJ080786; Tue, 30 Mar 2021 12:34:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1617125667; bh=91KLtnJPHFYqMOAUrPZa0i0rIGtEKDKLSR7nXt3JQHE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=MbeuqN1rE/6p/tqXTr0ZFRi4/gNOczP3JvoxYIS/uOl/ftgnzFDQNPzpcr4d9Abkm ww5EK3AWZ9t1WzQLobJVZYVnXI77qithBVAjxPHkzXilnQIyfM76LCaSZ20WQxcSAW QROKVELZbGEqEIzZS1CxVEd6+8yMUUHCnkQjDn0g= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12UHYRmd068158 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Mar 2021 12:34:27 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 30 Mar 2021 12:34:27 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 30 Mar 2021 12:34:27 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12UHXmgm125244; Tue, 30 Mar 2021 12:34:21 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab , Rob Herring , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Maxime Ripard , Benoit Parrot , Hans Verkuil , Alexandre Courbot , Laurent Pinchart , Stanimir Varbanov , Helen Koike , Michael Tretter , Peter Chen , Chunfeng Yun , , , , , CC: Pratyush Yadav , Vignesh Raghavendra , Tomi Valkeinen Subject: [PATCH 05/16] media: cadence: csi2rx: Add external DPHY support Date: Tue, 30 Mar 2021 23:03:37 +0530 Message-ID: <20210330173348.30135-6-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210330173348.30135-1-p.yadav@ti.com> References: <20210330173348.30135-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Some platforms like TI's J721E can have the CSI2RX paired with an external DPHY. Add support to enable and configure the DPHY using the generic PHY framework. Get the pixel rate and bpp from the subdev and pass them on to the DPHY along with the number of lanes. All other settings are left to their default values. Signed-off-by: Pratyush Yadav --- drivers/media/platform/cadence/cdns-csi2rx.c | 147 +++++++++++++++++-- 1 file changed, 137 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index c68a3eac62cd..31bd80e3f780 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -30,6 +30,12 @@ #define CSI2RX_STATIC_CFG_DLANE_MAP(llane, plane) ((plane) << (16 + (llane) * 4)) #define CSI2RX_STATIC_CFG_LANES_MASK GENMASK(11, 8) +#define CSI2RX_DPHY_LANE_CTRL_REG 0x40 +#define CSI2RX_DPHY_CL_RST BIT(16) +#define CSI2RX_DPHY_DL_RST(i) BIT((i) + 12) +#define CSI2RX_DPHY_CL_EN BIT(4) +#define CSI2RX_DPHY_DL_EN(i) BIT(i) + #define CSI2RX_STREAM_BASE(n) (((n) + 1) * 0x100) #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) @@ -54,6 +60,11 @@ enum csi2rx_pads { CSI2RX_PAD_MAX, }; +struct csi2rx_fmt { + u32 code; + u8 bpp; +}; + struct csi2rx_priv { struct device *dev; unsigned int count; @@ -85,6 +96,52 @@ struct csi2rx_priv { int source_pad; }; +static const struct csi2rx_fmt formats[] = { + { + .code = MEDIA_BUS_FMT_YUYV8_2X8, + .bpp = 16, + }, + { + .code = MEDIA_BUS_FMT_UYVY8_2X8, + .bpp = 16, + }, + { + .code = MEDIA_BUS_FMT_YVYU8_2X8, + .bpp = 16, + }, + { + .code = MEDIA_BUS_FMT_VYUY8_2X8, + .bpp = 16, + }, +}; + +static u8 csi2rx_get_bpp(u32 code) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(formats); i++) { + if (formats[i].code == code) + return formats[i].bpp; + } + + return 0; +} + +static s64 csi2rx_get_pixel_rate(struct csi2rx_priv *csi2rx) +{ + struct v4l2_ctrl *ctrl; + + ctrl = v4l2_ctrl_find(csi2rx->source_subdev->ctrl_handler, + V4L2_CID_PIXEL_RATE); + if (!ctrl) { + dev_err(csi2rx->dev, "no pixel rate control in subdev: %s\n", + csi2rx->source_subdev->name); + return -EINVAL; + } + + return v4l2_ctrl_g_ctrl_int64(ctrl); +} + static inline struct csi2rx_priv *v4l2_subdev_to_csi2rx(struct v4l2_subdev *subdev) { @@ -101,6 +158,55 @@ static void csi2rx_reset(struct csi2rx_priv *csi2rx) writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); } +static int csi2rx_configure_external_dphy(struct csi2rx_priv *csi2rx) +{ + union phy_configure_opts opts = { }; + struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy; + struct v4l2_subdev_format sd_fmt; + s64 pixel_rate; + int ret; + u8 bpp; + + sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; + sd_fmt.pad = 0; + + ret = v4l2_subdev_call(csi2rx->source_subdev, pad, get_fmt, NULL, + &sd_fmt); + if (ret) + return ret; + + bpp = csi2rx_get_bpp(sd_fmt.format.code); + if (!bpp) + return -EINVAL; + + pixel_rate = csi2rx_get_pixel_rate(csi2rx); + if (pixel_rate < 0) + return pixel_rate; + + ret = phy_mipi_dphy_get_default_config(pixel_rate, bpp, + csi2rx->num_lanes, cfg); + if (ret) + return ret; + + ret = phy_set_mode_ext(csi2rx->dphy, PHY_MODE_MIPI_DPHY, + PHY_MIPI_DPHY_SUBMODE_RX); + if (ret) + return ret; + + ret = phy_power_on(csi2rx->dphy); + if (ret) + return ret; + + ret = phy_configure(csi2rx->dphy, &opts); + if (ret) { + /* Can't do anything if it fails. Ignore the return value. */ + phy_power_off(csi2rx->dphy); + return ret; + } + + return 0; +} + static int csi2rx_start(struct csi2rx_priv *csi2rx) { unsigned int i; @@ -139,6 +245,17 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) if (ret) goto err_disable_pclk; + /* Enable DPHY clk and data lanes. */ + if (csi2rx->dphy) { + reg = CSI2RX_DPHY_CL_EN | CSI2RX_DPHY_CL_RST; + for (i = 0; i < csi2rx->num_lanes; i++) { + reg |= CSI2RX_DPHY_DL_EN(csi2rx->lanes[i] - 1); + reg |= CSI2RX_DPHY_DL_RST(csi2rx->lanes[i] - 1); + } + + writel(reg, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG); + } + /* * Create a static mapping between the CSI virtual channels * and the output stream. @@ -169,10 +286,21 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) if (ret) goto err_disable_pixclk; + if (csi2rx->dphy) { + ret = csi2rx_configure_external_dphy(csi2rx); + if (ret) { + dev_err(csi2rx->dev, + "Failed to configure external DPHY: %d\n", ret); + goto err_disable_sysclk; + } + } + clk_disable_unprepare(csi2rx->p_clk); return 0; +err_disable_sysclk: + clk_disable_unprepare(csi2rx->sys_clk); err_disable_pixclk: for (; i > 0; i--) clk_disable_unprepare(csi2rx->pixel_clk[i - 1]); @@ -200,6 +328,13 @@ static void csi2rx_stop(struct csi2rx_priv *csi2rx) if (v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, false)) dev_warn(csi2rx->dev, "Couldn't disable our subdev\n"); + + if (csi2rx->dphy) { + writel(0, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG); + + if (phy_power_off(csi2rx->dphy)) + dev_warn(csi2rx->dev, "Couldn't power off DPHY\n"); + } } static int csi2rx_s_stream(struct v4l2_subdev *subdev, int enable) @@ -306,15 +441,6 @@ static int csi2rx_get_resources(struct csi2rx_priv *csi2rx, return PTR_ERR(csi2rx->dphy); } - /* - * FIXME: Once we'll have external D-PHY support, the check - * will need to be removed. - */ - if (csi2rx->dphy) { - dev_err(&pdev->dev, "External D-PHY not supported yet\n"); - return -EINVAL; - } - clk_prepare_enable(csi2rx->p_clk); dev_cfg = readl(csi2rx->base + CSI2RX_DEVICE_CFG_REG); clk_disable_unprepare(csi2rx->p_clk); @@ -339,7 +465,7 @@ static int csi2rx_get_resources(struct csi2rx_priv *csi2rx, * FIXME: Once we'll have internal D-PHY support, the check * will need to be removed. */ - if (csi2rx->has_internal_dphy) { + if (!csi2rx->dphy && csi2rx->has_internal_dphy) { dev_err(&pdev->dev, "Internal D-PHY not supported yet\n"); return -EINVAL; } @@ -460,6 +586,7 @@ static int csi2rx_probe(struct platform_device *pdev) dev_info(&pdev->dev, "Probed CSI2RX with %u/%u lanes, %u streams, %s D-PHY\n", csi2rx->num_lanes, csi2rx->max_lanes, csi2rx->max_streams, + csi2rx->dphy ? "external" : csi2rx->has_internal_dphy ? "internal" : "no"); return 0; From patchwork Tue Mar 30 17:33:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12173309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B4A4C433E2 for ; Tue, 30 Mar 2021 17:35:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F14C8619D1 for ; Tue, 30 Mar 2021 17:35:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232552AbhC3RfO (ORCPT ); Tue, 30 Mar 2021 13:35:14 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:53184 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232531AbhC3Rex (ORCPT ); Tue, 30 Mar 2021 13:34:53 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12UHYYdR080831; Tue, 30 Mar 2021 12:34:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1617125674; bh=e0p31IW0rH6YdPTwIarvDVW5qoY2qL7bTzo3pAqOwkc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=CetWVJkiPzgFFaHLdUSCdCvyAAgQ8CWmMvx3M/Tqq9z9JIQr+Uomq32d727kSTaKS goiAU23mNqq1EBPmtcg7PTbQtLvd1Fptxq28mRLVYQ3VgjQj/jcvlg+lkbwI3XaFdS XpkWeaqJp93g9uqvhQ3eBDgYRk2DkoL8YY1I5lf0= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12UHYXA5025861 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Mar 2021 12:34:33 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 30 Mar 2021 12:34:33 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 30 Mar 2021 12:34:33 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12UHXmgn125244; Tue, 30 Mar 2021 12:34:27 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab , Rob Herring , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Maxime Ripard , Benoit Parrot , Hans Verkuil , Alexandre Courbot , Laurent Pinchart , Stanimir Varbanov , Helen Koike , Michael Tretter , Peter Chen , Chunfeng Yun , , , , , CC: Pratyush Yadav , Vignesh Raghavendra , Tomi Valkeinen Subject: [PATCH 06/16] media: cadence: csi2rx: Soft reset the streams before starting capture Date: Tue, 30 Mar 2021 23:03:38 +0530 Message-ID: <20210330173348.30135-7-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210330173348.30135-1-p.yadav@ti.com> References: <20210330173348.30135-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org This resets the stream state machines and FIFOs, giving them a clean slate. On J721E if the streams are not reset before starting the capture, the captured frame gets wrapped around vertically on every run after the first. Signed-off-by: Pratyush Yadav --- drivers/media/platform/cadence/cdns-csi2rx.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index 31bd80e3f780..b03d2d2e6762 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -39,6 +39,7 @@ #define CSI2RX_STREAM_BASE(n) (((n) + 1) * 0x100) #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) +#define CSI2RX_STREAM_CTRL_SOFT_RST BIT(4) #define CSI2RX_STREAM_CTRL_START BIT(0) #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) @@ -150,12 +151,22 @@ struct csi2rx_priv *v4l2_subdev_to_csi2rx(struct v4l2_subdev *subdev) static void csi2rx_reset(struct csi2rx_priv *csi2rx) { + int i; + writel(CSI2RX_SOFT_RESET_PROTOCOL | CSI2RX_SOFT_RESET_FRONT, csi2rx->base + CSI2RX_SOFT_RESET_REG); udelay(10); writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); + + /* Reset individual streams. */ + for (i = 0; i < csi2rx->max_streams; i++) { + writel(CSI2RX_STREAM_CTRL_SOFT_RST, + csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + usleep_range(10, 20); + writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + } } static int csi2rx_configure_external_dphy(struct csi2rx_priv *csi2rx) From patchwork Tue Mar 30 17:33:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12173311 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61340C433E4 for ; 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Tue, 30 Mar 2021 12:34:40 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 30 Mar 2021 12:34:39 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 30 Mar 2021 12:34:39 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12UHXmgo125244; Tue, 30 Mar 2021 12:34:34 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab , Rob Herring , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Maxime Ripard , Benoit Parrot , Hans Verkuil , Alexandre Courbot , Laurent Pinchart , Stanimir Varbanov , Helen Koike , Michael Tretter , Peter Chen , Chunfeng Yun , , , , , CC: Pratyush Yadav , Vignesh Raghavendra , Tomi Valkeinen Subject: [PATCH 07/16] media: cadence: csi2rx: Set the STOP bit when stopping a stream Date: Tue, 30 Mar 2021 23:03:39 +0530 Message-ID: <20210330173348.30135-8-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210330173348.30135-1-p.yadav@ti.com> References: <20210330173348.30135-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The stream stop procedure says that the STOP bit should be set when the stream is to be stopped, and then the ready bit in stream status register polled to make sure the STOP operation is finished. Signed-off-by: Pratyush Yadav --- drivers/media/platform/cadence/cdns-csi2rx.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index b03d2d2e6762..eca65b157f59 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -40,8 +41,12 @@ #define CSI2RX_STREAM_CTRL_REG(n) (CSI2RX_STREAM_BASE(n) + 0x000) #define CSI2RX_STREAM_CTRL_SOFT_RST BIT(4) +#define CSI2RX_STREAM_CTRL_STOP BIT(1) #define CSI2RX_STREAM_CTRL_START BIT(0) +#define CSI2RX_STREAM_STATUS_REG(n) (CSI2RX_STREAM_BASE(n) + 0x004) +#define CSI2RX_STREAM_STATUS_RDY BIT(31) + #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) #define CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT BIT(31) #define CSI2RX_STREAM_DATA_CFG_VC_SELECT(n) BIT((n) + 16) @@ -325,12 +330,23 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) static void csi2rx_stop(struct csi2rx_priv *csi2rx) { unsigned int i; + u32 val; + int ret; clk_prepare_enable(csi2rx->p_clk); clk_disable_unprepare(csi2rx->sys_clk); for (i = 0; i < csi2rx->max_streams; i++) { - writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + writel(CSI2RX_STREAM_CTRL_STOP, + csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); + + ret = readl_relaxed_poll_timeout(csi2rx->base + + CSI2RX_STREAM_STATUS_REG(i), + val, + (val & CSI2RX_STREAM_STATUS_RDY), + 10, 10000); + if (ret) + dev_warn(csi2rx->dev, "Failed to stop stream%d\n", i); clk_disable_unprepare(csi2rx->pixel_clk[i]); } From patchwork Tue Mar 30 17:33:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12173315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AB9AC433EB for ; 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Tue, 30 Mar 2021 12:34:46 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 30 Mar 2021 12:34:46 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 30 Mar 2021 12:34:46 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12UHXmgp125244; Tue, 30 Mar 2021 12:34:40 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab , Rob Herring , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Maxime Ripard , Benoit Parrot , Hans Verkuil , Alexandre Courbot , Laurent Pinchart , Stanimir Varbanov , Helen Koike , Michael Tretter , Peter Chen , Chunfeng Yun , , , , , CC: Pratyush Yadav , Vignesh Raghavendra , Tomi Valkeinen Subject: [PATCH 08/16] media: cadence: csi2rx: Fix stream data configuration Date: Tue, 30 Mar 2021 23:03:40 +0530 Message-ID: <20210330173348.30135-9-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210330173348.30135-1-p.yadav@ti.com> References: <20210330173348.30135-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Firstly, there is no VC_EN bit present in the STREAM_DATA_CFG register. Bit 31 is part of the VL_SELECT field. Remove it completely. Secondly, it makes little sense to enable ith virtual channel for ith stream. Sure, there might be a use-case that demands it. But there might also be a use case that demands all streams to use the 0th virtual channel. Prefer this case over the former because it is less arbitrary and also makes it very clear what the limitations of the current driver is instead of giving a false impression that multiple virtual channels are supported. Signed-off-by: Pratyush Yadav --- drivers/media/platform/cadence/cdns-csi2rx.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index eca65b157f59..7d1ac51e0698 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -48,7 +48,6 @@ #define CSI2RX_STREAM_STATUS_RDY BIT(31) #define CSI2RX_STREAM_DATA_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x008) -#define CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT BIT(31) #define CSI2RX_STREAM_DATA_CFG_VC_SELECT(n) BIT((n) + 16) #define CSI2RX_STREAM_CFG_REG(n) (CSI2RX_STREAM_BASE(n) + 0x00c) @@ -290,8 +289,11 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF, csi2rx->base + CSI2RX_STREAM_CFG_REG(i)); - writel(CSI2RX_STREAM_DATA_CFG_EN_VC_SELECT | - CSI2RX_STREAM_DATA_CFG_VC_SELECT(i), + /* + * Enable one virtual channel. When multiple virtual channels + * are supported this will have to be changed. + */ + writel(CSI2RX_STREAM_DATA_CFG_VC_SELECT(0), csi2rx->base + CSI2RX_STREAM_DATA_CFG_REG(i)); writel(CSI2RX_STREAM_CTRL_START, From patchwork Tue Mar 30 17:33:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12173313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CA26C433E9 for ; Tue, 30 Mar 2021 17:35:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D7506619D2 for ; Tue, 30 Mar 2021 17:35:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232562AbhC3RfS (ORCPT ); Tue, 30 Mar 2021 13:35:18 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59756 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232533AbhC3RfK (ORCPT ); Tue, 30 Mar 2021 13:35:10 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12UHYqev057185; Tue, 30 Mar 2021 12:34:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1617125692; bh=lbeVUbvAR4oductXBEoruja1yT2y8SvkHXqgYIrrklE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dBY1eZOMB8xhObsTadyWKSE+0DooNzUM5h+IMYv0KkpsU8YIuPLEvFlKKGPnyKlMI GVn78U7Hnk5X9pTndkOkUwMMYbnjciJ04HUm8trsH9n2BHYvqBkskyyUP3F+XWQaLD j4klMYe8qQZVVJPx+OjqECI5ctEwE1grlwl6rwXE= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12UHYqPN032783 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Mar 2021 12:34:52 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 30 Mar 2021 12:34:52 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 30 Mar 2021 12:34:52 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12UHXmgq125244; Tue, 30 Mar 2021 12:34:46 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab , Rob Herring , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Maxime Ripard , Benoit Parrot , Hans Verkuil , Alexandre Courbot , Laurent Pinchart , Stanimir Varbanov , Helen Koike , Michael Tretter , Peter Chen , Chunfeng Yun , , , , , CC: Pratyush Yadav , Vignesh Raghavendra , Tomi Valkeinen Subject: [PATCH 09/16] media: cadence: csi2rx: Turn subdev power on before starting stream Date: Tue, 30 Mar 2021 23:03:41 +0530 Message-ID: <20210330173348.30135-10-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210330173348.30135-1-p.yadav@ti.com> References: <20210330173348.30135-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The subdevice power needs to be turned on before the stream is started. Otherwise it might not be in the proper state to stream the data. Turn it off when stopping the stream. Signed-off-by: Pratyush Yadav --- drivers/media/platform/cadence/cdns-csi2rx.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index 7d1ac51e0698..3385e1bc213e 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -256,6 +256,10 @@ static int csi2rx_start(struct csi2rx_priv *csi2rx) writel(reg, csi2rx->base + CSI2RX_STATIC_CFG_REG); + ret = v4l2_subdev_call(csi2rx->source_subdev, core, s_power, true); + if (ret && ret != -ENOIOCTLCMD) + goto err_disable_pclk; + ret = v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, true); if (ret) goto err_disable_pclk; @@ -358,6 +362,10 @@ static void csi2rx_stop(struct csi2rx_priv *csi2rx) if (v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, false)) dev_warn(csi2rx->dev, "Couldn't disable our subdev\n"); + ret = v4l2_subdev_call(csi2rx->source_subdev, core, s_power, false); + if (ret && ret != -ENOIOCTLCMD) + dev_warn(csi2rx->dev, "Couldn't power off subdev\n"); + if (csi2rx->dphy) { writel(0, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG); From patchwork Tue Mar 30 17:33:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12173317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8613FC433E0 for ; Tue, 30 Mar 2021 17:36:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5FF3B61953 for ; Tue, 30 Mar 2021 17:36:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232439AbhC3Rfo (ORCPT ); Tue, 30 Mar 2021 13:35:44 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59888 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232553AbhC3RfQ (ORCPT ); Tue, 30 Mar 2021 13:35:16 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12UHYxnK057214; Tue, 30 Mar 2021 12:34:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1617125699; bh=oyLcX4zTICMuRbzkOD5Koeq3zdkXhldkZIUq9vZlncE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=K3Fnejc+96F4eclc1c3BTPfDLQgBJ9yiRk/DwOasZw7fDdE3p3iyws4MCPoqmXXgb Xy9XQ9zCa3hrdxuRW9vfNzD5mEmTrVaXSDDRJLG/UM5c41bvXmHCjk0RYG2tCRLFGh DwAnmE8QqoaP8bn+/Nn/6qecf6suPEAdnLiEp3eQ= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12UHYxEV068748 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Mar 2021 12:34:59 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 30 Mar 2021 12:34:58 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 30 Mar 2021 12:34:59 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12UHXmgr125244; Tue, 30 Mar 2021 12:34:53 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab , Rob Herring , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Maxime Ripard , Benoit Parrot , Hans Verkuil , Alexandre Courbot , Laurent Pinchart , Stanimir Varbanov , Helen Koike , Michael Tretter , Peter Chen , Chunfeng Yun , , , , , CC: Pratyush Yadav , Vignesh Raghavendra , Tomi Valkeinen Subject: [PATCH 10/16] media: cadence: csi2rx: Add wrappers for subdev calls Date: Tue, 30 Mar 2021 23:03:42 +0530 Message-ID: <20210330173348.30135-11-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210330173348.30135-1-p.yadav@ti.com> References: <20210330173348.30135-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org When this bridge driver is being user by another platform driver, it might want to call subdev operations like getting format, setting format, enumerating format codes, etc. Add wrapper functions that pass that call through to the sensor. Currently wrappers are added only for the ops used by TI's platform driver. More can be added later as needed. Signed-off-by: Pratyush Yadav --- drivers/media/platform/cadence/cdns-csi2rx.c | 77 ++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/media/platform/cadence/cdns-csi2rx.c b/drivers/media/platform/cadence/cdns-csi2rx.c index 3385e1bc213e..2e8bbc53cb8b 100644 --- a/drivers/media/platform/cadence/cdns-csi2rx.c +++ b/drivers/media/platform/cadence/cdns-csi2rx.c @@ -408,12 +408,89 @@ static int csi2rx_s_stream(struct v4l2_subdev *subdev, int enable) return ret; } +static int csi2rx_g_frame_interval(struct v4l2_subdev *subdev, + struct v4l2_subdev_frame_interval *fi) +{ + struct csi2rx_priv *csi2rx = v4l2_subdev_to_csi2rx(subdev); + + return v4l2_subdev_call(csi2rx->source_subdev, video, g_frame_interval, + fi); +} + +static int csi2rx_s_frame_interval(struct v4l2_subdev *subdev, + struct v4l2_subdev_frame_interval *fi) +{ + struct csi2rx_priv *csi2rx = v4l2_subdev_to_csi2rx(subdev); + + return v4l2_subdev_call(csi2rx->source_subdev, video, s_frame_interval, + fi); +} + +static int csi2rx_enum_mbus_code(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct csi2rx_priv *csi2rx = v4l2_subdev_to_csi2rx(subdev); + + return v4l2_subdev_call(csi2rx->source_subdev, pad, enum_mbus_code, + cfg, code); +} + +static int csi2rx_get_fmt(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct csi2rx_priv *csi2rx = v4l2_subdev_to_csi2rx(subdev); + + return v4l2_subdev_call(csi2rx->source_subdev, pad, get_fmt, cfg, fmt); +} + +static int csi2rx_set_fmt(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct csi2rx_priv *csi2rx = v4l2_subdev_to_csi2rx(subdev); + + return v4l2_subdev_call(csi2rx->source_subdev, pad, set_fmt, cfg, fmt); +} + +static int csi2rx_enum_frame_size(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct csi2rx_priv *csi2rx = v4l2_subdev_to_csi2rx(subdev); + + return v4l2_subdev_call(csi2rx->source_subdev, pad, enum_frame_size, + cfg, fse); +} + +static int csi2rx_enum_frame_interval(struct v4l2_subdev *subdev, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum *fie) +{ + struct csi2rx_priv *csi2rx = v4l2_subdev_to_csi2rx(subdev); + + return v4l2_subdev_call(csi2rx->source_subdev, pad, enum_frame_interval, + cfg, fie); +} + static const struct v4l2_subdev_video_ops csi2rx_video_ops = { .s_stream = csi2rx_s_stream, + .g_frame_interval = csi2rx_g_frame_interval, + .s_frame_interval = csi2rx_s_frame_interval, +}; + +static const struct v4l2_subdev_pad_ops csi2rx_pad_ops = { + .enum_mbus_code = csi2rx_enum_mbus_code, + .get_fmt = csi2rx_get_fmt, + .set_fmt = csi2rx_set_fmt, + .enum_frame_size = csi2rx_enum_frame_size, + .enum_frame_interval = csi2rx_enum_frame_interval, }; static const struct v4l2_subdev_ops csi2rx_subdev_ops = { .video = &csi2rx_video_ops, + .pad = &csi2rx_pad_ops, }; static int csi2rx_async_bound(struct v4l2_async_notifier *notifier, From patchwork Tue Mar 30 17:33:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12173319 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF797C433E3 for ; Tue, 30 Mar 2021 17:36:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 85C6E619DA for ; Tue, 30 Mar 2021 17:36:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232565AbhC3Rfp (ORCPT ); Tue, 30 Mar 2021 13:35:45 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59908 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232596AbhC3RfW (ORCPT ); Tue, 30 Mar 2021 13:35:22 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12UHZ5OJ057284; Tue, 30 Mar 2021 12:35:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1617125705; bh=exPtfFP357uEoI265sBSxQidNZbHwCy+lm1TSU/QwUI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=klAWR/g0XSp2ekS+fjDS4+DVOXI4pDzmUIoimtLc7c0L+6GJkGkI4W5QVV4YyAdYq nXuwWpMbVPfG4qZHoQi0QnX2MW9BGKQxHI2xvhdwrPA+r5w7CguUyusI6IMQA+BZGC ISZjLeYLrwKpIce8XWLipZvfufACHZndR2k3KpLw= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12UHZ5CD041024 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Mar 2021 12:35:05 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 30 Mar 2021 12:35:05 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 30 Mar 2021 12:35:05 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12UHXmgs125244; Tue, 30 Mar 2021 12:34:59 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab , Rob Herring , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Maxime Ripard , Benoit Parrot , Hans Verkuil , Alexandre Courbot , Laurent Pinchart , Stanimir Varbanov , Helen Koike , Michael Tretter , Peter Chen , Chunfeng Yun , , , , , CC: Pratyush Yadav , Vignesh Raghavendra , Tomi Valkeinen Subject: [PATCH 11/16] dmaengine: ti: k3-psil-j721e: Add entry for CSI2RX Date: Tue, 30 Mar 2021 23:03:43 +0530 Message-ID: <20210330173348.30135-12-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210330173348.30135-1-p.yadav@ti.com> References: <20210330173348.30135-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The CSI2RX subsystem uses PSI-L DMA to transfer frames to memory. It can have up to 32 threads but the current driver only supports using one. So add an entry for that one thread. Signed-off-by: Pratyush Yadav Acked-by: Peter Ujfalusi --- drivers/dma/ti/k3-psil-j721e.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/dma/ti/k3-psil-j721e.c b/drivers/dma/ti/k3-psil-j721e.c index 7580870ed746..19ffa31e6dc6 100644 --- a/drivers/dma/ti/k3-psil-j721e.c +++ b/drivers/dma/ti/k3-psil-j721e.c @@ -58,6 +58,14 @@ }, \ } +#define PSIL_CSI2RX(x) \ + { \ + .thread_id = x, \ + .ep_config = { \ + .ep_type = PSIL_EP_NATIVE, \ + }, \ + } + /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ static struct psil_ep j721e_src_ep_map[] = { /* SA2UL */ @@ -138,6 +146,8 @@ static struct psil_ep j721e_src_ep_map[] = { PSIL_PDMA_XY_PKT(0x4707), PSIL_PDMA_XY_PKT(0x4708), PSIL_PDMA_XY_PKT(0x4709), + /* CSI2RX */ + PSIL_CSI2RX(0x4940), /* CPSW9 */ PSIL_ETHERNET(0x4a00), /* CPSW0 */ From patchwork Tue Mar 30 17:33:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12173321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDD4DC433E2 for ; Tue, 30 Mar 2021 17:36:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9CE56619D4 for ; Tue, 30 Mar 2021 17:36:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232673AbhC3Rfq (ORCPT ); Tue, 30 Mar 2021 13:35:46 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:53404 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232533AbhC3Rf3 (ORCPT ); Tue, 30 Mar 2021 13:35:29 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12UHZBR8081000; Tue, 30 Mar 2021 12:35:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1617125712; bh=MPpPVeVWYZ+8y7/Bl7MCutZCIVpIdePmkSU7nZnIfkY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hDfIqO94uEz7SMUG0tdB1Mz+3+bjUhiL02eEMBnsV2XOg09ENAqu4e7ounaQ6Is5j 2fKpVpWDaxAKiKurEpuICFUpBgIPvFmHcWr0yucnff62RvLXnTU3amPoFZV4Pa/Toc 8GEoEf8R/NbRzzMA7yDcLmm/re0R+1vHyFOFqq3g= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12UHZB1C034207 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Mar 2021 12:35:11 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 30 Mar 2021 12:35:11 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 30 Mar 2021 12:35:11 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12UHXmgt125244; Tue, 30 Mar 2021 12:35:05 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab , Rob Herring , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Maxime Ripard , Benoit Parrot , Hans Verkuil , Alexandre Courbot , Laurent Pinchart , Stanimir Varbanov , Helen Koike , Michael Tretter , Peter Chen , Chunfeng Yun , , , , , CC: Pratyush Yadav , Vignesh Raghavendra , Tomi Valkeinen Subject: [PATCH 12/16] dt-bindings: media: Add DT bindings for TI CSI2RX driver Date: Tue, 30 Mar 2021 23:03:44 +0530 Message-ID: <20210330173348.30135-13-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210330173348.30135-1-p.yadav@ti.com> References: <20210330173348.30135-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org TI's J721E uses the Cadence CSI2RX and DPHY peripherals to facilitate capture over a CSI-2 bus. The TI CSI2RX platform driver glues all the parts together. Signed-off-by: Pratyush Yadav --- .../devicetree/bindings/media/ti,csi2rx.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/ti,csi2rx.yaml diff --git a/Documentation/devicetree/bindings/media/ti,csi2rx.yaml b/Documentation/devicetree/bindings/media/ti,csi2rx.yaml new file mode 100644 index 000000000000..ebd894364391 --- /dev/null +++ b/Documentation/devicetree/bindings/media/ti,csi2rx.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/ti,csi2rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI CSI2RX Wrapper Device Tree Bindings + +maintainers: + - Pratyush Yadav + +properties: + compatible: + items: + - const: ti,csi2rx + + dmas: + description: RX DMA Channel 0 + + dma-names: + items: + - const: rx0 + + reg: + maxItems: 1 + description: Base address and size of the TI wrapper registers. + + power-domains: + maxItems: 1 + description: + PM domain provider node and an args specifier containing + the device id value. + + ranges: true + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + +patternProperties: + "csi-bridge@": + type: object + description: CSI2 bridge node. + +required: + - compatible + - reg + - dmas + - dma-names + - power-domains + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + + ti_csi2rx0: ticsi2rx { + compatible = "ti,csi2rx"; + dmas = <&main_udmap 0x4940>; + dma-names = "rx0"; + reg = <0x0 0x4500000 0x0 0x1000>; + power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + }; From patchwork Tue Mar 30 17:33:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12173325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14D06C433E6 for ; Tue, 30 Mar 2021 17:36:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EBC7B619D4 for ; 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Tue, 30 Mar 2021 12:35:18 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 30 Mar 2021 12:35:17 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 30 Mar 2021 12:35:17 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12UHXmgu125244; Tue, 30 Mar 2021 12:35:12 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab , Rob Herring , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Maxime Ripard , Benoit Parrot , Hans Verkuil , Alexandre Courbot , Laurent Pinchart , Stanimir Varbanov , Helen Koike , Michael Tretter , Peter Chen , Chunfeng Yun , , , , , CC: Pratyush Yadav , Vignesh Raghavendra , Tomi Valkeinen Subject: [PATCH 13/16] media: ti-vpe: csi2rx: Add CSI2RX support Date: Tue, 30 Mar 2021 23:03:45 +0530 Message-ID: <20210330173348.30135-14-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210330173348.30135-1-p.yadav@ti.com> References: <20210330173348.30135-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org TI's J721E uses the Cadence CSI2RX and DPHY peripherals to facilitate capture over a CSI-2 bus. The Cadence CSI2RX IP acts as a bridge between the TI specific parts and the CSI-2 protocol parts. TI then has a wrapper on top of this bridge called the SHIM layer. It takes in data from stream 0, repacks it, and sends it to memory over PSI-L DMA. This driver acts as the "front end" to V4L2 client applications. It implements the required ioctls and buffer operations, passes the necessary calls on to the bridge, programs the SHIM layer, and performs DMA via the dmaengine API to finally return the data to a buffer supplied by the application. Signed-off-by: Pratyush Yadav --- MAINTAINERS | 7 + drivers/media/platform/Kconfig | 11 + drivers/media/platform/ti-vpe/Makefile | 1 + drivers/media/platform/ti-vpe/ti-csi2rx.c | 964 ++++++++++++++++++++++ 4 files changed, 983 insertions(+) create mode 100644 drivers/media/platform/ti-vpe/ti-csi2rx.c diff --git a/MAINTAINERS b/MAINTAINERS index 8c44fd8fd85d..06fb8fdb874d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18006,6 +18006,13 @@ S: Odd Fixes F: drivers/clk/ti/ F: include/linux/clk/ti.h +TI CSI2RX DRIVER +M: Pratyush Yadav +L: linux-media@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/media/ti,csi2rx.yaml +F: drivers/media/platform/ti-vpe/ti-csi2rx.c + TI DAVINCI MACHINE SUPPORT M: Sekhar Nori R: Bartosz Golaszewski diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index b238a923d1b4..3b240d8e4cb8 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -200,6 +200,17 @@ config VIDEO_TI_CAL_MC endif # VIDEO_TI_CAL +config VIDEO_TI_CSI2RX + tristate "TI CSI2RX wrapper layer driver" + depends on VIDEO_DEV && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && MEDIA_SUPPORT + depends on PHY_CADENCE_DPHY && VIDEO_CADENCE_CSI2RX + depends on ARCH_K3 || COMPILE_TEST + select VIDEOBUF2_DMA_CONTIG + select V4L2_FWNODE + help + Support for TI CSI2RX wrapper layer. This just enables the wrapper driver. + The Cadence CSI2RX bridge driver needs to be enabled separately. + endif # V4L_PLATFORM_DRIVERS menuconfig V4L_MEM2MEM_DRIVERS diff --git a/drivers/media/platform/ti-vpe/Makefile b/drivers/media/platform/ti-vpe/Makefile index ad624056e039..c4ee49484b73 100644 --- a/drivers/media/platform/ti-vpe/Makefile +++ b/drivers/media/platform/ti-vpe/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_VIDEO_TI_VPE) += ti-vpe.o obj-$(CONFIG_VIDEO_TI_VPDMA) += ti-vpdma.o obj-$(CONFIG_VIDEO_TI_SC) += ti-sc.o obj-$(CONFIG_VIDEO_TI_CSC) += ti-csc.o +obj-$(CONFIG_VIDEO_TI_CSI2RX) += ti-csi2rx.o ti-vpe-y := vpe.o ti-vpdma-y := vpdma.o diff --git a/drivers/media/platform/ti-vpe/ti-csi2rx.c b/drivers/media/platform/ti-vpe/ti-csi2rx.c new file mode 100644 index 000000000000..355204ae473b --- /dev/null +++ b/drivers/media/platform/ti-vpe/ti-csi2rx.c @@ -0,0 +1,964 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * TI CSI2 RX driver. + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * + * Author: Pratyush Yadav + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#define TI_CSI2RX_MODULE_NAME "ti-csi2rx" + +#define SHIM_CNTL 0x10 +#define SHIM_CNTL_PIX_RST BIT(0) + +#define SHIM_DMACNTX 0x20 +#define SHIM_DMACNTX_EN BIT(31) +#define SHIM_DMACNTX_YUV422 GENMASK(27, 26) +#define SHIM_DMACNTX_FMT GENMASK(5, 0) +#define SHIM_DMACNTX_UYVY 0 +#define SHIM_DMACNTX_VYUY 1 +#define SHIM_DMACNTX_YUYV 2 +#define SHIM_DMACNTX_YVYU 3 + +#define SHIM_PSI_CFG0 0x24 +#define SHIM_PSI_CFG0_SRC_TAG GENMASK(15, 0) +#define SHIM_PSI_CFG0_DST_TAG GENMASK(31, 15) + +#define CSI_DF_YUV420 0x18 +#define CSI_DF_YUV422 0x1e +#define CSI_DF_RGB444 0x20 +#define CSI_DF_RGB888 0x24 + +struct ti_csi2rx_fmt { + u32 fourcc; /* Four character code. */ + u32 code; /* Mbus code. */ + u32 csi_df; /* CSI Data format. */ + u8 bpp; /* Bits per pixel. */ +}; + +struct ti_csi2rx_buffer { + /* Common v4l2 buffer. Must be first. */ + struct vb2_v4l2_buffer vb; + struct list_head list; +}; + +struct ti_csi2rx_dmaq { + struct list_head list; +}; + +struct ti_csi2rx_dev { + struct device *dev; + void __iomem *shim; + struct v4l2_device v4l2_dev; + struct video_device vdev; + struct media_device mdev; + struct v4l2_async_notifier notifier; + struct v4l2_subdev *subdev; + struct vb2_queue vidq; + struct mutex mutex; /* To serialize ioctls. */ + const struct ti_csi2rx_fmt **supported_fmts; + unsigned int num_supported_fmts; + struct v4l2_format v_fmt; + struct dma_chan *dma; + struct ti_csi2rx_dmaq dmaq; + u32 sequence; +}; + +static const struct ti_csi2rx_fmt formats[] = { + { + .fourcc = V4L2_PIX_FMT_YUYV, + .code = MEDIA_BUS_FMT_YUYV8_2X8, + .csi_df = CSI_DF_YUV422, + .bpp = 16, + }, { + .fourcc = V4L2_PIX_FMT_UYVY, + .code = MEDIA_BUS_FMT_UYVY8_2X8, + .csi_df = CSI_DF_YUV422, + .bpp = 16, + }, { + .fourcc = V4L2_PIX_FMT_YVYU, + .code = MEDIA_BUS_FMT_YVYU8_2X8, + .csi_df = CSI_DF_YUV422, + .bpp = 16, + }, { + .fourcc = V4L2_PIX_FMT_VYUY, + .code = MEDIA_BUS_FMT_VYUY8_2X8, + .csi_df = CSI_DF_YUV422, + .bpp = 16, + }, + + /* More formats can be supported but they are not listed for now. */ +}; + +/* Forward declaration needed by ti_csi2rx_dma_callback. */ +static int ti_csi2rx_start_dma(struct ti_csi2rx_dev *csi, + struct ti_csi2rx_buffer *buf); + +static const struct ti_csi2rx_fmt *find_format_by_pix(struct ti_csi2rx_dev *csi, + u32 pixelformat) +{ + const struct ti_csi2rx_fmt *fmt; + unsigned int i; + + for (i = 0; i < csi->num_supported_fmts; i++) { + fmt = csi->supported_fmts[i]; + if (fmt->fourcc == pixelformat) + return fmt; + } + + return NULL; +} + +static const struct ti_csi2rx_fmt *find_format_by_code(struct ti_csi2rx_dev *csi, + u32 code) +{ + const struct ti_csi2rx_fmt *fmt; + unsigned int i; + + for (i = 0; i < csi->num_supported_fmts; i++) { + fmt = csi->supported_fmts[i]; + if (fmt->code == code) + return fmt; + } + + return NULL; +} + +static void ti_csi2rx_fill_fmt(struct v4l2_mbus_framefmt *mbus_fmt, + const struct ti_csi2rx_fmt *csi_fmt, + struct v4l2_format *v4l2_fmt) +{ + u32 bpl; + + v4l2_fill_pix_format(&v4l2_fmt->fmt.pix, mbus_fmt); + v4l2_fmt->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + v4l2_fmt->fmt.pix.pixelformat = csi_fmt->fourcc; + v4l2_fmt->fmt.pix.sizeimage = v4l2_fmt->fmt.pix.height * + v4l2_fmt->fmt.pix.width * + (csi_fmt->bpp / 8); + + bpl = (v4l2_fmt->fmt.pix.width * ALIGN(csi_fmt->bpp, 8)) >> 3; + v4l2_fmt->fmt.pix.bytesperline = ALIGN(bpl, 16); +} + +static int ti_csi2rx_init_formats(struct ti_csi2rx_dev *csi) +{ + struct v4l2_subdev_mbus_code_enum mbus_code; + struct v4l2_mbus_framefmt mbus_fmt; + struct v4l2_subdev_format sd_fmt; + const struct ti_csi2rx_fmt *fmt; + unsigned int i, j, k; + int ret = 0; + + csi->supported_fmts = devm_kcalloc(csi->dev, ARRAY_SIZE(formats), + sizeof(*csi->supported_fmts), + GFP_KERNEL); + if (!csi->supported_fmts) + return -ENOMEM; + + csi->num_supported_fmts = 0; + + /* Find a set of formarts supported by both CSI2RX and camera. */ + for (j = 0, i = 0; ret != -EINVAL; j++) { + memset(&mbus_code, 0, sizeof(mbus_code)); + mbus_code.index = j; + mbus_code.which = V4L2_SUBDEV_FORMAT_ACTIVE; + ret = v4l2_subdev_call(csi->subdev, pad, enum_mbus_code, NULL, + &mbus_code); + if (ret) + continue; + + for (k = 0; k < ARRAY_SIZE(formats); k++) { + const struct ti_csi2rx_fmt *fmt = &formats[k]; + + if (mbus_code.code == fmt->code) { + csi->supported_fmts[i] = fmt; + csi->num_supported_fmts = ++i; + } + } + } + + if (i == 0) + return -EINVAL; /* No format mutually supported. */ + + /* Get the current format from the subdev. */ + sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; + sd_fmt.pad = 0; + + ret = v4l2_subdev_call(csi->subdev, pad, get_fmt, NULL, &sd_fmt); + if (ret) + return ret; + + mbus_fmt = sd_fmt.format; + + fmt = find_format_by_code(csi, mbus_fmt.code); + if (!fmt) + return -EINVAL; + + /* + * YUV422 8-bit should always be sent by the camera in UYVY. Format + * conversions to other YUV422 formats will be done later by SHIM. + */ + if (fmt->csi_df == CSI_DF_YUV422 && + fmt->code != MEDIA_BUS_FMT_UYVY8_2X8) { + sd_fmt.format.code = MEDIA_BUS_FMT_UYVY8_2X8; + ret = v4l2_subdev_call(csi->subdev, pad, set_fmt, NULL, &sd_fmt); + if (ret) + return ret; + } + + ti_csi2rx_fill_fmt(&mbus_fmt, fmt, &csi->v_fmt); + + return 0; +} + +static int ti_csi2rx_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + struct ti_csi2rx_dev *csi = video_drvdata(file); + + strscpy(cap->driver, TI_CSI2RX_MODULE_NAME, sizeof(cap->driver)); + strscpy(cap->card, TI_CSI2RX_MODULE_NAME, sizeof(cap->card)); + + snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", + dev_name(csi->dev)); + + return 0; +} + +static int ti_csi2rx_enum_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + struct ti_csi2rx_dev *csi = video_drvdata(file); + const struct ti_csi2rx_fmt *fmt; + + if (f->index >= csi->num_supported_fmts) + return -EINVAL; + + if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + return -EINVAL; + + fmt = csi->supported_fmts[f->index]; + + f->pixelformat = fmt->fourcc; + + return 0; +} + +static int ti_csi2rx_g_fmt_vid_cap(struct file *file, void *prov, + struct v4l2_format *f) +{ + struct ti_csi2rx_dev *csi = video_drvdata(file); + + *f = csi->v_fmt; + + return 0; +} + +static int ti_csi2rx_try_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct ti_csi2rx_dev *csi = video_drvdata(file); + const struct ti_csi2rx_fmt *fmt; + struct v4l2_subdev_frame_size_enum fse; + int ret, found; + + fmt = find_format_by_pix(csi, f->fmt.pix.pixelformat); + if (!fmt) { + /* Just get the first one enumerated */ + fmt = csi->supported_fmts[0]; + f->fmt.pix.pixelformat = fmt->fourcc; + } + + f->fmt.pix.field = csi->v_fmt.fmt.pix.field; + + /* Check for/find a valid width/height. */ + ret = 0; + found = false; + fse.pad = 0; + fse.code = fmt->code; + fse.which = V4L2_SUBDEV_FORMAT_ACTIVE; + for (fse.index = 0; ; fse.index++) { + ret = v4l2_subdev_call(csi->subdev, pad, enum_frame_size, NULL, + &fse); + if (ret) + break; + + if (f->fmt.pix.width == fse.max_width && + f->fmt.pix.height == fse.max_height) { + found = true; + break; + } else if (f->fmt.pix.width >= fse.min_width && + f->fmt.pix.width <= fse.max_width && + f->fmt.pix.height >= fse.min_height && + f->fmt.pix.height <= fse.max_height) { + found = true; + break; + } + } + + if (!found) { + /* use existing values as default */ + f->fmt.pix.width = csi->v_fmt.fmt.pix.width; + f->fmt.pix.height = csi->v_fmt.fmt.pix.height; + } + + /* + * Use current colorspace for now, it will get + * updated properly during s_fmt + */ + f->fmt.pix.colorspace = csi->v_fmt.fmt.pix.colorspace; + f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height * + (fmt->bpp / 8); + + return 0; +} + +static int ti_csi2rx_s_fmt_vid_cap(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct ti_csi2rx_dev *csi = video_drvdata(file); + struct vb2_queue *q = &csi->vidq; + const struct ti_csi2rx_fmt *fmt; + struct v4l2_mbus_framefmt mbus_fmt; + struct v4l2_subdev_format sd_fmt; + int ret; + + if (vb2_is_busy(q)) + return -EBUSY; + + ret = ti_csi2rx_try_fmt_vid_cap(file, priv, f); + if (ret < 0) + return ret; + + fmt = find_format_by_pix(csi, f->fmt.pix.pixelformat); + if (!fmt) + return -EINVAL; + + v4l2_fill_mbus_format(&mbus_fmt, &f->fmt.pix, fmt->code); + + sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; + sd_fmt.pad = 0; + sd_fmt.format = mbus_fmt; + + /* + * The MIPI CSI-2 spec says that YUV422 8-bit data transmission is + * perfromed using UYVY sequence. So the hardware always expects UYVY + * for YUV422 streams. Ask the subdev to send UYVY data and then we can + * repack it later into the format requested by the application using + * the SHIM layer. + */ + if (fmt->csi_df == CSI_DF_YUV422) + sd_fmt.format.code = MEDIA_BUS_FMT_UYVY8_2X8; + else + sd_fmt.format.code = fmt->code; + + ret = v4l2_subdev_call(csi->subdev, pad, set_fmt, NULL, &sd_fmt); + if (ret) + return ret; + + ti_csi2rx_fill_fmt(&mbus_fmt, fmt, &csi->v_fmt); + *f = csi->v_fmt; + + return 0; +} + +static int ti_csi2rx_enum_framesizes(struct file *file, void *fh, + struct v4l2_frmsizeenum *fsize) +{ + struct ti_csi2rx_dev *csi = video_drvdata(file); + const struct ti_csi2rx_fmt *fmt; + struct v4l2_subdev_frame_size_enum fse; + int ret; + + fmt = find_format_by_pix(csi, fsize->pixel_format); + if (!fmt) + return -EINVAL; + + fse.index = fsize->index; + fse.code = fmt->code; + fse.which = V4L2_SUBDEV_FORMAT_ACTIVE; + fse.pad = 0; + + ret = v4l2_subdev_call(csi->subdev, pad, enum_frame_size, NULL, &fse); + if (ret) + return ret; + + fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; + fsize->discrete.width = fse.max_width; + fsize->discrete.height = fse.max_height; + + return 0; +} + +static int ti_csi2rx_enum_input(struct file *file, void *priv, + struct v4l2_input *inp) +{ + if (inp->index > 0) + return -EINVAL; + + inp->type = V4L2_INPUT_TYPE_CAMERA; + snprintf(inp->name, sizeof(inp->name), "Camera %u", inp->index); + + return 0; +} + +static int ti_csi2rx_g_input(struct file *file, void *priv, unsigned int *i) +{ + *i = 0; + return 0; +} + +static int ti_csi2rx_s_input(struct file *file, void *priv, unsigned int i) +{ + return i > 0 ? -EINVAL : 0; +} + +static int ti_csi2rx_enum_frameintervals(struct file *file, void *priv, + struct v4l2_frmivalenum *fival) +{ + struct ti_csi2rx_dev *csi = video_drvdata(file); + const struct ti_csi2rx_fmt *fmt; + struct v4l2_subdev_frame_interval_enum fie = { + .index = fival->index, + .width = fival->width, + .height = fival->height, + .which = V4L2_SUBDEV_FORMAT_ACTIVE, + }; + int ret; + + fmt = find_format_by_pix(csi, fival->pixel_format); + if (!fmt) + return -EINVAL; + + fie.code = fmt->code; + ret = v4l2_subdev_call(csi->subdev, pad, enum_frame_interval, + NULL, &fie); + if (ret) + return ret; + fival->type = V4L2_FRMIVAL_TYPE_DISCRETE; + fival->discrete = fie.interval; + + return 0; +} + +static int ti_csi2rx_g_parm(struct file *file, void *fh, + struct v4l2_streamparm *a) +{ + struct ti_csi2rx_dev *csi = video_drvdata(file); + + return v4l2_g_parm_cap(video_devdata(file), csi->subdev, a); +} + +static int ti_csi2rx_s_parm(struct file *file, void *fh, + struct v4l2_streamparm *a) +{ + struct ti_csi2rx_dev *csi = video_drvdata(file); + + return v4l2_s_parm_cap(video_devdata(file), csi->subdev, a); +} + +static const struct v4l2_ioctl_ops csi_ioctl_ops = { + .vidioc_querycap = ti_csi2rx_querycap, + .vidioc_enum_fmt_vid_cap = ti_csi2rx_enum_fmt_vid_cap, + .vidioc_try_fmt_vid_cap = ti_csi2rx_try_fmt_vid_cap, + .vidioc_g_fmt_vid_cap = ti_csi2rx_g_fmt_vid_cap, + .vidioc_s_fmt_vid_cap = ti_csi2rx_s_fmt_vid_cap, + .vidioc_enum_framesizes = ti_csi2rx_enum_framesizes, + .vidioc_enum_input = ti_csi2rx_enum_input, + .vidioc_g_input = ti_csi2rx_g_input, + .vidioc_s_input = ti_csi2rx_s_input, + .vidioc_enum_frameintervals = ti_csi2rx_enum_frameintervals, + .vidioc_g_parm = ti_csi2rx_g_parm, + .vidioc_s_parm = ti_csi2rx_s_parm, + .vidioc_reqbufs = vb2_ioctl_reqbufs, + .vidioc_create_bufs = vb2_ioctl_create_bufs, + .vidioc_prepare_buf = vb2_ioctl_prepare_buf, + .vidioc_querybuf = vb2_ioctl_querybuf, + .vidioc_qbuf = vb2_ioctl_qbuf, + .vidioc_dqbuf = vb2_ioctl_dqbuf, + .vidioc_expbuf = vb2_ioctl_expbuf, + .vidioc_streamon = vb2_ioctl_streamon, + .vidioc_streamoff = vb2_ioctl_streamoff, +}; + +static const struct v4l2_file_operations csi_fops = { + .owner = THIS_MODULE, + .open = v4l2_fh_open, + .release = vb2_fop_release, + .read = vb2_fop_read, + .poll = vb2_fop_poll, + .unlocked_ioctl = video_ioctl2, + .mmap = vb2_fop_mmap, +}; + +static int ti_csi2rx_init_video(struct ti_csi2rx_dev *csi) +{ + struct video_device *vdev = &csi->vdev; + int ret; + + strscpy(vdev->name, TI_CSI2RX_MODULE_NAME, sizeof(vdev->name)); + vdev->v4l2_dev = &csi->v4l2_dev; + vdev->vfl_dir = VFL_DIR_RX; + vdev->fops = &csi_fops; + vdev->ioctl_ops = &csi_ioctl_ops; + vdev->release = video_device_release_empty; + vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | + V4L2_CAP_STREAMING; + vdev->lock = &csi->mutex; + video_set_drvdata(vdev, csi); + + ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); + if (ret) + return ret; + + return 0; +} + +static int csi_async_notifier_bound(struct v4l2_async_notifier *notifier, + struct v4l2_subdev *subdev, + struct v4l2_async_subdev *asd) +{ + struct ti_csi2rx_dev *csi = dev_get_drvdata(notifier->v4l2_dev->dev); + + csi->subdev = subdev; + + return 0; +} + +static int csi_async_notifier_complete(struct v4l2_async_notifier *notifier) +{ + struct ti_csi2rx_dev *csi = dev_get_drvdata(notifier->v4l2_dev->dev); + int ret; + + ret = ti_csi2rx_init_formats(csi); + if (ret) + return ret; + + ret = ti_csi2rx_init_video(csi); + if (ret) + return ret; + + return 0; +} + +static const struct v4l2_async_notifier_operations csi_async_notifier_ops = { + .bound = csi_async_notifier_bound, + .complete = csi_async_notifier_complete, +}; + +static int ti_csi2rx_init_subdev(struct ti_csi2rx_dev *csi) +{ + struct fwnode_handle *fwnode; + struct v4l2_async_subdev *asd; + struct device_node *node; + int ret; + + node = of_get_child_by_name(csi->dev->of_node, "csi-bridge"); + if (!node) + return -EINVAL; + + v4l2_async_notifier_init(&csi->notifier); + csi->notifier.ops = &csi_async_notifier_ops; + + fwnode = of_fwnode_handle(node); + if (!fwnode) + return -EINVAL; + + asd = v4l2_async_notifier_add_fwnode_subdev(&csi->notifier, fwnode, + struct v4l2_async_subdev); + if (IS_ERR(asd)) + return PTR_ERR(asd); + + ret = v4l2_async_notifier_register(&csi->v4l2_dev, &csi->notifier); + if (ret) + return ret; + + return 0; +} + +static void ti_csi2rx_setup_shim(struct ti_csi2rx_dev *csi) +{ + const struct ti_csi2rx_fmt *fmt; + unsigned int reg; + + fmt = find_format_by_pix(csi, csi->v_fmt.fmt.pix.pixelformat); + if (!fmt) { + dev_err(csi->dev, "Unknown format\n"); + return; + } + + /* De-assert the pixel interface reset. */ + reg = SHIM_CNTL_PIX_RST; + writel(reg, csi->shim + SHIM_CNTL); + + reg = SHIM_DMACNTX_EN; + reg |= FIELD_PREP(SHIM_DMACNTX_FMT, fmt->csi_df); + + /* + * FIXME: Using the values from the documentation gives incorrect + * ordering for the luma and chroma components. In practice, the + * "reverse" format gives the correct image. So for example, if the + * image is in UYVY, the reverse would be YVYU. + */ + switch (fmt->fourcc) { + case V4L2_PIX_FMT_UYVY: + reg |= FIELD_PREP(SHIM_DMACNTX_YUV422, + SHIM_DMACNTX_YVYU); + break; + case V4L2_PIX_FMT_VYUY: + reg |= FIELD_PREP(SHIM_DMACNTX_YUV422, + SHIM_DMACNTX_YUYV); + break; + case V4L2_PIX_FMT_YUYV: + reg |= FIELD_PREP(SHIM_DMACNTX_YUV422, + SHIM_DMACNTX_VYUY); + break; + case V4L2_PIX_FMT_YVYU: + reg |= FIELD_PREP(SHIM_DMACNTX_YUV422, + SHIM_DMACNTX_UYVY); + break; + default: + /* Ignore if not YUV 4:2:2 */ + break; + } + + writel(reg, csi->shim + SHIM_DMACNTX); + + reg = FIELD_PREP(SHIM_PSI_CFG0_SRC_TAG, 0) | + FIELD_PREP(SHIM_PSI_CFG0_DST_TAG, 1); + writel(reg, csi->shim + SHIM_PSI_CFG0); +} + +static void ti_csi2rx_dma_callback(void *param) +{ + struct ti_csi2rx_dev *csi = param; + struct ti_csi2rx_buffer *buf; + struct ti_csi2rx_dmaq *dmaq = &csi->dmaq; + + buf = list_entry(dmaq->list.next, struct ti_csi2rx_buffer, list); + list_del(&buf->list); + + buf->vb.vb2_buf.timestamp = ktime_get_ns(); + buf->vb.sequence = csi->sequence++; + + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE); + + /* If there are more buffers to process then start their transfer. */ + if (list_empty(&dmaq->list)) + return; + + buf = list_entry(dmaq->list.next, struct ti_csi2rx_buffer, list); + + if (ti_csi2rx_start_dma(csi, buf)) + dev_err(csi->dev, "Failed to queue the next buffer for DMA\n"); +} + +static int ti_csi2rx_start_dma(struct ti_csi2rx_dev *csi, + struct ti_csi2rx_buffer *buf) +{ + unsigned long addr; + struct dma_async_tx_descriptor *desc; + size_t len = csi->v_fmt.fmt.pix.sizeimage; + dma_cookie_t cookie; + int ret = 0; + + addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0); + desc = dmaengine_prep_slave_single(csi->dma, addr, len, DMA_DEV_TO_MEM, + DMA_PREP_INTERRUPT | DMA_CTRL_ACK); + if (!desc) + return -EIO; + + desc->callback = ti_csi2rx_dma_callback; + desc->callback_param = csi; + + cookie = dmaengine_submit(desc); + ret = dma_submit_error(cookie); + if (ret) + return ret; + + dma_async_issue_pending(csi->dma); + + return 0; +} + +static int ti_csi2rx_queue_setup(struct vb2_queue *q, unsigned int *nbuffers, + unsigned int *nplanes, unsigned int sizes[], + struct device *alloc_devs[]) +{ + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(q); + unsigned int size = csi->v_fmt.fmt.pix.sizeimage; + + if (*nplanes) { + if (sizes[0] < size) + return -EINVAL; + size = sizes[0]; + } + + *nplanes = 1; + sizes[0] = size; + + return 0; +} + +static int ti_csi2rx_buffer_prepare(struct vb2_buffer *vb) +{ + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vb->vb2_queue); + unsigned long size = csi->v_fmt.fmt.pix.sizeimage; + + if (vb2_plane_size(vb, 0) < size) { + dev_err(csi->dev, "Data will not fit into plane\n"); + return -EINVAL; + } + + vb2_set_plane_payload(vb, 0, size); + return 0; +} + +static void ti_csi2rx_buffer_queue(struct vb2_buffer *vb) +{ + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vb->vb2_queue); + struct ti_csi2rx_buffer *buf; + struct ti_csi2rx_dmaq *dmaq = &csi->dmaq; + + buf = container_of(vb, struct ti_csi2rx_buffer, vb.vb2_buf); + + list_add_tail(&buf->list, &dmaq->list); +} + +static int ti_csi2rx_start_streaming(struct vb2_queue *vq, unsigned int count) +{ + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vq); + struct ti_csi2rx_dmaq *dmaq = &csi->dmaq; + struct ti_csi2rx_buffer *buf, *tmp; + int ret; + + if (list_empty(&dmaq->list)) + return -EIO; + + ti_csi2rx_setup_shim(csi); + + ret = v4l2_subdev_call(csi->subdev, video, s_stream, 1); + if (ret) + goto err; + + csi->sequence = 0; + + buf = list_entry(dmaq->list.next, struct ti_csi2rx_buffer, list); + ret = ti_csi2rx_start_dma(csi, buf); + if (ret) { + dev_err(csi->dev, "Failed to start DMA: %d\n", ret); + goto err; + } + + return 0; + +err: + v4l2_subdev_call(csi->subdev, video, s_stream, 0); + list_for_each_entry_safe(buf, tmp, &dmaq->list, list) { + list_del(&buf->list); + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED); + } + + return ret; +} + +static void ti_csi2rx_stop_streaming(struct vb2_queue *vq) +{ + struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vq); + struct ti_csi2rx_buffer *buf = NULL, *tmp; + int ret; + + ret = v4l2_subdev_call(csi->subdev, video, s_stream, 0); + if (ret) + dev_err(csi->dev, "Failed to stop subdev stream\n"); + + writel(0, csi->shim + SHIM_CNTL); + + ret = dmaengine_terminate_sync(csi->dma); + if (ret) + dev_err(csi->dev, "Failed to stop DMA\n"); + + writel(0, csi->shim + SHIM_DMACNTX); + + list_for_each_entry_safe(buf, tmp, &csi->dmaq.list, list) { + list_del(&buf->list); + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + } +} + +static const struct vb2_ops csi_vb2_qops = { + .queue_setup = ti_csi2rx_queue_setup, + .buf_prepare = ti_csi2rx_buffer_prepare, + .buf_queue = ti_csi2rx_buffer_queue, + .start_streaming = ti_csi2rx_start_streaming, + .stop_streaming = ti_csi2rx_stop_streaming, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, +}; + +static int ti_csi2rx_init_vb2q(struct ti_csi2rx_dev *csi) +{ + struct vb2_queue *q = &csi->vidq; + int ret; + + q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ; + q->drv_priv = csi; + q->buf_struct_size = sizeof(struct ti_csi2rx_buffer); + q->ops = &csi_vb2_qops; + q->mem_ops = &vb2_dma_contig_memops; + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; + q->dev = csi->dma->device->dev; + q->lock = &csi->mutex; + + ret = vb2_queue_init(q); + if (ret) + return ret; + + csi->vdev.queue = q; + + return 0; +} + +static int ti_csi2rx_init_dma(struct ti_csi2rx_dev *csi) +{ + struct dma_slave_config cfg; + int ret; + + INIT_LIST_HEAD(&csi->dmaq.list); + + csi->dma = NULL; + + csi->dma = dma_request_chan(csi->dev, "rx0"); + if (IS_ERR(csi->dma)) + return PTR_ERR(csi->dma); + + memset(&cfg, 0, sizeof(cfg)); + + cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_16_BYTES; + cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_16_BYTES; + + ret = dmaengine_slave_config(csi->dma, &cfg); + if (ret) + return ret; + + return 0; +} + +static int ti_csi2rx_media_init(struct ti_csi2rx_dev *csi) +{ + struct media_device *mdev = &csi->mdev; + + mdev->dev = csi->dev; + strscpy(mdev->model, "TI-CSI2RX", sizeof(mdev->model)); + snprintf(mdev->bus_info, sizeof(mdev->bus_info), "platform:%s", + dev_name(mdev->dev)); + + media_device_init(mdev); + + return 0; +} + +static int ti_csi2rx_probe(struct platform_device *pdev) +{ + struct ti_csi2rx_dev *csi; + struct resource *res; + int ret; + + csi = devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL); + if (!csi) + return -ENOMEM; + + csi->dev = &pdev->dev; + platform_set_drvdata(pdev, csi); + + mutex_init(&csi->mutex); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + csi->shim = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(csi->shim)) + return PTR_ERR(csi->shim); + + ret = ti_csi2rx_media_init(csi); + if (ret) + return ret; + + csi->v4l2_dev.mdev = &csi->mdev; + + ret = v4l2_device_register(csi->dev, &csi->v4l2_dev); + if (ret) + return ret; + + ret = ti_csi2rx_init_dma(csi); + if (ret) + return ret; + + ret = ti_csi2rx_init_vb2q(csi); + if (ret) + return ret; + + ret = ti_csi2rx_init_subdev(csi); + if (ret) + return ret; + + ret = of_platform_populate(csi->dev->of_node, NULL, NULL, csi->dev); + if (ret) { + dev_err(csi->dev, "Failed to create children: %d\n", ret); + return ret; + } + + return 0; +} + +static int ti_csi2rx_remove(struct platform_device *pdev) +{ + struct ti_csi2rx_dev *csi = platform_get_drvdata(pdev); + + if (vb2_is_busy(&csi->vidq)) + return -EBUSY; + + vb2_queue_release(&csi->vidq); + v4l2_async_notifier_unregister(&csi->notifier); + v4l2_async_notifier_cleanup(&csi->notifier); + v4l2_device_unregister(&csi->v4l2_dev); + video_unregister_device(&csi->vdev); + dma_release_channel(csi->dma); + + return 0; +} + +static const struct of_device_id ti_csi2rx_of_match[] = { + { + .compatible = "ti,csi2rx", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, ti_csi2rx_of_match); + +static struct platform_driver ti_csi2rx_pdrv = { + .probe = ti_csi2rx_probe, + .remove = ti_csi2rx_remove, + .driver = { + .name = TI_CSI2RX_MODULE_NAME, + .of_match_table = ti_csi2rx_of_match, + }, +}; + +module_platform_driver(ti_csi2rx_pdrv); + +MODULE_DESCRIPTION("TI CSI2 RX Driver"); +MODULE_AUTHOR("Pratyush Yadav "); +MODULE_LICENSE("GPL v2"); +MODULE_VERSION("1.0"); From patchwork Tue Mar 30 17:33:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12173323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38D63C433E8 for ; Tue, 30 Mar 2021 17:36:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 27335619D4 for ; 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Tue, 30 Mar 2021 12:35:24 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 30 Mar 2021 12:35:24 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 30 Mar 2021 12:35:24 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12UHXmgv125244; Tue, 30 Mar 2021 12:35:18 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab , Rob Herring , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Maxime Ripard , Benoit Parrot , Hans Verkuil , Alexandre Courbot , Laurent Pinchart , Stanimir Varbanov , Helen Koike , Michael Tretter , Peter Chen , Chunfeng Yun , , , , , CC: Pratyush Yadav , Vignesh Raghavendra , Tomi Valkeinen Subject: [PATCH 14/16] dt-bindings: phy: Convert Cadence DPHY binding to YAML Date: Tue, 30 Mar 2021 23:03:46 +0530 Message-ID: <20210330173348.30135-15-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210330173348.30135-1-p.yadav@ti.com> References: <20210330173348.30135-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Convert Cadence DPHY binding to YAML. Signed-off-by: Pratyush Yadav Reviewed-by: Laurent Pinchart --- .../devicetree/bindings/phy/cdns,dphy.txt | 20 -------- .../devicetree/bindings/phy/cdns,dphy.yaml | 51 +++++++++++++++++++ 2 files changed, 51 insertions(+), 20 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.txt create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.yaml diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.txt b/Documentation/devicetree/bindings/phy/cdns,dphy.txt deleted file mode 100644 index 1095bc4e72d9..000000000000 --- a/Documentation/devicetree/bindings/phy/cdns,dphy.txt +++ /dev/null @@ -1,20 +0,0 @@ -Cadence DPHY -============ - -Cadence DPHY block. - -Required properties: -- compatible: should be set to "cdns,dphy". -- reg: physical base address and length of the DPHY registers. -- clocks: DPHY reference clocks. -- clock-names: must contain "psm" and "pll_ref". -- #phy-cells: must be set to 0. - -Example: - dphy0: dphy@fd0e0000{ - compatible = "cdns,dphy"; - reg = <0x0 0xfd0e0000 0x0 0x1000>; - clocks = <&psm_clk>, <&pll_ref_clk>; - clock-names = "psm", "pll_ref"; - #phy-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml new file mode 100644 index 000000000000..d1bbf96a8250 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/cdns,dphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence DPHY Device Tree Bindings + +maintainers: + - Pratyush Yadav + +properties: + compatible: + items: + - const: cdns,dphy + + reg: + maxItems: 1 + description: Physical base address and length of the DPHY registers. + + clocks: + maxItems: 2 + description: DPHY reference clocks. + + clock-names: + items: + - const: psm + - const: pll_ref + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + + dphy0: dphy@fd0e0000{ + compatible = "cdns,dphy"; + reg = <0xfd0e0000 0x1000>; + clocks = <&psm_clk>, <&pll_ref_clk>; + clock-names = "psm", "pll_ref"; + #phy-cells = <0>; + }; From patchwork Tue Mar 30 17:33:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12173327 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A723CC433E0 for ; Tue, 30 Mar 2021 17:36:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 74C16619B1 for ; Tue, 30 Mar 2021 17:36:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232118AbhC3RgR (ORCPT ); Tue, 30 Mar 2021 13:36:17 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:53484 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232677AbhC3Rfr (ORCPT ); Tue, 30 Mar 2021 13:35:47 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12UHZU9p081116; Tue, 30 Mar 2021 12:35:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1617125730; bh=ewQUu325okFcaLjgG8+e0h6OWIBSBc+EpQyni7KIvkA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mpb/IeNPzO+DKsd/Z2BvZiVCfg67vsDlwsvKqNk5h7h0yA5MoPSXJ3pGI+daz/fOK I3QXzMZwIz3aXv7hMKC8hFhXYRVWQmkdR1Xw/kxS71m9x9t4dHA/CyVo4pC7o1OJ8b QlJhrAKuxYWmGqS0yGpZtXjB/QuXmRg2xmQjL8vw= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12UHZUwE034861 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Mar 2021 12:35:30 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 30 Mar 2021 12:35:30 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 30 Mar 2021 12:35:30 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12UHXmgw125244; Tue, 30 Mar 2021 12:35:24 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab , Rob Herring , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Maxime Ripard , Benoit Parrot , Hans Verkuil , Alexandre Courbot , Laurent Pinchart , Stanimir Varbanov , Helen Koike , Michael Tretter , Peter Chen , Chunfeng Yun , , , , , CC: Pratyush Yadav , Vignesh Raghavendra , Tomi Valkeinen Subject: [PATCH 15/16] dt-bindings: phy: cdns,dphy: make clocks optional Date: Tue, 30 Mar 2021 23:03:47 +0530 Message-ID: <20210330173348.30135-16-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210330173348.30135-1-p.yadav@ti.com> References: <20210330173348.30135-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The clocks are not used by the DPHY when used in Rx mode so make them optional. Signed-off-by: Pratyush Yadav --- Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml index d1bbf96a8250..0807ba68284d 100644 --- a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml @@ -33,8 +33,6 @@ properties: required: - compatible - reg - - clocks - - clock-names - "#phy-cells" additionalProperties: false From patchwork Tue Mar 30 17:33:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pratyush Yadav X-Patchwork-Id: 12173329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07D30C433E2 for ; Tue, 30 Mar 2021 17:36:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CD329619B1 for ; Tue, 30 Mar 2021 17:36:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232641AbhC3RgS (ORCPT ); Tue, 30 Mar 2021 13:36:18 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:59994 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232048AbhC3Rfz (ORCPT ); Tue, 30 Mar 2021 13:35:55 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 12UHZbfj057504; Tue, 30 Mar 2021 12:35:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1617125737; bh=SgDEhlMlYoyhgVUFt3uHpcKBgDC9JMfrq+gf8F529Po=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=g3IzKwvKzZAHWarCkFYaKMWsKbjXOFMLexnCkUtczrh1hVKFnQaeCfwQ/fsxHsXbM uQ97hk5LKEAOyZj+Is+AmaRhTwTN8YDsMeD+HBc3bjAjFZX5AQOLBW7TH4rUR7IVpe JPPHy3ENJz93RFSDMyx4HNsZFp6Y7DbpqbH70HGw= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 12UHZb7Y042880 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 30 Mar 2021 12:35:37 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 30 Mar 2021 12:35:37 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 30 Mar 2021 12:35:36 -0500 Received: from pratyush-OptiPlex-790.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 12UHXmgx125244; Tue, 30 Mar 2021 12:35:31 -0500 From: Pratyush Yadav To: Mauro Carvalho Chehab , Rob Herring , Kishon Vijay Abraham I , Vinod Koul , Peter Ujfalusi , Maxime Ripard , Benoit Parrot , Hans Verkuil , Alexandre Courbot , Laurent Pinchart , Stanimir Varbanov , Helen Koike , Michael Tretter , Peter Chen , Chunfeng Yun , , , , , CC: Pratyush Yadav , Vignesh Raghavendra , Tomi Valkeinen Subject: [PATCH 16/16] dt-bindings: phy: cdns,dphy: add power-domains property Date: Tue, 30 Mar 2021 23:03:48 +0530 Message-ID: <20210330173348.30135-17-p.yadav@ti.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210330173348.30135-1-p.yadav@ti.com> References: <20210330173348.30135-1-p.yadav@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org This property is needed on TI platforms to enable the PD of the DPHY before it can be used. Signed-off-by: Pratyush Yadav Reviewed-by: Laurent Pinchart --- Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml index 0807ba68284d..ddcd4de0aef6 100644 --- a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml +++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml @@ -30,6 +30,9 @@ properties: "#phy-cells": const: 0 + power-domains: + maxItems: 1 + required: - compatible - reg