From patchwork Thu Apr 1 11:26:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12179069 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D87CC43462 for ; Thu, 1 Apr 2021 18:08:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 04674610C7 for ; Thu, 1 Apr 2021 18:08:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237867AbhDASI4 (ORCPT ); Thu, 1 Apr 2021 14:08:56 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:34747 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237774AbhDASEY (ORCPT ); Thu, 1 Apr 2021 14:04:24 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617300265; x=1648836265; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZseDIZKjZBAQeshZzxvVySAICjj4gFiPGz57KZF5zJM=; b=mdJQJK5s5ZUwNbrbEtdva+vg1UvQD2RMigz2mzUNEaEkXd9zGjj5cHvD h1rL0ERk30ND7w6tGp+c9ABmOkEvei0pzNtl+mxAw0gjVKxcDO71ehu+c gH8N5r0YlGt6RDsJMBlQNAVt3hEsrfuNsrIX5UkMZ3fVuOwGnBGmgJwX9 xiRwIy9bfbXdhbxZw9N68+Xj/Zbs3MvSAgnPkhY24Bz1h1FhcF+1gonSA 1KMV9xAAJzJhMaZJ6A9R49w1RfPF56a9bOAY/YqAMmUO1thTUm0RZw3Qo F2OG2c5qICrGZq3ghRCKurGtW8UG9noYYtdtmW2OhkBeWCD8M2s9eFF/f A==; IronPort-SDR: yetGt6lfoPAV/3P9R0qhhBfvn8D444qdARsN0NSw/DCYCYnsjlfw79GXaKsasZODfTRNCRp7XS kXTof6W7LpJC+pt6PVQeohO6Xx2xzIdnR0E0LYJgr8wRo2qu0bf1ckLNe++qk574dS9KM9wtBM eitAvz/cByZomIpexS/VoG5ex6OvQ143EGA1fxwVOZJmcC/L7zBR1gvKUvvzMxkJHDne6vuz8I /PjD8d2ZlCMkj74646S2Obz6EuXfQLsGztmWagR8jo2xW9t8lFjAf3q2aq4G/Jv8Eks4OTxTtp e0M= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="112132377" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:28:52 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:28:52 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:28:24 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 01/30] media: atmel: atmel-isc: specialize gamma table into product specific Date: Thu, 1 Apr 2021 14:26:54 +0300 Message-ID: <20210401112723.189107-2-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Separate the gamma table from the isc base file into the specific sama5d2 product file. Add a pointer to the gamma table and entries count inside the platform driver specific struct. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 47 ++----------------- drivers/media/platform/atmel/atmel-isc.h | 11 +++-- .../media/platform/atmel/atmel-sama5d2-isc.c | 45 ++++++++++++++++++ 3 files changed, 56 insertions(+), 47 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index fe3ec8d0eaee..8b6c5e339cb8 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -176,48 +176,6 @@ struct isc_format formats_list[] = { }; -/* Gamma table with gamma 1/2.2 */ -const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES] = { - /* 0 --> gamma 1/1.8 */ - { 0x65, 0x66002F, 0x950025, 0xBB0020, 0xDB001D, 0xF8001A, - 0x1130018, 0x12B0017, 0x1420016, 0x1580014, 0x16D0013, 0x1810012, - 0x1940012, 0x1A60012, 0x1B80011, 0x1C90010, 0x1DA0010, 0x1EA000F, - 0x1FA000F, 0x209000F, 0x218000F, 0x227000E, 0x235000E, 0x243000E, - 0x251000E, 0x25F000D, 0x26C000D, 0x279000D, 0x286000D, 0x293000C, - 0x2A0000C, 0x2AC000C, 0x2B8000C, 0x2C4000C, 0x2D0000B, 0x2DC000B, - 0x2E7000B, 0x2F3000B, 0x2FE000B, 0x309000B, 0x314000B, 0x31F000A, - 0x32A000A, 0x334000B, 0x33F000A, 0x349000A, 0x354000A, 0x35E000A, - 0x368000A, 0x372000A, 0x37C000A, 0x386000A, 0x3900009, 0x399000A, - 0x3A30009, 0x3AD0009, 0x3B60009, 0x3BF000A, 0x3C90009, 0x3D20009, - 0x3DB0009, 0x3E40009, 0x3ED0009, 0x3F60009 }, - - /* 1 --> gamma 1/2 */ - { 0x7F, 0x800034, 0xB50028, 0xDE0021, 0x100001E, 0x11E001B, - 0x1390019, 0x1520017, 0x16A0015, 0x1800014, 0x1940014, 0x1A80013, - 0x1BB0012, 0x1CD0011, 0x1DF0010, 0x1EF0010, 0x200000F, 0x20F000F, - 0x21F000E, 0x22D000F, 0x23C000E, 0x24A000E, 0x258000D, 0x265000D, - 0x273000C, 0x27F000D, 0x28C000C, 0x299000C, 0x2A5000C, 0x2B1000B, - 0x2BC000C, 0x2C8000B, 0x2D3000C, 0x2DF000B, 0x2EA000A, 0x2F5000A, - 0x2FF000B, 0x30A000A, 0x314000B, 0x31F000A, 0x329000A, 0x333000A, - 0x33D0009, 0x3470009, 0x350000A, 0x35A0009, 0x363000A, 0x36D0009, - 0x3760009, 0x37F0009, 0x3880009, 0x3910009, 0x39A0009, 0x3A30009, - 0x3AC0008, 0x3B40009, 0x3BD0008, 0x3C60008, 0x3CE0008, 0x3D60009, - 0x3DF0008, 0x3E70008, 0x3EF0008, 0x3F70008 }, - - /* 2 --> gamma 1/2.2 */ - { 0x99, 0x9B0038, 0xD4002A, 0xFF0023, 0x122001F, 0x141001B, - 0x15D0019, 0x1760017, 0x18E0015, 0x1A30015, 0x1B80013, 0x1CC0012, - 0x1DE0011, 0x1F00010, 0x2010010, 0x2110010, 0x221000F, 0x230000F, - 0x23F000E, 0x24D000E, 0x25B000D, 0x269000C, 0x276000C, 0x283000C, - 0x28F000C, 0x29B000C, 0x2A7000C, 0x2B3000B, 0x2BF000B, 0x2CA000B, - 0x2D5000B, 0x2E0000A, 0x2EB000A, 0x2F5000A, 0x2FF000A, 0x30A000A, - 0x3140009, 0x31E0009, 0x327000A, 0x3310009, 0x33A0009, 0x3440009, - 0x34D0009, 0x3560009, 0x35F0009, 0x3680008, 0x3710008, 0x3790009, - 0x3820008, 0x38A0008, 0x3930008, 0x39B0008, 0x3A30008, 0x3AB0008, - 0x3B30008, 0x3BB0008, 0x3C30008, 0x3CB0007, 0x3D20008, 0x3DA0007, - 0x3E20007, 0x3E90007, 0x3F00008, 0x3F80007 }, -}; - #define ISC_IS_FORMAT_RAW(mbus_code) \ (((mbus_code) & 0xf000) == 0x3000) @@ -683,7 +641,7 @@ static void isc_set_pipeline(struct isc_device *isc, u32 pipeline) regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL); - gamma = &isc_gamma_table[ctrls->gamma_index][0]; + gamma = &isc->gamma_table[ctrls->gamma_index][0]; regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES); regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES); regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES); @@ -2070,7 +2028,8 @@ static int isc_ctrl_init(struct isc_device *isc) v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0); v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256); - v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, GAMMA_MAX, 1, 2); + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1, + isc->gamma_max); isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops, V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1); diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index fab8eca58d93..f1df47a4655b 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -187,6 +187,10 @@ struct isc_ctrls { * * @current_subdev: current subdevice: the sensor * @subdev_entities: list of subdevice entitites + * + * @gamma_table: pointer to the table with gamma values, has + * gamma_max sets of GAMMA_ENTRIES entries each + * @gamma_max: maximum number of sets of inside the gamma_table */ struct isc_device { struct regmap *regmap; @@ -245,16 +249,17 @@ struct isc_device { struct v4l2_ctrl *gr_off_ctrl; struct v4l2_ctrl *gb_off_ctrl; }; -}; -#define GAMMA_MAX 2 #define GAMMA_ENTRIES 64 + /* pointer to the defined gamma table */ + const u32 (*gamma_table)[GAMMA_ENTRIES]; + u32 gamma_max; +}; #define ATMEL_ISC_NAME "atmel-isc" extern struct isc_format formats_list[]; extern const struct isc_format controller_formats[]; -extern const u32 isc_gamma_table[GAMMA_MAX + 1][GAMMA_ENTRIES]; extern const struct regmap_config isc_regmap_config; extern const struct v4l2_async_notifier_operations isc_async_ops; diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index 0b78fecfd2a8..c74f36245bd5 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -54,6 +54,48 @@ #define ISC_CLK_MAX_DIV 255 +/* Gamma table with gamma 1/2.2 */ +const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { + /* 0 --> gamma 1/1.8 */ + { 0x65, 0x66002F, 0x950025, 0xBB0020, 0xDB001D, 0xF8001A, + 0x1130018, 0x12B0017, 0x1420016, 0x1580014, 0x16D0013, 0x1810012, + 0x1940012, 0x1A60012, 0x1B80011, 0x1C90010, 0x1DA0010, 0x1EA000F, + 0x1FA000F, 0x209000F, 0x218000F, 0x227000E, 0x235000E, 0x243000E, + 0x251000E, 0x25F000D, 0x26C000D, 0x279000D, 0x286000D, 0x293000C, + 0x2A0000C, 0x2AC000C, 0x2B8000C, 0x2C4000C, 0x2D0000B, 0x2DC000B, + 0x2E7000B, 0x2F3000B, 0x2FE000B, 0x309000B, 0x314000B, 0x31F000A, + 0x32A000A, 0x334000B, 0x33F000A, 0x349000A, 0x354000A, 0x35E000A, + 0x368000A, 0x372000A, 0x37C000A, 0x386000A, 0x3900009, 0x399000A, + 0x3A30009, 0x3AD0009, 0x3B60009, 0x3BF000A, 0x3C90009, 0x3D20009, + 0x3DB0009, 0x3E40009, 0x3ED0009, 0x3F60009 }, + + /* 1 --> gamma 1/2 */ + { 0x7F, 0x800034, 0xB50028, 0xDE0021, 0x100001E, 0x11E001B, + 0x1390019, 0x1520017, 0x16A0015, 0x1800014, 0x1940014, 0x1A80013, + 0x1BB0012, 0x1CD0011, 0x1DF0010, 0x1EF0010, 0x200000F, 0x20F000F, + 0x21F000E, 0x22D000F, 0x23C000E, 0x24A000E, 0x258000D, 0x265000D, + 0x273000C, 0x27F000D, 0x28C000C, 0x299000C, 0x2A5000C, 0x2B1000B, + 0x2BC000C, 0x2C8000B, 0x2D3000C, 0x2DF000B, 0x2EA000A, 0x2F5000A, + 0x2FF000B, 0x30A000A, 0x314000B, 0x31F000A, 0x329000A, 0x333000A, + 0x33D0009, 0x3470009, 0x350000A, 0x35A0009, 0x363000A, 0x36D0009, + 0x3760009, 0x37F0009, 0x3880009, 0x3910009, 0x39A0009, 0x3A30009, + 0x3AC0008, 0x3B40009, 0x3BD0008, 0x3C60008, 0x3CE0008, 0x3D60009, + 0x3DF0008, 0x3E70008, 0x3EF0008, 0x3F70008 }, + + /* 2 --> gamma 1/2.2 */ + { 0x99, 0x9B0038, 0xD4002A, 0xFF0023, 0x122001F, 0x141001B, + 0x15D0019, 0x1760017, 0x18E0015, 0x1A30015, 0x1B80013, 0x1CC0012, + 0x1DE0011, 0x1F00010, 0x2010010, 0x2110010, 0x221000F, 0x230000F, + 0x23F000E, 0x24D000E, 0x25B000D, 0x269000C, 0x276000C, 0x283000C, + 0x28F000C, 0x29B000C, 0x2A7000C, 0x2B3000B, 0x2BF000B, 0x2CA000B, + 0x2D5000B, 0x2E0000A, 0x2EB000A, 0x2F5000A, 0x2FF000A, 0x30A000A, + 0x3140009, 0x31E0009, 0x327000A, 0x3310009, 0x33A0009, 0x3440009, + 0x34D0009, 0x3560009, 0x35F0009, 0x3680008, 0x3710008, 0x3790009, + 0x3820008, 0x38A0008, 0x3930008, 0x39B0008, 0x3A30008, 0x3AB0008, + 0x3B30008, 0x3BB0008, 0x3C30008, 0x3CB0007, 0x3D20008, 0x3DA0007, + 0x3E20007, 0x3E90007, 0x3F00008, 0x3F80007 }, +}; + static int isc_parse_dt(struct device *dev, struct isc_device *isc) { struct device_node *np = dev->of_node; @@ -150,6 +192,9 @@ static int atmel_isc_probe(struct platform_device *pdev) return ret; } + isc->gamma_table = isc_sama5d2_gamma_table; + isc->gamma_max = 2; + ret = isc_pipeline_init(isc); if (ret) return ret; From patchwork Thu Apr 1 11:26:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12179279 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E56BEC433B4 for ; Thu, 1 Apr 2021 18:36:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C109E60FED for ; Thu, 1 Apr 2021 18:36:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237975AbhDASg3 (ORCPT ); Thu, 1 Apr 2021 14:36:29 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:60700 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240828AbhDASbi (ORCPT ); Thu, 1 Apr 2021 14:31:38 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617301899; x=1648837899; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jCzGB/5nxDRF5zHetU+FXH2sdCatrGHOQpHiMo1ettU=; b=L8o+i2qhuQDJizr6T/wt27dF7as5umxGI0sZAMT0nmhF7wKOASQHYMeg /Q8CRXpohm8AFv5Bszw07k2P1N72F85P5pmQ9+fNGFyVYOCLgnUk9zCfU Nnqnx+9e+yiy44y/0q06TTDDZ+J8dN09nOkxYAJL/n+uc6+ctPETmXEzt fmqUX9e+L24qUDcOwszyiwdYThKczdUYrDnHCmFZVYSosHNcKpUxU78I/ NzoHIaNggvApjFgwvu7gVCFOJMhC4wee71gpeoRlabGx1IZXU3WP+kGpb ffL4JAkX+QobmePOcXzZdBdrFdH+KlvAptDpOuqm//GhHBqMbg6YC6QEx Q==; IronPort-SDR: MeC3eHuwf+PoH+EQpHRmRP5z6lY02fAzawQm4i8a19dGak7j94eJ1tptfjm3UjCXd/L4JzbL+b R79mmxmrdbXAdTRs9B571ynkO/1OnwbEBzmXHC2bZOpo67G7LyKWI3BeKaJ/ZLaUZh9C0WG6dr 7RWLn/9M4suzK7uiIhbwuBcHoGLNSQ0DuR7h8Z1PlPXw5E6gFqV9j661F27PKKVvsg3Bk7ARRs jChCQacKNOb+FyYWm/hq+CHVbS+hXsN/O5BK+UNlgfnMTFsd764iH/UTtV9mpY9HIY2zsgbrEQ 2A8= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="114976413" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:29:03 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:29:02 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:28:56 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 02/30] media: atmel: atmel-isc: specialize driver name constant Date: Thu, 1 Apr 2021 14:26:55 +0300 Message-ID: <20210401112723.189107-3-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The driver name constant must defined based on product driver, thus moving the constant directly where it's required. This will allow each ISC based product to define it's own name. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 4 ++-- drivers/media/platform/atmel/atmel-isc.h | 2 -- drivers/media/platform/atmel/atmel-sama5d2-isc.c | 4 ++-- 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 8b6c5e339cb8..277a8fd8b83d 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -896,7 +896,7 @@ static int isc_querycap(struct file *file, void *priv, { struct isc_device *isc = video_drvdata(file); - strscpy(cap->driver, ATMEL_ISC_NAME, sizeof(cap->driver)); + strscpy(cap->driver, "microchip-isc", sizeof(cap->driver)); strscpy(cap->card, "Atmel Image Sensor Controller", sizeof(cap->card)); snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s", isc->v4l2_dev.name); @@ -2246,7 +2246,7 @@ static int isc_async_complete(struct v4l2_async_notifier *notifier) } /* Register video device */ - strscpy(vdev->name, ATMEL_ISC_NAME, sizeof(vdev->name)); + strscpy(vdev->name, "microchip-isc", sizeof(vdev->name)); vdev->release = video_device_release_empty; vdev->fops = &isc_fops; vdev->ioctl_ops = &isc_ioctl_ops; diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index f1df47a4655b..8d81d9967ad2 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -256,8 +256,6 @@ struct isc_device { u32 gamma_max; }; -#define ATMEL_ISC_NAME "atmel-isc" - extern struct isc_format formats_list[]; extern const struct isc_format controller_formats[]; extern const struct regmap_config isc_regmap_config; diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index c74f36245bd5..f45d8b96bfb8 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -185,7 +185,7 @@ static int atmel_isc_probe(struct platform_device *pdev) return irq; ret = devm_request_irq(dev, irq, isc_interrupt, 0, - ATMEL_ISC_NAME, isc); + "atmel-sama5d2-isc", isc); if (ret < 0) { dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", irq, ret); @@ -364,7 +364,7 @@ static struct platform_driver atmel_isc_driver = { .probe = atmel_isc_probe, .remove = atmel_isc_remove, .driver = { - .name = ATMEL_ISC_NAME, + .name = "atmel-sama5d2-isc", .pm = &atmel_isc_dev_pm_ops, .of_match_table = of_match_ptr(atmel_isc_of_match), }, From patchwork Thu Apr 1 11:26:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12178843 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA16CC43462 for ; Thu, 1 Apr 2021 18:01:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B051061159 for ; Thu, 1 Apr 2021 18:01:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235477AbhDASBo (ORCPT ); Thu, 1 Apr 2021 14:01:44 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:64963 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236125AbhDAR6J (ORCPT ); Thu, 1 Apr 2021 13:58:09 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617299890; x=1648835890; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=W9RTc4XTqmuga+DzPKp51siwwTSJHh6dtg9LlNk0M14=; b=JdISQQV71oRTMSbVyiDce3mAtp+DbF2qLFN+8Tx7iwjUeEMb4OfDAE76 44Y1WxYlLPl3lEOkFonxqoE5XJxFglqHSkXpzIZKxdFU7ljKDUmIvsdkN FTB8KLAnUeG4QG4ATb0QZ9qLZ3PmAuWswcO/n8OwWQv9ZBXcJklKjZBFk vTd1GkmnLHw6FsbvFtYxUSuJFWbILDFXNnlDhOnK4m+3rts8DglWhUa1i EfdIRyRAJqCbACizzXffyBJ1ZXgLaWVyTziYJm2oKGH56x7LCoxWQSZ4W HYWYz9qL7Ai9fjd2rjUTx46Yfcmy7tywFHzY33a1LQUet2YFwY6X+mf9v g==; IronPort-SDR: K+0CHeN8sXO2Clckg6iw7tDsPSThzOwwt247IYudrwp2ws8cRp42hOdW7SP6Q6MpJ/+4cANq0p 92VHzAhq0XZ2yCzUJD8z+D4g86MQQRseco5iUctWGUcfXml7tCvqwzDffzMfAgvC/tHw8BPV5v Cy+mdavvgdXvkn1Ojk5j3PdZhXHF03dWRLu1SVjtyVtf0ExBzypqZrodhdOF9D9Xy4kq+gTZDH E++Ezx5fAaHP0C0hL9ba+Yv87H4XY8Fyjg7UfWzHeESJSPBqC6FCglMSTlAs5Dto5NRn6abbfe JQg= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="49670689" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:29:04 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:29:04 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:29:02 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 03/30] media: atmel: atmel-isc: add checks for limiting frame sizes Date: Thu, 1 Apr 2021 14:26:56 +0300 Message-ID: <20210401112723.189107-4-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org When calling the subdev, certain subdev drivers will overwrite the frame size and adding sizes which are beyond the ISC's capabilities. Thus we need to ensure the frame size is cropped to the maximum caps. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 277a8fd8b83d..45fc8dbb7943 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -1326,6 +1326,12 @@ static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f, v4l2_fill_pix_format(pixfmt, &format.format); + /* Limit to Atmel ISC hardware capabilities */ + if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) + pixfmt->width = ISC_MAX_SUPPORT_WIDTH; + if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) + pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; + pixfmt->field = V4L2_FIELD_NONE; pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3; pixfmt->sizeimage = pixfmt->bytesperline * pixfmt->height; @@ -1361,6 +1367,12 @@ static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f) if (ret < 0) return ret; + /* Limit to Atmel ISC hardware capabilities */ + if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) + pixfmt->width = ISC_MAX_SUPPORT_WIDTH; + if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) + pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; + isc->fmt = *f; if (isc->try_config.sd_format && isc->config.sd_format && From patchwork Thu Apr 1 11:26:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12179275 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61B46C433B4 for ; Thu, 1 Apr 2021 18:36:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3D99960FED for ; Thu, 1 Apr 2021 18:36:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237751AbhDASg0 (ORCPT ); Thu, 1 Apr 2021 14:36:26 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:46406 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240056AbhDAS1B (ORCPT ); Thu, 1 Apr 2021 14:27:01 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617301621; x=1648837621; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mXosE0rlxsGKKT+7A7IfIECrJXlAhHskFLtgByoJ1l4=; b=efSakvHrksLWq5HjQh3+76q+fvVawYgV/cp3lknUGloQ/9mZNzRqiyDs y1kTi0UbE3XaiaPbADAF7gC01Y2INrtrLDMrDOmbhPrRw//Xuwt1Oikme GlPBCUYx60eNmYZR6fNgCne1CkVgXikEKvRVMFd78t6EL9IBAZqYHkFQk kJr2ip9EpxeyKLEWcWhmvHv40LmqksRBPkA6kZxG6MnyAsDqXzK2Jsa36 uizj1CDBh3umCGZuMhJi0xzEmViTw0L2SQ+2Ehrf8i8GDnW7c1RJRMZPt b70GAAoPzF/5XVuYp8XsuXWeLUBmCbFK8GOAG6VU5m8p+5BTW8RADl2iY A==; IronPort-SDR: yc3eAjuUufO/JSmkuIYIEuH6lv9BRw3KwhLpup6/ano0uzGSAwPTYfEbkZi35x366TEy0csPIa UjywuYxBBUnycNxv3uSUjWAi+S/SvS6cjW39UG5kdFHqclK/KiyTMnACOrEen2HHi0COBWcS45 QsWnahfX4C/9nVqtTige9BCgLbvMHLpZn6oqZtP2YIyzuiuTyXm34mvnB6V6r0NrtO0kmaDxOR ibI6fJ56+/SNXvQCD2Lq1feCcMSnsto76Hpa81l4Ea8ZIiZwItOU76RcEeIs4Up4dcxPm94yqn GEs= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="121401837" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:29:08 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:29:08 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:29:04 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 04/30] media: atmel: atmel-isc: specialize max width and max height Date: Thu, 1 Apr 2021 14:26:57 +0300 Message-ID: <20210401112723.189107-5-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Move the max width and max height constants to the product specific driver and have them in the device struct. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 28 +++++++++---------- drivers/media/platform/atmel/atmel-isc.h | 9 ++++-- .../media/platform/atmel/atmel-sama5d2-isc.c | 7 +++-- 3 files changed, 25 insertions(+), 19 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 45fc8dbb7943..350076dd029a 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -1204,8 +1204,8 @@ static void isc_try_fse(struct isc_device *isc, * just use the maximum ISC can receive. */ if (ret) { - pad_cfg->try_crop.width = ISC_MAX_SUPPORT_WIDTH; - pad_cfg->try_crop.height = ISC_MAX_SUPPORT_HEIGHT; + pad_cfg->try_crop.width = isc->max_width; + pad_cfg->try_crop.height = isc->max_height; } else { pad_cfg->try_crop.width = fse.max_width; pad_cfg->try_crop.height = fse.max_height; @@ -1282,10 +1282,10 @@ static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f, isc->try_config.sd_format = sd_fmt; /* Limit to Atmel ISC hardware capabilities */ - if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) - pixfmt->width = ISC_MAX_SUPPORT_WIDTH; - if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) - pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; + if (pixfmt->width > isc->max_width) + pixfmt->width = isc->max_width; + if (pixfmt->height > isc->max_height) + pixfmt->height = isc->max_height; /* * The mbus format is the one the subdev outputs. @@ -1327,10 +1327,10 @@ static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f, v4l2_fill_pix_format(pixfmt, &format.format); /* Limit to Atmel ISC hardware capabilities */ - if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) - pixfmt->width = ISC_MAX_SUPPORT_WIDTH; - if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) - pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; + if (pixfmt->width > isc->max_width) + pixfmt->width = isc->max_width; + if (pixfmt->height > isc->max_height) + pixfmt->height = isc->max_height; pixfmt->field = V4L2_FIELD_NONE; pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp) >> 3; @@ -1368,10 +1368,10 @@ static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f) return ret; /* Limit to Atmel ISC hardware capabilities */ - if (pixfmt->width > ISC_MAX_SUPPORT_WIDTH) - pixfmt->width = ISC_MAX_SUPPORT_WIDTH; - if (pixfmt->height > ISC_MAX_SUPPORT_HEIGHT) - pixfmt->height = ISC_MAX_SUPPORT_HEIGHT; + if (f->fmt.pix.width > isc->max_width) + f->fmt.pix.width = isc->max_width; + if (f->fmt.pix.height > isc->max_height) + f->fmt.pix.height = isc->max_height; isc->fmt = *f; diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index 8d81d9967ad2..6becc6c3aaf0 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -10,9 +10,6 @@ */ #ifndef _ATMEL_ISC_H_ -#define ISC_MAX_SUPPORT_WIDTH 2592 -#define ISC_MAX_SUPPORT_HEIGHT 1944 - #define ISC_CLK_MAX_DIV 255 enum isc_clk_id { @@ -191,6 +188,9 @@ struct isc_ctrls { * @gamma_table: pointer to the table with gamma values, has * gamma_max sets of GAMMA_ENTRIES entries each * @gamma_max: maximum number of sets of inside the gamma_table + * + * @max_width: maximum frame width, dependent on the internal RAM + * @max_height: maximum frame height, dependent on the internal RAM */ struct isc_device { struct regmap *regmap; @@ -254,6 +254,9 @@ struct isc_device { /* pointer to the defined gamma table */ const u32 (*gamma_table)[GAMMA_ENTRIES]; u32 gamma_max; + + u32 max_width; + u32 max_height; }; extern struct isc_format formats_list[]; diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index f45d8b96bfb8..f8d1c8ba99b3 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -49,8 +49,8 @@ #include "atmel-isc-regs.h" #include "atmel-isc.h" -#define ISC_MAX_SUPPORT_WIDTH 2592 -#define ISC_MAX_SUPPORT_HEIGHT 1944 +#define ISC_SAMA5D2_MAX_SUPPORT_WIDTH 2592 +#define ISC_SAMA5D2_MAX_SUPPORT_HEIGHT 1944 #define ISC_CLK_MAX_DIV 255 @@ -195,6 +195,9 @@ static int atmel_isc_probe(struct platform_device *pdev) isc->gamma_table = isc_sama5d2_gamma_table; isc->gamma_max = 2; + isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH; + isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; + ret = isc_pipeline_init(isc); if (ret) return ret; From patchwork Thu Apr 1 11:26:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12178847 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13E3FC43618 for ; Thu, 1 Apr 2021 18:01:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DDCB7611BD for ; Thu, 1 Apr 2021 18:01:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234481AbhDASBp (ORCPT ); Thu, 1 Apr 2021 14:01:45 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:65126 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236242AbhDAR6J (ORCPT ); Thu, 1 Apr 2021 13:58:09 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617299890; x=1648835890; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zGiPMKIR71RoJeRCsbyz2/Jkh0vjyf2K5BPASY5QkfU=; b=C/6jpNW4UaNGjXMnD+nD3RilY0qLZGA4A6b8U4Rl0Cy48i6Ufm7HznhV +U7QqsaupYRmjGLXSkVwjrgVmjtBRu3a8Ge/zhGINUIzd0zkwO+l0JJk1 6tZU005jcC/G+C3oHLZ/0+1JHCgNY14fuR55NV38JvHfHeOqztdcOwxxe VVZfIAQd74fFgfvM9lP2FmwrQqh/NFxA9ga4QF0cxAb3PV1QR7S/anJix A0YbBnMA5EU1ausPMsjMv91yQt8c8x5S0t1hHY6rQA2zIRxfDkI9Ow2ZH 9NkqIgoP1Fgu1bod892Xb2WaUAaU7cvyLL0xGh/1DyQieLxb08Xd1U6uG A==; IronPort-SDR: jC+RXg1VzIpUpBiJNFHJtK8gyMEW8DfuhUjgbWdG56DnDF0YOmja1Be374yE59UL8DGyzyPhQJ khyfjSG0uPpNY7yetMSP2SKxyFC8hoxOnvWJ1Rms+B43vYLI0/aX2RXbZU7vuteszoAMLFSuiT xPSgqHlSixpSvrZJTm6WVTofuSMugB/9/X7Ar8QH9uB+dnXqQY1er7ODNWNwhDkgdCCnUTdQJw 1IgjWsW+/40PxDkRVRRmLdEjegO398o465an9cujV8Z7H6VjgStO0lZURL4ucgBYLVblaSPqSJ pRk= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="49670700" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:29:17 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:29:17 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:29:08 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 05/30] media: atmel: atmel-isc: specialize dma cfg Date: Thu, 1 Apr 2021 14:26:58 +0300 Message-ID: <20210401112723.189107-6-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The dma configuration (DCFG) is specific to the product. Move this configuration in the product specific driver, and add the field inside the driver struct. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 3 +-- drivers/media/platform/atmel/atmel-isc.h | 2 ++ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 3 +++ 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 350076dd029a..ff40ee2e2759 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -716,8 +716,7 @@ static int isc_configure(struct isc_device *isc) rlp_mode = isc->config.rlp_cfg_mode; pipeline = isc->config.bits_pipeline; - dcfg = isc->config.dcfg_imode | - ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; + dcfg = isc->config.dcfg_imode | isc->dcfg; pfe_cfg0 |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE; mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW | diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index 6becc6c3aaf0..d14ae096fbf6 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -150,6 +150,7 @@ struct isc_ctrls { * @hclock: Hclock clock input (refer datasheet) * @ispck: iscpck clock (refer datasheet) * @isc_clks: ISC clocks + * @dcfg: DMA master configuration, architecture dependent * * @dev: Registered device driver * @v4l2_dev: v4l2 registered device @@ -197,6 +198,7 @@ struct isc_device { struct clk *hclock; struct clk *ispck; struct isc_clk isc_clks[2]; + u32 dcfg; struct device *dev; struct v4l2_device v4l2_dev; diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index f8d1c8ba99b3..6d9942dcd7c1 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -198,6 +198,9 @@ static int atmel_isc_probe(struct platform_device *pdev) isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH; isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; + /* sama5d2-isc - 8 bits per beat */ + isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; + ret = isc_pipeline_init(isc); if (ret) return ret; From patchwork Thu Apr 1 11:26:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12178931 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D869BC433B4 for ; Thu, 1 Apr 2021 18:03:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 81B3261001 for ; Thu, 1 Apr 2021 18:03:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237492AbhDASDz (ORCPT ); Thu, 1 Apr 2021 14:03:55 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:1272 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237484AbhDASAH (ORCPT ); Thu, 1 Apr 2021 14:00:07 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617300007; x=1648836007; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eW2KWb3ah7QJbnhIWY57Yzt2wHpYctXsGagdfidA/0A=; b=gQ/nR/9936ZbiFHnfotUq3DYikw+lyHJYn0I2pMMHag7alK9LTWaF8fW pWJzOMAC64hpU96eDD6KibZTKjYdwEck/ktMiiLFhJg0fq1618A0NtgeW FL1OKN6IhvwCElceSmDPugVYMCrvcHxZzxga0xFihhsXlw4EttWP/UYXs Vu5hvel0JHfj5+GbMuRw4QSEDxPYvVi7xNQIWbcPUJi0khTQW8pY7FHwJ occClHEKvbnPLDPGNPuH/YKcVznY0mXNfchkSlD+IO0Z+9cKbU52dX7ch 5gXoStegvohJaWQRvNa1MSYaEIsh7D7W94fKFQAaGBuLfXYaZ3QZbfJn9 g==; IronPort-SDR: Du7ikSv1sIdLlY/CHKPibWhwE6UKcvEBgHx0Ynq1vZc1fJdYb9U8S97qIPE+6gtJIXDRFPaktw 5PpX9YOb1RnHeQ7QEDEDAaSg4x69+Y4sT58PwBPYcyU8WmYL876qhvIj0khbYRB8ngV0dBVXTG WESPPVXmF1a2Hvd79rFgVdAzbrZWgTm4lUXi81Way3EGm1R32mUkAPXY0pE2C/Or7lTJFkGimL 9MGSVqIf/+dLeLTHZAjSrjqPfb1gEWwdVVpxk3naTSyhZFSWGbQw91UJ1VDymoUbaFY0cYcpP0 8Cg= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="49670702" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:29:19 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:29:19 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:29:18 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 06/30] media: atmel: atmel-isc: extract CSC submodule config into separate function Date: Thu, 1 Apr 2021 14:26:59 +0300 Message-ID: <20210401112723.189107-7-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The CSC submodule should be initialized in the product specific driver as it's product specific. Other products can implement it differently. Signed-off-by: Eugen Hristev Reported-by: kernel test robot --- drivers/media/platform/atmel/atmel-isc-base.c | 8 +------- drivers/media/platform/atmel/atmel-isc.h | 7 +++++++ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 15 +++++++++++++++ 3 files changed, 23 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index ff40ee2e2759..31f63ba90c71 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -646,13 +646,7 @@ static void isc_set_pipeline(struct isc_device *isc, u32 pipeline) regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES); regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES); - /* Convert RGB to YUV */ - regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16)); - regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16)); - regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16)); - regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16)); - regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16)); - regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16)); + isc->config_csc(isc); regmap_write(regmap, ISC_CBC_BRIGHT, ctrls->brightness); regmap_write(regmap, ISC_CBC_CONTRAST, ctrls->contrast); diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index d14ae096fbf6..bb0b4419deff 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -192,6 +192,9 @@ struct isc_ctrls { * * @max_width: maximum frame width, dependent on the internal RAM * @max_height: maximum frame height, dependent on the internal RAM + * + * @config_csc: pointer to a function that initializes product + * specific CSC module */ struct isc_device { struct regmap *regmap; @@ -259,6 +262,10 @@ struct isc_device { u32 max_width; u32 max_height; + + struct { + void (*config_csc)(struct isc_device *isc); + }; }; extern struct isc_format formats_list[]; diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index 6d9942dcd7c1..d9f06daffdf8 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -54,6 +54,19 @@ #define ISC_CLK_MAX_DIV 255 +void isc_sama5d2_config_csc(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + + /* Convert RGB to YUV */ + regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16)); + regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16)); + regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16)); + regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16)); + regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16)); + regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16)); +} + /* Gamma table with gamma 1/2.2 */ const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { /* 0 --> gamma 1/1.8 */ @@ -198,6 +211,8 @@ static int atmel_isc_probe(struct platform_device *pdev) isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH; isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; + isc->config_csc = isc_sama5d2_config_csc; + /* sama5d2-isc - 8 bits per beat */ isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; From patchwork Thu Apr 1 11:27:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12179057 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36C5FC43462 for ; Thu, 1 Apr 2021 18:08:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 06CC26044F for ; Thu, 1 Apr 2021 18:08:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237635AbhDASIp (ORCPT ); Thu, 1 Apr 2021 14:08:45 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:20061 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236386AbhDASCY (ORCPT ); Thu, 1 Apr 2021 14:02:24 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617300144; x=1648836144; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XFUIMGcuk2LQccy9mIU7wH0R7YLi14N6pV7ElUM4/Mg=; b=pfrmYSUlKLYv7+6fkqwlqThXpJzIjGtyZaM7eR2B30pAUnMxap1oeL/D aJZW89X3GuHamuIi13fgyIr/M6V/9ssFIEPec49rL/WSezkH0U/5WIKwS 9RqxnbPt22IKe6ZpewCID/NJ4nDqxJQYrPFJQEKupkrZ75K/+wJS+wtwG E/D1pbFQqblFOcIlxWCVAc9KnjKn7FuXoey12Fgzgi4BR4XSRH/foAp1U 3mvIyWC+B66Ll0OWB2oi1RC+gY58LoY/sbIbTS0u30sdatJBDWUuto7mX qHQz7/BG3yYXC/PKG4jYFdeCp3A+5KjRmEZjf9AOvyXzavRZk/cKSuW5K Q==; IronPort-SDR: 6+rrsr41a9Bw6kQQ7Fh0/d5m4vGlH9QKgJsbaNvv10O3x5ESPfJwhvmWnZUIY6bc/SaViTI8Wm 7hK3CRlyoRiPxzt/n77SXDMySZ9DBnyexsfEStD1NxDsrHNqSkldXnbmsq1pqsv4l7m6nbr0fe wjJ0CBhsC5VnthGoEp0daQP/k6avxFLVSqzM+eH0tuvDNxUjAsKdQefH+7mKjqjXZFZ41m7YUy ky0qgq4i2sv8TIXVX3cwZFaiJbrV7F2cXkCakd07iAxreQTDfzpEgLq9uvUfw97EFA0NfltPEL sQc= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="109338258" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:29:37 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:29:37 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:29:19 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 07/30] media: atmel: atmel-isc-base: add id to clock debug message Date: Thu, 1 Apr 2021 14:27:00 +0300 Message-ID: <20210401112723.189107-8-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add the clock id to the debug message regarding clock setup Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 31f63ba90c71..bc036e8ac4fe 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -277,8 +277,8 @@ static int isc_clk_enable(struct clk_hw *hw) unsigned long flags; unsigned int status; - dev_dbg(isc_clk->dev, "ISC CLK: %s, div = %d, parent id = %d\n", - __func__, isc_clk->div, isc_clk->parent_id); + dev_dbg(isc_clk->dev, "ISC CLK: %s, id = %d, div = %d, parent id = %d\n", + __func__, id, isc_clk->div, isc_clk->parent_id); spin_lock_irqsave(&isc_clk->lock, flags); regmap_update_bits(regmap, ISC_CLKCFG, From patchwork Thu Apr 1 11:27:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12179053 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84917C433ED for ; Thu, 1 Apr 2021 18:08:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5ADB56112F for ; Thu, 1 Apr 2021 18:08:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237257AbhDASIh (ORCPT ); Thu, 1 Apr 2021 14:08:37 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:64963 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235267AbhDASCK (ORCPT ); Thu, 1 Apr 2021 14:02:10 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617300130; x=1648836130; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=K54yuKq9sUa4dY4BiiebxXOounI4ch3hrCDmlYNhKJ8=; b=nCxzGKoFUwJMbKypBSAXGVgOhZSh4e8Ar8Ddtn4D45J4+4GjpUHCFBXt yQwS4qQYsaF44uNUvCSdF5QsjhmNwrSTL6OgY5uGm3557V2L7dPi9NDf4 KwqXT8xDrIkIapde7cOg74IriaI7pkfF5cX5aX+91tGtWi50BUMETNOzM 7mzTxySSCHFPqErv6BFvGTqUlWnerAYrJfvpvhJk3u5c7IMj9UxgTDl1D pjL+OjefmQGDVvooHTOuP2G7/qrLRIGLrqd4Oz9uv4cHX0j+ZGmdW5th8 oAPR9LbPjFlG4v7ocBQN4s+A7RAkOQeFO1pF8afA+kFc6eT6VFP49Rmv1 Q==; IronPort-SDR: /3Bi1d/8iERvZBn8x0xCGIz2wTAttakwMf7+3KsUb/BtHSmThSWv1s99lYbLV++Y2daGk7EqPD hYt4E39Q2m92tcEI8TAqrbvt+t/mvva+RjKOpb6clbo6m+OkoEHV9xTjvvgKYBmA1Nx/zMJzZ+ F9UgoTmjv82XlN8YEdeE+UKnp6VfeAs5/zPORSU4/H8DRANswcevW8ic45z+4H9o8L2MO/ec5f HTKJwZ1TG5wg+0YqBREfalBFit1boOG62gqUeiCKvoQwHtuzU0TqFHOZRzaWQseaG26Ybt5agb b24= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="49670751" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:29:57 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:29:57 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:29:47 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 08/30] media: atmel: atmel-isc: create register offsets struct Date: Thu, 1 Apr 2021 14:27:01 +0300 Message-ID: <20210401112723.189107-9-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Create a struct that holds register offsets that are product specific. Add initially the CSC register. This allows each product that contains a variant of the ISC to add their own register offset. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 2 +- drivers/media/platform/atmel/atmel-isc-regs.h | 3 +++ drivers/media/platform/atmel/atmel-isc.h | 12 +++++++++++ .../media/platform/atmel/atmel-sama5d2-isc.c | 20 +++++++++++++------ 4 files changed, 30 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index bc036e8ac4fe..019d931d1367 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -2311,7 +2311,7 @@ int isc_pipeline_init(struct isc_device *isc) REG_FIELD(ISC_GAM_CTRL, 1, 1), REG_FIELD(ISC_GAM_CTRL, 2, 2), REG_FIELD(ISC_GAM_CTRL, 3, 3), - REG_FIELD(ISC_CSC_CTRL, 0, 0), + REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), REG_FIELD(ISC_CBC_CTRL, 0, 0), REG_FIELD(ISC_SUB422_CTRL, 0, 0), REG_FIELD(ISC_SUB420_CTRL, 0, 0), diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h index f1e160ed4351..5a65600c5f88 100644 --- a/drivers/media/platform/atmel/atmel-isc-regs.h +++ b/drivers/media/platform/atmel/atmel-isc-regs.h @@ -153,6 +153,9 @@ /* ISC_Gamma Correction Green Entry Register */ #define ISC_GAM_RENTRY 0x00000298 +/* Offset for CSC register specific to sama5d2 product */ +#define ISC_SAMA5D2_CSC_OFFSET 0 + /* Color Space Conversion Control Register */ #define ISC_CSC_CTRL 0x00000398 diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index bb0b4419deff..ef3a0451192d 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -144,6 +144,14 @@ struct isc_ctrls { #define ISC_PIPE_LINE_NODE_NUM 11 +/* + * struct isc_reg_offsets - ISC device register offsets + * @csc: Offset for the CSC register + */ +struct isc_reg_offsets { + u32 csc; +}; + /* * struct isc_device - ISC device driver data/config struct * @regmap: Register map @@ -195,6 +203,8 @@ struct isc_ctrls { * * @config_csc: pointer to a function that initializes product * specific CSC module + * + * @offsets: struct holding the product specific register offsets */ struct isc_device { struct regmap *regmap; @@ -266,6 +276,8 @@ struct isc_device { struct { void (*config_csc)(struct isc_device *isc); }; + + struct isc_reg_offsets offsets; }; extern struct isc_format formats_list[]; diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index d9f06daffdf8..3b076b87454e 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -59,12 +59,18 @@ void isc_sama5d2_config_csc(struct isc_device *isc) struct regmap *regmap = isc->regmap; /* Convert RGB to YUV */ - regmap_write(regmap, ISC_CSC_YR_YG, 0x42 | (0x81 << 16)); - regmap_write(regmap, ISC_CSC_YB_OY, 0x19 | (0x10 << 16)); - regmap_write(regmap, ISC_CSC_CBR_CBG, 0xFDA | (0xFB6 << 16)); - regmap_write(regmap, ISC_CSC_CBB_OCB, 0x70 | (0x80 << 16)); - regmap_write(regmap, ISC_CSC_CRR_CRG, 0x70 | (0xFA2 << 16)); - regmap_write(regmap, ISC_CSC_CRB_OCR, 0xFEE | (0x80 << 16)); + regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, + 0x42 | (0x81 << 16)); + regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, + 0x19 | (0x10 << 16)); + regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, + 0xFDA | (0xFB6 << 16)); + regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, + 0x70 | (0x80 << 16)); + regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, + 0x70 | (0xFA2 << 16)); + regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, + 0xFEE | (0x80 << 16)); } /* Gamma table with gamma 1/2.2 */ @@ -213,6 +219,8 @@ static int atmel_isc_probe(struct platform_device *pdev) isc->config_csc = isc_sama5d2_config_csc; + isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; + /* sama5d2-isc - 8 bits per beat */ isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; From patchwork Thu Apr 1 11:27:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12179051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19124C43470 for ; Thu, 1 Apr 2021 18:08:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DBBF96112F for ; Thu, 1 Apr 2021 18:08:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237688AbhDASIk (ORCPT ); Thu, 1 Apr 2021 14:08:40 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:65126 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236115AbhDASCK (ORCPT ); Thu, 1 Apr 2021 14:02:10 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617300130; x=1648836130; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ulWPoLeocs+dWVdplnwdGoF96XkQIYb0xWpMWXdJoE4=; b=RZ/kBsuQGYcFmfVw5B+wq2ydXc1VnBixG6ACkigVgD6swtfntGSBSf6I C5r1pcvufI3m9j9y+QJY3udhTxavzMapIfr2+j+b3/OaegvTFZWo7mNO5 LZdNKRTZhiYyiCX06A3fxyfwhEQ+NZBRBN0KLThDNwd5eLbBFlNscB10T 8bPUhvQjVRtXSP3dTjmJN5jKrC5K7MhcRT9EnZty0jurpLPhQSMzOvpmY HOKi5QdNkj3yWpCqN5dFNLno3V9RXxnGcuCjOEGG1J02e/jhStfPe9Zna YsBHHo9142bKpJaVvaVg7CHewSVpBU4zxMmIQ+Jc2ibK4i35ADeQzDih/ g==; IronPort-SDR: vTxUdd3X09eBaYNmsnATbhEL0/HNrhmF6nry/K5R4lSr11pCDUF22ZXrnkiovcr5TeeMXvYa6D dHsMQJ9EejqXR0W+eAUfLAxQigqsQCSQSYG0zlw9Q0sL73kSBn6XNXqUcvvmzuly68Lvu+n7kp cA1aHnCX0Ibc45J7lRSfd634dLdVOJnIwKD5LJG6vrtk2OQn30EbTSRXjZR+1K3HkOjXtuxfOo XdepAjnCyx9IaooF47fQX0qeIiIc4OOGRoFhW0MucptDHG9Mjbz5bBdS/pQw9Hry/EsfDGmbry mik= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="49670788" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:30:11 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:30:11 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:29:59 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 09/30] media: atmel: atmel-isc: extract CBC submodule config into separate function Date: Thu, 1 Apr 2021 14:27:02 +0300 Message-ID: <20210401112723.189107-10-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The CBC submodule should be initialized in the product specific driver as it's product specific. Other products can implement it differently Signed-off-by: Eugen Hristev Reported-by: kernel test robot --- drivers/media/platform/atmel/atmel-isc-base.c | 4 +--- drivers/media/platform/atmel/atmel-isc.h | 3 +++ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 9 +++++++++ 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 019d931d1367..446fe232956b 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -647,9 +647,7 @@ static void isc_set_pipeline(struct isc_device *isc, u32 pipeline) regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES); isc->config_csc(isc); - - regmap_write(regmap, ISC_CBC_BRIGHT, ctrls->brightness); - regmap_write(regmap, ISC_CBC_CONTRAST, ctrls->contrast); + isc->config_cbc(isc); } static int isc_update_profile(struct isc_device *isc) diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index ef3a0451192d..cb47932197b1 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -203,6 +203,8 @@ struct isc_reg_offsets { * * @config_csc: pointer to a function that initializes product * specific CSC module + * @config_cbc: pointer to a function that initializes product + * specific CBC module * * @offsets: struct holding the product specific register offsets */ @@ -275,6 +277,7 @@ struct isc_device { struct { void (*config_csc)(struct isc_device *isc); + void (*config_cbc)(struct isc_device *isc); }; struct isc_reg_offsets offsets; diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index 3b076b87454e..36bf15a9607d 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -73,6 +73,14 @@ void isc_sama5d2_config_csc(struct isc_device *isc) 0xFEE | (0x80 << 16)); } +void isc_sama5d2_config_cbc(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + + regmap_write(regmap, ISC_CBC_BRIGHT, isc->ctrls.brightness); + regmap_write(regmap, ISC_CBC_CONTRAST, isc->ctrls.contrast); +} + /* Gamma table with gamma 1/2.2 */ const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { /* 0 --> gamma 1/1.8 */ @@ -218,6 +226,7 @@ static int atmel_isc_probe(struct platform_device *pdev) isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; isc->config_csc = isc_sama5d2_config_csc; + isc->config_cbc = isc_sama5d2_config_cbc; isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; From patchwork Thu Apr 1 11:27:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12178933 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93754C433ED for ; Thu, 1 Apr 2021 18:04:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 65CA36112E for ; Thu, 1 Apr 2021 18:04:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235615AbhDASEA (ORCPT ); Thu, 1 Apr 2021 14:04:00 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:65126 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237491AbhDASAI (ORCPT ); Thu, 1 Apr 2021 14:00:08 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617300008; x=1648836008; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5CAS53/++Li9k7hQhqqVrVX32Fe/I7vzDF5LZE6z+Fw=; b=tve5o87hYXhgcATGI3mARhMo3y4t4nZ9vDLe7xSvoAam25EnOVq6lKpL 1e95fpvXcDLO/W19Xqu69C0jjpMMZKOCy8ojMtCQAmt/CkXIgwmK4AgTN JZx32NKN5NTe3aO4KXs1mJ/j5J4DSZ1CF1YmnESgFOQRFHMKV8hRGnywO e9agsov45EPn1LjmJetrFr3vuQdByCPFxmYJg14GHX78cDRHHklwKLDKL +wPr85gsRwvlKM1FYtgfLjVvhfU8CUJpN2iVdiGgS6ajRXFQzSnttrGBU j2fag6cvlYngl2bEtp8DHx7o65d2iX58EbVMfysHNkdNzCBcxbAgtXcrJ A==; IronPort-SDR: TEWygatqKULbCqx2GqeWXPLSHFjDohr7tQEH0FL4I+ISoX/q9wXmwXrcuMA+pjgWprAhc/8ckR kAJabgLbicB6zDKEyY+774Xp+zgnQafhFhXxW/CxN7qoynLoO5lNTFEuxZWUrHQcx2PBMQBy9s mWXBVwFLPt2XXcHUQjlzmV/tk6wqNDYWl3p3oOw+OGl5rGsBDaiG1Xp1vXMndvAlufFCosVlbs HFnBqmSxnSJVV9dOJb87ihvS7JbmsmfjtS5JyEI3sB55MOYFjcFyUhvCuHIYmTph7iGEZiPfgP RQ0= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="49670823" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:30:21 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:30:21 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:30:16 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 10/30] media: atmel: atmel-isc: add CBC to the reg offsets struct Date: Thu, 1 Apr 2021 14:27:03 +0300 Message-ID: <20210401112723.189107-11-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add cbc to the reg offsets struct. This will allow different products to have a different reg offset for this particular module. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 2 +- drivers/media/platform/atmel/atmel-isc-regs.h | 3 +++ drivers/media/platform/atmel/atmel-isc.h | 2 ++ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 7 +++++-- 4 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 446fe232956b..d4bf7fd5929f 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -2310,7 +2310,7 @@ int isc_pipeline_init(struct isc_device *isc) REG_FIELD(ISC_GAM_CTRL, 2, 2), REG_FIELD(ISC_GAM_CTRL, 3, 3), REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), - REG_FIELD(ISC_CBC_CTRL, 0, 0), + REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0), REG_FIELD(ISC_SUB422_CTRL, 0, 0), REG_FIELD(ISC_SUB420_CTRL, 0, 0), }; diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h index 5a65600c5f88..a5e2fe01ba9f 100644 --- a/drivers/media/platform/atmel/atmel-isc-regs.h +++ b/drivers/media/platform/atmel/atmel-isc-regs.h @@ -177,6 +177,9 @@ /* Color Space Conversion CRB OCR Register */ #define ISC_CSC_CRB_OCR 0x000003b0 +/* Offset for CBC register specific to sama5d2 product */ +#define ISC_SAMA5D2_CBC_OFFSET 0 + /* Contrast And Brightness Control Register */ #define ISC_CBC_CTRL 0x000003b4 diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index cb47932197b1..b1fe93c93c61 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -147,9 +147,11 @@ struct isc_ctrls { /* * struct isc_reg_offsets - ISC device register offsets * @csc: Offset for the CSC register + * @cbc: Offset for the CBC register */ struct isc_reg_offsets { u32 csc; + u32 cbc; }; /* diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index 36bf15a9607d..275999314e61 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -77,8 +77,10 @@ void isc_sama5d2_config_cbc(struct isc_device *isc) { struct regmap *regmap = isc->regmap; - regmap_write(regmap, ISC_CBC_BRIGHT, isc->ctrls.brightness); - regmap_write(regmap, ISC_CBC_CONTRAST, isc->ctrls.contrast); + regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, + isc->ctrls.brightness); + regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, + isc->ctrls.contrast); } /* Gamma table with gamma 1/2.2 */ @@ -229,6 +231,7 @@ static int atmel_isc_probe(struct platform_device *pdev) isc->config_cbc = isc_sama5d2_config_cbc; isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; + isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; /* sama5d2-isc - 8 bits per beat */ isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; From patchwork Thu Apr 1 11:27:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12179055 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEE03C43461 for ; Thu, 1 Apr 2021 18:08:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BF4596112E for ; Thu, 1 Apr 2021 18:08:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237694AbhDASIm (ORCPT ); Thu, 1 Apr 2021 14:08:42 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:19898 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236389AbhDASCY (ORCPT ); Thu, 1 Apr 2021 14:02:24 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617300144; x=1648836144; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AQJEQgxg0dYK65pobo2TAYjrkhPkUnYyMd5LnexLNkE=; b=PAeYdoyFknBh07bZCFZgDsmn7O5ZIRv2fAQVOVC16jbOOArpo67AyC24 04gyYNW9Lgs4OcsuUvDAxhjCZh87UuQlmi63Kc+XryYuZtkaTsPGUlIWz 22LKlloGr1FLOhet7f3MD2Zc6nreXXP6OzgVaaOQHcirMWTYhkO/buCBl C24HtmwNxdWg7k1ILoa7yqoKkkTZlXTQjKAFVamnZ2Xa2a8OIE9lUN3Pp dXixxuROM7NoYMXHq9rPq5XFl75G66tsXE50r7B3lfHw5vaugVIFMc4UR aJQoB6UPxAsuR50NsK+1sYLNAGR6BbjXAthBL9Ea7sXRIKiIanAE9Y5Bw Q==; IronPort-SDR: aHuXYiIkgG1ikQoj79SNHlhLiI0ZGhUhou2fTuJY15le9MnJe5LjgAahaPrlkCiDJ0Mv8rVIl2 1tJ28oSSALsD/F2wBAuhI0MYM0tfru5E5cIHEJsTYsgoHbVAY6llasMbNJsCyxyU3NWs19SvQ1 Akog63QJo5VhTLxHs7EZ0/6cd+Xf+/oUpSG0btxjswYGUNpVS0mwJdbfatBT+YF72dT3D82j1+ AcctcWsYIuiB8eaCvLlqLNhm0VQDNHngDdfwDsch3Nik+5+j4vsidn5xijSPTRBnl4/u2VeYDN 9+E= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="109338418" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:30:31 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:30:31 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:30:22 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 11/30] media: atmel: atmel-isc: add SUB422 and SUB420 to register offsets Date: Thu, 1 Apr 2021 14:27:04 +0300 Message-ID: <20210401112723.189107-12-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add sub420 and sub422 to the reg offsets struct. This will allow different products to have a different reg offset for these particular modules. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 4 ++-- drivers/media/platform/atmel/atmel-isc-regs.h | 4 ++++ drivers/media/platform/atmel/atmel-isc.h | 4 ++++ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 2 ++ 4 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index d4bf7fd5929f..b2067d75499b 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -2311,8 +2311,8 @@ int isc_pipeline_init(struct isc_device *isc) REG_FIELD(ISC_GAM_CTRL, 3, 3), REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0), - REG_FIELD(ISC_SUB422_CTRL, 0, 0), - REG_FIELD(ISC_SUB420_CTRL, 0, 0), + REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0), + REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0), }; for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) { diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h index a5e2fe01ba9f..04839def6ef6 100644 --- a/drivers/media/platform/atmel/atmel-isc-regs.h +++ b/drivers/media/platform/atmel/atmel-isc-regs.h @@ -194,9 +194,13 @@ #define ISC_CBC_CONTRAST 0x000003c0 #define ISC_CBC_CONTRAST_MASK GENMASK(11, 0) +/* Offset for SUB422 register specific to sama5d2 product */ +#define ISC_SAMA5D2_SUB422_OFFSET 0 /* Subsampling 4:4:4 to 4:2:2 Control Register */ #define ISC_SUB422_CTRL 0x000003c4 +/* Offset for SUB420 register specific to sama5d2 product */ +#define ISC_SAMA5D2_SUB420_OFFSET 0 /* Subsampling 4:2:2 to 4:2:0 Control Register */ #define ISC_SUB420_CTRL 0x000003cc diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index b1fe93c93c61..fb7257872e7c 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -148,10 +148,14 @@ struct isc_ctrls { * struct isc_reg_offsets - ISC device register offsets * @csc: Offset for the CSC register * @cbc: Offset for the CBC register + * @sub422: Offset for the SUB422 register + * @sub420: Offset for the SUB420 register */ struct isc_reg_offsets { u32 csc; u32 cbc; + u32 sub422; + u32 sub420; }; /* diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index 275999314e61..1bf83959a9e4 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -232,6 +232,8 @@ static int atmel_isc_probe(struct platform_device *pdev) isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; + isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET; + isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET; /* sama5d2-isc - 8 bits per beat */ isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; From patchwork Thu Apr 1 11:27:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12179071 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CFB6C43460 for ; Thu, 1 Apr 2021 18:09:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1F232610C7 for ; Thu, 1 Apr 2021 18:09:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236770AbhDASI5 (ORCPT ); Thu, 1 Apr 2021 14:08:57 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:19744 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237779AbhDASEY (ORCPT ); Thu, 1 Apr 2021 14:04:24 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617300265; x=1648836265; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XhzC42OpEuuZbRiFkhPyJBwbf2DhtCryGSIJP5xQ8GU=; b=B+LYfF/DH505Hxs39Y/0+KyKuroRzohIJD8DVzKl4PGXM0jzAXMo0CHJ DgAmlyMvWH5FijDNy/28KsuU9msGvslb0YjP89Lr3nMoKyBJGK45/gsRI G/gv8rWO9L5wTlogT6o3Yz4dxugiBCVuy+Qu5Y+gNNF+ydjKCEBtf4rJx RdIsYxM3ujE59LeuIwYbTS6NrHjJFH9ThAufGqvDvKkYn/v90qN45QUcM uH1R1JW22YdP0nAGqo1cZTWTus6q+9O+WR9txzBUYS1fIQUdP8ywZkJx3 hNhHPD5esjXP8ZhwkFFuaxXPSbHJYM17mFQmr3gYFTEKyo7PMNhnznPin A==; IronPort-SDR: +o8ycAI5mnJ5QRwL5cPiEwkq6mnsQYtDiUNWm1eSY+OI+ppWNLoD+867TnwLQm8sQJPaALldH+ AL1yOuE/rPQdUjdxxwVMacYUpXBetb/TcVaCgQVYwhIVYe1XPAfcepy390NmygU3joAy7VCU/b t5iarpO8TG+WCdMM6fMyfE4PECM7hHq41PH/MTWOwSOyl3mEf99GADqjEYs5/lXYUU87fDupkN sa9Oo5PVSAjlEEX5o+gm4tXUXZDlpu4MpYWTKwBgrLCSssqKqS4+NvpVUhyfm10Lj/q5tbZQHa zpU= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="109338449" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:30:39 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:30:38 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:30:32 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 12/30] media: atmel: atmel-isc: add RLP to register offsets Date: Thu, 1 Apr 2021 14:27:05 +0300 Message-ID: <20210401112723.189107-13-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add rlp to the reg offsets struct. This will allow different products to have a different reg offset for this particular module. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 4 ++-- drivers/media/platform/atmel/atmel-isc-regs.h | 2 ++ drivers/media/platform/atmel/atmel-isc.h | 2 ++ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 1 + 4 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index b2067d75499b..317172959370 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -718,8 +718,8 @@ static int isc_configure(struct isc_device *isc) regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0); - regmap_update_bits(regmap, ISC_RLP_CFG, ISC_RLP_CFG_MODE_MASK, - rlp_mode); + regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, + ISC_RLP_CFG_MODE_MASK, rlp_mode); regmap_write(regmap, ISC_DCFG, dcfg); diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h index 04839def6ef6..2205484e04fc 100644 --- a/drivers/media/platform/atmel/atmel-isc-regs.h +++ b/drivers/media/platform/atmel/atmel-isc-regs.h @@ -204,6 +204,8 @@ /* Subsampling 4:2:2 to 4:2:0 Control Register */ #define ISC_SUB420_CTRL 0x000003cc +/* Offset for RLP register specific to sama5d2 product */ +#define ISC_SAMA5D2_RLP_OFFSET 0 /* Rounding, Limiting and Packing Configuration Register */ #define ISC_RLP_CFG 0x000003d0 diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index fb7257872e7c..b7d4e7fab570 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -150,12 +150,14 @@ struct isc_ctrls { * @cbc: Offset for the CBC register * @sub422: Offset for the SUB422 register * @sub420: Offset for the SUB420 register + * @rlp: Offset for the RLP register */ struct isc_reg_offsets { u32 csc; u32 cbc; u32 sub422; u32 sub420; + u32 rlp; }; /* diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index 1bf83959a9e4..32c05eb1c16d 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -234,6 +234,7 @@ static int atmel_isc_probe(struct platform_device *pdev) isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET; isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET; + isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET; /* sama5d2-isc - 8 bits per beat */ isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; From patchwork Thu Apr 1 11:27:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12179065 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6149CC43611 for ; Thu, 1 Apr 2021 18:08:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 33DCE60FE6 for ; Thu, 1 Apr 2021 18:08:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237861AbhDASIz (ORCPT ); Thu, 1 Apr 2021 14:08:55 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:44187 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237776AbhDASEY (ORCPT ); Thu, 1 Apr 2021 14:04:24 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617300265; x=1648836265; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cV7pIY+3sDQXdVwlrzAphNU2hs+f8yThuBN6ce6+z0o=; b=ClitHeteAvlwnJKHxydInBonhn66It6h6AAN7ivN8vpfJnzQ3+cL6t4K nDrEiR7Jp7d3VP8XL5y9wDaziir/er5mtS+2TpVOCCHwL29zsJd/l26g/ N66f8Bom9QQpr4GdTcuWJSafN9fUsdnXt5sG0UadKWWd2LLJ4aCmJ7l2O E4qaBbZ6a4DWN6MpkBZzEXk7FXbNZTYdHspCAAh258bYuiMcg7E95MJei 4zfepol8xcf/GQk0IfaJSqXXnRN3aVWfTeRDyUCz3yLxeefn9x+2J7Cad tG8yau4V/qc4mabxqltXn9HhXpk9C5yOnkLZsts0mp7A2EnayXO8rs6Wd g==; IronPort-SDR: opE8pjPQjyD/WifVyxrUAyEkCTEsAbOlD1H3TIxzGmckIlNSTNZL0EdrgXj5YMn5kXbrMUw7WB 8a4lqUV97kh4Xf+oHo/II29jrl6q9xOaIVUYY1hXM0OWeqS1yHH7H5SlIFINj8ugME9f3ifVwx Z74RVUqfrAiCD4QO50N3zJJuyGa/sHmMDU51/yHoxdCDdAcFrQ0uE97PsxHqJuO3yG6gsnFBey 4Ax4o7fpQkxniOsAyKLpaF00/lRMEJc7t9JsZiM+D4dmTbKWlOQvuOXTbbBYSVgyuHRfgCxr+J DYw= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="112132544" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:30:51 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:30:50 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:30:39 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 13/30] media: atmel: atmel-isc: add HIS to register offsets Date: Thu, 1 Apr 2021 14:27:06 +0300 Message-ID: <20210401112723.189107-14-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add his to the reg offsets struct. This will allow different products to have a different reg offset for this particular module. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 11 +++++++---- drivers/media/platform/atmel/atmel-isc-regs.h | 2 ++ drivers/media/platform/atmel/atmel-isc.h | 2 ++ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 1 + 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 317172959370..aa7a9a7ca0e6 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -678,12 +678,13 @@ static void isc_set_histogram(struct isc_device *isc, bool enable) struct isc_ctrls *ctrls = &isc->ctrls; if (enable) { - regmap_write(regmap, ISC_HIS_CFG, + regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his, ISC_HIS_CFG_MODE_GR | (isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT) | ISC_HIS_CFG_RAR); - regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_EN); + regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his, + ISC_HIS_CTRL_EN); regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE); ctrls->hist_id = ISC_HIS_CFG_MODE_GR; isc_update_profile(isc); @@ -692,7 +693,8 @@ static void isc_set_histogram(struct isc_device *isc, bool enable) ctrls->hist_stat = HIST_ENABLED; } else { regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE); - regmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_DIS); + regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his, + ISC_HIS_CTRL_DIS); ctrls->hist_stat = HIST_DISABLED; } @@ -1821,7 +1823,8 @@ static void isc_awb_work(struct work_struct *w) ctrls->awb = ISC_WB_NONE; } } - regmap_write(regmap, ISC_HIS_CFG, hist_id | baysel | ISC_HIS_CFG_RAR); + regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his, + hist_id | baysel | ISC_HIS_CFG_RAR); isc_update_profile(isc); /* if awb has been disabled, we don't need to start another histogram */ if (ctrls->awb) diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h index 2205484e04fc..0ab280ab59ec 100644 --- a/drivers/media/platform/atmel/atmel-isc-regs.h +++ b/drivers/media/platform/atmel/atmel-isc-regs.h @@ -224,6 +224,8 @@ #define ISC_RLP_CFG_MODE_YYCC_LIMITED 0xc #define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0) +/* Offset for HIS register specific to sama5d2 product */ +#define ISC_SAMA5D2_HIS_OFFSET 0 /* Histogram Control Register */ #define ISC_HIS_CTRL 0x000003d4 diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index b7d4e7fab570..652285dc9f52 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -151,6 +151,7 @@ struct isc_ctrls { * @sub422: Offset for the SUB422 register * @sub420: Offset for the SUB420 register * @rlp: Offset for the RLP register + * @his: Offset for the HIS related registers */ struct isc_reg_offsets { u32 csc; @@ -158,6 +159,7 @@ struct isc_reg_offsets { u32 sub422; u32 sub420; u32 rlp; + u32 his; }; /* diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index 32c05eb1c16d..886dea8b7b1c 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -235,6 +235,7 @@ static int atmel_isc_probe(struct platform_device *pdev) isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET; isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET; isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET; + isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET; /* sama5d2-isc - 8 bits per beat */ isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; From patchwork Thu Apr 1 11:27:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12178839 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 178BFC433B4 for ; Thu, 1 Apr 2021 17:59:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E587860FF3 for ; Thu, 1 Apr 2021 17:58:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235201AbhDAR6z (ORCPT ); Thu, 1 Apr 2021 13:58:55 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:19744 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235323AbhDAR4S (ORCPT ); Thu, 1 Apr 2021 13:56:18 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617299778; x=1648835778; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/YR83v3iNrlSY/SHAVyK3TyP+czbbOylAO068334qq0=; b=DtQ0ytROQLt6J10MyOti81n0jIMiLa8unmnlXixMUxPS7tUabicT4lO1 8ZO588nEWAblbmM5xFQ0aBF1q3IlDIDA1+MLAW43K68oB4PtkRqwlXtJi YZFo2shXvilYvdR+vV6cT9fJTmi/CI28OsAfeWasKGhlnz/PVLwvsrtEh Yb8HmiLrW25KWOiQYUbGS/E2uL2OQq+M0xrGaIogJt4EqSWPOOnMkV0+n am65k+Jg1r6psm4JSy/3WT1l8tsh9vn1X1IC/T2FUSjBLw4aCk1Y0uAng i4KSuson/zpxAeeEe4u9DxvFe0NGCIZMqsxlqywN/G5ou7ILV9QNUsl69 A==; IronPort-SDR: yvS4/gljrf6a27pksFWaPsv5agOFzG2VLbelUEmUc+KXWolwaLkc7SqJHZmN86vW0AqvHTZE/N da9xvk+QQwDeJZQE6jx5T2uQe+SH7NJSmuB1dW4SUzUYot0SIdnpPCh60Ku4zDxdrECpjILJFB 2PvUMCqszUELo+JyXjDIQ8NGLFDTGLDVFjXSttgk+Yd/tmXe50yLjp4UsKF5055+Pp++JSn4no S5KSulRMJ4L1lIWVb9YStvhohSZMRi86WUnh29G5m88mF3HRp8foYXHfJ9bYXwMwTkmXXI4Z8B k7E= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="109338497" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:30:57 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:30:57 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:30:50 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 14/30] media: atmel: atmel-isc: add DMA to register offsets Date: Thu, 1 Apr 2021 14:27:07 +0300 Message-ID: <20210401112723.189107-15-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add dma to the reg offsets struct. This will allow different products to have a different reg offset for this particular module. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 19 ++++++++++++------- drivers/media/platform/atmel/atmel-isc-regs.h | 3 +++ drivers/media/platform/atmel/atmel-isc.h | 2 ++ .../media/platform/atmel/atmel-sama5d2-isc.c | 1 + 4 files changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index aa7a9a7ca0e6..11121943d2cb 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -593,16 +593,20 @@ static void isc_start_dma(struct isc_device *isc) ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN); addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0); - regmap_write(regmap, ISC_DAD0, addr0); + regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0); switch (isc->config.fourcc) { case V4L2_PIX_FMT_YUV420: - regmap_write(regmap, ISC_DAD1, addr0 + (sizeimage * 2) / 3); - regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 5) / 6); + regmap_write(regmap, ISC_DAD1 + isc->offsets.dma, + addr0 + (sizeimage * 2) / 3); + regmap_write(regmap, ISC_DAD2 + isc->offsets.dma, + addr0 + (sizeimage * 5) / 6); break; case V4L2_PIX_FMT_YUV422P: - regmap_write(regmap, ISC_DAD1, addr0 + sizeimage / 2); - regmap_write(regmap, ISC_DAD2, addr0 + (sizeimage * 3) / 4); + regmap_write(regmap, ISC_DAD1 + isc->offsets.dma, + addr0 + sizeimage / 2); + regmap_write(regmap, ISC_DAD2 + isc->offsets.dma, + addr0 + (sizeimage * 3) / 4); break; default: break; @@ -610,7 +614,8 @@ static void isc_start_dma(struct isc_device *isc) dctrl_dview = isc->config.dctrl_dview; - regmap_write(regmap, ISC_DCTRL, dctrl_dview | ISC_DCTRL_IE_IS); + regmap_write(regmap, ISC_DCTRL + isc->offsets.dma, + dctrl_dview | ISC_DCTRL_IE_IS); spin_lock(&isc->awb_lock); regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE); spin_unlock(&isc->awb_lock); @@ -723,7 +728,7 @@ static int isc_configure(struct isc_device *isc) regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, ISC_RLP_CFG_MODE_MASK, rlp_mode); - regmap_write(regmap, ISC_DCFG, dcfg); + regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg); /* Set the pipeline */ isc_set_pipeline(isc, pipeline); diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h index 0ab280ab59ec..4940998c82a2 100644 --- a/drivers/media/platform/atmel/atmel-isc-regs.h +++ b/drivers/media/platform/atmel/atmel-isc-regs.h @@ -247,6 +247,9 @@ #define ISC_HIS_CFG_RAR BIT(8) +/* Offset for DMA register specific to sama5d2 product */ +#define ISC_SAMA5D2_DMA_OFFSET 0 + /* DMA Configuration Register */ #define ISC_DCFG 0x000003e0 #define ISC_DCFG_IMODE_PACKED8 0x0 diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index 652285dc9f52..52a9199d65ee 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -152,6 +152,7 @@ struct isc_ctrls { * @sub420: Offset for the SUB420 register * @rlp: Offset for the RLP register * @his: Offset for the HIS related registers + * @dma: Offset for the DMA related registers */ struct isc_reg_offsets { u32 csc; @@ -160,6 +161,7 @@ struct isc_reg_offsets { u32 sub420; u32 rlp; u32 his; + u32 dma; }; /* diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index 886dea8b7b1c..f583288f0503 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -236,6 +236,7 @@ static int atmel_isc_probe(struct platform_device *pdev) isc->offsets.sub420 = ISC_SAMA5D2_SUB420_OFFSET; isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET; isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET; + isc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET; /* sama5d2-isc - 8 bits per beat */ isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; From patchwork Thu Apr 1 11:27:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12178837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 687D8C43603 for ; Thu, 1 Apr 2021 17:58:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 381F06112E for ; Thu, 1 Apr 2021 17:58:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235625AbhDAR6x (ORCPT ); Thu, 1 Apr 2021 13:58:53 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:19898 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236019AbhDAR4S (ORCPT ); Thu, 1 Apr 2021 13:56:18 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617299778; x=1648835778; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BqgkVlx1wDp81RVlVAWD1R2MET36e/zdD/q1Q3pa2Q8=; b=15wxNN/OWoj/Vw75Ff+M8EWwbnrW+Kn0ERGEFQywLRYeFCwz5nQF/Xth 2RY8pm9mZRu6k8l3BcCGSygerhT4v/Rg2Srcj6NklFxX4uv+AWPB5PkC6 TH7zMfK83u5G6LWQxmvwA8vR5R8ENJl3j/ZSMVFqnWdR5f9mIB8cVLZmm Vr1O2PfGK461watd0pQ1itrimfheymi7J7rnhwuyoJyCKgr6mWI3BI3s4 9QIJT/blii/rFdK7FYhoVHlhQ3Gy6dF7UuwX2wW6mvqp3dSOinqYHldpg J/Io17sbgGGA+jHBcX8C/CktYwWmSmTliZWoLH+l5gMdTCMLUog43VQXs g==; IronPort-SDR: YoXY73OsGRQmf/DhN558yxVBXQevyaWCEVCmzF+TO7fCU1h9tvQmc05TgvDUsgDT16B6Aq+Z7r R/Vu8BDxPrN6QYnJqn4n0odsjqJ18L5DcwxJlqVb/DXy1jdlSLrUGrK4NQByW/g+haBn4FvprS yNjUg8ND8no8vMvDBxYZGKJlVcP/2TP7KlDkGkOzKmK7waWXJeKzT2W6i7++efMjESlC23S5sl dJ5OpTWv4xzT0EgeDQ5H5+Y0KD2GJpnNyssDKIvo9nUozzvV+Om6Q6Mgdbq4l1Zd0nCGavYLyr N1I= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="109338577" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:31:19 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:31:19 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:31:03 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 15/30] media: atmel: atmel-isc: add support for version register Date: Thu, 1 Apr 2021 14:27:08 +0300 Message-ID: <20210401112723.189107-16-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add support for version register and print it at probe time. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-regs.h | 5 +++++ drivers/media/platform/atmel/atmel-isc.h | 2 ++ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 5 +++++ 3 files changed, 12 insertions(+) diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h index 4940998c82a2..344668dcfcf4 100644 --- a/drivers/media/platform/atmel/atmel-isc-regs.h +++ b/drivers/media/platform/atmel/atmel-isc-regs.h @@ -295,6 +295,11 @@ /* DMA Address 2 Register */ #define ISC_DAD2 0x000003fc +/* Offset for version register specific to sama5d2 product */ +#define ISC_SAMA5D2_VERSION_OFFSET 0 +/* Version Register */ +#define ISC_VERSION 0x0000040c + /* Histogram Entry */ #define ISC_HIS_ENTRY 0x00000410 diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index 52a9199d65ee..676a5be1ee8c 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -153,6 +153,7 @@ struct isc_ctrls { * @rlp: Offset for the RLP register * @his: Offset for the HIS related registers * @dma: Offset for the DMA related registers + * @version: Offset for the version register */ struct isc_reg_offsets { u32 csc; @@ -162,6 +163,7 @@ struct isc_reg_offsets { u32 rlp; u32 his; u32 dma; + u32 version; }; /* diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index f583288f0503..500618240fc2 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -189,6 +189,7 @@ static int atmel_isc_probe(struct platform_device *pdev) struct isc_subdev_entity *subdev_entity; int irq; int ret; + u32 ver; isc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL); if (!isc) @@ -237,6 +238,7 @@ static int atmel_isc_probe(struct platform_device *pdev) isc->offsets.rlp = ISC_SAMA5D2_RLP_OFFSET; isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET; isc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET; + isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET; /* sama5d2-isc - 8 bits per beat */ isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; @@ -332,6 +334,9 @@ static int atmel_isc_probe(struct platform_device *pdev) pm_runtime_enable(dev); pm_request_idle(dev); + regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver); + dev_info(dev, "Microchip ISC version %x\n", ver); + return 0; cleanup_subdev: From patchwork Thu Apr 1 11:27:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12178849 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EE2CC43460 for ; Thu, 1 Apr 2021 18:01:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2BE7061159 for ; Thu, 1 Apr 2021 18:01:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235536AbhDASBq (ORCPT ); Thu, 1 Apr 2021 14:01:46 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:19898 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236628AbhDAR6T (ORCPT ); Thu, 1 Apr 2021 13:58:19 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617299900; x=1648835900; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MFJmyfx6WKWCPMiE879BubSdjCxUsUZViec4erdNPGQ=; b=ZCM1d8tomC0trSLdukUfj99852fBkTsnqbY+U8yvdlks3on13lqq+EZj tavoVwRLpgg8+BvXZheoFk11zsR49E+E98DET80EFfeY4yx2zku1s73tL OyBUngzkYtOnjNCl8pItTP+zU38vVZ2QtXV92nDrxDucYX02D9XCQZvWn ncLlb4OdaGePehY1hyqyrfMWz+xmPKuup+zFQQKhIeccgEAXLLU9ZLv5X X1eukWuCRKEAN9jmNHaa09wTjbYKdDnimi5x5jpawrTtZmOJqPm2Eqoj6 imzyqavc2kEMAfN6db62jj6wBQSUJJhV5hz9Ripd7AjWNgkiFHzPChyhe g==; IronPort-SDR: pi3R2LS2JZK4aOl4ooAisLWKTf2pUMyK1YD+tNiv/502EFOW8QiEd33iNnV8Ed/VqQ7bTglTXv pdlsGCzFwpQzhvB9pnRExVxQoV6IM6Aqibh0sNXpw0ulYaVkxVtyJEmhj+QqnVl0CdxYXYVHeA 2U9JIpBtkFsA4sMf08UHiu0v8o5acBBJcXca5M+dV16XEQSJr9RXcFjz64x42k+UK/DeOFP8eh mmJagZyIXPGaqxwZ04ooXywVmHhzsd6KxywOmKEI6bcERolw5y5WmarnQkUlciXOgSTvqt8XC1 8G0= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="109338642" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:31:46 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:31:45 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:31:19 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 16/30] media: atmel: atmel-isc: add his_entry to register offsets Date: Thu, 1 Apr 2021 14:27:09 +0300 Message-ID: <20210401112723.189107-17-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add his_entry to the reg offsets struct. This will allow different products to have a different reg offset for this particular module. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 3 ++- drivers/media/platform/atmel/atmel-isc-regs.h | 2 ++ drivers/media/platform/atmel/atmel-isc.h | 2 ++ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 1 + 4 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 11121943d2cb..2a619eef6aa3 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -1672,7 +1672,8 @@ static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max) *min = 0; *max = HIST_ENTRIES; - regmap_bulk_read(regmap, ISC_HIS_ENTRY, hist_entry, HIST_ENTRIES); + regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry, + hist_entry, HIST_ENTRIES); *hist_count = 0; /* diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h index 344668dcfcf4..a15c13e1a833 100644 --- a/drivers/media/platform/atmel/atmel-isc-regs.h +++ b/drivers/media/platform/atmel/atmel-isc-regs.h @@ -300,6 +300,8 @@ /* Version Register */ #define ISC_VERSION 0x0000040c +/* Offset for version register specific to sama5d2 product */ +#define ISC_SAMA5D2_HIS_ENTRY_OFFSET 0 /* Histogram Entry */ #define ISC_HIS_ENTRY 0x00000410 diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index 676a5be1ee8c..c5d956fd20a0 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -154,6 +154,7 @@ struct isc_ctrls { * @his: Offset for the HIS related registers * @dma: Offset for the DMA related registers * @version: Offset for the version register + * @his_entry: Offset for the HIS entries registers */ struct isc_reg_offsets { u32 csc; @@ -164,6 +165,7 @@ struct isc_reg_offsets { u32 his; u32 dma; u32 version; + u32 his_entry; }; /* diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index 500618240fc2..da516f2f5ca9 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -239,6 +239,7 @@ static int atmel_isc_probe(struct platform_device *pdev) isc->offsets.his = ISC_SAMA5D2_HIS_OFFSET; isc->offsets.dma = ISC_SAMA5D2_DMA_OFFSET; isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET; + isc->offsets.his_entry = ISC_SAMA5D2_HIS_ENTRY_OFFSET; /* sama5d2-isc - 8 bits per beat */ isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; From patchwork Thu Apr 1 11:27:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12178937 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC343C433B4 for ; Thu, 1 Apr 2021 18:04:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A3CE36112E for ; Thu, 1 Apr 2021 18:04:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237670AbhDASEG (ORCPT ); Thu, 1 Apr 2021 14:04:06 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:44187 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237538AbhDASAW (ORCPT ); Thu, 1 Apr 2021 14:00:22 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617300022; x=1648836022; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eEFZK/hSf05itEILHRf197/MjzOOVQu1dFzDN6v4vnA=; b=SCOZyRNMbITsB5eXVPZbtQ4++Pi/RbpHJO0OHiPSscZMsLVcHA8MOr/j EL0prtc+n08rLxPP8NORG/pRejU11DQ+hMfGda7ZopikptM++0Y+y71dF vdDg2gbj6u44Og2q5qmo+Jrj17AlF1aNYSugf28t1pw/P59W7KKFvhZ3N OMZw1YeHmNIDWdOl4KxPGz7CTTMGSMVq7Qem/69BF0cQC0fQIdRu/DhfE T71t6aV7OzajhamSMUoa6rXC4UWeTu1dy7/8pQT6lUEEbJDcZOxSDvdgB uac25HnERIVYcLfbi3V1J/itbRuhOp8MtTsU7QuXr8Xew4uACOOxFond0 A==; IronPort-SDR: HXfZ9RMzmQjY7CuO+/qpFKoOhz+m28Oeg8dpY2G2rHfoLKAYBag7LxIp4ci6VTGpOCshYztolJ AVukyjYm+Mm9D7b6DRwUiBZQ3JVcDjcnz1MT8ypGmZB11yTAMdhzu4oGLZhk3E+Amp5+vmzU0j QVndBs0/7kPXOg8/BmyhFCSrDhMVyZLTg8y1MOh8qPo8J/X3g5M3ze2RPaKSNOokSmRt9lcu3k ltl9hgts9btbSUl9KsBk1UqII7d/PCCpZPUcif7ZbHnM3OyFEILY8fw2Pq8QoHG5xF9EQ/bgiE ma0= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="112132659" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:32:02 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:32:02 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:31:46 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 17/30] media: atmel: atmel-isc: add register description for additional modules Date: Thu, 1 Apr 2021 14:27:10 +0300 Message-ID: <20210401112723.189107-18-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add register description for additional pipeline modules: the Defective Pixel Correction (DPC) and the Vertical and Horizontal Scaler(VHXS) Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-regs.h | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h index a15c13e1a833..457eed74cda9 100644 --- a/drivers/media/platform/atmel/atmel-isc-regs.h +++ b/drivers/media/platform/atmel/atmel-isc-regs.h @@ -90,6 +90,46 @@ #define ISC_INT_DDONE BIT(8) #define ISC_INT_HISDONE BIT(12) +/* ISC DPC Control Register */ +#define ISC_DPC_CTRL 0x40 + +#define ISC_DPC_CTRL_DPCEN BIT(0) +#define ISC_DPC_CTRL_GDCEN BIT(1) +#define ISC_DPC_CTRL_BLCEN BIT(2) + +/* ISC DPC Config Register */ +#define ISC_DPC_CFG 0x44 + +#define ISC_DPC_CFG_BAYSEL_SHIFT 0 + +#define ISC_DPC_CFG_EITPOL BIT(4) + +#define ISC_DPC_CFG_TA_ENABLE BIT(14) +#define ISC_DPC_CFG_TC_ENABLE BIT(13) +#define ISC_DPC_CFG_TM_ENABLE BIT(12) + +#define ISC_DPC_CFG_RE_MODE BIT(17) + +#define ISC_DPC_CFG_GDCCLP_SHIFT 20 +#define ISC_DPC_CFG_GDCCLP_MASK GENMASK(22, 20) + +#define ISC_DPC_CFG_BLOFF_SHIFT 24 +#define ISC_DPC_CFG_BLOFF_MASK GENMASK(31, 24) + +#define ISC_DPC_CFG_BAYCFG_SHIFT 0 +#define ISC_DPC_CFG_BAYCFG_MASK GENMASK(1, 0) +/* ISC DPC Threshold Median Register */ +#define ISC_DPC_THRESHM 0x48 + +/* ISC DPC Threshold Closest Register */ +#define ISC_DPC_THRESHC 0x4C + +/* ISC DPC Threshold Average Register */ +#define ISC_DPC_THRESHA 0x50 + +/* ISC DPC STatus Register */ +#define ISC_DPC_SR 0x54 + /* ISC White Balance Control Register */ #define ISC_WB_CTRL 0x00000058 @@ -153,6 +193,33 @@ /* ISC_Gamma Correction Green Entry Register */ #define ISC_GAM_RENTRY 0x00000298 +/* ISC VHXS Control Register */ +#define ISC_VHXS_CTRL 0x398 + +/* ISC VHXS Source Size Register */ +#define ISC_VHXS_SS 0x39C + +/* ISC VHXS Destination Size Register */ +#define ISC_VHXS_DS 0x3A0 + +/* ISC Vertical Factor Register */ +#define ISC_VXS_FACT 0x3a4 + +/* ISC Horizontal Factor Register */ +#define ISC_HXS_FACT 0x3a8 + +/* ISC Vertical Config Register */ +#define ISC_VXS_CFG 0x3ac + +/* ISC Horizontal Config Register */ +#define ISC_HXS_CFG 0x3b0 + +/* ISC Vertical Tap Register */ +#define ISC_VXS_TAP 0x3b4 + +/* ISC Horizontal Tap Register */ +#define ISC_HXS_TAP 0x434 + /* Offset for CSC register specific to sama5d2 product */ #define ISC_SAMA5D2_CSC_OFFSET 0 From patchwork Thu Apr 1 11:27:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12179067 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18AC6C43603 for ; Thu, 1 Apr 2021 18:08:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EE2D461139 for ; Thu, 1 Apr 2021 18:08:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236091AbhDASIx (ORCPT ); Thu, 1 Apr 2021 14:08:53 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:65126 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237697AbhDASEK (ORCPT ); Thu, 1 Apr 2021 14:04:10 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617300251; x=1648836251; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TBEXU4Ly8SglyXAY2VWYA9gAClSi/maWKT5ll7y8lYs=; b=DXDHg4LtQWivLSZWba8uRPFSZNew9OC/43no6+8FY068mFwpMgIpEqoo ir2AhCeh5s3imAIenD1nHqS3ha2eYqcBQi+LkUCS2qB1MSVeL2rTvksHd Odhhr4WK16D64h7OPfjP5BHok5eqndLKVqbvgCklNCuASehgMMyP0Q8XF 46e+MTQG5XdLXIfHzyKABrOwqDBMZOgd7WQuLkzWP8UB0XwQfcuZOq8ta U6gy1ibe65avierawVi2YIbBx4VDGGucfhe0jLpFutpPRXa1hOcIUA7Pz SIiamzHOkyGaqZllhISXwGIjzO9Uor3NIAW6hXb8UvunIfR5iYYpwbQ+2 A==; IronPort-SDR: QrgXnl2tk0fAntPKCx1zA5LXV+TUiqAHKvmAFXezK7860d/W3yGiEGTNEJBbauZ6WLcMua1Z9V iSUD+GwBgdyD0Lz+DuRTVcmYYYVOkERYB/Z6N9XlrhHGT/Fwmr+h4lAfvN9/jDsb1Jq5ogxWYa jEZm8oK+nmlk6hNlTCKDW13xR8EcEndahTHrFaLdCuyh5iYai7AjNh1Evpa0JdsovsdJ8JmBba NFGRk1hhgxSBZH0C48WZ7QOTUPq18oQg87qqH3REx7zTj3yvAv+vKiXWallsvXPXCdxIHeJsT1 7ag= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="49671045" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:32:37 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:32:37 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:32:03 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 18/30] media: atmel: atmel-isc: extend pipeline with extra modules Date: Thu, 1 Apr 2021 14:27:11 +0300 Message-ID: <20210401112723.189107-19-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Newer ISC pipelines have the additional modules of Defective Pixel Correction -> DPC itself, Defective Pixel Correction -> Green Disparity Correction (DPC_GDC) Defective Pixel Correction -> Black Level Correction (DPC_BLC) Vertical and Horizontal Scaler -> VHXS Some products have this full pipeline (sama7g5), other products do not (sama5d2) Add the modules to the isc base, and also extend the register range to include the modules. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 11 ++++++-- drivers/media/platform/atmel/atmel-isc.h | 28 +++++++++++-------- 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 2a619eef6aa3..66005cb3940f 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -2309,8 +2309,14 @@ int isc_pipeline_init(struct isc_device *isc) struct regmap_field *regs; unsigned int i; - /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */ + /* + * DPCEN-->GDCEN-->BLCEN-->WB-->CFA-->CC--> + * GAM-->VHXS-->CSC-->CBC-->SUB422-->SUB420 + */ const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = { + REG_FIELD(ISC_DPC_CTRL, 0, 0), + REG_FIELD(ISC_DPC_CTRL, 1, 1), + REG_FIELD(ISC_DPC_CTRL, 2, 2), REG_FIELD(ISC_WB_CTRL, 0, 0), REG_FIELD(ISC_CFA_CTRL, 0, 0), REG_FIELD(ISC_CC_CTRL, 0, 0), @@ -2318,6 +2324,7 @@ int isc_pipeline_init(struct isc_device *isc) REG_FIELD(ISC_GAM_CTRL, 1, 1), REG_FIELD(ISC_GAM_CTRL, 2, 2), REG_FIELD(ISC_GAM_CTRL, 3, 3), + REG_FIELD(ISC_VHXS_CTRL, 0, 0), REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0), REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0), REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0), @@ -2336,7 +2343,7 @@ int isc_pipeline_init(struct isc_device *isc) } /* regmap configuration */ -#define ATMEL_ISC_REG_MAX 0xbfc +#define ATMEL_ISC_REG_MAX 0xd5c const struct regmap_config isc_regmap_config = { .reg_bits = 32, .reg_stride = 4, diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index c5d956fd20a0..f574bcc3ba67 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -68,17 +68,21 @@ struct isc_format { }; /* Pipeline bitmap */ -#define WB_ENABLE BIT(0) -#define CFA_ENABLE BIT(1) -#define CC_ENABLE BIT(2) -#define GAM_ENABLE BIT(3) -#define GAM_BENABLE BIT(4) -#define GAM_GENABLE BIT(5) -#define GAM_RENABLE BIT(6) -#define CSC_ENABLE BIT(7) -#define CBC_ENABLE BIT(8) -#define SUB422_ENABLE BIT(9) -#define SUB420_ENABLE BIT(10) +#define DPC_DPCENABLE BIT(0) +#define DPC_GDCENABLE BIT(1) +#define DPC_BLCENABLE BIT(2) +#define WB_ENABLE BIT(3) +#define CFA_ENABLE BIT(4) +#define CC_ENABLE BIT(5) +#define GAM_ENABLE BIT(6) +#define GAM_BENABLE BIT(7) +#define GAM_GENABLE BIT(8) +#define GAM_RENABLE BIT(9) +#define VHXS_ENABLE BIT(10) +#define CSC_ENABLE BIT(11) +#define CBC_ENABLE BIT(12) +#define SUB422_ENABLE BIT(13) +#define SUB420_ENABLE BIT(14) #define GAM_ENABLES (GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE) @@ -142,7 +146,7 @@ struct isc_ctrls { u32 hist_minmax[HIST_BAYER][2]; }; -#define ISC_PIPE_LINE_NODE_NUM 11 +#define ISC_PIPE_LINE_NODE_NUM 15 /* * struct isc_reg_offsets - ISC device register offsets From patchwork Thu Apr 1 11:27:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12178853 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B595C433B4 for ; Thu, 1 Apr 2021 18:01:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0148E6112F for ; Thu, 1 Apr 2021 18:01:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234207AbhDASBs (ORCPT ); Thu, 1 Apr 2021 14:01:48 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:19744 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236626AbhDAR6T (ORCPT ); Thu, 1 Apr 2021 13:58:19 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617299900; x=1648835900; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XeaF4eWaLDP8UECnNygoHMfnBPpBZkWuK4VeDitjExs=; b=uWBDjuGVnGupI3tSt2rc34qZKfxr3jpQAEVaIvnhAKHdBHYnXJ2kqDjD mchzH5xcRXCRYGWTD5MafjCQqmo9ETFZAEw7VHKFGt64uRcFPYwX8nqTV v7fUSOo/D917Kynf3CqxdY5DsfcWVG7FZIeMSGKOU2OIQXJBYCaNDejgM Va2BIzUxC1fkazwFOzw9yqyNvyM+3wkF0j2AdFhXJl84xcZgfCCiPI/c0 jb3TulboaJNhezfxqYs2wqli9AHFOjEreL7oXeDYysB+kChHWv+gMwL3N kfvsv2e8UtEs8M014UjPAuJfSIrI3yjPFpN2i2GY/IDPsqRG7hLY2vnOS g==; IronPort-SDR: 5Xp65OnpDItby1PclhVcvOpXV4PBTBlrhnfxkvg0zUGs488fPh1nlWZE/d2wfMd5xgOULGTQBu dSEe3hhG/DaPrHs8pdJULyRzoZw9rd14h6BBCpXOWRepTgtPHczaw+QUpuZWNXIvKwJBGNaTbO VtDiGPKhjDaiOq+Rfm4Q9fbxcCfkEKx0vBAW81snti3YF7KyeybghBxw/8RtpF4z3bvQXLRqhz PmnxdcTV6kfmYeYAaya8qLD7pM8A50cUciznFbSpv66TxPz/Us+jY9Z+9odNsDgvEmkhP5H1Nz Ui0= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="109338722" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:33:02 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:33:02 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:32:40 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 19/30] media: atmel: atmel-isc: add CC initialization function Date: Thu, 1 Apr 2021 14:27:12 +0300 Message-ID: <20210401112723.189107-20-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Implement the color correction (CC) submodule initialization, as a product specific function, which currently configures the neutral point in color correction. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 1 + drivers/media/platform/atmel/atmel-isc.h | 3 +++ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 14 ++++++++++++++ 3 files changed, 18 insertions(+) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 66005cb3940f..182903803c05 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -653,6 +653,7 @@ static void isc_set_pipeline(struct isc_device *isc, u32 pipeline) isc->config_csc(isc); isc->config_cbc(isc); + isc->config_cc(isc); } static int isc_update_profile(struct isc_device *isc) diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index f574bcc3ba67..a5f8d5001381 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -225,6 +225,8 @@ struct isc_reg_offsets { * specific CSC module * @config_cbc: pointer to a function that initializes product * specific CBC module + * @config_cc: pointer to a function that initializes product + * specific CC module * * @offsets: struct holding the product specific register offsets */ @@ -298,6 +300,7 @@ struct isc_device { struct { void (*config_csc)(struct isc_device *isc); void (*config_cbc)(struct isc_device *isc); + void (*config_cc)(struct isc_device *isc); }; struct isc_reg_offsets offsets; diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index da516f2f5ca9..917d10baa525 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -83,6 +83,19 @@ void isc_sama5d2_config_cbc(struct isc_device *isc) isc->ctrls.contrast); } +void isc_sama5d2_config_cc(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + + /* Configure each register at the neutral fixed point 1.0 or 0.0 */ + regmap_write(regmap, ISC_CC_RR_RG, (1 << 8)); + regmap_write(regmap, ISC_CC_RB_OR, 0); + regmap_write(regmap, ISC_CC_GR_GG, (1 << 8) << 16); + regmap_write(regmap, ISC_CC_GB_OG, 0); + regmap_write(regmap, ISC_CC_BR_BG, 0); + regmap_write(regmap, ISC_CC_BB_OB, (1 << 8)); +} + /* Gamma table with gamma 1/2.2 */ const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { /* 0 --> gamma 1/1.8 */ @@ -230,6 +243,7 @@ static int atmel_isc_probe(struct platform_device *pdev) isc->config_csc = isc_sama5d2_config_csc; isc->config_cbc = isc_sama5d2_config_cbc; + isc->config_cc = isc_sama5d2_config_cc; isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; From patchwork Thu Apr 1 11:27:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12179063 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F97FC43600 for ; Thu, 1 Apr 2021 18:08:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2F99660FE6 for ; Thu, 1 Apr 2021 18:08:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237802AbhDASIv (ORCPT ); Thu, 1 Apr 2021 14:08:51 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:1272 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237699AbhDASEK (ORCPT ); Thu, 1 Apr 2021 14:04:10 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617300251; x=1648836251; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NwVmuhcuP0mbkPb9G0ZjUPRewv6a/UcN2N/zsqQK+6E=; b=hXN7hAWvLlwl2R/5WJrcuIWFoXO1FFoY8C5X4dNtC/KAbEwjyU46iIGb sfPeqS0UPdc3/JG3xJIp1Xg0QBreEcmdjb+jPRUZX6o3Bi7ddXw15Fw1h 7t7q6hwcJsHd4V7wVvu32KEkYNOyOh7LIxbSz/qZOVGsZbzO4nzJFEqaE e/g/tOBZ9y3Zu28lf7evGTgP4u0gZPtrBSljh7Wm2AL+qcrp2feEnRLPd wpjw4V8GX84erSPJy7IsxHtn5XrQ+T0BIbKnqJaRR0j7ccnKsR/keP9db 0O/0RZPEt/a2YGRAI8g2v40wafh5YGGSJMgLb28nlQzvr5UaWXXn8zO+p g==; IronPort-SDR: 2avqN/GIltDF063VwkTMNBT47ALPCK0XA3TbL0GVsoK+CG7X4rOOO8bg1szaFyEKc14J44u+Pi 8STEd17EnsZBSUQdnVGs1dGWZI2eu3In/F3G2ANjdPmwj8BpVvOSUoYmuGz97Yq3G1MeFyl0mj v3D8MYDu/5d7Y/CTVwYQUGUNG/+cfCfo7QKLZ8Kj11IjtaCS4CowGijsE2eWFwW/m9yFGH7ajK Itzk1Kl+XiXyedMiG0N4cLKLYT6DPvZUbXiRnSV+vIJgMJHz5ydgfdJP3dqT9L04WeJaSUDKwp 30k= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="49671114" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:33:28 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:33:28 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:33:02 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 20/30] media: atmel: atmel-isc: create product specific v4l2 controls config Date: Thu, 1 Apr 2021 14:27:13 +0300 Message-ID: <20210401112723.189107-21-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Create product specific callback for initializing v4l2 controls. Call this from v4l2 controls init function. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 5 +++-- drivers/media/platform/atmel/atmel-isc.h | 5 +++++ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 12 ++++++++++++ 3 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 182903803c05..69952b6ac401 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -2036,11 +2036,12 @@ static int isc_ctrl_init(struct isc_device *isc) if (ret < 0) return ret; + /* Initialize product specific controls. For example, contrast */ + isc->config_ctrls(isc, ops); + ctrls->brightness = 0; - ctrls->contrast = 256; v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0); - v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256); v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1, isc->gamma_max); isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops, diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index a5f8d5001381..eb549fadb1a8 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -227,6 +227,8 @@ struct isc_reg_offsets { * specific CBC module * @config_cc: pointer to a function that initializes product * specific CC module + * @config_ctrls: pointer to a functoin that initializes product + * specific v4l2 controls. * * @offsets: struct holding the product specific register offsets */ @@ -301,6 +303,9 @@ struct isc_device { void (*config_csc)(struct isc_device *isc); void (*config_cbc)(struct isc_device *isc); void (*config_cc)(struct isc_device *isc); + + void (*config_ctrls)(struct isc_device *isc, + const struct v4l2_ctrl_ops *ops); }; struct isc_reg_offsets offsets; diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index 917d10baa525..a8375961f97d 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -96,6 +96,17 @@ void isc_sama5d2_config_cc(struct isc_device *isc) regmap_write(regmap, ISC_CC_BB_OB, (1 << 8)); } +void isc_sama5d2_config_ctrls(struct isc_device *isc, + const struct v4l2_ctrl_ops *ops) +{ + struct isc_ctrls *ctrls = &isc->ctrls; + struct v4l2_ctrl_handler *hdl = &ctrls->handler; + + ctrls->contrast = 256; + + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256); +} + /* Gamma table with gamma 1/2.2 */ const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { /* 0 --> gamma 1/1.8 */ @@ -244,6 +255,7 @@ static int atmel_isc_probe(struct platform_device *pdev) isc->config_csc = isc_sama5d2_config_csc; isc->config_cbc = isc_sama5d2_config_cbc; isc->config_cc = isc_sama5d2_config_cc; + isc->config_ctrls = isc_sama5d2_config_ctrls; isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; From patchwork Thu Apr 1 11:27:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12179273 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9997FC433ED for ; Thu, 1 Apr 2021 18:36:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7BE26601FC for ; Thu, 1 Apr 2021 18:36:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236313AbhDASgY (ORCPT ); Thu, 1 Apr 2021 14:36:24 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:46540 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240057AbhDAS1B (ORCPT ); Thu, 1 Apr 2021 14:27:01 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617301621; x=1648837621; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GVvIsZVQNrPMN1hvtWjBMXJ1JLr9Fd87AOEdQTPgcIk=; b=Rd7VLyWhf8ddys2AYPRgwdDKm0//R3wGiTs9qvO1NuTN6wE3lssmYleL oNoaLZEgkGHFpWolM06i3Kfx+tZaaZbv4fE89a1p/6sn9tlBqdtmB5Pmf JbvOCYzdt+h8ii8KFScAJxhT5klLEAvsLv6ERN0sbM0Ye3bM/9WuxzhVC Aq5LbF5LanHEjgCVBlnVL8G9OtAq93/F0VG061hKktxiw/+0x88w+ILzI 4VrlDjKHUUupvVchR4o+RBSd1cTC5Xdw2PggEbGf2L8fNlZ133hst4QK5 GqDQS8eyXMflszwGKP6b1Pti9bFkRCIU1PQNBTFJ6qBG/z8k+tiy+aZH1 A==; IronPort-SDR: nHdQnCDb6C7TBFjD1RAlb/KXxyl/VTykt5tJfKvqnNkKKAcIebDSVCkx2k+Hy9fXYT+1QmIDz/ +OnYjdK6OpjDFXG/UIS6pP3y2Y3Vx79bg5Dmur+6OtzFuev8Mk9/qxmoDBAM8VPShKQFDt2WRe 5UpnR87trs0vcCu45mIUsM5+TZDLE+VNqOcACP2pYRwhq5mGybXegLv3ZkzEOUvyUOJorEMfud NUFEI32UACLNRISUHf/RAtc5Of2s8mGp6lDwnGPWT2JEJfSaNFSS0Tq6oBCr23e0fMxMRBmCAS AvQ= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="121402132" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:33:40 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:33:40 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:33:30 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 21/30] media: atmel: atmel-isc: create callback for DPC submodule product specific Date: Thu, 1 Apr 2021 14:27:14 +0300 Message-ID: <20210401112723.189107-22-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Create a product specific callback for initializing the DPC submodule of the pipeline. For sama5d2 product, this module does not exist, thus this function is a noop. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 1 + drivers/media/platform/atmel/atmel-isc.h | 3 +++ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 6 ++++++ 3 files changed, 10 insertions(+) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 69952b6ac401..1f7116abc61a 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -651,6 +651,7 @@ static void isc_set_pipeline(struct isc_device *isc, u32 pipeline) regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES); regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES); + isc->config_dpc(isc); isc->config_csc(isc); isc->config_cbc(isc); isc->config_cc(isc); diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index eb549fadb1a8..d6cd85a4c3e9 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -221,6 +221,8 @@ struct isc_reg_offsets { * @max_width: maximum frame width, dependent on the internal RAM * @max_height: maximum frame height, dependent on the internal RAM * + * @config_dpc: pointer to a function that initializes product + * specific DPC module * @config_csc: pointer to a function that initializes product * specific CSC module * @config_cbc: pointer to a function that initializes product @@ -300,6 +302,7 @@ struct isc_device { u32 max_height; struct { + void (*config_dpc)(struct isc_device *isc); void (*config_csc)(struct isc_device *isc); void (*config_cbc)(struct isc_device *isc); void (*config_cc)(struct isc_device *isc); diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index a8375961f97d..ae906126ffb8 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -107,6 +107,11 @@ void isc_sama5d2_config_ctrls(struct isc_device *isc, v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 256); } +void isc_sama5d2_config_dpc(struct isc_device *isc) +{ + /* This module is not present on sama5d2 pipeline */ +} + /* Gamma table with gamma 1/2.2 */ const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { /* 0 --> gamma 1/1.8 */ @@ -252,6 +257,7 @@ static int atmel_isc_probe(struct platform_device *pdev) isc->max_width = ISC_SAMA5D2_MAX_SUPPORT_WIDTH; isc->max_height = ISC_SAMA5D2_MAX_SUPPORT_HEIGHT; + isc->config_dpc = isc_sama5d2_config_dpc; isc->config_csc = isc_sama5d2_config_csc; isc->config_cbc = isc_sama5d2_config_cbc; isc->config_cc = isc_sama5d2_config_cc; From patchwork Thu Apr 1 11:27:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12178941 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48704C43461 for ; Thu, 1 Apr 2021 18:06:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1A63D61130 for ; Thu, 1 Apr 2021 18:06:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237682AbhDASEI (ORCPT ); Thu, 1 Apr 2021 14:04:08 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:20061 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237541AbhDASAW (ORCPT ); Thu, 1 Apr 2021 14:00:22 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617300022; x=1648836022; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+X6BGvSt1VLnTLPppX+gBlHPzID6mcWeaE9aLHzxe58=; b=HT5NntrFMFmnE3iGDHIWHgLKEHCPKSb0glEC9ihejlbfIadNfsg5Bfdl 4/3ekt/jeGtzeIuaYIxeSK33Xr0TOT+YnL953Uh2+Oz5y9xXwzyATsM1h DNkMUkCF6jTJgaKtf9aDBJ4B8VpiZADsj0xiLg1hTGNGMzmx41fACBzAc /WEKFKrmfxf+MB1saAcOVBXK1lOHHIbQPwlDadbGtJTiLtTSLL8ZeKJ5c rsHsHz227/P6HMYVGEV1oZCt0o2v+69brtUUcIO6TLIxn+8kOQpNof1UC ZLmXSfCMDJ5THh69wBvOBMsvqUV2PyHxBiZ5iswL1xkTl0jJJ+ORPyfuV A==; IronPort-SDR: EuZxxln5XO2wuqNiPf7CLQvEz/L/qNTDs/EJImY6OLxguPYIqC0ZZaAgvEyYFTFkgES/7CwYr4 Y/gnfjhmazctFeei3THHdek6kR4xo1tHAjMbiskWwQraO2v/Q6aypBNrJC1u6XkRkxQRGWUrkU VFlYT2JMe/rl9FYLt4I/MHCQncPeF0ZgbIAoCSHNhN5O3h6VNxd+yUU7LbmPkmbKNY9VLU5H17 y8RO6B8ddE/lcfG5x0BX3Cj522X8VhI//278Nv9xsh+ow4RhhhQp1dtUAt3cmbdKBP1z9bJSbt z/I= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="109338789" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:33:57 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:33:56 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:33:41 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 22/30] media: atmel: atmel-isc: create callback for GAM submodule product specific Date: Thu, 1 Apr 2021 14:27:15 +0300 Message-ID: <20210401112723.189107-23-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Create a product specific callback for initializing the GAM submodule of the pipeline. For sama5d2 product, there is no special configuration at this moment, thus this function is a noop. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 1 + drivers/media/platform/atmel/atmel-isc.h | 3 +++ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 6 ++++++ 3 files changed, 10 insertions(+) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 1f7116abc61a..bd24e0c99613 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -655,6 +655,7 @@ static void isc_set_pipeline(struct isc_device *isc, u32 pipeline) isc->config_csc(isc); isc->config_cbc(isc); isc->config_cc(isc); + isc->config_gam(isc); } static int isc_update_profile(struct isc_device *isc) diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index d6cd85a4c3e9..1e6988f1876e 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -229,6 +229,8 @@ struct isc_reg_offsets { * specific CBC module * @config_cc: pointer to a function that initializes product * specific CC module + * @config_gam: pointer to a function that initializes product + * specific GAMMA module * @config_ctrls: pointer to a functoin that initializes product * specific v4l2 controls. * @@ -306,6 +308,7 @@ struct isc_device { void (*config_csc)(struct isc_device *isc); void (*config_cbc)(struct isc_device *isc); void (*config_cc)(struct isc_device *isc); + void (*config_gam)(struct isc_device *isc); void (*config_ctrls)(struct isc_device *isc, const struct v4l2_ctrl_ops *ops); diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index ae906126ffb8..f5863bf3ac32 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -112,6 +112,11 @@ void isc_sama5d2_config_dpc(struct isc_device *isc) /* This module is not present on sama5d2 pipeline */ } +void isc_sama5d2_config_gam(struct isc_device *isc) +{ + /* No specific gamma configuration */ +} + /* Gamma table with gamma 1/2.2 */ const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { /* 0 --> gamma 1/1.8 */ @@ -261,6 +266,7 @@ static int atmel_isc_probe(struct platform_device *pdev) isc->config_csc = isc_sama5d2_config_csc; isc->config_cbc = isc_sama5d2_config_cbc; isc->config_cc = isc_sama5d2_config_cc; + isc->config_gam = isc_sama5d2_config_gam; isc->config_ctrls = isc_sama5d2_config_ctrls; isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; From patchwork Thu Apr 1 11:27:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12178851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A028FC43619 for ; Thu, 1 Apr 2021 18:01:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7252B611C9 for ; Thu, 1 Apr 2021 18:01:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235226AbhDASBr (ORCPT ); Thu, 1 Apr 2021 14:01:47 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:34747 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236641AbhDAR6T (ORCPT ); Thu, 1 Apr 2021 13:58:19 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617299900; x=1648835900; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7gj/UFI0HQr5zvf4EEX4GJfFFABCl5ee36+3k1GuHRk=; b=dP/HdGwQrWTMjAn5DsHgGQ2QbAAhm4lGQ2wzbdUaHg6H+kZOo7RXw8da HxfE490kERRaSIvLbQHxSw5LNF2h9UgVHYANVPVkdt1Jem17wSAnkr0rD 3RCtLo2wE1HMHTMYkGD4jCxhbp8Q5eUQbyGvmJHOkWJVHJqoV6v42tT7C FRjUZOsvSdgi6FOL1zNCRS2fT2B+4vYlQS7Fp+DXBroe9i/LdPH6ndEmg qe+7nrIzhdYBu3L51WeKDGak2VYQMzm215Ha6NsQdmL/LbHjzKQE+q99Y xoHNy6K5Er+v30Rab7pykvsbBgv1gowS/c4swcLOuPQkbWONsHJVw1h3s Q==; IronPort-SDR: sdDDHs+sGnLl9wYfziaRgGmxdybaZV6o1KLlIExxXyM0CuwTahiNO2PrVMBdmm6Wqjqx1ShzIh MvS5+hgrmM8938f7M3WfMbYN5GyEioyMz2aPBhp5WX/4tWT5ZMIblLgAB7x7fTbDg45kc3tLw+ rj2ycGw8jdOa1UjGTDR7g3U4Kva0JtYeOTMdQFD0vBbVsOux+4ptpgkK0XCRZlKgmTIOfqDnRa g/HLf9NKF/hG09UxTVGp5BALDBgqhqEZSAqO52UPsiQWfzzDSvPIxQTmB0S1uSwwmK/aqQBrfq DSA= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="112132843" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:34:02 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:34:02 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:33:57 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 23/30] media: atmel: atmel-isc: create callback for RLP submodule product specific Date: Thu, 1 Apr 2021 14:27:16 +0300 Message-ID: <20210401112723.189107-24-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Create a product specific callback for initializing the RLP submodule of the pipeline Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 6 ++---- drivers/media/platform/atmel/atmel-isc.h | 3 +++ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 10 ++++++++++ 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index bd24e0c99613..8422df41f083 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -711,11 +711,10 @@ static void isc_set_histogram(struct isc_device *isc, bool enable) static int isc_configure(struct isc_device *isc) { struct regmap *regmap = isc->regmap; - u32 pfe_cfg0, rlp_mode, dcfg, mask, pipeline; + u32 pfe_cfg0, dcfg, mask, pipeline; struct isc_subdev_entity *subdev = isc->current_subdev; pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps; - rlp_mode = isc->config.rlp_cfg_mode; pipeline = isc->config.bits_pipeline; dcfg = isc->config.dcfg_imode | isc->dcfg; @@ -728,8 +727,7 @@ static int isc_configure(struct isc_device *isc) regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0); - regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, - ISC_RLP_CFG_MODE_MASK, rlp_mode); + isc->config_rlp(isc); regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg); diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index 1e6988f1876e..abeef7b2ab27 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -231,6 +231,8 @@ struct isc_reg_offsets { * specific CC module * @config_gam: pointer to a function that initializes product * specific GAMMA module + * @config_rlp: pointer to a function that initializes product + * specific RLP module * @config_ctrls: pointer to a functoin that initializes product * specific v4l2 controls. * @@ -309,6 +311,7 @@ struct isc_device { void (*config_cbc)(struct isc_device *isc); void (*config_cc)(struct isc_device *isc); void (*config_gam)(struct isc_device *isc); + void (*config_rlp)(struct isc_device *isc); void (*config_ctrls)(struct isc_device *isc, const struct v4l2_ctrl_ops *ops); diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index f5863bf3ac32..342259ad3690 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -117,6 +117,15 @@ void isc_sama5d2_config_gam(struct isc_device *isc) /* No specific gamma configuration */ } +void isc_sama5d2_config_rlp(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + u32 rlp_mode = isc->config.rlp_cfg_mode; + + regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, + ISC_RLP_CFG_MODE_MASK, rlp_mode); +} + /* Gamma table with gamma 1/2.2 */ const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { /* 0 --> gamma 1/1.8 */ @@ -267,6 +276,7 @@ static int atmel_isc_probe(struct platform_device *pdev) isc->config_cbc = isc_sama5d2_config_cbc; isc->config_cc = isc_sama5d2_config_cc; isc->config_gam = isc_sama5d2_config_gam; + isc->config_rlp = isc_sama5d2_config_rlp; isc->config_ctrls = isc_sama5d2_config_ctrls; isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; From patchwork Thu Apr 1 11:27:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12178739 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D39AC43460 for ; Thu, 1 Apr 2021 17:57:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6674360BD3 for ; Thu, 1 Apr 2021 17:57:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235862AbhDAR5e (ORCPT ); Thu, 1 Apr 2021 13:57:34 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:1272 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236272AbhDARyF (ORCPT ); Thu, 1 Apr 2021 13:54:05 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617299646; x=1648835646; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZtAKjGZKkNqMDffH/+/8loWem8Yys+5ZHDx/DISyOxs=; b=YlXKhGJneKAxXErQJ3D93CwwhC15rvf27OS+X//rWb3zLa5usIh7Ml3s AEDyw/vEv3KYzCxZZ5iKn2J5W1cFSUuTxrI6UU4oZqozEt5RNuQtgsYqz VOq+zbelfEAaZfKf3zS80oNQcGmNkUoO01DywCuhamDd0vGi0MNg2KcCT +grKNllSmvAVB5jeUUa+DyIddUNPiGlr/T7VcmKK+SCCn6nuODHkLclbe BXcZZwJ48ydzDrkFSYowdsh6deaSdperwbNqNTu1nItbvh8V9DBJ3E29w hHY5+2kbuBDNs0V401wPFsntjbXkax/aWzUXrB7Qpr72yZbe7Rojw8+eA Q==; IronPort-SDR: 8XKNofAwtQ4IrlouWTtlbY6QhC9ZScEu636EoitqI87wsp9Zcfe+X5fyt5zpOlMU/fVk1Hto51 /YUV1ptOlX1YPmUt7ewz8/kzU+Iy+E/kzqHgpxvbo4mpXD2ZZzFHL5fT1Xg1RB3upmHSTdS4Ps GwkZwFmpkVefU4H/GW1Py/MP3bs+wEpLMZ+7MQNqzB+iybnSespNclN1bwgTGHeKHgOvXalZgS trUWt3MWZiYuvY2oX43EE5+SiS97yqfYktY2DngaogqU5V2o0b0V/5hUxP4cwQLyEtvoCbgy/A 0j4= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="49671192" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:34:07 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:34:07 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:34:02 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 24/30] media: atmel: atmel-isc: move the formats list into product specific code Date: Thu, 1 Apr 2021 14:27:17 +0300 Message-ID: <20210401112723.189107-25-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The list of input and output formats has to be product specific. Move this list into the product specific code. Have pointers to these arrays inside the device struct. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 167 ++---------------- drivers/media/platform/atmel/atmel-isc.h | 12 +- .../media/platform/atmel/atmel-sama5d2-isc.c | 136 ++++++++++++++ 3 files changed, 165 insertions(+), 150 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 8422df41f083..6746c9060e3f 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -45,137 +45,6 @@ module_param(sensor_preferred, uint, 0644); MODULE_PARM_DESC(sensor_preferred, "Sensor is preferred to output the specified format (1-on 0-off), default 1"); -/* This is a list of the formats that the ISC can *output* */ -const struct isc_format controller_formats[] = { - { - .fourcc = V4L2_PIX_FMT_ARGB444, - }, - { - .fourcc = V4L2_PIX_FMT_ARGB555, - }, - { - .fourcc = V4L2_PIX_FMT_RGB565, - }, - { - .fourcc = V4L2_PIX_FMT_ABGR32, - }, - { - .fourcc = V4L2_PIX_FMT_XBGR32, - }, - { - .fourcc = V4L2_PIX_FMT_YUV420, - }, - { - .fourcc = V4L2_PIX_FMT_YUYV, - }, - { - .fourcc = V4L2_PIX_FMT_YUV422P, - }, - { - .fourcc = V4L2_PIX_FMT_GREY, - }, - { - .fourcc = V4L2_PIX_FMT_Y10, - }, -}; - -/* This is a list of formats that the ISC can receive as *input* */ -struct isc_format formats_list[] = { - { - .fourcc = V4L2_PIX_FMT_SBGGR8, - .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, - .cfa_baycfg = ISC_BAY_CFG_BGBG, - }, - { - .fourcc = V4L2_PIX_FMT_SGBRG8, - .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, - .cfa_baycfg = ISC_BAY_CFG_GBGB, - }, - { - .fourcc = V4L2_PIX_FMT_SGRBG8, - .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, - .cfa_baycfg = ISC_BAY_CFG_GRGR, - }, - { - .fourcc = V4L2_PIX_FMT_SRGGB8, - .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, - .cfa_baycfg = ISC_BAY_CFG_RGRG, - }, - { - .fourcc = V4L2_PIX_FMT_SBGGR10, - .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, - .cfa_baycfg = ISC_BAY_CFG_RGRG, - }, - { - .fourcc = V4L2_PIX_FMT_SGBRG10, - .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, - .cfa_baycfg = ISC_BAY_CFG_GBGB, - }, - { - .fourcc = V4L2_PIX_FMT_SGRBG10, - .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, - .cfa_baycfg = ISC_BAY_CFG_GRGR, - }, - { - .fourcc = V4L2_PIX_FMT_SRGGB10, - .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, - .cfa_baycfg = ISC_BAY_CFG_RGRG, - }, - { - .fourcc = V4L2_PIX_FMT_SBGGR12, - .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, - .cfa_baycfg = ISC_BAY_CFG_BGBG, - }, - { - .fourcc = V4L2_PIX_FMT_SGBRG12, - .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, - .cfa_baycfg = ISC_BAY_CFG_GBGB, - }, - { - .fourcc = V4L2_PIX_FMT_SGRBG12, - .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, - .cfa_baycfg = ISC_BAY_CFG_GRGR, - }, - { - .fourcc = V4L2_PIX_FMT_SRGGB12, - .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, - .cfa_baycfg = ISC_BAY_CFG_RGRG, - }, - { - .fourcc = V4L2_PIX_FMT_GREY, - .mbus_code = MEDIA_BUS_FMT_Y8_1X8, - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, - }, - { - .fourcc = V4L2_PIX_FMT_YUYV, - .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, - }, - { - .fourcc = V4L2_PIX_FMT_RGB565, - .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, - }, - { - .fourcc = V4L2_PIX_FMT_Y10, - .mbus_code = MEDIA_BUS_FMT_Y10_1X10, - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, - }, - -}; - #define ISC_IS_FORMAT_RAW(mbus_code) \ (((mbus_code) & 0xf000) == 0x3000) @@ -906,25 +775,26 @@ static int isc_querycap(struct file *file, void *priv, static int isc_enum_fmt_vid_cap(struct file *file, void *priv, struct v4l2_fmtdesc *f) { + struct isc_device *isc = video_drvdata(file); u32 index = f->index; u32 i, supported_index; - if (index < ARRAY_SIZE(controller_formats)) { - f->pixelformat = controller_formats[index].fourcc; + if (index < isc->controller_formats_size) { + f->pixelformat = isc->controller_formats[index].fourcc; return 0; } - index -= ARRAY_SIZE(controller_formats); + index -= isc->controller_formats_size; i = 0; supported_index = 0; - for (i = 0; i < ARRAY_SIZE(formats_list); i++) { - if (!ISC_IS_FORMAT_RAW(formats_list[i].mbus_code) || - !formats_list[i].sd_support) + for (i = 0; i < isc->formats_list_size; i++) { + if (!ISC_IS_FORMAT_RAW(isc->formats_list[i].mbus_code) || + !isc->formats_list[i].sd_support) continue; if (supported_index == index) { - f->pixelformat = formats_list[i].fourcc; + f->pixelformat = isc->formats_list[i].fourcc; return 0; } supported_index++; @@ -1465,8 +1335,8 @@ static int isc_enum_framesizes(struct file *file, void *fh, if (isc->user_formats[i]->fourcc == fsize->pixel_format) ret = 0; - for (i = 0; i < ARRAY_SIZE(controller_formats); i++) - if (controller_formats[i].fourcc == fsize->pixel_format) + for (i = 0; i < isc->controller_formats_size; i++) + if (isc->controller_formats[i].fourcc == fsize->pixel_format) ret = 0; if (ret) @@ -1502,8 +1372,8 @@ static int isc_enum_frameintervals(struct file *file, void *fh, if (isc->user_formats[i]->fourcc == fival->pixel_format) ret = 0; - for (i = 0; i < ARRAY_SIZE(controller_formats); i++) - if (controller_formats[i].fourcc == fival->pixel_format) + for (i = 0; i < isc->controller_formats_size; i++) + if (isc->controller_formats[i].fourcc == fival->pixel_format) ret = 0; if (ret) @@ -2111,12 +1981,13 @@ static void isc_async_unbind(struct v4l2_async_notifier *notifier, v4l2_ctrl_handler_free(&isc->ctrls.handler); } -static struct isc_format *find_format_by_code(unsigned int code, int *index) +static struct isc_format *find_format_by_code(struct isc_device *isc, + unsigned int code, int *index) { - struct isc_format *fmt = &formats_list[0]; + struct isc_format *fmt = &isc->formats_list[0]; unsigned int i; - for (i = 0; i < ARRAY_SIZE(formats_list); i++) { + for (i = 0; i < isc->formats_list_size; i++) { if (fmt->mbus_code == code) { *index = i; return fmt; @@ -2133,7 +2004,7 @@ static int isc_formats_init(struct isc_device *isc) struct isc_format *fmt; struct v4l2_subdev *subdev = isc->current_subdev->sd; unsigned int num_fmts, i, j; - u32 list_size = ARRAY_SIZE(formats_list); + u32 list_size = isc->formats_list_size; struct v4l2_subdev_mbus_code_enum mbus_code = { .which = V4L2_SUBDEV_FORMAT_ACTIVE, }; @@ -2143,7 +2014,7 @@ static int isc_formats_init(struct isc_device *isc) NULL, &mbus_code)) { mbus_code.index++; - fmt = find_format_by_code(mbus_code.code, &i); + fmt = find_format_by_code(isc, mbus_code.code, &i); if (!fmt) { v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n", mbus_code.code); @@ -2164,7 +2035,7 @@ static int isc_formats_init(struct isc_device *isc) if (!isc->user_formats) return -ENOMEM; - fmt = &formats_list[0]; + fmt = &isc->formats_list[0]; for (i = 0, j = 0; i < list_size; i++) { if (fmt->sd_support) isc->user_formats[j++] = fmt; diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index abeef7b2ab27..14e318a7373c 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -237,6 +237,12 @@ struct isc_reg_offsets { * specific v4l2 controls. * * @offsets: struct holding the product specific register offsets + * @controller_formats: pointer to the array of possible formats that the + * controller can output + * @formats_list: pointer to the array of possible formats that can + * be used as an input to the controller + * @controller_formats_size: size of controller_formats array + * @formats_list_size: size of formats_list array */ struct isc_device { struct regmap *regmap; @@ -318,10 +324,12 @@ struct isc_device { }; struct isc_reg_offsets offsets; + const struct isc_format *controller_formats; + struct isc_format *formats_list; + u32 controller_formats_size; + u32 formats_list_size; }; -extern struct isc_format formats_list[]; -extern const struct isc_format controller_formats[]; extern const struct regmap_config isc_regmap_config; extern const struct v4l2_async_notifier_operations isc_async_ops; diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index 342259ad3690..38b9667537a3 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -54,6 +54,137 @@ #define ISC_CLK_MAX_DIV 255 +/* This is a list of the formats that the ISC can *output* */ +const struct isc_format sama5d2_controller_formats[] = { + { + .fourcc = V4L2_PIX_FMT_ARGB444, + }, + { + .fourcc = V4L2_PIX_FMT_ARGB555, + }, + { + .fourcc = V4L2_PIX_FMT_RGB565, + }, + { + .fourcc = V4L2_PIX_FMT_ABGR32, + }, + { + .fourcc = V4L2_PIX_FMT_XBGR32, + }, + { + .fourcc = V4L2_PIX_FMT_YUV420, + }, + { + .fourcc = V4L2_PIX_FMT_YUYV, + }, + { + .fourcc = V4L2_PIX_FMT_YUV422P, + }, + { + .fourcc = V4L2_PIX_FMT_GREY, + }, + { + .fourcc = V4L2_PIX_FMT_Y10, + }, +}; + +/* This is a list of formats that the ISC can receive as *input* */ +struct isc_format sama5d2_formats_list[] = { + { + .fourcc = V4L2_PIX_FMT_SBGGR8, + .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + .cfa_baycfg = ISC_BAY_CFG_BGBG, + }, + { + .fourcc = V4L2_PIX_FMT_SGBRG8, + .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + .cfa_baycfg = ISC_BAY_CFG_GBGB, + }, + { + .fourcc = V4L2_PIX_FMT_SGRBG8, + .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + .cfa_baycfg = ISC_BAY_CFG_GRGR, + }, + { + .fourcc = V4L2_PIX_FMT_SRGGB8, + .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + .cfa_baycfg = ISC_BAY_CFG_RGRG, + }, + { + .fourcc = V4L2_PIX_FMT_SBGGR10, + .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + .cfa_baycfg = ISC_BAY_CFG_RGRG, + }, + { + .fourcc = V4L2_PIX_FMT_SGBRG10, + .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + .cfa_baycfg = ISC_BAY_CFG_GBGB, + }, + { + .fourcc = V4L2_PIX_FMT_SGRBG10, + .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + .cfa_baycfg = ISC_BAY_CFG_GRGR, + }, + { + .fourcc = V4L2_PIX_FMT_SRGGB10, + .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + .cfa_baycfg = ISC_BAY_CFG_RGRG, + }, + { + .fourcc = V4L2_PIX_FMT_SBGGR12, + .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, + .cfa_baycfg = ISC_BAY_CFG_BGBG, + }, + { + .fourcc = V4L2_PIX_FMT_SGBRG12, + .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, + .cfa_baycfg = ISC_BAY_CFG_GBGB, + }, + { + .fourcc = V4L2_PIX_FMT_SGRBG12, + .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, + .cfa_baycfg = ISC_BAY_CFG_GRGR, + }, + { + .fourcc = V4L2_PIX_FMT_SRGGB12, + .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, + .cfa_baycfg = ISC_BAY_CFG_RGRG, + }, + { + .fourcc = V4L2_PIX_FMT_GREY, + .mbus_code = MEDIA_BUS_FMT_Y8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + }, + { + .fourcc = V4L2_PIX_FMT_YUYV, + .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + }, + { + .fourcc = V4L2_PIX_FMT_RGB565, + .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + }, + { + .fourcc = V4L2_PIX_FMT_Y10, + .mbus_code = MEDIA_BUS_FMT_Y10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + }, + +}; + void isc_sama5d2_config_csc(struct isc_device *isc) { struct regmap *regmap = isc->regmap; @@ -289,6 +420,11 @@ static int atmel_isc_probe(struct platform_device *pdev) isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET; isc->offsets.his_entry = ISC_SAMA5D2_HIS_ENTRY_OFFSET; + isc->controller_formats = sama5d2_controller_formats; + isc->controller_formats_size = ARRAY_SIZE(sama5d2_controller_formats); + isc->formats_list = sama5d2_formats_list; + isc->formats_list_size = ARRAY_SIZE(sama5d2_formats_list); + /* sama5d2-isc - 8 bits per beat */ isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8; From patchwork Thu Apr 1 11:27:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12178835 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A57EC433B4 for ; Thu, 1 Apr 2021 17:58:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3CD9F61285 for ; Thu, 1 Apr 2021 17:58:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236846AbhDAR6v (ORCPT ); Thu, 1 Apr 2021 13:58:51 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:1272 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235559AbhDAR4G (ORCPT ); Thu, 1 Apr 2021 13:56:06 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617299766; x=1648835766; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iBZmWbvl9sEPKdC1MPZcesj17YCVzTSDdzfTNXGF2es=; b=WHeEvvz4qCoSe4qwmpgV7NrNmmhsetOJQRi0mExfCRrHK/zRiR/EuKgH LkY5Ai837VwaTGSOQ45nBFS5iGSlb87vRW57//7WCZAAd8Ckjabc0obca LV7uk83mfBo+RcLxKXGqNKXq0UTWPA3bmWzuBpzN4l1uaQCpIj1MetpAP VjYd0/nxexevaa6i3BoL3gdwwJdPSSxdsGLeA105Hm4LV+EVQ2dgjYTaa rU8FLdfET04INx9UUtvFMJxqrj4C6DD9zAtUiJprPOxLy68zztxOSqdvZ 4z0rLM+9sgLwiJz+89xclIig5kDFolHhG78I6PTpPie0i7W/MAOVoFtcV A==; IronPort-SDR: g659neIUvBhz+PbQbMZwMZKEB0VldDI+uRSO+QBp0qtiDJqf5N5obBa9tKR2/s01pOInUTy6RU FIC/EQ6p4H1NajwFu1LSc5G6BeQGxtQy7WBkAxOv1u0atx/kfeJFeYlGspObllzCgd4NWL2K0L MJ1PD4d9yQMcOETUCSa3ekgy3x6DSllHuxUOCoQmk3lemL1tmmZOA4NXuzSJMzcgZUH75/dCgy 1Nz3deluBU6OMK4cQY/4m6MlGjq0scJ0p3W8ZtHypghqoiLmjxZIQk91jAdevYcW6d9zNcKGhp 5io= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="49671216" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:34:15 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:34:15 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:34:14 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 25/30] media: atmel: atmel-isc: create an adapt pipeline callback for product specific Date: Thu, 1 Apr 2021 14:27:18 +0300 Message-ID: <20210401112723.189107-26-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Once the pipeline is set in the base code, create a callback that will adapt the ISC pipeline to each product. Create the adapt_pipeline callback that will be used in this fashion. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 4 ++++ drivers/media/platform/atmel/atmel-isc.h | 5 +++++ drivers/media/platform/atmel/atmel-sama5d2-isc.c | 11 +++++++++++ 3 files changed, 20 insertions(+) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index 6746c9060e3f..a3c299068bd5 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -1047,6 +1047,10 @@ static int isc_try_configure_pipeline(struct isc_device *isc) default: isc->try_config.bits_pipeline = 0x0; } + + /* Tune the pipeline to product specific */ + isc->adapt_pipeline(isc); + return 0; } diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h index 14e318a7373c..19cc60dfcbe0 100644 --- a/drivers/media/platform/atmel/atmel-isc.h +++ b/drivers/media/platform/atmel/atmel-isc.h @@ -236,6 +236,9 @@ struct isc_reg_offsets { * @config_ctrls: pointer to a functoin that initializes product * specific v4l2 controls. * + * @adapt_pipeline: pointer to a function that adapts the pipeline bits + * to the product specific pipeline + * * @offsets: struct holding the product specific register offsets * @controller_formats: pointer to the array of possible formats that the * controller can output @@ -321,6 +324,8 @@ struct isc_device { void (*config_ctrls)(struct isc_device *isc, const struct v4l2_ctrl_ops *ops); + + void (*adapt_pipeline)(struct isc_device *isc); }; struct isc_reg_offsets offsets; diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index 38b9667537a3..c5687fb5b022 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -54,6 +54,10 @@ #define ISC_CLK_MAX_DIV 255 +#define ISC_SAMA5D2_PIPELINE \ + (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ + CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) + /* This is a list of the formats that the ISC can *output* */ const struct isc_format sama5d2_controller_formats[] = { { @@ -257,6 +261,11 @@ void isc_sama5d2_config_rlp(struct isc_device *isc) ISC_RLP_CFG_MODE_MASK, rlp_mode); } +void isc_sama5d2_adapt_pipeline(struct isc_device *isc) +{ + isc->try_config.bits_pipeline &= ISC_SAMA5D2_PIPELINE; +} + /* Gamma table with gamma 1/2.2 */ const u32 isc_sama5d2_gamma_table[][GAMMA_ENTRIES] = { /* 0 --> gamma 1/1.8 */ @@ -410,6 +419,8 @@ static int atmel_isc_probe(struct platform_device *pdev) isc->config_rlp = isc_sama5d2_config_rlp; isc->config_ctrls = isc_sama5d2_config_ctrls; + isc->adapt_pipeline = isc_sama5d2_adapt_pipeline; + isc->offsets.csc = ISC_SAMA5D2_CSC_OFFSET; isc->offsets.cbc = ISC_SAMA5D2_CBC_OFFSET; isc->offsets.sub422 = ISC_SAMA5D2_SUB422_OFFSET; From patchwork Thu Apr 1 11:27:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12178935 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D17AC433ED for ; Thu, 1 Apr 2021 18:04:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0B3FF610C7 for ; Thu, 1 Apr 2021 18:04:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237008AbhDASEB (ORCPT ); Thu, 1 Apr 2021 14:04:01 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:62179 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237536AbhDASAW (ORCPT ); Thu, 1 Apr 2021 14:00:22 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617300022; x=1648836022; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JB3dr1U/DWt6qBqOVHSGXJCImGHTndPyXb9YXu64Mas=; b=g3yN7yvGzDGSmfJXoZCnWPf6LMgPeYXsMQZVJ1x+uTkBdgQqbVlxWT6q vL7KYnlHDS4kVY9RU/s/7qnHcXRZHlCKdfiu2PNM7VJ0Dx5jtzaYHBfOk q+a8sZBLSM5HjsH6sogp2G6kUGCiSOsTscJRp5Y/0WbVapI9t0jOaMlJM BWyUW8hVX+7uv3d/rlcilpcarI/o+oUdn0khBb6saG38aXNuMskqDCAu5 13/c4+hO4IGU5e+OHm/WH+hKnzk0OpuiFcfciOXQpf1QT1hElRzgkhKHF bW2+MTJnV2IQUyxS+ZqzVRVF+oRFQJaCpeeAnM2SmC2NYdLCY4Z1AFHfO w==; IronPort-SDR: Oei+FeSuQcleZaNtuSm08xLLIxw7ewRIe8osxtJtc4svklrg/d9AIynFsQ1GZR2FPEpEPJndWl rsS21FKOaHa0IXPqHACuiiLeI7bYcXB2KvjohX6pNuv70LWzJyOnklns92dKDHtukWKabNwhIl 3AhuWeurBsfVjnJe0aVrHh3SMn3Ul1x3wl55PodALTGQxRl+DJexknOzzOPZ/LZgrCuIzGYQsa EoFbJDO40sUmOlS7JMk4O9PEuDWmRm8if2SmV5FjsFkoGNQ7TNd8FVOzF0I48HjndjkRma7i3F Q48= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="112132857" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:34:17 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:34:17 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:34:15 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 26/30] media: atmel: atmel-isc-regs: add additional fields for sama7g5 type pipeline Date: Thu, 1 Apr 2021 14:27:19 +0300 Message-ID: <20210401112723.189107-27-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add additional fields for registers present in sama7g5 type pipeline. Extend register masks for additional bits in sama7g5 type pipeline registers. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-regs.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h index 457eed74cda9..5f99bf7717c1 100644 --- a/drivers/media/platform/atmel/atmel-isc-regs.h +++ b/drivers/media/platform/atmel/atmel-isc-regs.h @@ -289,8 +289,18 @@ #define ISC_RLP_CFG_MODE_ARGB32 0xa #define ISC_RLP_CFG_MODE_YYCC 0xb #define ISC_RLP_CFG_MODE_YYCC_LIMITED 0xc +#define ISC_RLP_CFG_MODE_YCYC 0xd #define ISC_RLP_CFG_MODE_MASK GENMASK(3, 0) +#define ISC_RLP_CFG_LSH BIT(5) + +#define ISC_RLP_CFG_YMODE_YUYV (3 << 6) +#define ISC_RLP_CFG_YMODE_YVYU (2 << 6) +#define ISC_RLP_CFG_YMODE_VYUY (0 << 6) +#define ISC_RLP_CFG_YMODE_UYVY (1 << 6) + +#define ISC_RLP_CFG_YMODE_MASK GENMASK(7, 6) + /* Offset for HIS register specific to sama5d2 product */ #define ISC_SAMA5D2_HIS_OFFSET 0 /* Histogram Control Register */ @@ -332,13 +342,15 @@ #define ISC_DCFG_YMBSIZE_BEATS4 (0x1 << 4) #define ISC_DCFG_YMBSIZE_BEATS8 (0x2 << 4) #define ISC_DCFG_YMBSIZE_BEATS16 (0x3 << 4) -#define ISC_DCFG_YMBSIZE_MASK GENMASK(5, 4) +#define ISC_DCFG_YMBSIZE_BEATS32 (0x4 << 4) +#define ISC_DCFG_YMBSIZE_MASK GENMASK(6, 4) #define ISC_DCFG_CMBSIZE_SINGLE (0x0 << 8) #define ISC_DCFG_CMBSIZE_BEATS4 (0x1 << 8) #define ISC_DCFG_CMBSIZE_BEATS8 (0x2 << 8) #define ISC_DCFG_CMBSIZE_BEATS16 (0x3 << 8) -#define ISC_DCFG_CMBSIZE_MASK GENMASK(9, 8) +#define ISC_DCFG_CMBSIZE_BEATS32 (0x4 << 8) +#define ISC_DCFG_CMBSIZE_MASK GENMASK(10, 8) /* DMA Control Register */ #define ISC_DCTRL 0x000003e4 From patchwork Thu Apr 1 11:27:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12179061 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F943C433ED for ; Thu, 1 Apr 2021 18:08:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 66B2861139 for ; Thu, 1 Apr 2021 18:08:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237746AbhDASIr (ORCPT ); Thu, 1 Apr 2021 14:08:47 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:62179 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236384AbhDASCY (ORCPT ); Thu, 1 Apr 2021 14:02:24 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617300145; x=1648836145; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=L0ubezju1a2v2fOHoFbJx+Tkrd4cQqmjDLOQsJU/n+8=; b=EHqBa21dRwD4c9wF5hbM8/ote9XQNeyL6w3C4pzOF9KrC+xsQxMElcHg O1OK3rdD/qKHUSNUGJxN65zUOcT8NIDhgyy7kB/nF7qnrNlMq8iiiaVb3 y8KdJ3vBxPBCXxaIRK78T7QWTJUSrdk4Faz278DlYH3WIO0ok1wX03NB0 fCxbcjNInF8QZG35GeJOOrYvCZypVA4unIajcRe8uuTKcQbV0DvnD2aRb Qi4J2htx07HIPNwTTfTzrZM0ArMeTu4lAAT5weklMVQeNxdmJiNfjSMtZ fgR/bwVfqAp+rU0QvOnCBe6qrfdluJA3tMAQDTN/zOeRyYTkIYL3PoBoB A==; IronPort-SDR: S/pkNKb7HxGslXFGHwGadqVL0WtxVhne5KeCkMiRQ5DOWM5o26A84staS93b5TEqt+y7V+cOUs BN8nauKhC61MeR5u1I7iVCo4WjGfhNzlZMl9j02/+Jr3XvaOO8x2LvfHlOuJ0GOVcQMzNGkV4P iS7OeSaKtvGuKzoo5wQNrwEWNYfk9xvBx7lrxM67s4sXZ4IwgtdtKmBIM0/BOb2/i5dmKlziGL 5pswdaeN3cewfy6YLykQe13RITW0PKh0B+jzZjSs08B/wuHbtiui2KoIIf/sVi2mZd1ulhF87K 0Mw= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="112132861" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:34:19 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:34:18 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:34:17 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 27/30] media: atmel: atmel-isc-base: add support for more formats and additional pipeline modules Date: Thu, 1 Apr 2021 14:27:20 +0300 Message-ID: <20210401112723.189107-28-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add support for additional formats supported by newer pipelines, and for additional pipeline modules. Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-isc-base.c | 48 +++++++++++++++---- 1 file changed, 38 insertions(+), 10 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index a3c299068bd5..f30493a1dccd 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -843,6 +843,8 @@ static int isc_try_validate_formats(struct isc_device *isc) case V4L2_PIX_FMT_YUV420: case V4L2_PIX_FMT_YUV422P: case V4L2_PIX_FMT_YUYV: + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_VYUY: ret = 0; yuv = true; break; @@ -857,6 +859,7 @@ static int isc_try_validate_formats(struct isc_device *isc) break; case V4L2_PIX_FMT_GREY: case V4L2_PIX_FMT_Y10: + case V4L2_PIX_FMT_Y16: ret = 0; grey = true; break; @@ -887,6 +890,8 @@ static int isc_try_validate_formats(struct isc_device *isc) */ static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump) { + isc->try_config.rlp_cfg_mode = 0; + switch (isc->try_config.fourcc) { case V4L2_PIX_FMT_SBGGR8: case V4L2_PIX_FMT_SGBRG8: @@ -953,7 +958,19 @@ static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump) isc->try_config.bpp = 16; break; case V4L2_PIX_FMT_YUYV: - isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC; + isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 16; + break; + case V4L2_PIX_FMT_UYVY: + isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY; + isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; + isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; + isc->try_config.bpp = 16; + break; + case V4L2_PIX_FMT_VYUY: + isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY; isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32; isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; isc->try_config.bpp = 16; @@ -964,8 +981,11 @@ static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump) isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; isc->try_config.bpp = 8; break; + case V4L2_PIX_FMT_Y16: + isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH; + fallthrough; case V4L2_PIX_FMT_Y10: - isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10; + isc->try_config.rlp_cfg_mode |= ISC_RLP_CFG_MODE_DATY10; isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16; isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED; isc->try_config.bpp = 16; @@ -999,7 +1019,8 @@ static int isc_try_configure_pipeline(struct isc_device *isc) /* if sensor format is RAW, we convert inside ISC */ if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { isc->try_config.bits_pipeline = CFA_ENABLE | - WB_ENABLE | GAM_ENABLES; + WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE | + CC_ENABLE; } else { isc->try_config.bits_pipeline = 0x0; } @@ -1008,8 +1029,9 @@ static int isc_try_configure_pipeline(struct isc_device *isc) /* if sensor format is RAW, we convert inside ISC */ if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { isc->try_config.bits_pipeline = CFA_ENABLE | - CSC_ENABLE | WB_ENABLE | GAM_ENABLES | - SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE; + CSC_ENABLE | GAM_ENABLES | WB_ENABLE | + SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE | + DPC_BLCENABLE; } else { isc->try_config.bits_pipeline = 0x0; } @@ -1019,33 +1041,39 @@ static int isc_try_configure_pipeline(struct isc_device *isc) if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { isc->try_config.bits_pipeline = CFA_ENABLE | CSC_ENABLE | WB_ENABLE | GAM_ENABLES | - SUB422_ENABLE | CBC_ENABLE; + SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; } else { isc->try_config.bits_pipeline = 0x0; } break; case V4L2_PIX_FMT_YUYV: + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_VYUY: /* if sensor format is RAW, we convert inside ISC */ if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { isc->try_config.bits_pipeline = CFA_ENABLE | CSC_ENABLE | WB_ENABLE | GAM_ENABLES | - SUB422_ENABLE | CBC_ENABLE; + SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE; } else { isc->try_config.bits_pipeline = 0x0; } break; case V4L2_PIX_FMT_GREY: - if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { + case V4L2_PIX_FMT_Y16: /* if sensor format is RAW, we convert inside ISC */ + if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) { isc->try_config.bits_pipeline = CFA_ENABLE | CSC_ENABLE | WB_ENABLE | GAM_ENABLES | - CBC_ENABLE; + CBC_ENABLE | DPC_BLCENABLE; } else { isc->try_config.bits_pipeline = 0x0; } break; default: - isc->try_config.bits_pipeline = 0x0; + if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) + isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE; + else + isc->try_config.bits_pipeline = 0x0; } /* Tune the pipeline to product specific */ From patchwork Thu Apr 1 11:27:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12178833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87942C43462 for ; Thu, 1 Apr 2021 17:58:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5118A611BD for ; Thu, 1 Apr 2021 17:58:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235493AbhDAR6w (ORCPT ); Thu, 1 Apr 2021 13:58:52 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:64963 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236938AbhDAR4G (ORCPT ); Thu, 1 Apr 2021 13:56:06 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617299766; x=1648835766; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=84VHzcsJ4TUt5svlhMIaet84Qj9F0UavrZGGg9pJD1A=; b=0j1dj9xNvkOHC/EWsMlbFG4IX6n97+mBWebteuUiVo4ceNiFBwPZmQoY voN/76WViYMF0zNpAcSkixcgMSXzjsQBSHSKpcfHueurhW1s8yQDAX4Cp 6eey1mhpBKvs8BjpRFhzt2VZ/rmfe7Lsy9oPOnmiCztTSEyQ6iltM4shT WfwG816HMKr1vQ7GUzj8KEZJFC7Uos2GcYgCgSslQWgEg6ZpMk4mDexTe GxdtDd9f6NWROeUfmpJSeR8xumGlPVIQIoeNhHIG54lVB5ZqwWJzkRtkA lQK7abOxduSbQFq8V/9yPuJxJQ2PIkFcGtiZEVlwUYOe+4DuCHKNed49l g==; IronPort-SDR: hGF7t1o5vyrXOWv44bSddjFkWj2ABF4+p/s/aYFlZ56JJPAMxefxIKKhZLk9ORuQgdL9C52mqV HtoKmm+JT9FJnkUTyvsNnNg2jTlfAY2CzBFm37fX9L4MA7zY4MIIYCmj0keoYDxMK7DEFIdMjV K5IAcLU5fP/c25EyYTQKcpJxXL7Tc2Ku4OTOM/WS1QBbOA5/v6kTr0O38TQyp4AjciqeiaCKyv /dngYVp4TRnu44mdmU3urmIwx/UfPb2vrsui1/bALACeMzp7kCA/FBAz8Q5QOXOLawjuReG+xA WEo= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="49671239" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:34:32 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:34:32 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:34:19 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 28/30] dt-bindings: media: atmel: add microchip-xisc binding Date: Thu, 1 Apr 2021 14:27:21 +0300 Message-ID: <20210401112723.189107-29-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add bindings for the microchip xisc, a driver based on atmel-isc. It shares common code with atmel-isc, but the xisc is the next generation ISC which is present on sama7g5 product. It has an enhanced pipeline, additional modules, formats, and it supports not only parallel sensors, but also serial sensors, by connecting to a demux endpoint present on sama7g5. One of the key points for creating a new binding is the clocking scheme, as atmel-isc requires 3 mandatory clocks, the microchip-xisc requires a single input clock. Signed-off-by: Eugen Hristev --- Hello Rob, all, I did not convert this yet to yaml because I would like first your feedback if the binding is good. If it's fine I will convert both this new binding and the old atmel-isc to yaml. Thanks for your feedback, Eugen .../bindings/media/microchip-xisc.txt | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/microchip-xisc.txt diff --git a/Documentation/devicetree/bindings/media/microchip-xisc.txt b/Documentation/devicetree/bindings/media/microchip-xisc.txt new file mode 100644 index 000000000000..080a357ed84d --- /dev/null +++ b/Documentation/devicetree/bindings/media/microchip-xisc.txt @@ -0,0 +1,64 @@ +Microchip eXtended Image Sensor Controller (XISC) +---------------------------------------------- + +Required properties for XISC: +- compatible + Must be "microchip,sama7g5-xisc". +- reg + Physical base address and length of the registers set for the device. +- interrupts + Should contain IRQ line for the XISC. +- clocks + List of clock specifiers, corresponding to entries in + the clock-names property; + Please refer to clock-bindings.txt. +- clock-names + Required elements: "hclock". + This is the clock that clocks the sensor controller, and is usually + fed from the clock tree. It is used for the internal controller logic. +- #clock-cells + Should be 0. +- clock-output-names + Should be "isc-mck". +- pinctrl-names, pinctrl-0 + Please refer to pinctrl-bindings.txt. + +Optional properties for XISC: +- microchip,mipi-mode; + As the XISC is usually connected to a demux/bridge, the XISC receives + the same type of input, however, it should be aware of the type of + signals received. The mipi-mode enables different internal handling + of the data and clock lines. + +XISC supports a single port node with internal parallel bus. +It should contain one 'port' child node with child 'endpoint' node. +Please refer to the bindings defined in +Documentation/devicetree/bindings/media/video-interfaces.txt. + +This endpoint has to be connected to a bridge that acts as a demux from either +a serial interface or acts as a simple direct bridge to a parallel sensor. + +Example: +xisc: xisc@e1408000 { + compatible = "microchip,sama7g5-isc"; + reg = <0xe1408000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; + clock-names = "hclock"; + #clock-cells = <0>; + clock-output-names = "isc-mck"; + microchip,mipi-mode; + + port@1 { + reg = <1>; + xisc_in: endpoint { + bus-width = <12>; + hsync-active = <1>; + vsync-active = <1>; + remote-endpoint = <&csi2dc_out>; + }; + }; +}; + From patchwork Thu Apr 1 11:27:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12178845 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11730C4360C for ; Thu, 1 Apr 2021 18:01:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CF69C611BD for ; Thu, 1 Apr 2021 18:01:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235378AbhDASBn (ORCPT ); Thu, 1 Apr 2021 14:01:43 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:1272 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235352AbhDAR6J (ORCPT ); Thu, 1 Apr 2021 13:58:09 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617299889; x=1648835889; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4b/HIspMjMe9EaUqpqUCEm+c5tUwE7L+PCPp/jb42Rw=; b=FWDnVqZv39cgRL9B896gzrEVw3TlkH0dHgBcQn9VP0Rw3tt++UD0OgHu 3cTOPbpa6F8cKbe006x4Xu5KDLrPwRD0vqPcbT4G7RrMcmj9RqLxNFWsg w3ANIXMUlpSY8l1hkrWUxCcuzrip3JTHicDyQg1ouBx1MLB46L7IdnEwS fY6PQUPQxpI34ivQWVDXdWrsSEn5wkIYBReFf/c5S4glZrWafgkrZ4Cpg rQVqDW/eafdD+HcHrnfr5OSLvyzSupIcxY6iWzi6Lu+2x1fb3H6NKLsTL 4gztNgWlJGAqhRqsAsM1v2q0Q78MRUjk8BA7mzTcUZMtedCIfJ/OEFVNt A==; IronPort-SDR: 3hCNdH3UU/E4IwG4WTukniJTubDVLPWK8Y5dpaofTQCKmjrMxrZZumx4MhleX2RAGJgxPOxMXt c4tbdNtPxgBm/r2zICOwMzjrq/f2sxxEIkaebdkMv2g3SXoMmRQQZcz/yekRp1F+jhRtRb+ie2 fafjANLPapeqVlQsedeihruhm3QJL+mRh80pOMC5mavH6nXAe7e8lL1pQLDOHjziuA1HXtVk17 URBYIN0M2JVM+GXAbBb/lOjmkF7siw4b1AV6CAsW6e8/+tj2+dzy7R3cbQvdXegyNNXQi5ghRc Xn8= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="49671243" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:34:34 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:34:34 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:34:33 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 29/30] media: atmel: atmel-isc-sama5d2: remove duplicate define Date: Thu, 1 Apr 2021 14:27:22 +0300 Message-ID: <20210401112723.189107-30-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Remove a duplicate definition of clock max divider Signed-off-by: Eugen Hristev --- drivers/media/platform/atmel/atmel-sama5d2-isc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c index c5687fb5b022..b34c3ab0b888 100644 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c @@ -52,8 +52,6 @@ #define ISC_SAMA5D2_MAX_SUPPORT_WIDTH 2592 #define ISC_SAMA5D2_MAX_SUPPORT_HEIGHT 1944 -#define ISC_CLK_MAX_DIV 255 - #define ISC_SAMA5D2_PIPELINE \ (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) From patchwork Thu Apr 1 11:27:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 12179059 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DC18C43460 for ; Thu, 1 Apr 2021 18:08:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2FF3860FE6 for ; Thu, 1 Apr 2021 18:08:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237713AbhDASIn (ORCPT ); Thu, 1 Apr 2021 14:08:43 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:19744 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236392AbhDASCY (ORCPT ); Thu, 1 Apr 2021 14:02:24 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1617300144; x=1648836144; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=igf0kkYoOVqDqg+RAXk2vjuo15nQpvq1z9zl7asnf8w=; b=XqSRdAqoTAg59nQ68nX42QYlQspRx0/VjpHO1FdR2x3aB78Vicd8wtSI 6P9aQgzia7Z5eZqEv51cXHExFdft6n+p/AHAFFjtNwT3OT9cK5vxpHH9J G08Fclq9g2TrWAMJ5S1dUr7goUKHpuxxa5Jo2jDLJolVDNNcwynkqETd7 hCD6+qSxo1M9LWOZspjTQDAeMLT6g4vMMZTy+Dip1OqNInrJzsvVqSyEb TprfYjcTZ1gyiF5nKQndCSVZSucO6dWb9mI/IkEbQma1maCpkXFAsWWIp LoquhLHvy3GPqk3nqU2qIyL9ozRdPFePGtp+o2IOqfpCpeLITe1V/RelW Q==; IronPort-SDR: TTLdfeRJND+SRpz0fczywQZjmZ9RD88QL5IDZqyNfkbytlXLm2LlCOiIlM5zrr/HtLXaLQGeYG OAs4WeRTBPbwtRbXrDU9ydfHXgkfAFHnEKEVXR+jC5HcEr2LhK8rrZlrY9CqfQ4sezTlUy6pYc eD5RpZdmcKOYhVvamICXjfHKeUDiWZrXdOAuS9knGjlvx92/SATv1St93pZo+i7A8GEjZulqnn PqzRIILSSIc7UYX9VeEjofo6VwWUEv1roc0ap4oXINf1uZcewwG3msPUcqps2JtCaN9UZDmWqy dfA= X-IronPort-AV: E=Sophos;i="5.81,296,1610434800"; d="scan'208";a="109338826" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 01 Apr 2021 04:34:36 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 1 Apr 2021 04:34:36 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 1 Apr 2021 04:34:35 -0700 From: Eugen Hristev To: , CC: , , Eugen Hristev Subject: [PATCH 30/30] media: atmel: atmel-isc: add microchip-xisc driver Date: Thu, 1 Apr 2021 14:27:23 +0300 Message-ID: <20210401112723.189107-31-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210401112723.189107-1-eugen.hristev@microchip.com> References: <20210401112723.189107-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add driver for the extended variant of the isc, the microchip XISC present on sama7g5 product. Signed-off-by: Eugen Hristev Reported-by: kernel test robot --- drivers/media/platform/Makefile | 1 + drivers/media/platform/atmel/Kconfig | 11 + drivers/media/platform/atmel/Makefile | 2 + drivers/media/platform/atmel/atmel-isc-base.c | 2 +- drivers/media/platform/atmel/atmel-isc-regs.h | 26 + .../media/platform/atmel/atmel-sama7g5-isc.c | 644 ++++++++++++++++++ 6 files changed, 685 insertions(+), 1 deletion(-) create mode 100644 drivers/media/platform/atmel/atmel-sama7g5-isc.c diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile index eedc14aafb32..73ce083c2fc6 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile @@ -67,6 +67,7 @@ obj-$(CONFIG_VIDEO_RCAR_VIN) += rcar-vin/ obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel/ obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel/ +obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel/ obj-$(CONFIG_VIDEO_STM32_DCMI) += stm32/ diff --git a/drivers/media/platform/atmel/Kconfig b/drivers/media/platform/atmel/Kconfig index 1850fe7f9360..99b51213f871 100644 --- a/drivers/media/platform/atmel/Kconfig +++ b/drivers/media/platform/atmel/Kconfig @@ -12,6 +12,17 @@ config VIDEO_ATMEL_ISC This module makes the ATMEL Image Sensor Controller available as a v4l2 device. +config VIDEO_ATMEL_XISC + tristate "ATMEL eXtended Image Sensor Controller (XISC) support" + depends on VIDEO_V4L2 && COMMON_CLK && VIDEO_V4L2_SUBDEV_API + depends on ARCH_AT91 || COMPILE_TEST + select VIDEOBUF2_DMA_CONTIG + select REGMAP_MMIO + select V4L2_FWNODE + help + This module makes the ATMEL eXtended Image Sensor Controller + available as a v4l2 device. + config VIDEO_ATMEL_ISI tristate "ATMEL Image Sensor Interface (ISI) support" depends on VIDEO_V4L2 && OF diff --git a/drivers/media/platform/atmel/Makefile b/drivers/media/platform/atmel/Makefile index 2dba38994a70..c5c01556c653 100644 --- a/drivers/media/platform/atmel/Makefile +++ b/drivers/media/platform/atmel/Makefile @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only atmel-isc-objs = atmel-sama5d2-isc.o atmel-isc-base.o +atmel-xisc-objs = atmel-sama7g5-isc.o atmel-isc-base.o obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o obj-$(CONFIG_VIDEO_ATMEL_ISC) += atmel-isc.o +obj-$(CONFIG_VIDEO_ATMEL_XISC) += atmel-xisc.o diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c index f30493a1dccd..d6409406ce2f 100644 --- a/drivers/media/platform/atmel/atmel-isc-base.c +++ b/drivers/media/platform/atmel/atmel-isc-base.c @@ -592,7 +592,7 @@ static int isc_configure(struct isc_device *isc) mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW | ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW | ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC | - ISC_PFE_CFG0_CCIR656; + ISC_PFE_CFG0_CCIR656 | ISC_PFE_CFG0_MIPI; regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0); diff --git a/drivers/media/platform/atmel/atmel-isc-regs.h b/drivers/media/platform/atmel/atmel-isc-regs.h index 5f99bf7717c1..d06b72228d4f 100644 --- a/drivers/media/platform/atmel/atmel-isc-regs.h +++ b/drivers/media/platform/atmel/atmel-isc-regs.h @@ -26,6 +26,7 @@ #define ISC_PFE_CFG0_PPOL_LOW BIT(2) #define ISC_PFE_CFG0_CCIR656 BIT(9) #define ISC_PFE_CFG0_CCIR_CRC BIT(10) +#define ISC_PFE_CFG0_MIPI BIT(14) #define ISC_PFE_CFG0_MODE_PROGRESSIVE (0x0 << 4) #define ISC_PFE_CFG0_MODE_MASK GENMASK(6, 4) @@ -184,6 +185,8 @@ /* ISC Gamma Correction Control Register */ #define ISC_GAM_CTRL 0x00000094 +#define ISC_GAM_CTRL_BIPART BIT(4) + /* ISC_Gamma Correction Blue Entry Register */ #define ISC_GAM_BENTRY 0x00000098 @@ -222,6 +225,8 @@ /* Offset for CSC register specific to sama5d2 product */ #define ISC_SAMA5D2_CSC_OFFSET 0 +/* Offset for CSC register specific to sama7g5 product */ +#define ISC_SAMA7G5_CSC_OFFSET 0x11c /* Color Space Conversion Control Register */ #define ISC_CSC_CTRL 0x00000398 @@ -246,6 +251,8 @@ /* Offset for CBC register specific to sama5d2 product */ #define ISC_SAMA5D2_CBC_OFFSET 0 +/* Offset for CBC register specific to sama7g5 product */ +#define ISC_SAMA7G5_CBC_OFFSET 0x11c /* Contrast And Brightness Control Register */ #define ISC_CBC_CTRL 0x000003b4 @@ -261,18 +268,30 @@ #define ISC_CBC_CONTRAST 0x000003c0 #define ISC_CBC_CONTRAST_MASK GENMASK(11, 0) +/* Hue Register */ +#define ISC_CBCHS_HUE 0x4e0 +/* Saturation Register */ +#define ISC_CBCHS_SAT 0x4e4 + /* Offset for SUB422 register specific to sama5d2 product */ #define ISC_SAMA5D2_SUB422_OFFSET 0 +/* Offset for SUB422 register specific to sama7g5 product */ +#define ISC_SAMA7G5_SUB422_OFFSET 0x124 + /* Subsampling 4:4:4 to 4:2:2 Control Register */ #define ISC_SUB422_CTRL 0x000003c4 /* Offset for SUB420 register specific to sama5d2 product */ #define ISC_SAMA5D2_SUB420_OFFSET 0 +/* Offset for SUB420 register specific to sama7g5 product */ +#define ISC_SAMA7G5_SUB420_OFFSET 0x124 /* Subsampling 4:2:2 to 4:2:0 Control Register */ #define ISC_SUB420_CTRL 0x000003cc /* Offset for RLP register specific to sama5d2 product */ #define ISC_SAMA5D2_RLP_OFFSET 0 +/* Offset for RLP register specific to sama7g5 product */ +#define ISC_SAMA7G5_RLP_OFFSET 0x124 /* Rounding, Limiting and Packing Configuration Register */ #define ISC_RLP_CFG 0x000003d0 @@ -303,6 +322,8 @@ /* Offset for HIS register specific to sama5d2 product */ #define ISC_SAMA5D2_HIS_OFFSET 0 +/* Offset for HIS register specific to sama7g5 product */ +#define ISC_SAMA7G5_HIS_OFFSET 0x124 /* Histogram Control Register */ #define ISC_HIS_CTRL 0x000003d4 @@ -326,6 +347,8 @@ /* Offset for DMA register specific to sama5d2 product */ #define ISC_SAMA5D2_DMA_OFFSET 0 +/* Offset for DMA register specific to sama7g5 product */ +#define ISC_SAMA7G5_DMA_OFFSET 0x13c /* DMA Configuration Register */ #define ISC_DCFG 0x000003e0 @@ -376,11 +399,14 @@ /* Offset for version register specific to sama5d2 product */ #define ISC_SAMA5D2_VERSION_OFFSET 0 +#define ISC_SAMA7G5_VERSION_OFFSET 0x13c /* Version Register */ #define ISC_VERSION 0x0000040c /* Offset for version register specific to sama5d2 product */ #define ISC_SAMA5D2_HIS_ENTRY_OFFSET 0 +/* Offset for version register specific to sama7g5 product */ +#define ISC_SAMA7G5_HIS_ENTRY_OFFSET 0x14c /* Histogram Entry */ #define ISC_HIS_ENTRY 0x00000410 diff --git a/drivers/media/platform/atmel/atmel-sama7g5-isc.c b/drivers/media/platform/atmel/atmel-sama7g5-isc.c new file mode 100644 index 000000000000..0bc914615e76 --- /dev/null +++ b/drivers/media/platform/atmel/atmel-sama7g5-isc.c @@ -0,0 +1,644 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Microchip eXtended Image Sensor Controller (XISC) driver + * + * Copyright (C) 2019-2021 Microchip Technology, Inc. and its subsidiaries + * + * Author: Eugen Hristev + * + * Sensor-->PFE-->DPC-->WB-->CFA-->CC-->GAM-->VHXS-->CSC-->CBHS-->SUB-->RLP-->DMA-->HIS + * + * ISC video pipeline integrates the following submodules: + * PFE: Parallel Front End to sample the camera sensor input stream + * DPC: Defective Pixel Correction with black offset correction, green disparity + * correction and defective pixel correction (3 modules total) + * WB: Programmable white balance in the Bayer domain + * CFA: Color filter array interpolation module + * CC: Programmable color correction + * GAM: Gamma correction + *VHXS: Vertical and Horizontal Scaler + * CSC: Programmable color space conversion + *CBHS: Contrast Brightness Hue and Saturation control + * SUB: This module performs YCbCr444 to YCbCr420 chrominance subsampling + * RLP: This module performs rounding, range limiting + * and packing of the incoming data + * DMA: This module performs DMA master accesses to write frames to external RAM + * HIS: Histogram module performs statistic counters on the frames + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "atmel-isc-regs.h" +#include "atmel-isc.h" + +#define ISC_SAMA7G5_MAX_SUPPORT_WIDTH 3264 +#define ISC_SAMA7G5_MAX_SUPPORT_HEIGHT 2464 + +#define ISC_SAMA7G5_PIPELINE \ + (WB_ENABLE | CFA_ENABLE | CC_ENABLE | GAM_ENABLES | CSC_ENABLE | \ + CBC_ENABLE | SUB422_ENABLE | SUB420_ENABLE) + +/* This is a list of the formats that the ISC can *output* */ +const struct isc_format sama7g5_controller_formats[] = { + { + .fourcc = V4L2_PIX_FMT_ARGB444, + }, + { + .fourcc = V4L2_PIX_FMT_ARGB555, + }, + { + .fourcc = V4L2_PIX_FMT_RGB565, + }, + { + .fourcc = V4L2_PIX_FMT_ABGR32, + }, + { + .fourcc = V4L2_PIX_FMT_XBGR32, + }, + { + .fourcc = V4L2_PIX_FMT_YUV420, + }, + { + .fourcc = V4L2_PIX_FMT_UYVY, + }, + { + .fourcc = V4L2_PIX_FMT_VYUY, + }, + { + .fourcc = V4L2_PIX_FMT_YUYV, + }, + { + .fourcc = V4L2_PIX_FMT_YUV422P, + }, + { + .fourcc = V4L2_PIX_FMT_GREY, + }, + { + .fourcc = V4L2_PIX_FMT_Y10, + }, + { + .fourcc = V4L2_PIX_FMT_Y16, + }, +}; + +/* This is a list of formats that the ISC can receive as *input* */ +struct isc_format sama7g5_formats_list[] = { + { + .fourcc = V4L2_PIX_FMT_SBGGR8, + .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + .cfa_baycfg = ISC_BAY_CFG_BGBG, + }, + { + .fourcc = V4L2_PIX_FMT_SGBRG8, + .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + .cfa_baycfg = ISC_BAY_CFG_GBGB, + }, + { + .fourcc = V4L2_PIX_FMT_SGRBG8, + .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + .cfa_baycfg = ISC_BAY_CFG_GRGR, + }, + { + .fourcc = V4L2_PIX_FMT_SRGGB8, + .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + .cfa_baycfg = ISC_BAY_CFG_RGRG, + }, + { + .fourcc = V4L2_PIX_FMT_SBGGR10, + .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + .cfa_baycfg = ISC_BAY_CFG_RGRG, + }, + { + .fourcc = V4L2_PIX_FMT_SGBRG10, + .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + .cfa_baycfg = ISC_BAY_CFG_GBGB, + }, + { + .fourcc = V4L2_PIX_FMT_SGRBG10, + .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + .cfa_baycfg = ISC_BAY_CFG_GRGR, + }, + { + .fourcc = V4L2_PIX_FMT_SRGGB10, + .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + .cfa_baycfg = ISC_BAY_CFG_RGRG, + }, + { + .fourcc = V4L2_PIX_FMT_SBGGR12, + .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, + .cfa_baycfg = ISC_BAY_CFG_BGBG, + }, + { + .fourcc = V4L2_PIX_FMT_SGBRG12, + .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, + .cfa_baycfg = ISC_BAY_CFG_GBGB, + }, + { + .fourcc = V4L2_PIX_FMT_SGRBG12, + .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, + .cfa_baycfg = ISC_BAY_CFG_GRGR, + }, + { + .fourcc = V4L2_PIX_FMT_SRGGB12, + .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE, + .cfa_baycfg = ISC_BAY_CFG_RGRG, + }, + { + .fourcc = V4L2_PIX_FMT_GREY, + .mbus_code = MEDIA_BUS_FMT_Y8_1X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + }, + { + .fourcc = V4L2_PIX_FMT_YUYV, + .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + }, + { + .fourcc = V4L2_PIX_FMT_UYVY, + .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + }, + { + .fourcc = V4L2_PIX_FMT_RGB565, + .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT, + }, + { + .fourcc = V4L2_PIX_FMT_Y10, + .mbus_code = MEDIA_BUS_FMT_Y10_1X10, + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN, + }, + +}; + +void isc_sama7g5_config_csc(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + + /* Convert RGB to YUV */ + regmap_write(regmap, ISC_CSC_YR_YG + isc->offsets.csc, + 0x42 | (0x81 << 16)); + regmap_write(regmap, ISC_CSC_YB_OY + isc->offsets.csc, + 0x19 | (0x10 << 16)); + regmap_write(regmap, ISC_CSC_CBR_CBG + isc->offsets.csc, + 0xFDA | (0xFB6 << 16)); + regmap_write(regmap, ISC_CSC_CBB_OCB + isc->offsets.csc, + 0x70 | (0x80 << 16)); + regmap_write(regmap, ISC_CSC_CRR_CRG + isc->offsets.csc, + 0x70 | (0xFA2 << 16)); + regmap_write(regmap, ISC_CSC_CRB_OCR + isc->offsets.csc, + 0xFEE | (0x80 << 16)); +} + +void isc_sama7g5_config_cbc(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + + /* Configure what is set via v4l2 ctrls */ + regmap_write(regmap, ISC_CBC_BRIGHT + isc->offsets.cbc, isc->ctrls.brightness); + regmap_write(regmap, ISC_CBC_CONTRAST + isc->offsets.cbc, isc->ctrls.contrast); + /* Configure Hue and Saturation as neutral midpoint */ + regmap_write(regmap, ISC_CBCHS_HUE, 0); + regmap_write(regmap, ISC_CBCHS_SAT, (1 << 4)); +} + +void isc_sama7g5_config_cc(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + + /* Configure each register at the neutral fixed point 1.0 or 0.0 */ + regmap_write(regmap, ISC_CC_RR_RG, (1 << 8)); + regmap_write(regmap, ISC_CC_RB_OR, 0); + regmap_write(regmap, ISC_CC_GR_GG, (1 << 8) << 16); + regmap_write(regmap, ISC_CC_GB_OG, 0); + regmap_write(regmap, ISC_CC_BR_BG, 0); + regmap_write(regmap, ISC_CC_BB_OB, (1 << 8)); +} + +void isc_sama7g5_config_ctrls(struct isc_device *isc, + const struct v4l2_ctrl_ops *ops) +{ + struct isc_ctrls *ctrls = &isc->ctrls; + struct v4l2_ctrl_handler *hdl = &ctrls->handler; + + ctrls->contrast = 16; + + v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -2048, 2047, 1, 16); +} + +void isc_sama7g5_config_dpc(struct isc_device *isc) +{ + u32 bay_cfg = isc->config.sd_format->cfa_baycfg; + struct regmap *regmap = isc->regmap; + + regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BLOFF_MASK, + (64 << ISC_DPC_CFG_BLOFF_SHIFT)); + regmap_update_bits(regmap, ISC_DPC_CFG, ISC_DPC_CFG_BAYCFG_MASK, + (bay_cfg << ISC_DPC_CFG_BAYCFG_SHIFT)); +} + +void isc_sama7g5_config_gam(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + + regmap_update_bits(regmap, ISC_GAM_CTRL, ISC_GAM_CTRL_BIPART, + ISC_GAM_CTRL_BIPART); +} + +void isc_sama7g5_config_rlp(struct isc_device *isc) +{ + struct regmap *regmap = isc->regmap; + u32 rlp_mode = isc->config.rlp_cfg_mode; + + regmap_update_bits(regmap, ISC_RLP_CFG + isc->offsets.rlp, + ISC_RLP_CFG_MODE_MASK | ISC_RLP_CFG_LSH | + ISC_RLP_CFG_YMODE_MASK, rlp_mode); +} + +void isc_sama7g5_adapt_pipeline(struct isc_device *isc) +{ + isc->try_config.bits_pipeline &= ISC_SAMA7G5_PIPELINE; +} + +/* Gamma table with gamma 1/2.2 */ +const u32 isc_sama7g5_gamma_table[][GAMMA_ENTRIES] = { + /* index 0 --> gamma bipartite */ + { + 0x980, 0x4c0320, 0x650260, 0x7801e0, 0x8701a0, 0x940180, + 0xa00160, 0xab0120, 0xb40120, 0xbd0120, 0xc60100, 0xce0100, + 0xd600e0, 0xdd00e0, 0xe400e0, 0xeb00c0, 0xf100c0, 0xf700c0, + 0xfd00c0, 0x10300a0, 0x10800c0, 0x10e00a0, 0x11300a0, 0x11800a0, + 0x11d00a0, 0x12200a0, 0x12700a0, 0x12c0080, 0x13000a0, 0x1350080, + 0x13900a0, 0x13e0080, 0x1420076, 0x17d0062, 0x1ae0054, 0x1d8004a, + 0x1fd0044, 0x21f003e, 0x23e003a, 0x25b0036, 0x2760032, 0x28f0030, + 0x2a7002e, 0x2be002c, 0x2d4002c, 0x2ea0028, 0x2fe0028, 0x3120026, + 0x3250024, 0x3370024, 0x3490022, 0x35a0022, 0x36b0020, 0x37b0020, + 0x38b0020, 0x39b001e, 0x3aa001e, 0x3b9001c, 0x3c7001c, 0x3d5001c, + 0x3e3001c, 0x3f1001c, 0x3ff001a, 0x40c001a }, +}; + +static int xisc_parse_dt(struct device *dev, struct isc_device *isc) +{ + struct device_node *np = dev->of_node; + struct device_node *epn = NULL, *rem; + struct isc_subdev_entity *subdev_entity; + unsigned int flags; + int ret; + bool mipi_mode; + + INIT_LIST_HEAD(&isc->subdev_entities); + + mipi_mode = of_property_read_bool(np, "microchip,mipi-mode"); + + while (1) { + struct v4l2_fwnode_endpoint v4l2_epn = { .bus_type = 0 }; + + epn = of_graph_get_next_endpoint(np, epn); + if (!epn) + return 0; + + rem = of_graph_get_remote_port_parent(epn); + if (!rem) { + dev_notice(dev, "Remote device at %pOF not found\n", + epn); + continue; + } + + ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(epn), + &v4l2_epn); + if (ret) { + of_node_put(rem); + ret = -EINVAL; + dev_err(dev, "Could not parse the endpoint\n"); + break; + } + + subdev_entity = devm_kzalloc(dev, sizeof(*subdev_entity), + GFP_KERNEL); + if (!subdev_entity) { + of_node_put(rem); + ret = -ENOMEM; + break; + } + + /* asd will be freed by the subsystem once it's added to the + * notifier list + */ + subdev_entity->asd = kzalloc(sizeof(*subdev_entity->asd), + GFP_KERNEL); + if (!subdev_entity->asd) { + of_node_put(rem); + ret = -ENOMEM; + break; + } + + flags = v4l2_epn.bus.parallel.flags; + + if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) + subdev_entity->pfe_cfg0 = ISC_PFE_CFG0_HPOL_LOW; + + if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) + subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_VPOL_LOW; + + if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) + subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_PPOL_LOW; + + if (v4l2_epn.bus_type == V4L2_MBUS_BT656) + subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_CCIR_CRC | + ISC_PFE_CFG0_CCIR656; + + if (mipi_mode) + subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_MIPI; + + subdev_entity->asd->match_type = V4L2_ASYNC_MATCH_FWNODE; + subdev_entity->asd->match.fwnode = of_fwnode_handle(rem); + list_add_tail(&subdev_entity->list, &isc->subdev_entities); + } + + of_node_put(epn); + return ret; +} + +static int microchip_xisc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct isc_device *isc; + struct resource *res; + void __iomem *io_base; + struct isc_subdev_entity *subdev_entity; + int irq; + int ret; + u32 ver; + + isc = devm_kzalloc(dev, sizeof(*isc), GFP_KERNEL); + if (!isc) + return -ENOMEM; + + platform_set_drvdata(pdev, isc); + isc->dev = dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + io_base = devm_ioremap_resource(dev, res); + if (IS_ERR(io_base)) + return PTR_ERR(io_base); + + isc->regmap = devm_regmap_init_mmio(dev, io_base, &isc_regmap_config); + if (IS_ERR(isc->regmap)) { + ret = PTR_ERR(isc->regmap); + dev_err(dev, "failed to init register map: %d\n", ret); + return ret; + } + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret = devm_request_irq(dev, irq, isc_interrupt, 0, + "microchip-sama7g5-xisc", isc); + if (ret < 0) { + dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n", + irq, ret); + return ret; + } + + isc->gamma_table = isc_sama7g5_gamma_table; + isc->gamma_max = 0; + + isc->max_width = ISC_SAMA7G5_MAX_SUPPORT_WIDTH; + isc->max_height = ISC_SAMA7G5_MAX_SUPPORT_HEIGHT; + + isc->config_dpc = isc_sama7g5_config_dpc; + isc->config_csc = isc_sama7g5_config_csc; + isc->config_cbc = isc_sama7g5_config_cbc; + isc->config_cc = isc_sama7g5_config_cc; + isc->config_gam = isc_sama7g5_config_gam; + isc->config_rlp = isc_sama7g5_config_rlp; + isc->config_ctrls = isc_sama7g5_config_ctrls; + + isc->adapt_pipeline = isc_sama7g5_adapt_pipeline; + + isc->offsets.csc = ISC_SAMA7G5_CSC_OFFSET; + isc->offsets.cbc = ISC_SAMA7G5_CBC_OFFSET; + isc->offsets.sub422 = ISC_SAMA7G5_SUB422_OFFSET; + isc->offsets.sub420 = ISC_SAMA7G5_SUB420_OFFSET; + isc->offsets.rlp = ISC_SAMA7G5_RLP_OFFSET; + isc->offsets.his = ISC_SAMA7G5_HIS_OFFSET; + isc->offsets.dma = ISC_SAMA7G5_DMA_OFFSET; + isc->offsets.version = ISC_SAMA7G5_VERSION_OFFSET; + isc->offsets.his_entry = ISC_SAMA7G5_HIS_ENTRY_OFFSET; + + isc->controller_formats = sama7g5_controller_formats; + isc->controller_formats_size = ARRAY_SIZE(sama7g5_controller_formats); + isc->formats_list = sama7g5_formats_list; + isc->formats_list_size = ARRAY_SIZE(sama7g5_formats_list); + + /* sama7g5-isc RAM access port is full AXI4 - 32 bits per beat */ + isc->dcfg = ISC_DCFG_YMBSIZE_BEATS32 | ISC_DCFG_CMBSIZE_BEATS32; + + ret = isc_pipeline_init(isc); + if (ret) + return ret; + + isc->hclock = devm_clk_get(dev, "hclock"); + if (IS_ERR(isc->hclock)) { + ret = PTR_ERR(isc->hclock); + dev_err(dev, "failed to get hclock: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(isc->hclock); + if (ret) { + dev_err(dev, "failed to enable hclock: %d\n", ret); + return ret; + } + + ret = isc_clk_init(isc); + if (ret) { + dev_err(dev, "failed to init isc clock: %d\n", ret); + goto unprepare_hclk; + } + + isc->ispck = isc->isc_clks[ISC_ISPCK].clk; + + ret = clk_prepare_enable(isc->ispck); + if (ret) { + dev_err(dev, "failed to enable ispck: %d\n", ret); + goto unprepare_hclk; + } + + /* ispck should be greater or equal to hclock */ + ret = clk_set_rate(isc->ispck, clk_get_rate(isc->hclock)); + if (ret) { + dev_err(dev, "failed to set ispck rate: %d\n", ret); + goto unprepare_clk; + } + + ret = v4l2_device_register(dev, &isc->v4l2_dev); + if (ret) { + dev_err(dev, "unable to register v4l2 device.\n"); + goto unprepare_clk; + } + + ret = xisc_parse_dt(dev, isc); + if (ret) { + dev_err(dev, "fail to parse device tree\n"); + goto unregister_v4l2_device; + } + + if (list_empty(&isc->subdev_entities)) { + dev_err(dev, "no subdev found\n"); + ret = -ENODEV; + goto unregister_v4l2_device; + } + + list_for_each_entry(subdev_entity, &isc->subdev_entities, list) { + v4l2_async_notifier_init(&subdev_entity->notifier); + + ret = v4l2_async_notifier_add_subdev(&subdev_entity->notifier, + subdev_entity->asd); + if (ret) { + fwnode_handle_put(subdev_entity->asd->match.fwnode); + goto cleanup_subdev; + } + + subdev_entity->notifier.ops = &isc_async_ops; + + ret = v4l2_async_notifier_register(&isc->v4l2_dev, + &subdev_entity->notifier); + if (ret) { + dev_err(dev, "fail to register async notifier\n"); + goto cleanup_subdev; + } + + if (video_is_registered(&isc->video_dev)) + break; + } + + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + pm_request_idle(dev); + + regmap_read(isc->regmap, ISC_VERSION + isc->offsets.version, &ver); + dev_info(dev, "Microchip XISC version %x\n", ver); + + return 0; + +cleanup_subdev: + isc_subdev_cleanup(isc); + +unregister_v4l2_device: + v4l2_device_unregister(&isc->v4l2_dev); + +unprepare_clk: + clk_disable_unprepare(isc->ispck); +unprepare_hclk: + clk_disable_unprepare(isc->hclock); + + isc_clk_cleanup(isc); + + return ret; +} + +static int microchip_xisc_remove(struct platform_device *pdev) +{ + struct isc_device *isc = platform_get_drvdata(pdev); + + pm_runtime_disable(&pdev->dev); + + isc_subdev_cleanup(isc); + + v4l2_device_unregister(&isc->v4l2_dev); + + clk_disable_unprepare(isc->ispck); + clk_disable_unprepare(isc->hclock); + + isc_clk_cleanup(isc); + + return 0; +} + +static int __maybe_unused xisc_runtime_suspend(struct device *dev) +{ + struct isc_device *isc = dev_get_drvdata(dev); + + clk_disable_unprepare(isc->ispck); + clk_disable_unprepare(isc->hclock); + + return 0; +} + +static int __maybe_unused xisc_runtime_resume(struct device *dev) +{ + struct isc_device *isc = dev_get_drvdata(dev); + int ret; + + ret = clk_prepare_enable(isc->hclock); + if (ret) + return ret; + + ret = clk_prepare_enable(isc->ispck); + if (ret) + clk_disable_unprepare(isc->hclock); + + return ret; +} + +static const struct dev_pm_ops microchip_xisc_dev_pm_ops = { + SET_RUNTIME_PM_OPS(xisc_runtime_suspend, xisc_runtime_resume, NULL) +}; + +static const struct of_device_id microchip_xisc_of_match[] = { + { .compatible = "microchip,sama7g5-isc" }, + { } +}; +MODULE_DEVICE_TABLE(of, microchip_xisc_of_match); + +static struct platform_driver microchip_xisc_driver = { + .probe = microchip_xisc_probe, + .remove = microchip_xisc_remove, + .driver = { + .name = "microchip-sama7g5-xisc", + .pm = µchip_xisc_dev_pm_ops, + .of_match_table = of_match_ptr(microchip_xisc_of_match), + }, +}; + +module_platform_driver(microchip_xisc_driver); + +MODULE_AUTHOR("Eugen Hristev "); +MODULE_DESCRIPTION("The V4L2 driver for Microchip-XISC"); +MODULE_LICENSE("GPL v2"); +MODULE_SUPPORTED_DEVICE("video");