From patchwork Fri Apr 2 03:56:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 12180293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72320C433ED for ; Fri, 2 Apr 2021 03:56:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 39D12610E7 for ; Fri, 2 Apr 2021 03:56:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233863AbhDBD4N (ORCPT ); Thu, 1 Apr 2021 23:56:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233841AbhDBD4N (ORCPT ); Thu, 1 Apr 2021 23:56:13 -0400 Received: from mail-pg1-x52c.google.com (mail-pg1-x52c.google.com [IPv6:2607:f8b0:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 420AFC0613E6 for ; Thu, 1 Apr 2021 20:56:13 -0700 (PDT) Received: by mail-pg1-x52c.google.com with SMTP id y32so2831475pga.11 for ; Thu, 01 Apr 2021 20:56:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iB9SooeXb8aToQh6AowZmjkOEn+DBwCWyr7GlC/6EWI=; b=cKmDZO+u7GCe0yd64RSuCnAZwpInO3JEx86HCovfkz4oAkJ5kbDx6FMCsGcIhtZrtF STG+3oduJAAav78IMRfBsI8WE9es3vI3eHXl+91Y74zEL7VYBC/XyGX+D2PIkzp9CDeu XnS2HOWNRytTBOOGd2tOBRwQHbljpHnA9B9SdEQZY+tn6wIlvxtBJyi/4PQM2acVrIuc XRGeo7Ym6NA2b5+nFqIpm6Wl8cRoDGXccMLmnbL2u8tYOAQel7WP5jBdcfgCyZ+OGo+w nXdSfftIyP0WrccBIwCYAzcZqP2xElCUcY2Z2Au0tHQW5piFPywPju/lea1QdRR9fu7e YqoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iB9SooeXb8aToQh6AowZmjkOEn+DBwCWyr7GlC/6EWI=; b=F3LIx2nVOay2wTtTStSajYaHA+CfEPo0CNkDtA+3g3t4tOt56E0Eaq+P6pDAlIohlm aenc6LUqrhJd+5YSaxCgOGwZ27Vq+fY5KJBpOvLvoEnxrVgYsQpboPbW2BvmcQ9SkRbH 7Y/7Iqa0WWnqS/vbx50roKgd7/6LaoAjykinZ1pie2LaSy0qJb44ucaf8jLpYnnEDnWL cLDwEivW3f/PefT4hO0n3N37b0TLGRsInS+yqgVFTHh6oMbyFZrehdLMCsHJoHPFiCiR dB79e3TF6/Sp7wYJvcp4gm48WDmmDXv9n2iN/dMW0qVbMc4+2E/hhsn2pgpv9Cse6DBd 5vbA== X-Gm-Message-State: AOAM531I9BIHZd30zk13JJPNTWS8SczhTlNFVuoLoV+oANYYYv68eEzE E1bRLf83H7G7aDuWyjaL9Hl2dw== X-Google-Smtp-Source: ABdhPJyt6wA15AntzKhNCSCuYVREINHKVKOH4FBYIcW6a9EZ8fEDHIW8eBa5tXP60ZQ50rgbUpy0ZA== X-Received: by 2002:a63:5807:: with SMTP id m7mr10211892pgb.73.1617335772757; Thu, 01 Apr 2021 20:56:12 -0700 (PDT) Received: from localhost.localdomain (80.251.214.228.16clouds.com. [80.251.214.228]) by smtp.gmail.com with ESMTPSA id 81sm6875972pfu.164.2021.04.01.20.56.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Apr 2021 20:56:12 -0700 (PDT) From: Shawn Guo To: Will Deacon Cc: Robin Murphy , Bjorn Andersson , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Shawn Guo Subject: [PATCH v2 1/3] ACPI/IORT: Consolidate use of SMMU device platdata Date: Fri, 2 Apr 2021 11:56:00 +0800 Message-Id: <20210402035602.9484-2-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210402035602.9484-1-shawn.guo@linaro.org> References: <20210402035602.9484-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Currently the platdata is being used in different way by SMMU and PMCG device. The former uses it for acpi_iort_node pointer passing, while the later uses it for model identifier. As it's been seen that the model identifier is useful for SMMU devices as well, let's consolidate the platdata use to get it accommodate both acpi_iort_node pointer and model identifier, so that all IORT devices (SMMU, SMMUv3 and PMCG) pass platdata in a consistent manner. With this change, model identifier is not specific to PMCG, so IORT_SMMU_V3_PMCG_GENERIC gets renamed to IORT_SMMU_GENERIC. While at it, the spaces used in model defines are converted to tabs. Signed-off-by: Shawn Guo --- drivers/acpi/arm64/iort.c | 31 ++++++++------------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 6 +++- drivers/iommu/arm/arm-smmu/arm-smmu.c | 9 ++++-- drivers/perf/arm_smmuv3_pmu.c | 8 ++++-- include/linux/acpi_iort.h | 11 ++++++-- 5 files changed, 36 insertions(+), 29 deletions(-) diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index 2494138a6905..e2a96d2d399a 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -1463,25 +1463,28 @@ static void __init arm_smmu_v3_pmcg_init_resources(struct resource *res, ACPI_EDGE_SENSITIVE, &res[2]); } -static struct acpi_platform_list pmcg_plat_info[] __initdata = { +static struct acpi_platform_list iort_plat_info[] __initdata = { /* HiSilicon Hip08 Platform */ {"HISI ", "HIP08 ", 0, ACPI_SIG_IORT, greater_than_or_equal, "Erratum #162001800", IORT_SMMU_V3_PMCG_HISI_HIP08}, { } }; -static int __init arm_smmu_v3_pmcg_add_platdata(struct platform_device *pdev) +static int __init iort_smmu_add_platdata(struct platform_device *pdev, + struct acpi_iort_node *node) { - u32 model; + struct iort_smmu_pdata pdata; int idx; - idx = acpi_match_platform_list(pmcg_plat_info); + pdata.node = node; + + idx = acpi_match_platform_list(iort_plat_info); if (idx >= 0) - model = pmcg_plat_info[idx].data; + pdata.model = iort_plat_info[idx].data; else - model = IORT_SMMU_V3_PMCG_GENERIC; + pdata.model = IORT_SMMU_GENERIC; - return platform_device_add_data(pdev, &model, sizeof(model)); + return platform_device_add_data(pdev, &pdata, sizeof(pdata)); } struct iort_dev_config { @@ -1494,7 +1497,6 @@ struct iort_dev_config { struct acpi_iort_node *node); int (*dev_set_proximity)(struct device *dev, struct acpi_iort_node *node); - int (*dev_add_platdata)(struct platform_device *pdev); }; static const struct iort_dev_config iort_arm_smmu_v3_cfg __initconst = { @@ -1516,7 +1518,6 @@ static const struct iort_dev_config iort_arm_smmu_v3_pmcg_cfg __initconst = { .name = "arm-smmu-v3-pmcg", .dev_count_resources = arm_smmu_v3_pmcg_count_resources, .dev_init_resources = arm_smmu_v3_pmcg_init_resources, - .dev_add_platdata = arm_smmu_v3_pmcg_add_platdata, }; static __init const struct iort_dev_config *iort_get_dev_cfg( @@ -1579,17 +1580,7 @@ static int __init iort_add_platform_device(struct acpi_iort_node *node, if (ret) goto dev_put; - /* - * Platform devices based on PMCG nodes uses platform_data to - * pass the hardware model info to the driver. For others, add - * a copy of IORT node pointer to platform_data to be used to - * retrieve IORT data information. - */ - if (ops->dev_add_platdata) - ret = ops->dev_add_platdata(pdev); - else - ret = platform_device_add_data(pdev, &node, sizeof(node)); - + ret = iort_smmu_add_platdata(pdev, node); if (ret) goto dev_put; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 8ca7415d785d..91c9a74d8ac6 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3397,9 +3397,13 @@ static int arm_smmu_device_acpi_probe(struct platform_device *pdev, { struct acpi_iort_smmu_v3 *iort_smmu; struct device *dev = smmu->dev; + struct iort_smmu_pdata *pdata = dev_get_platdata(dev); struct acpi_iort_node *node; - node = *(struct acpi_iort_node **)dev_get_platdata(dev); + if (pdata == NULL) + return -ENODEV; + + node = pdata->node; /* Retrieve SMMUv3 specific data */ iort_smmu = (struct acpi_iort_smmu_v3 *)node->node_data; diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index d8c6bfde6a61..d53ab3927a30 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1991,11 +1991,16 @@ static int arm_smmu_device_acpi_probe(struct platform_device *pdev, struct arm_smmu_device *smmu) { struct device *dev = smmu->dev; - struct acpi_iort_node *node = - *(struct acpi_iort_node **)dev_get_platdata(dev); + struct iort_smmu_pdata *pdata = dev_get_platdata(dev); + struct acpi_iort_node *node; struct acpi_iort_smmu *iort_smmu; int ret; + if (pdata == NULL) + return -ENODEV; + + node = pdata->node; + /* Retrieve SMMU1/2 specific data */ iort_smmu = (struct acpi_iort_smmu *)node->node_data; diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c index 74474bb322c3..77fcf5e7413a 100644 --- a/drivers/perf/arm_smmuv3_pmu.c +++ b/drivers/perf/arm_smmuv3_pmu.c @@ -747,17 +747,19 @@ static void smmu_pmu_reset(struct smmu_pmu *smmu_pmu) static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu) { - u32 model; + struct iort_smmu_pdata *pdata = dev_get_platdata(smmu_pmu->dev); - model = *(u32 *)dev_get_platdata(smmu_pmu->dev); + if (pdata == NULL) + goto done; - switch (model) { + switch (pdata->model) { case IORT_SMMU_V3_PMCG_HISI_HIP08: /* HiSilicon Erratum 162001800 */ smmu_pmu->options |= SMMU_PMCG_EVCNTR_RDONLY; break; } +done: dev_notice(smmu_pmu->dev, "option mask 0x%x\n", smmu_pmu->options); } diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 1a12baa58e40..678cdf036948 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -15,12 +15,17 @@ #define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL) /* - * PMCG model identifiers for use in smmu pmu driver. Please note + * Model identifiers for use in SMMU drivers. Please note * that this is purely for the use of software and has nothing to * do with hardware or with IORT specification. */ -#define IORT_SMMU_V3_PMCG_GENERIC 0x00000000 /* Generic SMMUv3 PMCG */ -#define IORT_SMMU_V3_PMCG_HISI_HIP08 0x00000001 /* HiSilicon HIP08 PMCG */ +#define IORT_SMMU_GENERIC 0x00000000 /* Generic SMMU */ +#define IORT_SMMU_V3_PMCG_HISI_HIP08 0x00000001 /* HiSilicon HIP08 PMCG */ + +struct iort_smmu_pdata { + struct acpi_iort_node *node; + u32 model; +}; int iort_register_domain_token(int trans_id, phys_addr_t base, struct fwnode_handle *fw_node); From patchwork Fri Apr 2 03:56:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 12180295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D694C433B4 for ; Fri, 2 Apr 2021 03:56:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 39BEF610E7 for ; Fri, 2 Apr 2021 03:56:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233841AbhDBD4R (ORCPT ); Thu, 1 Apr 2021 23:56:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233786AbhDBD4R (ORCPT ); Thu, 1 Apr 2021 23:56:17 -0400 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 189A3C0613E6 for ; Thu, 1 Apr 2021 20:56:16 -0700 (PDT) Received: by mail-pf1-x42c.google.com with SMTP id v10so2846865pfn.5 for ; Thu, 01 Apr 2021 20:56:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=/1tfZ3KHdBRbQ7iOu9GTGKGQQTHAyTZW2kSrQXENCl0=; b=xy6IMHoIjKIxBBq1kpYTDQkjsdBtbEb9bsTqof3z3+10iqaOGUpFsKODpR2BJE3V9l GmHQkPX+aJ2RR3K3StqZLC8YUG97r6rnTP0DUEOCtlI45bDPntoC5EDK8/o/40jBt+f6 i4DpeVwqoXl/vTCrrToqU1FTaunO+/av8VfWuE9t5zC+ZIURcbT7dLpY27n5VNF1kIgE oZ7+0JcvmhEF5Al57VnaIZ8tvVoUPybyc+uccsmJzhB1U2vxUeXO8ahOxWyIefHDk/YQ v4rQbwt2snwgK37SuSn/xwWdY7/zh3Y2dIqm4pzm3G97MzEveVEI5ydK+0teBebf4qCo rGFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/1tfZ3KHdBRbQ7iOu9GTGKGQQTHAyTZW2kSrQXENCl0=; b=j7aI31C17oHz75JYi6MSUZQOxafyqwyHeRnvstHP6rLlqsAa+VwDsXwc5zKQYqiXjC 0FaZz0zgNDGWhJ3WYxGpVNTHvgevu/ykvhKO1iY40U6kWXDff5VF/lpJKrXg28r8HLuv AALbsfIsFZ/6LlMjQpsQv9PcBbU1SYgM8NY47k1r50Qj+6hL+cj/z4QniR+v/O9DfJvh RZ7oT38zXkAikAA8lOMNHXz76asKJjlIGoIXJUzlOD/oLHO/qwa/liTN9fjWr8C6epWf zgghaeLzVNWvfrBBIYO231/tL5Bk+kecOHBFm6oKdcxL1SO04/125ycuYm6+sg0I9IH+ u+pg== X-Gm-Message-State: AOAM531sVDDMVWkPWtMlL0cueT06arDEGvvG1mf6j8Cs5Nevv07V1FGj 0om36mifQzzF1ts/Og9e2hVqsw== X-Google-Smtp-Source: ABdhPJxq0/P3BZCjsJltqsSX1E8fe3pwGt3mKPGSYK3eBXms5/r6xe7yM/u4Bry3jlTaGPDMJyCnlw== X-Received: by 2002:a65:6a01:: with SMTP id m1mr10169543pgu.215.1617335775654; Thu, 01 Apr 2021 20:56:15 -0700 (PDT) Received: from localhost.localdomain (80.251.214.228.16clouds.com. [80.251.214.228]) by smtp.gmail.com with ESMTPSA id 81sm6875972pfu.164.2021.04.01.20.56.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Apr 2021 20:56:15 -0700 (PDT) From: Shawn Guo To: Will Deacon Cc: Robin Murphy , Bjorn Andersson , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Shawn Guo Subject: [PATCH v2 2/3] ACPI/IORT: Add Qualcomm Snapdragon platforms to iort_plat_info[] Date: Fri, 2 Apr 2021 11:56:01 +0800 Message-Id: <20210402035602.9484-3-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210402035602.9484-1-shawn.guo@linaro.org> References: <20210402035602.9484-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SMMU driver on Qualcomm Snapdragon platforms needs to hook up some QCOM specific arm_smmu_impl. Define model identifier for QCOM SMMU and add Qualcomm SC8180X platform to iort_plat_info[], so that SMMU driver can detect the model and handle QCOM specific arm_smmu_impl. Some device chooses to use manufacturer name in IORT table, like Lenovo Flex 5G, while others use SoC vendor name, such as Microsoft Surface Pro X and Samsung Galaxy Book S. Signed-off-by: Shawn Guo --- drivers/acpi/arm64/iort.c | 5 +++++ include/linux/acpi_iort.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c index e2a96d2d399a..f88b8c0a7d84 100644 --- a/drivers/acpi/arm64/iort.c +++ b/drivers/acpi/arm64/iort.c @@ -1467,6 +1467,11 @@ static struct acpi_platform_list iort_plat_info[] __initdata = { /* HiSilicon Hip08 Platform */ {"HISI ", "HIP08 ", 0, ACPI_SIG_IORT, greater_than_or_equal, "Erratum #162001800", IORT_SMMU_V3_PMCG_HISI_HIP08}, + /* Qualcomm Snapdragon Platform */ + { "LENOVO", "CB-01 ", 0x8180, ACPI_SIG_IORT, equal, + "QCOM SMMU", IORT_SMMU_QCOM }, + { "QCOM ", "QCOMEDK2", 0x8180, ACPI_SIG_IORT, equal, + "QCOM SMMU", IORT_SMMU_QCOM }, { } }; diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h index 678cdf036948..66c859ea2abf 100644 --- a/include/linux/acpi_iort.h +++ b/include/linux/acpi_iort.h @@ -21,6 +21,7 @@ */ #define IORT_SMMU_GENERIC 0x00000000 /* Generic SMMU */ #define IORT_SMMU_V3_PMCG_HISI_HIP08 0x00000001 /* HiSilicon HIP08 PMCG */ +#define IORT_SMMU_QCOM 0x00000002 /* QCOM SMMU */ struct iort_smmu_pdata { struct acpi_iort_node *node; From patchwork Fri Apr 2 03:56:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 12180297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87B6BC433ED for ; Fri, 2 Apr 2021 03:56:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 47F1A610E7 for ; Fri, 2 Apr 2021 03:56:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233665AbhDBD4T (ORCPT ); Thu, 1 Apr 2021 23:56:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233786AbhDBD4T (ORCPT ); Thu, 1 Apr 2021 23:56:19 -0400 Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FB1CC0613E6 for ; Thu, 1 Apr 2021 20:56:19 -0700 (PDT) Received: by mail-pg1-x536.google.com with SMTP id f10so2837365pgl.9 for ; Thu, 01 Apr 2021 20:56:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3nQhD90sdJSzQdgo78ZKmX3OfUzD+szW/4QnSrBPjH4=; b=P3kuftwOPyckZywrWcQWSfwihuGdzQTnGOBic65JfGR5wzUcOgpXw89JlKDQT7rkS0 RbqTYL/yLLalyBJs88wj5lqkVOya+/SIZptgBr18VHj4ZT/R4ZRnwaObwxukjsYcRe6f jaoRNyNZx9awptdKzVQJvSLmvekEBrXYls+B3UMG5ECMPaXT7Mhh8gzK1KsHe28zv3+U JBBmzgRn3GOTdrPevhVN2AclStD2Jxp0uJVW1Y0+DurvyijGHynD+AQyKBMps2aW6uYa pyfbVa+8zVXyIuaElf+Pckvgf2rG1bbuSpmJacHa8FCMHUWuyL4YX+XbRJfGzykFAqJI mYWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3nQhD90sdJSzQdgo78ZKmX3OfUzD+szW/4QnSrBPjH4=; b=gxgVu7Np4m3DopuBpovn8/GaSXR6rBN+Nunjzhn4bqlJJXhZDEZF584n0QKFicbEl5 lfsOCbEdkD65sMGod7NVbcb/dCG0w9q3Hx501oEuKb7YCrBj0jgyj/XouaK7SH96Rqv0 NJrzalE+dcMbsT3P0lHVkSIqAVL+2hPUG78Z9LUALr8u/DJpaRwthmdxV3DQIdYQFeCQ tt+lCRCcNHZJdoxxgJKFG+sDeIz5iuvyyJKNYKsE/y94yRSV1iTz9VKVI4KBVyRFcc9A CoAhQh2pZC/2DfEaXR1AdeLYaSgwSsOeC6yUJY5ASCSHyHvNlFGV3DtLThECkJwoKxy0 /jwQ== X-Gm-Message-State: AOAM532bt7t7b347pJpOW5noL/nvOESk1ryUqu3hBft3mrWyuYLEnT7H jCI7sD3HofMNvt0wV+AjsEiJ3Q== X-Google-Smtp-Source: ABdhPJy32aJ5h5W9VDt0+416R7LPGrBxJo/5XMIv4vXMiY/T97i7LwN6fp7RvRCavYrY/JMeod4r9A== X-Received: by 2002:a63:78cc:: with SMTP id t195mr10067403pgc.196.1617335778655; Thu, 01 Apr 2021 20:56:18 -0700 (PDT) Received: from localhost.localdomain (80.251.214.228.16clouds.com. [80.251.214.228]) by smtp.gmail.com with ESMTPSA id 81sm6875972pfu.164.2021.04.01.20.56.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Apr 2021 20:56:18 -0700 (PDT) From: Shawn Guo To: Will Deacon Cc: Robin Murphy , Bjorn Andersson , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Shawn Guo Subject: [PATCH v2 3/3] iommu/arm-smmu-qcom: hook up qcom_smmu_impl for ACPI boot Date: Fri, 2 Apr 2021 11:56:02 +0800 Message-Id: <20210402035602.9484-4-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210402035602.9484-1-shawn.guo@linaro.org> References: <20210402035602.9484-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The hookup with qcom_smmu_impl is required to do ACPI boot on SC8180X based devices like Lenovo Flex 5G laptop and Microsoft Surface Pro X. Check IORT SMMU model identifier and create qcom_smmu_impl accordingly. (np == NULL) is used to check ACPI boot, because fwnode of SMMU device is a static allocation and thus helpers like has_acpi_companion() don't work here. Signed-off-by: Shawn Guo --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 82c7edc6e025..7ced0f93bc99 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -3,6 +3,7 @@ * Copyright (c) 2019, The Linux Foundation. All rights reserved. */ +#include #include #include #include @@ -340,6 +341,14 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu) { const struct device_node *np = smmu->dev->of_node; + if (np == NULL) { + /* ACPI boot */ + struct iort_smmu_pdata *pdata = dev_get_platdata(smmu->dev); + + if (pdata && pdata->model == IORT_SMMU_QCOM) + return qcom_smmu_create(smmu, &qcom_smmu_impl); + } + if (of_match_node(qcom_smmu_impl_of_match, np)) return qcom_smmu_create(smmu, &qcom_smmu_impl);