From patchwork Wed Nov 21 18:13:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabiano Rosas X-Patchwork-Id: 10692945 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C99621709 for ; Wed, 21 Nov 2018 18:18:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B6AD02C470 for ; Wed, 21 Nov 2018 18:18:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A791C2C633; Wed, 21 Nov 2018 18:18:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 982C92C470 for ; Wed, 21 Nov 2018 18:18:00 +0000 (UTC) Received: from localhost ([::1]:41061 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gPX4Z-0001PL-7V for patchwork-qemu-devel@patchwork.kernel.org; Wed, 21 Nov 2018 13:17:59 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57908) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gPX37-0008W2-SZ for qemu-devel@nongnu.org; Wed, 21 Nov 2018 13:16:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gPX0p-0006d9-9W for qemu-devel@nongnu.org; Wed, 21 Nov 2018 13:14:11 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:57770 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gPX0o-0006ab-2W for qemu-devel@nongnu.org; Wed, 21 Nov 2018 13:14:06 -0500 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id wALI4KNU131771 for ; Wed, 21 Nov 2018 13:14:04 -0500 Received: from e12.ny.us.ibm.com (e12.ny.us.ibm.com [129.33.205.202]) by mx0a-001b2d01.pphosted.com with ESMTP id 2nwae2ddu0-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 21 Nov 2018 13:14:03 -0500 Received: from localhost by e12.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 21 Nov 2018 18:13:57 -0000 Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id wALIDuwA62259264 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 21 Nov 2018 18:13:56 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BC61EAC05B; Wed, 21 Nov 2018 18:13:56 +0000 (GMT) Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8AB2EAC060; Wed, 21 Nov 2018 18:13:53 +0000 (GMT) Received: from farosas.linux.ibm.com.br.ibm.com (unknown [9.86.27.87]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 21 Nov 2018 18:13:53 +0000 (GMT) From: Fabiano Rosas To: qemu-devel@nongnu.org Date: Wed, 21 Nov 2018 16:13:45 -0200 X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181121181347.24035-1-farosas@linux.ibm.com> References: <20181121181347.24035-1-farosas@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18112118-0060-0000-0000-000002D69C0D X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00010095; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000270; SDB=6.01120765; UDB=6.00581594; IPR=6.00900886; MB=3.00024266; MTD=3.00000008; XFM=3.00000015; UTC=2018-11-21 18:14:01 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18112118-0061-0000-0000-000047458FD9 Message-Id: <20181121181347.24035-2-farosas@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-11-21_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=684 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1811210157 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [RFC PATCH v2 1/3] target/ppc: Add macro definitions for relocated interrupt vectors offsets X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Cornelia Huck , Eduardo Habkost , Peter Crosthwaite , James Hogan , Marcelo Tosatti , David Hildenbrand , Christian Borntraeger , Aleksandar Markovic , Paolo Bonzini , David Gibson , philmd@redhat.com, Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The PowerISA prescribes that depending on the values of MSR_IR, MSR_DR, MSR_HV and LPCR_AIL, the interrupt vectors might be relocated by specific offsets. This patch defines macros for these offsets so that they can be used by another part of the code in a future patch. Signed-off-by: Fabiano Rosas --- target/ppc/cpu.h | 3 +++ target/ppc/excp_helper.c | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index ab68abe8a2..5147db4460 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2390,6 +2390,9 @@ enum { AIL_C000_0000_0000_4000 = 3, }; +#define AIL_0001_8000_OFFSET 0x18000 +#define AIL_C000_0000_0000_4000_OFFSET 0xc000000000004000ull + /*****************************************************************************/ #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300)) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 0ec7ae1ad4..49bdf7dd54 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -687,10 +687,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) new_msr |= (1 << MSR_IR) | (1 << MSR_DR); switch(ail) { case AIL_0001_8000: - vector |= 0x18000; + vector |= AIL_0001_8000_OFFSET; break; case AIL_C000_0000_0000_4000: - vector |= 0xc000000000004000ull; + vector |= AIL_C000_0000_0000_4000_OFFSET; break; default: cpu_abort(cs, "Invalid AIL combination %d\n", ail); From patchwork Wed Nov 21 18:13:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Fabiano Rosas X-Patchwork-Id: 10692953 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 77A6E1709 for ; Wed, 21 Nov 2018 18:23:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 669F32C610 for ; Wed, 21 Nov 2018 18:23:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 59D0F2C615; Wed, 21 Nov 2018 18:23:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9C6CB2C61F for ; Wed, 21 Nov 2018 18:23:43 +0000 (UTC) Received: from localhost ([::1]:41102 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gPXA5-0007Qa-LR for patchwork-qemu-devel@patchwork.kernel.org; Wed, 21 Nov 2018 13:23:41 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57839) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gPX3A-0008Ts-Fs for qemu-devel@nongnu.org; Wed, 21 Nov 2018 13:16:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gPX0v-0006i7-5r for qemu-devel@nongnu.org; Wed, 21 Nov 2018 13:14:16 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:58360 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gPX0p-0006ct-A8 for qemu-devel@nongnu.org; Wed, 21 Nov 2018 13:14:08 -0500 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id wALI4JYq131728 for ; Wed, 21 Nov 2018 13:14:06 -0500 Received: from e11.ny.us.ibm.com (e11.ny.us.ibm.com [129.33.205.201]) by mx0a-001b2d01.pphosted.com with ESMTP id 2nwae2ddvm-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 21 Nov 2018 13:14:06 -0500 Received: from localhost by e11.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 21 Nov 2018 18:14:02 -0000 Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id wALIE1mb34668582 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 21 Nov 2018 18:14:01 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4BA82AC05E; Wed, 21 Nov 2018 18:14:01 +0000 (GMT) Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 28421AC05F; Wed, 21 Nov 2018 18:13:58 +0000 (GMT) Received: from farosas.linux.ibm.com.br.ibm.com (unknown [9.86.27.87]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 21 Nov 2018 18:13:57 +0000 (GMT) From: Fabiano Rosas To: qemu-devel@nongnu.org Date: Wed, 21 Nov 2018 16:13:46 -0200 X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181121181347.24035-1-farosas@linux.ibm.com> References: <20181121181347.24035-1-farosas@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18112118-2213-0000-0000-0000031C5D47 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00010095; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000270; SDB=6.01120765; UDB=6.00581594; IPR=6.00900887; MB=3.00024266; MTD=3.00000008; XFM=3.00000015; UTC=2018-11-21 18:14:05 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18112118-2214-0000-0000-00005C55C8E0 Message-Id: <20181121181347.24035-3-farosas@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-11-21_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1811210157 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 Subject: [Qemu-devel] [RFC PATCH v2 2/3] kvm-all: Introduce kvm_set_singlestep X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Cornelia Huck , Eduardo Habkost , Peter Crosthwaite , James Hogan , Marcelo Tosatti , David Hildenbrand , Christian Borntraeger , Aleksandar Markovic , Paolo Bonzini , David Gibson , philmd@redhat.com, Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This will be used in a future patch to implement an architecture-specific single step mechanism for POWER. Signed-off-by: Fabiano Rosas Reviewed-by: Philippe Mathieu-Daudé --- accel/kvm/kvm-all.c | 10 ++++++++++ exec.c | 1 + include/sysemu/kvm.h | 4 ++++ target/arm/kvm.c | 4 ++++ target/i386/kvm.c | 4 ++++ target/mips/kvm.c | 4 ++++ target/ppc/kvm.c | 4 ++++ target/s390x/kvm.c | 4 ++++ 8 files changed, 35 insertions(+) diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 4880a05399..4fb7199a15 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -2313,6 +2313,11 @@ int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap) return data.err; } +void kvm_set_singlestep(CPUState *cs, int enabled) +{ + kvm_arch_set_singlestep(cs, enabled); +} + int kvm_insert_breakpoint(CPUState *cpu, target_ulong addr, target_ulong len, int type) { @@ -2439,6 +2444,11 @@ int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr, void kvm_remove_all_breakpoints(CPUState *cpu) { } + +void kvm_set_singlestep(CPUState *cs, int enabled) +{ +} + #endif /* !KVM_CAP_SET_GUEST_DEBUG */ static int kvm_set_signal_mask(CPUState *cpu, const sigset_t *sigset) diff --git a/exec.c b/exec.c index bb6170dbff..55614822c3 100644 --- a/exec.c +++ b/exec.c @@ -1233,6 +1233,7 @@ void cpu_single_step(CPUState *cpu, int enabled) if (cpu->singlestep_enabled != enabled) { cpu->singlestep_enabled = enabled; if (kvm_enabled()) { + kvm_set_singlestep(cpu, enabled); kvm_update_guest_debug(cpu, 0); } else { /* must flush all the translated code to avoid inconsistencies */ diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 97d8d9d0d5..a01a8d58dd 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -259,6 +259,8 @@ int kvm_remove_breakpoint(CPUState *cpu, target_ulong addr, void kvm_remove_all_breakpoints(CPUState *cpu); int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap); +void kvm_set_singlestep(CPUState *cpu, int enabled); + int kvm_on_sigbus_vcpu(CPUState *cpu, int code, void *addr); int kvm_on_sigbus(int code, void *addr); @@ -431,6 +433,8 @@ void kvm_arch_remove_all_hw_breakpoints(void); void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg); +void kvm_arch_set_singlestep(CPUState *cpu, int enabled); + bool kvm_arch_stop_on_emulation_error(CPUState *cpu); int kvm_check_extension(KVMState *s, unsigned int extension); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 44dd0ce6ce..dd8e43ab7e 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -670,6 +670,10 @@ int kvm_arch_process_async_events(CPUState *cs) return 0; } +void kvm_arch_set_singlestep(CPUState *cs, int enabled) +{ +} + /* The #ifdef protections are until 32bit headers are imported and can * be removed once both 32 and 64 bit reach feature parity. */ diff --git a/target/i386/kvm.c b/target/i386/kvm.c index f524e7d929..ba56f2ee1f 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -3521,6 +3521,10 @@ static int kvm_handle_debug(X86CPU *cpu, return ret; } +void kvm_arch_set_singlestep(CPUState *cs, int enabled) +{ +} + void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg) { const uint8_t type_code[] = { diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 8e72850962..8035262131 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -119,6 +119,10 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) return 0; } +void kvm_arch_set_singlestep(CPUState *cs, int enabled) +{ +} + static inline int cpu_mips_io_interrupts_pending(MIPSCPU *cpu) { CPUMIPSState *env = &cpu->env; diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index f81327d6cd..9d0b4f1f3f 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -1551,6 +1551,10 @@ void kvm_arch_remove_all_hw_breakpoints(void) nb_hw_breakpoint = nb_hw_watchpoint = 0; } +void kvm_arch_set_singlestep(CPUState *cs, int enabled) +{ +} + void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) { int n; diff --git a/target/s390x/kvm.c b/target/s390x/kvm.c index 2ebf26adfe..4bde183458 100644 --- a/target/s390x/kvm.c +++ b/target/s390x/kvm.c @@ -975,6 +975,10 @@ void kvm_arch_remove_all_hw_breakpoints(void) hw_breakpoints = NULL; } +void kvm_arch_set_singlestep(CPUState *cs, int enabled) +{ +} + void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg) { int i; From patchwork Wed Nov 21 18:13:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabiano Rosas X-Patchwork-Id: 10692951 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E898713B5 for ; Wed, 21 Nov 2018 18:20:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D61CE2C511 for ; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 21 Nov 2018 18:14:07 -0000 Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id wALIE61X37617840 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 21 Nov 2018 18:14:06 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id ECDB8AC059; Wed, 21 Nov 2018 18:14:05 +0000 (GMT) Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9FB09AC05E; Wed, 21 Nov 2018 18:14:02 +0000 (GMT) Received: from farosas.linux.ibm.com.br.ibm.com (unknown [9.86.27.87]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTP; Wed, 21 Nov 2018 18:14:02 +0000 (GMT) From: Fabiano Rosas To: qemu-devel@nongnu.org Date: Wed, 21 Nov 2018 16:13:47 -0200 X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181121181347.24035-1-farosas@linux.ibm.com> References: <20181121181347.24035-1-farosas@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18112118-0040-0000-0000-0000049626FB X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00010095; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000270; SDB=6.01120765; UDB=6.00577119; IPR=6.00900886; MB=3.00024266; MTD=3.00000008; XFM=3.00000015; UTC=2018-11-21 18:14:10 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18112118-0041-0000-0000-0000089F3832 Message-Id: <20181121181347.24035-4-farosas@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-11-21_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=904 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1811210157 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 Subject: [Qemu-devel] [RFC PATCH v2 3/3] target/ppc: support single stepping with KVM HV X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Cornelia Huck , Eduardo Habkost , Peter Crosthwaite , James Hogan , Marcelo Tosatti , David Hildenbrand , Christian Borntraeger , Aleksandar Markovic , Paolo Bonzini , David Gibson , philmd@redhat.com, Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP The hardware singlestep mechanism in POWER works via a Trace Interrupt (0xd00) that happens after any instruction executes, whenever MSR_SE = 1 (PowerISA Section 6.5.15 - Trace Interrupt). However, with kvm_hv, the Trace Interrupt happens inside the guest and KVM has no visibility of it. Therefore, when the gdbstub uses the KVM_SET_GUEST_DEBUG ioctl to enable singlestep, KVM simply ignores it. This patch takes advantage of the Trace Interrupt to perform the step inside the guest, but uses a breakpoint at the Trace Interrupt handler to return control to KVM. The exit is treated by KVM as a regular breakpoint and it returns to the host (and QEMU eventually). Before signalling GDB, QEMU sets the Next Instruction Pointer to the instruction following the one being stepped, effectively skipping the interrupt handler execution and hiding the trace interrupt breakpoint from GDB. This approach works with both of GDB's 'scheduler-locking' options (off, step). Signed-off-by: Fabiano Rosas --- target/ppc/kvm.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 60 insertions(+), 1 deletion(-) diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 9d0b4f1f3f..93c20099e6 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -94,6 +94,7 @@ static int cap_ppc_safe_indirect_branch; static int cap_ppc_nested_kvm_hv; static uint32_t debug_inst_opcode; +static target_ulong trace_handler_addr; /* XXX We have a race condition where we actually have a level triggered * interrupt, but the infrastructure can't expose that yet, so the guest @@ -509,6 +510,9 @@ int kvm_arch_init_vcpu(CPUState *cs) kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode); kvmppc_hw_debug_points_init(cenv); + trace_handler_addr = (cenv->excp_vectors[POWERPC_EXCP_TRACE] | + AIL_C000_0000_0000_4000_OFFSET); + return ret; } @@ -1553,6 +1557,24 @@ void kvm_arch_remove_all_hw_breakpoints(void) void kvm_arch_set_singlestep(CPUState *cs, int enabled) { + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + + if (kvmppc_is_pr(kvm_state)) { + return; + } + + if (enabled) { + /* MSR_SE = 1 will cause a Trace Interrupt in the guest after + * the next instruction executes. */ + env->msr |= (1ULL << MSR_SE); + + /* We set a breakpoint at the interrupt handler address so + * that the singlestep will be seen by KVM (this is treated by + * KVM like an ordinary breakpoint) and control is returned to + * QEMU. */ + kvm_insert_breakpoint(cs, trace_handler_addr, 4, GDB_BREAKPOINT_SW); + } } void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) @@ -1594,6 +1616,43 @@ void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) } } +static int kvm_handle_singlestep(CPUState *cs, + struct kvm_debug_exit_arch *arch_info) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + target_ulong msr = env->msr; + uint32_t insn; + int ret = 1; + int reg; + + if (kvmppc_is_pr(kvm_state)) { + return ret; + } + + if (arch_info->address == trace_handler_addr) { + cpu_synchronize_state(cs); + kvm_remove_breakpoint(cs, trace_handler_addr, 4, GDB_BREAKPOINT_SW); + + cpu_memory_rw_debug(cs, env->spr[SPR_SRR0] - 4, (uint8_t *)&insn, + sizeof(insn), 0); + + /* If the last instruction was a mfmsr, make sure that the + * MSR_SE bit is not set to avoid the guest kernel knowing + * that it is being single-stepped */ + if (extract32(insn, 26, 6) == 31 && extract32(insn, 1, 10) == 83) { + reg = extract32(insn, 21, 5); + env->gpr[reg] &= ~(1ULL << MSR_SE); + } + + env->nip = env->spr[SPR_SRR0]; + env->msr = msr &= ~(1ULL << MSR_SE); + cpu_synchronize_state(cs); + } + + return ret; +} + static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run) { CPUState *cs = CPU(cpu); @@ -1604,7 +1663,7 @@ static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run) int flag = 0; if (cs->singlestep_enabled) { - handle = 1; + handle = kvm_handle_singlestep(cs, arch_info); } else if (arch_info->status) { if (nb_hw_breakpoint + nb_hw_watchpoint > 0) { if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) {