From patchwork Sat Apr 3 06:19:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Lipnitskiy X-Patchwork-Id: 12181815 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8608FC433B4 for ; Sat, 3 Apr 2021 06:19:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 488206120D for ; Sat, 3 Apr 2021 06:19:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232140AbhDCGTU (ORCPT ); Sat, 3 Apr 2021 02:19:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231282AbhDCGTU (ORCPT ); Sat, 3 Apr 2021 02:19:20 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 227A7C0613E6; Fri, 2 Apr 2021 23:19:18 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id f17so3405549plr.0; Fri, 02 Apr 2021 23:19:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=CBCIQHgUyAG2ZGSKzfcjypqTPr8Hjug+h1YTnKY5wjs=; b=etTmaMG/X35UknYs65i78HG3uAez5LaE097mDlhRe4dJsujsEPlNTBIxs0GUv9ryCH OJEAWEH2S58EBcd72jum8klzXCke0zQPaJlpFUqWhVpi1PZmyLNKlTWg1vHjZbVhsBhS s/R3+5n3kp3pkF7EcWSDy7SswrKs927B4MJc0njNYDWX29PzixubDUq7ILsqNQU26/w4 95R1AW4amePmNvDCWkALRcziiR6g4edrsXhazDOwOqnjn2atSBDdRGH7UBL2q2mRxZjg Bz5FEw9wj/wtu0EpXWk5HopwYbKxOFteyDd2u8YKIYR7IJxv17T8Dj1Tw16rhUHQidWd GwHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=CBCIQHgUyAG2ZGSKzfcjypqTPr8Hjug+h1YTnKY5wjs=; b=KoO571I9A2WARUD/4kVXjhesBZ5nVYmLrx9V6Fu1orOCCWyvs6mQ7pcC8M82Ts5sZN FkrpJUJtgtidBE3JHYOlRtAI5DlMWdvTXj0F4X1wZ0V2/fuAIz3hS8QFOHf7xeKYgfAN yMXD/bkVLzPs8AcCgkDy5UJ+Tq/cLdJVbakwipkjWzFpAeCVq+ImkfxxulwfVpoiTz+9 uKsVsNR8Lh51c8Ck/2XVe07ZOaMwQwIHDPW9CS9l0+FdYqbR8x1hAgCedE8RXxJyUZkB fjOdBnEQfh35dzPmIpp0jPZoJ8V4Q+AlgYRBp+3dTEB/6GT83BrxTbHNPU29NlhG1M88 2oKg== X-Gm-Message-State: AOAM531iZwFheb7ZNGSsBjjjLrApHtdUknhTkSJmg1OdwczF9COrWjXq 46AF+rCKGADkid9MUb4aJDk= X-Google-Smtp-Source: ABdhPJzBvu4vNX3rq+Sr9fLDESRf+liLR4Ve21s0wdbMVPiZ8RDtaz9hNeI6G66m9jvKmmkDEcRZeQ== X-Received: by 2002:a17:90b:3692:: with SMTP id mj18mr16606663pjb.44.1617430757530; Fri, 02 Apr 2021 23:19:17 -0700 (PDT) Received: from z640-arch.lan ([2602:61:7344:f100::678]) by smtp.gmail.com with ESMTPSA id n25sm9436174pff.154.2021.04.02.23.19.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Apr 2021 23:19:16 -0700 (PDT) From: Ilya Lipnitskiy To: Thomas Bogendoerfer , Wei Li , Tiezhu Yang , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Ilya Lipnitskiy , Felix Fietkau Subject: [PATCH] MIPS: add support for buggy MT7621S core detection Date: Fri, 2 Apr 2021 23:19:12 -0700 Message-Id: <20210403061912.1012509-1-ilya.lipnitskiy@gmail.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Most MT7621 SoCs have 2 cores, which is detected and supported properly by CPS. Unfortunately, MT7621 SoC has a less common S variant with only one core. On MT7621S, GCR_CONFIG still reports 2 cores, which leads to hangs when starting SMP. CPULAUNCH registers can be used in that case to detect the absence of the second core and override the GCR_CONFIG PCORES field. Rework a long-standing OpenWrt patch to override the value of mips_cps_numcores on single-core MT7621 systems. Tested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core MT7621 device (Netgear R6220). Original 4.14 OpenWrt patch: Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=4cdbc90a376dd0555201c1434a2081e055e9ceb7 Current 5.10 OpenWrt patch: Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch;h=c63f0f4c1ec742e24d8480e80553863744b58f6a;hb=10267e17299806f9885d086147878f6c492cb904 Suggested-by: Felix Fietkau Signed-off-by: Ilya Lipnitskiy --- arch/mips/include/asm/bugs.h | 18 ++++++++++++++++++ arch/mips/kernel/smp-cps.c | 3 +++ 2 files changed, 21 insertions(+) diff --git a/arch/mips/include/asm/bugs.h b/arch/mips/include/asm/bugs.h index d72dc6e1cf3c..d32f0c4e61f7 100644 --- a/arch/mips/include/asm/bugs.h +++ b/arch/mips/include/asm/bugs.h @@ -16,6 +16,7 @@ #include #include +#include extern int daddiu_bug; @@ -50,4 +51,21 @@ static inline int r4k_daddiu_bug(void) return daddiu_bug != 0; } +static inline void cm_gcr_pcores_bug(unsigned int *ncores) +{ + struct cpulaunch *launch; + + if (!IS_ENABLED(CONFIG_SOC_MT7621) || !ncores) + return; + + /* + * Ralink MT7621S SoC is single core, but GCR_CONFIG always reports 2 cores. + * Use legacy amon method to detect if the second core is missing. + */ + launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH); + launch += 2; /* MT7621 has 2 VPEs per core */ + if (!(launch->flags & LAUNCH_FREADY)) + *ncores = 1; +} + #endif /* _ASM_BUGS_H */ diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index bcd6a944b839..e1e9c11e8a7c 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -15,6 +15,7 @@ #include #include +#include #include #include #include @@ -60,6 +61,7 @@ static void __init cps_smp_setup(void) pr_cont("{"); ncores = mips_cps_numcores(cl); + cm_gcr_pcores_bug(&ncores); for (c = 0; c < ncores; c++) { core_vpes = core_vpe_count(cl, c); @@ -170,6 +172,7 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) /* Allocate core boot configuration structs */ ncores = mips_cps_numcores(0); + cm_gcr_pcores_bug(&ncores); mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg), GFP_KERNEL); if (!mips_cps_core_bootcfg) {