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Mon, 05 Apr 2021 10:30:09 -0700 (PDT) From: Fabien Parent To: Rob Herring , Matthias Brugger Cc: mkorpershoek@baylibre.com, Fabien Parent , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] arm64: dts: mediatek: mt8167: add power domains Date: Mon, 5 Apr 2021 19:28:36 +0200 Message-Id: <20210405172836.2038526-1-fparent@baylibre.com> X-Mailer: git-send-email 2.31.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210405_183010_891562_CB24E6E1 X-CRM114-Status: GOOD ( 11.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add support for the MT8167 power domains. Signed-off-by: Fabien Parent --- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 68 ++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index 1c5639ead622..156fbdad01fb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -7,6 +7,7 @@ #include #include +#include #include "mt8167-pinfunc.h" @@ -34,6 +35,73 @@ apmixedsys: apmixedsys@10018000 { #clock-cells = <1>; }; + scpsys: syscon@10006000 { + compatible = "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + #power-domain-cells = <1>; + + spm: power-controller { + compatible = "mediatek,mt8167-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domains of the SoC */ + power-domain@MT8167_POWER_DOMAIN_MM { + reg = ; + clocks = <&topckgen CLK_TOP_SMI_MM>; + clock-names = "mm"; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + + power-domain@MT8167_POWER_DOMAIN_VDEC { + reg = ; + clocks = <&topckgen CLK_TOP_SMI_MM>, + <&topckgen CLK_TOP_RG_VDEC>; + clock-names = "mm", "vdec"; + #power-domain-cells = <0>; + }; + + power-domain@MT8167_POWER_DOMAIN_ISP { + reg = ; + clocks = <&topckgen CLK_TOP_SMI_MM>; + clock-names = "mm"; + #power-domain-cells = <0>; + }; + + power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC { + reg = ; + clocks = <&topckgen CLK_TOP_RG_AXI_MFG>, + <&topckgen CLK_TOP_RG_SLOW_MFG>; + clock-names = "axi_mfg", "mfg"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + mediatek,infracfg = <&infracfg>; + + power-domain@MT8167_POWER_DOMAIN_MFG_2D { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8167_POWER_DOMAIN_MFG { + reg = ; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + }; + + power-domain@MT8167_POWER_DOMAIN_CONN { + reg = ; + #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; + }; + }; + }; + imgsys: syscon@15000000 { compatible = "mediatek,mt8167-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>;