From patchwork Tue Apr 6 01:32:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Voon, Weifeng" X-Patchwork-Id: 12183909 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 406B4C433B4 for ; Tue, 6 Apr 2021 01:35:24 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BE689613E8 for ; Tue, 6 Apr 2021 01:35:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BE689613E8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:MIME-Version:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:Message-Id:Date:Subject:Cc:To:From:Reply-To: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=T15fgklMW1fiMka52djUPmqvF3Vc/rJVCVfyLwJGBlc=; b=rAxXz8wgOwNIstokWrGLafX5hz OWkeH7f7BBn7nksDnrIHzJ3bWcZlkguvyZYV5EMRkyod0y6WZf/qtjOxD1i5Em8eD2SfxqdwRZye8 XH3XfdY0lq5miAtJ2nT9mgSRVcXbJHU6jSJTub00dl/QysMLdK+UMakANNj2mhmtjfMLpEp/41acN SpvDrQjVJT/9W4UkWAdSaouDAb4hd8v+NBO97erFDiD+T5oxwFU8wh+yFVhTjwoaVuRAp4E5vMKUL 0FsCDu50fCZM2tvguyVPGflVmFTHm9Mlc2/IxJl3Og9hBZwil/lk5qOO01S5q0o7G7071i4Te9C3U pWCqXeXQ==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lTaab-001AQ6-Eh; Tue, 06 Apr 2021 01:33:09 +0000 Received: from mga07.intel.com ([134.134.136.100]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lTaaR-001AO2-MI for linux-arm-kernel@lists.infradead.org; Tue, 06 Apr 2021 01:33:03 +0000 IronPort-SDR: VOFJ38sWvbI+yj1Y6RDTgdtcRFW0jMrGyKe+XNI0BHWLOEVwLdzM15ELeKChKUlD1dJPbcwsV9 zzSQZkkOo61Q== X-IronPort-AV: E=McAfee;i="6000,8403,9945"; a="256944959" X-IronPort-AV: E=Sophos;i="5.81,308,1610438400"; d="scan'208";a="256944959" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Apr 2021 18:32:54 -0700 IronPort-SDR: vYV/ERUKjRELAc4zoPuduFJq5T14mSjVDqQZgV0QGCcjyPllKdU0rV2ml1qTH17HyV+P6RLEDV GX5R44VEdEYQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,308,1610438400"; d="scan'208";a="609081809" Received: from climb.png.intel.com ([10.221.118.165]) by fmsmga006.fm.intel.com with ESMTP; 05 Apr 2021 18:32:51 -0700 From: Voon Weifeng To: "David S . Miller" , Maxime Coquelin Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Jose Abreu , Jakub Kicinski , Giuseppe Cavallaro , Alexandre Torgue , linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Ong Boon Leong , Voon Weifeng , Wong Vee Khee Subject: [PATCH v2 net-next] stmmac: intel: Enable SERDES PHY rx clk for PSE Date: Tue, 6 Apr 2021 09:32:50 +0800 Message-Id: <20210406013250.17171-1-weifeng.voon@intel.com> X-Mailer: git-send-email 2.17.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210406_023300_407426_5518EC65 X-CRM114-Status: UNSURE ( 9.97 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org EHL PSE SGMII mode requires to ungate the SERDES PHY rx clk for power up sequence and vice versa. Signed-off-by: Voon Weifeng --- Changes: v1 -> v2 -change subject from "net: intel" to "stmmac: intel" --- drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 10 ++++++++++ drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h | 1 + 2 files changed, 11 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c index add95e20548d..a4fec5fe0779 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -153,6 +153,11 @@ static int intel_serdes_powerup(struct net_device *ndev, void *priv_data) return data; } + /* PSE only - ungate SGMII PHY Rx Clock */ + if (intel_priv->is_pse) + mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0, + 0, SERDES_PHY_RX_CLK); + return 0; } @@ -168,6 +173,11 @@ static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data) serdes_phy_addr = intel_priv->mdio_adhoc_addr; + /* PSE only - gate SGMII PHY Rx Clock */ + if (intel_priv->is_pse) + mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0, + SERDES_PHY_RX_CLK, 0); + /* move power state to P3 */ data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h index e723096c0b15..542acb8ce467 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h @@ -14,6 +14,7 @@ /* SERDES defines */ #define SERDES_PLL_CLK BIT(0) /* PLL clk valid signal */ +#define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */ #define SERDES_RST BIT(2) /* Serdes Reset */ #define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/ #define SERDES_PWR_ST_SHIFT 4