From patchwork Mon Apr 12 15:30:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Peled X-Patchwork-Id: 12198331 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6570BC433B4 for ; Mon, 12 Apr 2021 15:31:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3D6CA61287 for ; Mon, 12 Apr 2021 15:31:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242904AbhDLPbu (ORCPT ); Mon, 12 Apr 2021 11:31:50 -0400 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:47208 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S242899AbhDLPbr (ORCPT ); Mon, 12 Apr 2021 11:31:47 -0400 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 13CFVBk6004588; Mon, 12 Apr 2021 08:31:11 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=pfpt0220; bh=1w1aOW3ghY/Ww+N67gF96mJvYXQ0kxUthm1XoYVB+Qs=; b=kaq9aYBbPal/PUIU6NyIipJ3FFRg9k5/qlYxy/dijCi2a8Th+ZJ5W/f7zD0rVHXzlxl/ wtAwGWpPZxhUasZ5SRQ78t9VkOJGLPhgHfUDG22ODTUYV7+EhvYrpvdRVBTEzs2+ozZM R2MKqkYdfqBZYcQ2JeRGjhk9JlV0QCJypYEprxwG5UWDq+kD9Wp7GmFlP++T1AxjpVI4 FHoTbB0M9LZLoJTvfuw6BqXgNQI8VONqTl49C7poomwPR0XQ5e0aaiubDQrDCgo52ssz j+wi0gOD84gVbwl2mFu+vJhJ09KA90/VER8Xb39/Nl9R+LBWP8VLqcs287PFfImCSDPE 4A== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 37vcu99xp8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 12 Apr 2021 08:31:11 -0700 Received: from SC-EXCH04.marvell.com (10.93.176.84) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 12 Apr 2021 08:31:09 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 12 Apr 2021 08:31:09 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 12 Apr 2021 08:31:09 -0700 Received: from nw-bp.marvell.com (nw-bp.marvell.com [10.5.24.22]) by maili.marvell.com (Postfix) with ESMTP id 5290F3F7043; Mon, 12 Apr 2021 08:31:05 -0700 (PDT) From: To: , , CC: , , , , , , , , , , , , , , , "Marc St-Amand" Subject: =?utf-8?q?=5B=E2=80=9DPATCH=E2=80=9D_1/5=5D_PCI=3A_armada8k=3A_Disa?= =?utf-8?q?ble_LTSSM_on_link_down_interrupts?= Date: Mon, 12 Apr 2021 18:30:52 +0300 Message-ID: <1618241456-27200-2-git-send-email-bpeled@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618241456-27200-1-git-send-email-bpeled@marvell.com> References: <1618241456-27200-1-git-send-email-bpeled@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: lH0eozCtIxCe8ZuBdcND7yXWxwbA3kra X-Proofpoint-ORIG-GUID: lH0eozCtIxCe8ZuBdcND7yXWxwbA3kra X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-04-12_11:2021-04-12,2021-04-12 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ben Peled When a PCI link down condition is detected, the link training state machine must be disabled immediately. Signed-off-by: Marc St-Amand Signed-off-by: Konstantin Porotchkin Signed-off-by: Ben Peled --- drivers/pci/controller/dwc/pcie-armada8k.c | 38 ++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c index 13901f3..b2278b1 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -54,6 +54,10 @@ struct armada8k_pcie { #define PCIE_INT_C_ASSERT_MASK BIT(11) #define PCIE_INT_D_ASSERT_MASK BIT(12) +#define PCIE_GLOBAL_INT_CAUSE2_REG (PCIE_VENDOR_REGS_OFFSET + 0x24) +#define PCIE_GLOBAL_INT_MASK2_REG (PCIE_VENDOR_REGS_OFFSET + 0x28) +#define PCIE_INT2_PHY_RST_LINK_DOWN BIT(1) + #define PCIE_ARCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x50) #define PCIE_AWCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x54) #define PCIE_ARUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x5C) @@ -193,6 +197,11 @@ static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie) PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK; dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg); + /* Also enable link down interrupts */ + reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK2_REG); + reg |= PCIE_INT2_PHY_RST_LINK_DOWN; + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK2_REG, reg); + if (!dw_pcie_link_up(pci)) { /* Configuration done. Start LTSSM */ reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); @@ -230,6 +239,35 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG); dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val); + val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE2_REG); + + if (PCIE_INT2_PHY_RST_LINK_DOWN & val) { + u32 ctrl_reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG); + /* + * The link went down. Disable LTSSM immediately. This + * unlocks the root complex config registers. Downstream + * device accesses will return all-Fs + */ + ctrl_reg &= ~(PCIE_APP_LTSSM_EN); + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, ctrl_reg); + /* + * Mask link down interrupts. They can be re-enabled once + * the link is retrained. + */ + ctrl_reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK2_REG); + ctrl_reg &= ~PCIE_INT2_PHY_RST_LINK_DOWN; + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK2_REG, ctrl_reg); + /* + * At this point a worker thread can be triggered to + * initiate a link retrain. If link retrains were + * possible, that is. + */ + dev_dbg(pci->dev, "%s: link went down\n", __func__); + } + + /* Now clear the second interrupt cause. */ + dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE2_REG, val); + return IRQ_HANDLED; } From patchwork Mon Apr 12 15:30:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Peled X-Patchwork-Id: 12198335 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 226A8C43460 for ; Mon, 12 Apr 2021 15:31:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 00A9661357 for ; Mon, 12 Apr 2021 15:31:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242912AbhDLPby (ORCPT ); Mon, 12 Apr 2021 11:31:54 -0400 Received: from mx0a-0016f401.pphosted.com ([67.231.148.174]:8832 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S242897AbhDLPbs (ORCPT ); Mon, 12 Apr 2021 11:31:48 -0400 Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 13CFV7Ua004582; Mon, 12 Apr 2021 08:31:15 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=pfpt0220; bh=RexkldyiWF9tZFzZsnrDwTW8chiyq0PpHMBC00a8QLE=; b=RdiWzifQamqPypkPFmPsg7ZO9evnHUnO2qktMbN7ONGtJCv2+oWLWX52p9iu7qyOpDqu FjCFei9qtxG9OQrc2dlKdXQDpe8vDyLvv93QzvHuG7FTcrAtzuGg1/ztMsNqt/gfkYtR xDdgivbuSspEqYvMHxMbw6cqeOVCpqZAS6WZ5ZvbEBMl1qiPVp9NdfOEVOsB++3dzjk6 +182Hu3PGByhrun/E86x6gz1X8G8O142uDcqKrRQivm7sOfO/ZtQDXX1SnPJvKolA/5b hEq7Xm4VAhlUI38ZUcinu0KshYONxvwy/VTHkV6EiobG8cU5NqzGtxdvV1JekgncTuO9 ww== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 37vcu99xpq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 12 Apr 2021 08:31:15 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 12 Apr 2021 08:31:13 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 12 Apr 2021 08:31:14 -0700 Received: from nw-bp.marvell.com (nw-bp.marvell.com [10.5.24.22]) by maili.marvell.com (Postfix) with ESMTP id DCEC33F7041; Mon, 12 Apr 2021 08:31:09 -0700 (PDT) From: To: , , CC: , , , , , , , , , , , , , , Subject: =?utf-8?b?W+KAnVBBVENI4oCdIDIvNV0gUENJOiBhcm1hZGE4azogQWRkIGxpbmst?= =?utf-8?b?ZG93biBoYW5kbGU=?= Date: Mon, 12 Apr 2021 18:30:53 +0300 Message-ID: <1618241456-27200-3-git-send-email-bpeled@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618241456-27200-1-git-send-email-bpeled@marvell.com> References: <1618241456-27200-1-git-send-email-bpeled@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: RWQfULCncbRL2HVMf5TzRz8HAgeHj0GO X-Proofpoint-ORIG-GUID: RWQfULCncbRL2HVMf5TzRz8HAgeHj0GO X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-04-12_11:2021-04-12,2021-04-12 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ben Peled In PCIE ISR routine caused by RST_LINK_DOWN we schedule work to handle the link-down procedure. Link-down procedure will: 1. Remove PCIe bus 2. Reset the MAC 3. Reconfigure link back up 4. Rescan PCIe bus Signed-off-by: Ben Peled --- drivers/pci/controller/dwc/pcie-armada8k.c | 68 ++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c index b2278b1..4eb8607 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include #include "pcie-designware.h" @@ -33,6 +35,9 @@ struct armada8k_pcie { struct clk *clk_reg; struct phy *phy[ARMADA8K_PCIE_MAX_LANES]; unsigned int phy_count; + struct regmap *sysctrl_base; + u32 mac_rest_bitmask; + struct work_struct recover_link_work; }; #define PCIE_VENDOR_REGS_OFFSET 0x8000 @@ -73,6 +78,8 @@ struct armada8k_pcie { #define AX_USER_DOMAIN_MASK 0x3 #define AX_USER_DOMAIN_SHIFT 4 +#define UNIT_SOFT_RESET_CONFIG_REG 0x268 + #define to_armada8k_pcie(x) dev_get_drvdata((x)->dev) static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie) @@ -224,6 +231,49 @@ static int armada8k_pcie_host_init(struct pcie_port *pp) return 0; } +static void armada8k_pcie_recover_link(struct work_struct *ws) +{ + struct armada8k_pcie *pcie = container_of(ws, struct armada8k_pcie, recover_link_work); + struct pcie_port *pp = &pcie->pci->pp; + struct pci_bus *bus = pp->bridge->bus; + struct pci_dev *root_port; + int ret; + + root_port = pci_get_slot(bus, 0); + if (!root_port) { + dev_err(pcie->pci->dev, "failed to get root port\n"); + return; + } + pci_lock_rescan_remove(); + pci_stop_and_remove_bus_device(root_port); + /* + * Sleep needed to make sure all pcie transactions and access + * are flushed before resetting the mac + */ + msleep(100); + + /* Reset mac */ + regmap_update_bits_base(pcie->sysctrl_base, UNIT_SOFT_RESET_CONFIG_REG, + pcie->mac_rest_bitmask, 0, NULL, false, true); + udelay(1); + regmap_update_bits_base(pcie->sysctrl_base, UNIT_SOFT_RESET_CONFIG_REG, + pcie->mac_rest_bitmask, pcie->mac_rest_bitmask, + NULL, false, true); + udelay(1); + ret = armada8k_pcie_host_init(pp); + if (ret) { + dev_err(pcie->pci->dev, "failed to initialize host: %d\n", ret); + pci_unlock_rescan_remove(); + pci_dev_put(root_port); + return; + } + + bus = NULL; + while ((bus = pci_find_next_bus(bus)) != NULL) + pci_rescan_bus(bus); + pci_unlock_rescan_remove(); + pci_dev_put(root_port); +} static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) { @@ -262,6 +312,9 @@ static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg) * initiate a link retrain. If link retrains were * possible, that is. */ + if (pcie->sysctrl_base && pcie->mac_rest_bitmask) + schedule_work(&pcie->recover_link_work); + dev_dbg(pci->dev, "%s: link went down\n", __func__); } @@ -330,6 +383,8 @@ static int armada8k_pcie_probe(struct platform_device *pdev) pcie->pci = pci; + INIT_WORK(&pcie->recover_link_work, armada8k_pcie_recover_link); + pcie->clk = devm_clk_get(dev, NULL); if (IS_ERR(pcie->clk)) return PTR_ERR(pcie->clk); @@ -357,6 +412,19 @@ static int armada8k_pcie_probe(struct platform_device *pdev) goto fail_clkreg; } + pcie->sysctrl_base = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "marvell,system-controller"); + if (IS_ERR(pcie->sysctrl_base)) { + dev_warn(dev, "failed to find marvell,system-controller\n"); + pcie->sysctrl_base = 0x0; + } + + ret = of_property_read_u32(pdev->dev.of_node, "marvell,mac-reset-bit-mask", + &pcie->mac_rest_bitmask); + if (ret < 0) { + dev_warn(dev, "couldn't find mac reset bit mask: %d\n", ret); + pcie->mac_rest_bitmask = 0x0; + } ret = armada8k_pcie_setup_phys(pcie); if (ret) goto fail_clkreg; From patchwork Mon Apr 12 15:30:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Peled X-Patchwork-Id: 12198333 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FB2EC43470 for ; Mon, 12 Apr 2021 15:31:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E072161246 for ; Mon, 12 Apr 2021 15:31:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242908AbhDLPb4 (ORCPT ); Mon, 12 Apr 2021 11:31:56 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:50708 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242898AbhDLPbu (ORCPT ); Mon, 12 Apr 2021 11:31:50 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 13CFUnNG024627; Mon, 12 Apr 2021 08:31:20 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=pfpt0220; bh=GymurhClTLZ4ST/n6Oo2CGklmnbA31pLqRq8fnRk7Yg=; b=cItsbCT3D2i0nD2xiPTTA5PGk2PQJGfSUoIrw1TR0UmN6x2suIhXj7aAw4iLBPuJC+Zm iLzobZlbS/CUAP3YxUkaCBvAFHVkKgpjRtVNZb1VkA8ekgrjv9CDholqalW/MtoqND05 o7QImIRnHUxmqmbDfkHBAtmZUNZsemNWCTDFtbhyR0/jWyTuPAVvYGAYv1NILIXeBrN0 0BrOwOSnm+W+kCb75v8Hwo8zq9vg0jgYx0Bj91lZiNYgBGwYj8VH5R5UQXD01ayCAEhI HqwPaRQIboe/Ufs+SHP9U/GnxwJJmeJO981Jx3Mn4nxkIAgMhWN6vzPDRlAMXY5lzAK6 wA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 37vpuu0d4y-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 12 Apr 2021 08:31:20 -0700 Received: from SC-EXCH04.marvell.com (10.93.176.84) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 12 Apr 2021 08:31:19 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 12 Apr 2021 08:31:18 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 12 Apr 2021 08:31:18 -0700 Received: from nw-bp.marvell.com (nw-bp.marvell.com [10.5.24.22]) by maili.marvell.com (Postfix) with ESMTP id 3EC3B3F7050; Mon, 12 Apr 2021 08:31:14 -0700 (PDT) From: To: , , CC: , , , , , , , , , , , , , , Subject: =?utf-8?q?=5B=E2=80=9DPATCH=E2=80=9D_3/5=5D_dt-bindings=3A_pci=3A_a?= =?utf-8?q?dd_system_controller_and_MAC_reset_bit_to_Armada_7K/8K_controller?= =?utf-8?q?_bindings?= Date: Mon, 12 Apr 2021 18:30:54 +0300 Message-ID: <1618241456-27200-4-git-send-email-bpeled@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618241456-27200-1-git-send-email-bpeled@marvell.com> References: <1618241456-27200-1-git-send-email-bpeled@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: ZvWg6RacSjyd6IIIF1KGIgKw8aW92UQF X-Proofpoint-ORIG-GUID: ZvWg6RacSjyd6IIIF1KGIgKw8aW92UQF X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-04-12_11:2021-04-12,2021-04-12 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ben Peled Adding optional system-controller and mac-reset-bit-mask needed for linkdown procedure. Signed-off-by: Ben Peled --- Documentation/devicetree/bindings/pci/pci-armada8k.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt index 7a813d0..2696e79 100644 --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt @@ -24,6 +24,10 @@ Optional properties: - phy-names: names of the PHYs corresponding to the number of lanes. Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for 2 PHYs. +- marvell,system-controller: address of system controller needed + in order to reset MAC used by link-down handle +- marvell,mac-reset-bit-mask: MAC reset bit of system controller + needed in order to reset MAC used by link-down handle Example: @@ -45,4 +49,6 @@ Example: interrupts = ; num-lanes = <1>; clocks = <&cpm_syscon0 1 13>; + marvell,system-controller = <&CP11X_LABEL(syscon0)>; + marvell,mac-reset-bit-mask = ; }; From patchwork Mon Apr 12 15:30:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Peled X-Patchwork-Id: 12198337 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFD1FC433B4 for ; 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Mon, 12 Apr 2021 08:31:25 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 12 Apr 2021 08:31:23 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 12 Apr 2021 08:31:23 -0700 Received: from nw-bp.marvell.com (nw-bp.marvell.com [10.5.24.22]) by maili.marvell.com (Postfix) with ESMTP id 9E8273F7040; Mon, 12 Apr 2021 08:31:18 -0700 (PDT) From: To: , , CC: , , , , , , , , , , , , , , Subject: =?utf-8?q?=5B=E2=80=9DPATCH=E2=80=9D_4/5=5D_arm64=3A_dts=3A_marvell?= =?utf-8?q?=3A_add_pcie_mac_reset_to_pcie?= Date: Mon, 12 Apr 2021 18:30:55 +0300 Message-ID: <1618241456-27200-5-git-send-email-bpeled@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618241456-27200-1-git-send-email-bpeled@marvell.com> References: <1618241456-27200-1-git-send-email-bpeled@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: xxF7JF9ABn3SlXK77lCc09HyVPk6wxZ4 X-Proofpoint-ORIG-GUID: xxF7JF9ABn3SlXK77lCc09HyVPk6wxZ4 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-04-12_11:2021-04-12,2021-04-12 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ben Peled Add system controller and reset bit to each pcie to enable pcie mac reset Signed-off-by: Ben Peled --- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 9dcf16b..eb60e73 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -11,6 +11,7 @@ #include "armada-common.dtsi" #define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface)) +#define CP11X_PCIEx_MAC_RESET_BIT_MASK(n) (0x1 << 11 + ((n + 2) % 3)) / { /* @@ -513,6 +514,8 @@ num-lanes = <1>; clock-names = "core", "reg"; clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>; + marvell,system-controller = <&CP11X_LABEL(syscon0)>; + marvell,mac-reset-bit-mask = ; status = "disabled"; }; @@ -538,6 +541,8 @@ num-lanes = <1>; clock-names = "core", "reg"; clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>; + marvell,system-controller = <&CP11X_LABEL(syscon0)>; + marvell,mac-reset-bit-mask = ; status = "disabled"; }; @@ -563,6 +568,8 @@ num-lanes = <1>; clock-names = "core", "reg"; clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>; + marvell,system-controller = <&CP11X_LABEL(syscon0)>; + marvell,mac-reset-bit-mask = ; status = "disabled"; }; }; From patchwork Mon Apr 12 15:30:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Peled X-Patchwork-Id: 12198339 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC468C433B4 for ; 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Mon, 12 Apr 2021 08:31:28 -0700 Received: from SC-EXCH04.marvell.com (10.93.176.84) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 12 Apr 2021 08:31:27 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 12 Apr 2021 08:31:27 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 12 Apr 2021 08:31:27 -0700 Received: from nw-bp.marvell.com (nw-bp.marvell.com [10.5.24.22]) by maili.marvell.com (Postfix) with ESMTP id F3DE73F7043; Mon, 12 Apr 2021 08:31:22 -0700 (PDT) From: To: , , CC: , , , , , , , , , , , , , , Subject: =?utf-8?q?=5B=E2=80=9DPATCH=E2=80=9D_5/5=5D_PCI=3A_armada8k=3A_add_?= =?utf-8?q?device_reset_to_link-down_handle?= Date: Mon, 12 Apr 2021 18:30:56 +0300 Message-ID: <1618241456-27200-6-git-send-email-bpeled@marvell.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1618241456-27200-1-git-send-email-bpeled@marvell.com> References: <1618241456-27200-1-git-send-email-bpeled@marvell.com> MIME-Version: 1.0 X-Proofpoint-GUID: YDRy_dGnY5Gad4s8J5DMr13f1F-C1kzp X-Proofpoint-ORIG-GUID: YDRy_dGnY5Gad4s8J5DMr13f1F-C1kzp X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-04-12_11:2021-04-12,2021-04-12 signatures=0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Ben Peled Added pcie reset via gpio support as described in the designware-pcie.txt DT binding document. In cases link down cause still exist in device. The device need to be reset to reestablish the link. If reset-gpio pin provided in the device tree, then the linkdown handle resets the device before reestablishing link. Signed-off-by: Ben Peled --- drivers/pci/controller/dwc/pcie-armada8k.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-armada8k.c b/drivers/pci/controller/dwc/pcie-armada8k.c index 4eb8607..83ac91e 100644 --- a/drivers/pci/controller/dwc/pcie-armada8k.c +++ b/drivers/pci/controller/dwc/pcie-armada8k.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "pcie-designware.h" @@ -38,6 +39,7 @@ struct armada8k_pcie { struct regmap *sysctrl_base; u32 mac_rest_bitmask; struct work_struct recover_link_work; + enum of_gpio_flags flags; }; #define PCIE_VENDOR_REGS_OFFSET 0x8000