From patchwork Thu Nov 22 21:40:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 10694895 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 564B65A4 for ; Thu, 22 Nov 2018 21:40:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 46CC62CBED for ; Thu, 22 Nov 2018 21:40:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3B1BD2CC45; Thu, 22 Nov 2018 21:40:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D9F992CBED for ; Thu, 22 Nov 2018 21:40:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2407523AbeKWIVn (ORCPT ); Fri, 23 Nov 2018 03:21:43 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:37056 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2392318AbeKWIVm (ORCPT ); Fri, 23 Nov 2018 03:21:42 -0500 Received: by mail-wm1-f66.google.com with SMTP id p2-v6so10283936wmc.2; Thu, 22 Nov 2018 13:40:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c35wEySsf8pHFZUenvpaQ26wiyDQ3+mASoSpr1z00aE=; b=unhWHO96JHXhR6zCO/TRUi9gnUx205dtNDO6NlEiNLn6dzfSOO9jq48q+r2zdhNiLG DFc4AcTx1F3Nz15i+SaBi24K1L55yM61DRKVsofQYLCYT0jUkBDi+0V4zTPdqdKiNgBI nt3st8GaRbgOsMhY5wCMXHQpBtfJiQiSQyQlpf+Zvg3aEfyzNYhEQqvuEtbrRqwh3hS/ KbZICVWgkxVMY5RBM1SS/16Sf97tCJBwLUYKsQnZCjo8BvQ7+umSqc95mkqR5F2l8e8D TYkCeEkvKZf841GmXdnSDbzZfYReUiZZ/rsCIADc4putukj7mXasfYcpxx4FQeNTvRLx bo8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c35wEySsf8pHFZUenvpaQ26wiyDQ3+mASoSpr1z00aE=; b=jYAmvitCDcY3O+DuqRlj0PvVTbB6jX21TZHK7vDl5QgS5KoSeg6/CIimmrLUJFLaCx dgMCI6KHeiZ25Sls4ZUmcNWUr/aII+sUuczxogfmgkDKjRFGybEbX4MoaB3eWTW4r8qb B+Pdy6nZ3pBCB4MhqliKjuqAWvUEvrHXvVKxUs2B0mcSdN6lIG5DGH2fTjqINoVEoaAn 5rqQhI3Te5M6l5mAtr3nHlUYoB8Tkqxbe4uDRWVvwKRHwFEBikAKoOFMwCc6L/UDsxUy menDiYRSQ1VlwZlxDrl9e/KCreosN9deqbE0lGX5IGtCCyKBM1iCFquSLYSxCFcT2UP0 KeoA== X-Gm-Message-State: AGRZ1gKZwZcFgNQPd4ZYFrPy4Xi2a71KCN4FclBzmr+FjGQc2KVcXXLQ VILepKyjX8Axd5XEYwBR29E= X-Google-Smtp-Source: AFSGD/XdGcWblshyY+GHZ6J5PRI+qWtybkR9dWixf6Z90dRcmpWAmZjn4/a9x4jdf5YiAtc9G37yug== X-Received: by 2002:a1c:ccb:: with SMTP id 194-v6mr11794328wmm.102.1542922826150; Thu, 22 Nov 2018 13:40:26 -0800 (PST) Received: from blackbox.darklights.net (p200300DCD732F5007DE18DA1F72FF8D9.dip0.t-ipconnect.de. [2003:dc:d732:f500:7de1:8da1:f72f:f8d9]) by smtp.googlemail.com with ESMTPSA id x14sm29755554wrm.65.2018.11.22.13.40.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 22 Nov 2018 13:40:25 -0800 (PST) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, narmstrong@baylibre.com, jbrunet@baylibre.com Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH v2 1/4] dt-bindings: clock: meson8b: export the CPU post dividers Date: Thu, 22 Nov 2018 22:40:14 +0100 Message-Id: <20181122214017.25643-2-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181122214017.25643-1-martin.blumenstingl@googlemail.com> References: <20181122214017.25643-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There are four CPU clock post dividers: - ABP - PERIPH (used as input for the ARM global timer and ARM TWD timer) - AXI - L2 DRAM Export these so we can use them in .dts files. Signed-off-by: Martin Blumenstingl Acked-by: Jerome Brunet --- include/dt-bindings/clock/meson8b-clkc.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h index a60f47b49231..5fe2923382d0 100644 --- a/include/dt-bindings/clock/meson8b-clkc.h +++ b/include/dt-bindings/clock/meson8b-clkc.h @@ -103,5 +103,9 @@ #define CLKID_MPLL1 94 #define CLKID_MPLL2 95 #define CLKID_NAND_CLK 112 +#define CLKID_ABP 124 +#define CLKID_PERIPH 126 +#define CLKID_AXI 128 +#define CLKID_L2_DRAM 130 #endif /* __MESON8B_CLKC_H */ From patchwork Thu Nov 22 21:40:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 10694885 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C95E716B1 for ; Thu, 22 Nov 2018 21:40:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BA18F2CBED for ; Thu, 22 Nov 2018 21:40:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id AE55B2CC3A; Thu, 22 Nov 2018 21:40:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 53D032CBED for ; Thu, 22 Nov 2018 21:40:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2407537AbeKWIVo (ORCPT ); Fri, 23 Nov 2018 03:21:44 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:33341 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2392303AbeKWIVn (ORCPT ); Fri, 23 Nov 2018 03:21:43 -0500 Received: by mail-wm1-f65.google.com with SMTP id 79so10366683wmo.0; Thu, 22 Nov 2018 13:40:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b9M5DcWvweBjr9MSqSee+Ke/uuzQ3f30SLXtYeUgc+M=; b=UEXDe6QItdSuH3bNff1e1akAKk6mkD3tlHnQbqprXE8ssCVhJnqK+hHtK8fvWwWiwg IbH+5XXQpOyXfEKc5NJPJTIaMEWsg1yNonm+XSHQVaa8F/5Up8yPlG7w/L0t84gouf/p kF4xwl8ROBpFX7z9BzGo+QLuMYoxMQahf42kx196Y16L9qyBimTM5t1YCSGhJpvbAs7m dmAh3V8dGN+y4ae2JgqObZZ5ckn6U7zomWYSDlcoV8SFct+apl2QYwvO54DdbkWSzTua aBKi0ggHWbNPOqpqALq34JODwpPt616Dqq+EhyJMqR8s3dn+nOs4+dUnW4Ms0uN2kzPD Hv9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b9M5DcWvweBjr9MSqSee+Ke/uuzQ3f30SLXtYeUgc+M=; b=BFEt+yJ7piS7x9yAPsEJeNImvxO3VE9ccdORcJV49/YtyVTExIHyQdpIATmfnL+qa4 Q1hKPhBYNSzSBx0CEna9iix9GLAm7TIRakC1Js5Tzm1rlH/e6k8t1jByFf4uWzmmqJsS TQi2LPuYfzhPgaL/A+nw9yiDB44nVC6uSDMPJ8G7YLMju4090BUiuko80RwudD4ca/SZ t5nM3ngL41ILo9pSKGAoOYWorPL5BwxcYTnwQEV5q3xZwoG/oJ9Nm8VquohtqzROq68i NS5WYKiphzRqjo9LQfO/E8UH6RPDF9wtrlVTCyc29KLuL3FPMWhA35wB+iaT5FZq4on/ 0PhQ== X-Gm-Message-State: AA+aEWZzvYoMKJCTI/po71wUrqnGBn2Qq1YufgMJYsJTnbDJ6a7hWD2t KRoA5f0T+Zg3vyghdCvd9jw= X-Google-Smtp-Source: AJdET5fNiPpDlyTLDu6CgaP3zgmU4rBXdeViebX02cZkJNOM9Yl5k5LGiDklIL0DZ0gpnxw9RM9z0g== X-Received: by 2002:a1c:cb4c:: with SMTP id b73mr12010713wmg.69.1542922827423; Thu, 22 Nov 2018 13:40:27 -0800 (PST) Received: from blackbox.darklights.net (p200300DCD732F5007DE18DA1F72FF8D9.dip0.t-ipconnect.de. [2003:dc:d732:f500:7de1:8da1:f72f:f8d9]) by smtp.googlemail.com with ESMTPSA id x14sm29755554wrm.65.2018.11.22.13.40.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 22 Nov 2018 13:40:26 -0800 (PST) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, narmstrong@baylibre.com, jbrunet@baylibre.com Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH v2 2/4] clk: meson: clk-regmap: add read-only gate ops Date: Thu, 22 Nov 2018 22:40:15 +0100 Message-Id: <20181122214017.25643-3-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181122214017.25643-1-martin.blumenstingl@googlemail.com> References: <20181122214017.25643-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Some of the gate clocks are described as "just in case" bits in the datasheet. Examples are the ABP, PERIPH, AXI and L2 DRAM clocks on Meson8b. The datasheet suggests that these bits are not touched. The full explanation is: "Set to 1 to manually disable the [...] clock when changing the mux selection. Typically this bit is set to 0 since the clock muxes can switch without glitches.". This adds new read-only ops for gate clocks so we can describe these clocks in our clock controller drivers while ensuring that we can't accidentally modify the registers. Signed-off-by: Martin Blumenstingl Acked-by: Neil Armstrong --- drivers/clk/meson/clk-regmap.c | 5 +++++ drivers/clk/meson/clk-regmap.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/clk/meson/clk-regmap.c b/drivers/clk/meson/clk-regmap.c index 305ee307c003..c515f67322a3 100644 --- a/drivers/clk/meson/clk-regmap.c +++ b/drivers/clk/meson/clk-regmap.c @@ -50,6 +50,11 @@ const struct clk_ops clk_regmap_gate_ops = { }; EXPORT_SYMBOL_GPL(clk_regmap_gate_ops); +const struct clk_ops clk_regmap_gate_ro_ops = { + .is_enabled = clk_regmap_gate_is_enabled, +}; +EXPORT_SYMBOL_GPL(clk_regmap_gate_ro_ops); + static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw, unsigned long prate) { diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h index ed2d4348dbe2..e9c5728d40eb 100644 --- a/drivers/clk/meson/clk-regmap.h +++ b/drivers/clk/meson/clk-regmap.h @@ -51,6 +51,7 @@ clk_get_regmap_gate_data(struct clk_regmap *clk) } extern const struct clk_ops clk_regmap_gate_ops; +extern const struct clk_ops clk_regmap_gate_ro_ops; /** * struct clk_regmap_div_data - regmap backed adjustable divider specific data From patchwork Thu Nov 22 21:40:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Martin Blumenstingl X-Patchwork-Id: 10694893 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1B94A1709 for ; Thu, 22 Nov 2018 21:40:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0B3922CC30 for ; Thu, 22 Nov 2018 21:40:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F39502CC71; Thu, 22 Nov 2018 21:40:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 960212CC30 for ; Thu, 22 Nov 2018 21:40:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2392303AbeKWIVo (ORCPT ); Fri, 23 Nov 2018 03:21:44 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:38652 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2407522AbeKWIVo (ORCPT ); Fri, 23 Nov 2018 03:21:44 -0500 Received: by mail-wm1-f66.google.com with SMTP id k198so10360525wmd.3; Thu, 22 Nov 2018 13:40:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DownjwjeOEnZH3e88ykBjvED3HOTGAzn5RoqAbXS+qA=; b=W7EqpwoufhiW52oKaFV8zmAwVwCbly9g/Kp0fQuBw37Y22K2iuhtdmrSgzgmePsj+n YQMkolFBaaWTXAxe/3t0sh/eT9PRFQ5Wa92rtrI4ND52Dzo2SLwci7dRdcXsjCo9ZkfA 2PdzqP1kMGWVksabKMqNh+IgHRiTWWOQG/CFo3lwOZdiHz6cTdS0WQcB3hhoeWUZkX82 MzTOCLeIiZII4wROHaCpUhfowuZcN6bl3NiKFUoQk3XkWuva5322cbGp7+IMlfJ5JSN6 Fo7cIr31tqeOvAEtoLslB9kc0+f32CwvaYKSqeLKUHXyj9HYzyVRdxQdWunsAyvSnCwn zxSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DownjwjeOEnZH3e88ykBjvED3HOTGAzn5RoqAbXS+qA=; b=syS9hHxDxAjhVzcf9mJxxInPYzzUEknuZG38IcswwtxJBAY6POj9zs3J36akmVnv47 KnwG/rOzF47Heyp5o8wSEcRZFKor4BLl9GyW1TaypBzp0Mc4g2I/7VeyCT21x65YS4bc 1PYVGbN6I4XRHAOPHoNr9n7pVJyEyedqqKkOOdwppfoejwqI45dS0ysnkDRO4pXOlMrZ gG0sYzQebXL9tStMwLB6wKyvaq/F411R6QmqEWHrT4JlFsJV4kzRlX5AHB4UqRXGcg/n 0w+VuVn4htZKUdnUHVt7q4py6rCYkv64AqxM3W38AiQXHE7AB/zjUqKJlqDXBbyclU6z czQQ== X-Gm-Message-State: AGRZ1gIZ7pa54YUghM2UcFEtzRGuizyAJs/z4UbvmtSLNqGmTI9w4+cs tyuKxKvxlNuwyKFEAMJ4I8Q= X-Google-Smtp-Source: AFSGD/XDnHNF1qWcHGFT3fRwS02TvIwwxiWnXZqaCAaQvwA6urL+H6xZwO+Gg8ZDOPXweFl4ribSUg== X-Received: by 2002:a1c:d14d:: with SMTP id i74mr10716213wmg.100.1542922828527; Thu, 22 Nov 2018 13:40:28 -0800 (PST) Received: from blackbox.darklights.net (p200300DCD732F5007DE18DA1F72FF8D9.dip0.t-ipconnect.de. [2003:dc:d732:f500:7de1:8da1:f72f:f8d9]) by smtp.googlemail.com with ESMTPSA id x14sm29755554wrm.65.2018.11.22.13.40.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 22 Nov 2018 13:40:27 -0800 (PST) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, narmstrong@baylibre.com, jbrunet@baylibre.com Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH v2 3/4] clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3 Date: Thu, 22 Nov 2018 22:40:16 +0100 Message-Id: <20181122214017.25643-4-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181122214017.25643-1-martin.blumenstingl@googlemail.com> References: <20181122214017.25643-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The "cpu_div2" and "cpu_div3" take "cpu_in" as input and divide that by 2 or 3. The clock controller can also generate various CPU clock post-dividers (2, 3, 4, 5, 6, 7, 8) which are derived from "cpu_clk". When adding support for these post-dividers our clock naming could be misleading as we have "cpu_div2" as well as "cpu_clk_div2". Rename the existing "cpu_in" dividers so the name of the divider's parent is part of the divider clock's name. Signed-off-by: Martin Blumenstingl Acked-by: Jerome Brunet --- drivers/clk/meson/meson8b.c | 20 ++++++++++---------- drivers/clk/meson/meson8b.h | 4 ++-- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index b3bdc7e05441..010dccc86b5d 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -560,11 +560,11 @@ static struct clk_regmap meson8b_cpu_in_sel = { }, }; -static struct clk_fixed_factor meson8b_cpu_div2 = { +static struct clk_fixed_factor meson8b_cpu_in_div2 = { .mult = 1, .div = 2, .hw.init = &(struct clk_init_data){ - .name = "cpu_div2", + .name = "cpu_in_div2", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "cpu_in_sel" }, .num_parents = 1, @@ -572,11 +572,11 @@ static struct clk_fixed_factor meson8b_cpu_div2 = { }, }; -static struct clk_fixed_factor meson8b_cpu_div3 = { +static struct clk_fixed_factor meson8b_cpu_in_div3 = { .mult = 1, .div = 3, .hw.init = &(struct clk_init_data){ - .name = "cpu_div3", + .name = "cpu_in_div3", .ops = &clk_fixed_factor_ops, .parent_names = (const char *[]){ "cpu_in_sel" }, .num_parents = 1, @@ -626,12 +626,12 @@ static struct clk_regmap meson8b_cpu_scale_out_sel = { .ops = &clk_regmap_mux_ops, /* * NOTE: We are skipping the parent with value 0x2 (which is - * "cpu_div3") because it results in a duty cycle of 33% which - * makes the system unstable and can result in a lockup of the - * whole system. + * "cpu_in_div3") because it results in a duty cycle of 33% + * which makes the system unstable and can result in a lockup + * of the whole system. */ .parent_names = (const char *[]) { "cpu_in_sel", - "cpu_div2", + "cpu_in_div2", "cpu_scale_div" }, .num_parents = 3, .flags = CLK_SET_RATE_PARENT, @@ -889,8 +889,8 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw, [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw, [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw, - [CLKID_CPU_DIV2] = &meson8b_cpu_div2.hw, - [CLKID_CPU_DIV3] = &meson8b_cpu_div3.hw, + [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw, + [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw, [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw, [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw, [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw, diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index 1c6fb180e6a2..9cba34c6cb92 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -63,8 +63,8 @@ #define CLKID_MPLL1_DIV 97 #define CLKID_MPLL2_DIV 98 #define CLKID_CPU_IN_SEL 99 -#define CLKID_CPU_DIV2 100 -#define CLKID_CPU_DIV3 101 +#define CLKID_CPU_IN_DIV2 100 +#define CLKID_CPU_IN_DIV3 101 #define CLKID_CPU_SCALE_DIV 102 #define CLKID_CPU_SCALE_OUT_SEL 103 #define CLKID_MPLL_PREDIV 104 From patchwork Thu Nov 22 21:40:17 2018 Content-Type: text/plain; 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[2003:dc:d732:f500:7de1:8da1:f72f:f8d9]) by smtp.googlemail.com with ESMTPSA id x14sm29755554wrm.65.2018.11.22.13.40.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 22 Nov 2018 13:40:29 -0800 (PST) From: Martin Blumenstingl To: linux-amlogic@lists.infradead.org, narmstrong@baylibre.com, jbrunet@baylibre.com Cc: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Martin Blumenstingl Subject: [PATCH v2 4/4] clk: meson: meson8b: add the CPU clock post divider clocks Date: Thu, 22 Nov 2018 22:40:17 +0100 Message-Id: <20181122214017.25643-5-martin.blumenstingl@googlemail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20181122214017.25643-1-martin.blumenstingl@googlemail.com> References: <20181122214017.25643-1-martin.blumenstingl@googlemail.com> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There are four CPU clock post dividers: - ABP - PERIPH (used for the ARM global timer and ARM TWD timer) - AXI - L2 DRAM Each of these clocks consists of two clocks: - a mux to select between "cpu_clk" divided by 2, 3, 4, 5, 6, 7 or 8 - a "_clk_dis" gate. The public S805 datasheet states that this should be set to 1 to disable the clock, the default value is 0. There is also a hint that these are "just in case" bits which only exist in case the corresponding mux implementation does not allow glitch-free parent changes (the muxes are designed in a way that the clock can stay enabled when changing the mux). It's still good practise to describe this clock even if we're not supposed to modify it. Thus this uses the read-only gate ops. Signed-off-by: Martin Blumenstingl Acked-by: Jerome Brunet --- drivers/clk/meson/meson8b.c | 244 ++++++++++++++++++++++++++++++++++++ drivers/clk/meson/meson8b.h | 13 +- 2 files changed, 256 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 010dccc86b5d..f906a9f0eefd 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -704,6 +704,227 @@ static struct clk_regmap meson8b_nand_clk_gate = { }, }; +static struct clk_fixed_factor meson8b_cpu_clk_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div2", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_cpu_clk_div3 = { + .mult = 1, + .div = 3, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div3", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_cpu_clk_div4 = { + .mult = 1, + .div = 4, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div4", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_cpu_clk_div5 = { + .mult = 1, + .div = 5, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div5", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_cpu_clk_div6 = { + .mult = 1, + .div = 6, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div6", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_cpu_clk_div7 = { + .mult = 1, + .div = 7, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div7", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static struct clk_fixed_factor meson8b_cpu_clk_div8 = { + .mult = 1, + .div = 8, + .hw.init = &(struct clk_init_data){ + .name = "cpu_clk_div8", + .ops = &clk_fixed_factor_ops, + .parent_names = (const char *[]){ "cpu_clk" }, + .num_parents = 1, + }, +}; + +static u32 mux_table_abp[] = { 1, 2, 3, 4, 5, 6, 7 }; +static struct clk_regmap meson8b_abp_clk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .mask = 0x7, + .shift = 3, + .table = mux_table_abp, + }, + .hw.init = &(struct clk_init_data){ + .name = "abp_clk_sel", + .ops = &clk_regmap_mux_ops, + .parent_names = (const char *[]){ "cpu_clk_div2", + "cpu_clk_div3", + "cpu_clk_div4", + "cpu_clk_div5", + "cpu_clk_div6", + "cpu_clk_div7", + "cpu_clk_div8", }, + .num_parents = 7, + }, +}; + +static struct clk_regmap meson8b_abp_clk_gate = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .bit_idx = 16, + .flags = CLK_GATE_SET_TO_DISABLE, + }, + .hw.init = &(struct clk_init_data){ + .name = "abp_clk_dis", + .ops = &clk_regmap_gate_ro_ops, + .parent_names = (const char *[]){ "abp_clk_sel" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap meson8b_periph_clk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .mask = 0x7, + .shift = 6, + }, + .hw.init = &(struct clk_init_data){ + .name = "periph_clk_sel", + .ops = &clk_regmap_mux_ops, + .parent_names = (const char *[]){ "cpu_clk_div2", + "cpu_clk_div3", + "cpu_clk_div4", + "cpu_clk_div5", + "cpu_clk_div6", + "cpu_clk_div7", + "cpu_clk_div8", }, + .num_parents = 7, + }, +}; + +static struct clk_regmap meson8b_periph_clk_gate = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .bit_idx = 17, + .flags = CLK_GATE_SET_TO_DISABLE, + }, + .hw.init = &(struct clk_init_data){ + .name = "periph_clk_dis", + .ops = &clk_regmap_gate_ro_ops, + .parent_names = (const char *[]){ "periph_clk_sel" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static u32 mux_table_axi[] = { 1, 2, 3, 4, 5, 6, 7 }; +static struct clk_regmap meson8b_axi_clk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .mask = 0x7, + .shift = 9, + .table = mux_table_axi, + }, + .hw.init = &(struct clk_init_data){ + .name = "axi_clk_sel", + .ops = &clk_regmap_mux_ops, + .parent_names = (const char *[]){ "cpu_clk_div2", + "cpu_clk_div3", + "cpu_clk_div4", + "cpu_clk_div5", + "cpu_clk_div6", + "cpu_clk_div7", + "cpu_clk_div8", }, + .num_parents = 7, + }, +}; + +static struct clk_regmap meson8b_axi_clk_gate = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .bit_idx = 18, + .flags = CLK_GATE_SET_TO_DISABLE, + }, + .hw.init = &(struct clk_init_data){ + .name = "axi_clk_dis", + .ops = &clk_regmap_gate_ro_ops, + .parent_names = (const char *[]){ "axi_clk_sel" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap meson8b_l2_dram_clk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .mask = 0x7, + .shift = 12, + }, + .hw.init = &(struct clk_init_data){ + .name = "l2_dram_clk_sel", + .ops = &clk_regmap_mux_ops, + .parent_names = (const char *[]){ "cpu_clk_div2", + "cpu_clk_div3", + "cpu_clk_div4", + "cpu_clk_div5", + "cpu_clk_div6", + "cpu_clk_div7", + "cpu_clk_div8", }, + .num_parents = 7, + }, +}; + +static struct clk_regmap meson8b_l2_dram_clk_gate = { + .data = &(struct clk_regmap_gate_data){ + .offset = HHI_SYS_CPU_CLK_CNTL1, + .bit_idx = 19, + .flags = CLK_GATE_SET_TO_DISABLE, + }, + .hw.init = &(struct clk_init_data){ + .name = "l2_dram_clk_dis", + .ops = &clk_regmap_gate_ro_ops, + .parent_names = (const char *[]){ "l2_dram_clk_sel" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + /* Everything Else (EE) domain gates */ static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0); @@ -905,6 +1126,21 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw, [CLKID_PLL_VID_DCO] = &meson8b_vid_pll_dco.hw, [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw, + [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw, + [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw, + [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw, + [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw, + [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw, + [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw, + [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw, + [CLKID_ABP_SEL] = &meson8b_abp_clk_sel.hw, + [CLKID_ABP] = &meson8b_abp_clk_gate.hw, + [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw, + [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw, + [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw, + [CLKID_AXI] = &meson8b_axi_clk_gate.hw, + [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw, + [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw, [CLK_NR_CLKS] = NULL, }, .num = CLK_NR_CLKS, @@ -1016,6 +1252,14 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { &meson8b_fixed_pll_dco, &meson8b_vid_pll_dco, &meson8b_sys_pll_dco, + &meson8b_abp_clk_sel, + &meson8b_abp_clk_gate, + &meson8b_periph_clk_sel, + &meson8b_periph_clk_gate, + &meson8b_axi_clk_sel, + &meson8b_axi_clk_gate, + &meson8b_l2_dram_clk_sel, + &meson8b_l2_dram_clk_gate, }; static const struct meson8b_clk_reset_line { diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index 9cba34c6cb92..0abb331162ab 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -78,8 +78,19 @@ #define CLKID_PLL_FIXED_DCO 113 #define CLKID_PLL_VID_DCO 114 #define CLKID_PLL_SYS_DCO 115 +#define CLKID_CPU_CLK_DIV2 116 +#define CLKID_CPU_CLK_DIV3 117 +#define CLKID_CPU_CLK_DIV4 118 +#define CLKID_CPU_CLK_DIV5 119 +#define CLKID_CPU_CLK_DIV6 120 +#define CLKID_CPU_CLK_DIV7 121 +#define CLKID_CPU_CLK_DIV8 122 +#define CLKID_ABP_SEL 123 +#define CLKID_PERIPH_SEL 125 +#define CLKID_AXI_SEL 127 +#define CLKID_L2_DRAM_SEL 129 -#define CLK_NR_CLKS 116 +#define CLK_NR_CLKS 131 /* * include the CLKID and RESETID that have