From patchwork Wed Apr 14 02:23:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12201739 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19F58C433B4 for ; Wed, 14 Apr 2021 02:23:20 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CD6D9610E8 for ; Wed, 14 Apr 2021 02:23:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CD6D9610E8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B5A856E429; Wed, 14 Apr 2021 02:23:17 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id C63436E429 for ; Wed, 14 Apr 2021 02:23:16 +0000 (UTC) IronPort-SDR: nBt8sxyi5Bs4NirDu1tctEiMUMozCJYiAhHyRqP92ul3kijsutO+0LZWvbCvK5fPo57mW1EoEE Lq5ZvyCgvixg== X-IronPort-AV: E=McAfee;i="6200,9189,9953"; a="194110982" X-IronPort-AV: E=Sophos;i="5.82,221,1613462400"; d="scan'208";a="194110982" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2021 19:23:15 -0700 IronPort-SDR: OECLkUIS8rvdIMpXQGtoSK0y6h2Nm5BXYfeL87HZHx35N6VsPG4xwmxPruFiSaFgdIjCMBUv2r EyRh+Cv24nGQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,221,1613462400"; d="scan'208";a="460816558" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga001.jf.intel.com with SMTP; 13 Apr 2021 19:23:13 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 14 Apr 2021 05:23:12 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Wed, 14 Apr 2021 05:23:02 +0300 Message-Id: <20210414022309.30898-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210414022309.30898-1-ville.syrjala@linux.intel.com> References: <20210414022309.30898-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/8] drm/i915: Add frontbuffer tracking tracepoints X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Add some tracpoints for frontbuffer tracking so we can try to figure out what's going on. Signed-off-by: Ville Syrjälä Acked-by: Jani Nikula --- .../gpu/drm/i915/display/intel_frontbuffer.c | 5 +++ drivers/gpu/drm/i915/i915_trace.h | 38 +++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c index 6fc6965b6133..8161d49e78ba 100644 --- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c +++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c @@ -58,6 +58,7 @@ #include "display/intel_dp.h" #include "i915_drv.h" +#include "i915_trace.h" #include "intel_display_types.h" #include "intel_fbc.h" #include "intel_frontbuffer.h" @@ -87,6 +88,8 @@ static void frontbuffer_flush(struct drm_i915_private *i915, if (!frontbuffer_bits) return; + trace_intel_frontbuffer_flush(frontbuffer_bits, origin); + might_sleep(); intel_edp_drrs_flush(i915, frontbuffer_bits); intel_psr_flush(i915, frontbuffer_bits, origin); @@ -173,6 +176,8 @@ void __intel_fb_invalidate(struct intel_frontbuffer *front, spin_unlock(&i915->fb_tracking.lock); } + trace_intel_frontbuffer_invalidate(frontbuffer_bits, origin); + might_sleep(); intel_psr_invalidate(i915, frontbuffer_bits, origin); intel_edp_drrs_invalidate(i915, frontbuffer_bits); diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h index a4addcc64978..81f5e1721180 100644 --- a/drivers/gpu/drm/i915/i915_trace.h +++ b/drivers/gpu/drm/i915/i915_trace.h @@ -474,6 +474,44 @@ TRACE_EVENT(intel_pipe_update_end, __entry->scanline) ); +/* frontbuffer tracking */ + +TRACE_EVENT(intel_frontbuffer_invalidate, + TP_PROTO(unsigned int frontbuffer_bits, unsigned int origin), + TP_ARGS(frontbuffer_bits, origin), + + TP_STRUCT__entry( + __field(unsigned int, frontbuffer_bits) + __field(unsigned int, origin) + ), + + TP_fast_assign( + __entry->frontbuffer_bits = frontbuffer_bits; + __entry->origin = origin; + ), + + TP_printk("frontbuffer_bits=0x%08x, origin=%u", + __entry->frontbuffer_bits, __entry->origin) +); + +TRACE_EVENT(intel_frontbuffer_flush, + TP_PROTO(unsigned int frontbuffer_bits, unsigned int origin), + TP_ARGS(frontbuffer_bits, origin), + + TP_STRUCT__entry( + __field(unsigned int, frontbuffer_bits) + __field(unsigned int, origin) + ), + + TP_fast_assign( + __entry->frontbuffer_bits = frontbuffer_bits; + __entry->origin = origin; + ), + + TP_printk("frontbuffer_bits=0x%08x, origin=%u", + __entry->frontbuffer_bits, __entry->origin) +); + /* object tracking */ TRACE_EVENT(i915_gem_object_create, From patchwork Wed Apr 14 02:23:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12201741 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AEB52C43460 for ; Wed, 14 Apr 2021 02:23:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 71CD66100B for ; Wed, 14 Apr 2021 02:23:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 71CD66100B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DA5A96E42C; Wed, 14 Apr 2021 02:23:20 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id D781E6E42C for ; Wed, 14 Apr 2021 02:23:19 +0000 (UTC) IronPort-SDR: o1dju/xcQS/3zW0bFj8wUEvo0YyZDQDrd18XzKPsLGIBxNZyuVL7k8aaRVmh/Am1tZ8DN57j0M t6aY0u+ZtXng== X-IronPort-AV: E=McAfee;i="6200,9189,9953"; a="191361644" X-IronPort-AV: E=Sophos;i="5.82,221,1613462400"; d="scan'208";a="191361644" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2021 19:23:19 -0700 IronPort-SDR: HEeAK84GpdmPe2XsMrlNQxbSZFakUgAQM8/+GPkMxSR7cD7DfSUCSBPSZnNlv+jGBlMx0lCktV hFKAO7oJOJPA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,221,1613462400"; d="scan'208";a="521825847" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga001.fm.intel.com with SMTP; 13 Apr 2021 19:23:16 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 14 Apr 2021 05:23:15 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Wed, 14 Apr 2021 05:23:03 +0300 Message-Id: <20210414022309.30898-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210414022309.30898-1-ville.syrjala@linux.intel.com> References: <20210414022309.30898-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/8] drm/i915: Rewrite the FBC tiling check a bit X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Write the tiling check in a nicer form. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_fbc.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 04d9c7d22b04..178243a6d3a2 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -681,11 +681,9 @@ static bool tiling_is_valid(struct drm_i915_private *dev_priv, { switch (modifier) { case DRM_FORMAT_MOD_LINEAR: - if (DISPLAY_VER(dev_priv) >= 9) - return true; - return false; - case I915_FORMAT_MOD_X_TILED: case I915_FORMAT_MOD_Y_TILED: + return DISPLAY_VER(dev_priv) >= 9; + case I915_FORMAT_MOD_X_TILED: return true; default: return false; From patchwork Wed Apr 14 02:23:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12201743 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B63FAC433B4 for ; Wed, 14 Apr 2021 02:23:24 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7941F610E8 for ; Wed, 14 Apr 2021 02:23:24 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7941F610E8 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 145A86E42D; Wed, 14 Apr 2021 02:23:24 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 75FBF6E42D for ; Wed, 14 Apr 2021 02:23:22 +0000 (UTC) IronPort-SDR: MDxfzlcVfG2+sN7QKW+HzFJbFltmj7+tOPH71ICck89Nj6efzQ1eZLPY2k/0GhihAeDnR5G0Qn xFel0MPtRHIw== X-IronPort-AV: E=McAfee;i="6200,9189,9953"; a="174652197" X-IronPort-AV: E=Sophos;i="5.82,221,1613462400"; d="scan'208";a="174652197" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2021 19:23:21 -0700 IronPort-SDR: 9Jfw9ezqoaVcvk1eZZmzrvL96F+Dar25v70dpeD5E0PiNgY5DRSfeNNNeSLusC8W8cfYUckgsI mwvWkPEdrghA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,221,1613462400"; d="scan'208";a="398998603" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga002.jf.intel.com with SMTP; 13 Apr 2021 19:23:19 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 14 Apr 2021 05:23:18 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Wed, 14 Apr 2021 05:23:04 +0300 Message-Id: <20210414022309.30898-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210414022309.30898-1-ville.syrjala@linux.intel.com> References: <20210414022309.30898-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/8] drm/i915: Extract intel_fbc_update() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Pull the fbc enable vs. disable stuff into a small helper so we don't have to have it pollute the higher level modeset code. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 5 +--- drivers/gpu/drm/i915/display/intel_fbc.c | 26 ++++++++++++++++++-- drivers/gpu/drm/i915/display/intel_fbc.h | 2 +- 3 files changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 411b46c012f8..a4b8fb5c20f0 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -9799,10 +9799,7 @@ static void intel_update_crtc(struct intel_atomic_state *state, intel_encoders_update_pipe(state, crtc); } - if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc) - intel_fbc_disable(crtc); - else - intel_fbc_enable(state, crtc); + intel_fbc_update(state, crtc); /* Perform vblank evasion around commit operation */ intel_pipe_update_start(new_crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 178243a6d3a2..4968e79a6235 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1250,8 +1250,8 @@ void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, * intel_fbc_enable multiple times for the same pipe without an * intel_fbc_disable in the middle, as long as it is deactivated. */ -void intel_fbc_enable(struct intel_atomic_state *state, - struct intel_crtc *crtc) +static void intel_fbc_enable(struct intel_atomic_state *state, + struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_plane *plane = to_intel_plane(crtc->base.primary); @@ -1324,6 +1324,28 @@ void intel_fbc_disable(struct intel_crtc *crtc) mutex_unlock(&fbc->lock); } +/** + * intel_fbc_update: enable/disable FBC on the CRTC + * @state: atomic state + * @crtc: the CRTC + * + * This function checks if the given CRTC was chosen for FBC, then enables it if + * possible. Notice that it doesn't activate FBC. It is valid to call + * intel_fbc_update multiple times for the same pipe without an + * intel_fbc_disable in the middle. + */ +void intel_fbc_update(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + const struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + + if (crtc_state->update_pipe && !crtc_state->enable_fbc) + intel_fbc_disable(crtc); + else + intel_fbc_enable(state, crtc); +} + /** * intel_fbc_global_disable - globally disable FBC * @dev_priv: i915 device instance diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h index 6dc1edefe81b..b97d908738e6 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.h +++ b/drivers/gpu/drm/i915/display/intel_fbc.h @@ -24,7 +24,7 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state, void intel_fbc_post_update(struct intel_atomic_state *state, struct intel_crtc *crtc); void intel_fbc_init(struct drm_i915_private *dev_priv); -void intel_fbc_enable(struct intel_atomic_state *state, +void intel_fbc_update(struct intel_atomic_state *state, struct intel_crtc *crtc); void intel_fbc_disable(struct intel_crtc *crtc); void intel_fbc_global_disable(struct drm_i915_private *dev_priv); From patchwork Wed Apr 14 02:23:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12201745 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D536C433ED for ; Wed, 14 Apr 2021 02:23:26 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 303646100B for ; Wed, 14 Apr 2021 02:23:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 303646100B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C25566E430; Wed, 14 Apr 2021 02:23:25 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id A22326E431 for ; Wed, 14 Apr 2021 02:23:24 +0000 (UTC) IronPort-SDR: UvOYr497k64bEP3QYYARS4uKthV5JrUhV7OjFzW0h4Q/4yI4XLjQe0SF6MD3RmQLx39nFsWTJS Hex2jT870I1w== X-IronPort-AV: E=McAfee;i="6200,9189,9953"; a="279857535" X-IronPort-AV: E=Sophos;i="5.82,221,1613462400"; d="scan'208";a="279857535" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2021 19:23:23 -0700 IronPort-SDR: GMLum5/poolErPPkc/trWjlnMmqwOpbSVpkrsm0ooOO//sYBz8HOGBfwUOt/f38OcAN0nCz12e MYwh5cKhfiNw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,221,1613462400"; d="scan'208";a="450628764" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by FMSMGA003.fm.intel.com with SMTP; 13 Apr 2021 19:23:22 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 14 Apr 2021 05:23:21 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Wed, 14 Apr 2021 05:23:05 +0300 Message-Id: <20210414022309.30898-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210414022309.30898-1-ville.syrjala@linux.intel.com> References: <20210414022309.30898-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/8] drm/i915: Clear no_fbc_reason on activate X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä We try to set no_fbc_reason when FBC is not possible, let's consistently clear when activating FBC. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_fbc.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 4968e79a6235..fb8c0872a2b7 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -411,6 +411,17 @@ bool intel_fbc_is_active(struct drm_i915_private *dev_priv) return dev_priv->fbc.active; } +static void intel_fbc_activate(struct drm_i915_private *dev_priv) +{ + struct intel_fbc *fbc = &dev_priv->fbc; + + drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock)); + + intel_fbc_hw_activate(dev_priv); + + fbc->no_fbc_reason = NULL; +} + static void intel_fbc_deactivate(struct drm_i915_private *dev_priv, const char *reason) { @@ -1094,7 +1105,7 @@ static void __intel_fbc_post_update(struct intel_crtc *crtc) return; if (!fbc->busy_bits) - intel_fbc_hw_activate(dev_priv); + intel_fbc_activate(dev_priv); else intel_fbc_deactivate(dev_priv, "frontbuffer write"); } From patchwork Wed Apr 14 02:23:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12201747 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 807C8C433B4 for ; Wed, 14 Apr 2021 02:23:29 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3AB3E6100B for ; Wed, 14 Apr 2021 02:23:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3AB3E6100B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DC8606E431; Wed, 14 Apr 2021 02:23:28 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9264A6E431 for ; Wed, 14 Apr 2021 02:23:27 +0000 (UTC) IronPort-SDR: WSigthQrz2D/1ISrZXSPjq6o2LIzxknAQApczGjpyw0ZvQgUGD1gBODcWMIV2aXf6RRTBHddAK HG3XO8Izz4LA== X-IronPort-AV: E=McAfee;i="6200,9189,9953"; a="215034816" X-IronPort-AV: E=Sophos;i="5.82,221,1613462400"; d="scan'208";a="215034816" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2021 19:23:26 -0700 IronPort-SDR: IhMvlCS5Hduqr00laRa59p5VgwNPyFhBjowh0NtFqZoHHSK4MhYaJnDzP07aUpuv7OmtZ040Aj mRFVtboV8HbQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,221,1613462400"; d="scan'208";a="383515522" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga006.jf.intel.com with SMTP; 13 Apr 2021 19:23:24 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 14 Apr 2021 05:23:24 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Wed, 14 Apr 2021 05:23:06 +0300 Message-Id: <20210414022309.30898-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210414022309.30898-1-ville.syrjala@linux.intel.com> References: <20210414022309.30898-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/8] drm/i915: Move the "recompress on activate" to a central place X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä On ILK+ we current do a nuke right after activating FBC. If my memory isn't playing tricks on me this is actially required if FBC didn't stay disabled for a full frame. In that case the deactivate+reactivate may not invalidate the cfb. I'd have to double chekc to be sure though. So let's keep the nuke, and just extend it backwards to cover all the platforms by doing it a bit higher up. Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_fbc.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index fb8c0872a2b7..8165bdb6f921 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -212,16 +212,16 @@ static void i965_fbc_recompress(struct drm_i915_private *dev_priv) /* This function forces a CFB recompression through the nuke operation. */ static void snb_fbc_recompress(struct drm_i915_private *dev_priv) { - struct intel_fbc *fbc = &dev_priv->fbc; - - trace_intel_fbc_nuke(fbc->crtc); - intel_de_write(dev_priv, MSG_FBC_REND_STATE, FBC_REND_NUKE); intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE); } static void intel_fbc_recompress(struct drm_i915_private *dev_priv) { + struct intel_fbc *fbc = &dev_priv->fbc; + + trace_intel_fbc_nuke(fbc->crtc); + if (DISPLAY_VER(dev_priv) >= 6) snb_fbc_recompress(dev_priv); else if (DISPLAY_VER(dev_priv) >= 4) @@ -274,8 +274,6 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv) params->fence_y_offset); /* enable it... */ intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); - - intel_fbc_recompress(dev_priv); } static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv) @@ -348,8 +346,6 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) dpfc_ctl |= FBC_CTL_FALSE_COLOR; intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); - - intel_fbc_recompress(dev_priv); } static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv) @@ -418,6 +414,7 @@ static void intel_fbc_activate(struct drm_i915_private *dev_priv) drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock)); intel_fbc_hw_activate(dev_priv); + intel_fbc_recompress(dev_priv); fbc->no_fbc_reason = NULL; } From patchwork Wed Apr 14 02:23:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12201749 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7CBDC433ED for ; Wed, 14 Apr 2021 02:23:32 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6D9F76100B for ; Wed, 14 Apr 2021 02:23:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6D9F76100B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 15AA86E8BA; Wed, 14 Apr 2021 02:23:32 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9D76F6E8B3 for ; Wed, 14 Apr 2021 02:23:30 +0000 (UTC) IronPort-SDR: Lcr/k/84eMYngvSGxhlQVfPdKdY5onEQK5CoTHxtEXkKL7Yh4pgc0eGxK7R3SI6Uqpvdc0zPIR 8B6jiXUVvCLg== X-IronPort-AV: E=McAfee;i="6200,9189,9953"; a="182057293" X-IronPort-AV: E=Sophos;i="5.82,221,1613462400"; d="scan'208";a="182057293" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2021 19:23:29 -0700 IronPort-SDR: FoiQMh09WtstjkiWyF+iYthPp5743ntI7aMF7h+lacKXrASVm4V7k9oHbvl+OoZe7IAHyXcqFH LRehO8oh6dXg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,221,1613462400"; d="scan'208";a="421070651" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga007.jf.intel.com with SMTP; 13 Apr 2021 19:23:27 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 14 Apr 2021 05:23:27 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Wed, 14 Apr 2021 05:23:07 +0300 Message-Id: <20210414022309.30898-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210414022309.30898-1-ville.syrjala@linux.intel.com> References: <20210414022309.30898-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 6/8] drm/i915: Nuke lots of crap from intel_fbc_state_cache X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä There's no need to store all this stuff in intel_fbc_state_cache. Just check it all against the plane/crtc states and store only what we need. Probably more should get nuked still, but this is a start. So what we'll do is: - each crtc will check its own state and update its local no_fbc_reason - the per-crtc no_fbc_reason (if any) then gets propagated to the cache->no_fbc_reason while doing the actual update - fbc->no_fbc_reason gets updated in the end with either the value from the cache or directly from frontbuffer tracing It's still a bit messy, but should hopefuly get cleaned up more in the future. At least now we can observe each pipe's reasons for rejecting FBC now more consistently, and we don't have so mcuh redundant state store all over the place. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 5 +- .../drm/i915/display/intel_display_types.h | 2 +- drivers/gpu/drm/i915/display/intel_fbc.c | 363 ++++++++---------- drivers/gpu/drm/i915/display/intel_fbc.h | 3 +- drivers/gpu/drm/i915/i915_drv.h | 21 +- 5 files changed, 177 insertions(+), 217 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a4b8fb5c20f0..f1d71cb7952e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -9575,7 +9575,6 @@ static int intel_atomic_check(struct drm_device *dev, if (ret) goto fail; - intel_fbc_choose_crtc(dev_priv, state); ret = calc_watermark_data(state); if (ret) goto fail; @@ -9604,6 +9603,10 @@ static int intel_atomic_check(struct drm_device *dev, if (ret) goto fail; + ret = intel_fbc_atomic_check(state); + if (ret) + goto fail; + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { if (new_crtc_state->uapi.async_flip) { diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index e2e707c4dff5..c08fae63bae5 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1084,7 +1084,7 @@ struct intel_crtc_state { bool crc_enabled; - bool enable_fbc; + const char *no_fbc_reason; bool double_wide; diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 8165bdb6f921..a8565c58d1f1 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -43,6 +43,7 @@ #include "i915_drv.h" #include "i915_trace.h" #include "i915_vgpu.h" +#include "intel_cdclk.h" #include "intel_display_types.h" #include "intel_fbc.h" #include "intel_frontbuffer.h" @@ -588,9 +589,16 @@ void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) mutex_unlock(&fbc->lock); } -static bool stride_is_valid(struct drm_i915_private *dev_priv, - u64 modifier, unsigned int stride) +static bool stride_is_valid(const struct intel_plane_state *plane_state) { + struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev); + const struct drm_framebuffer *fb = plane_state->hw.fb; + unsigned int stride; + + stride = plane_state->view.color_plane[0].stride; + if (drm_rotation_90_or_270(plane_state->hw.rotation)) + stride *= fb->format->cpp[0]; + /* This should have been caught earlier. */ if (drm_WARN_ON_ONCE(&dev_priv->drm, (stride & (64 - 1)) != 0)) return false; @@ -607,7 +615,7 @@ static bool stride_is_valid(struct drm_i915_private *dev_priv, /* Display WA #1105: skl,bxt,kbl,cfl,glk */ if (IS_DISPLAY_VER(dev_priv, 9) && - modifier == DRM_FORMAT_MOD_LINEAR && stride & 511) + fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511) return false; if (stride > 16384) @@ -616,10 +624,12 @@ static bool stride_is_valid(struct drm_i915_private *dev_priv, return true; } -static bool pixel_format_is_valid(struct drm_i915_private *dev_priv, - u32 pixel_format) +static bool pixel_format_is_valid(const struct intel_plane_state *plane_state) { - switch (pixel_format) { + struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev); + const struct drm_framebuffer *fb = plane_state->hw.fb; + + switch (fb->format->format) { case DRM_FORMAT_XRGB8888: case DRM_FORMAT_XBGR8888: return true; @@ -637,10 +647,14 @@ static bool pixel_format_is_valid(struct drm_i915_private *dev_priv, } } -static bool rotation_is_valid(struct drm_i915_private *dev_priv, - u32 pixel_format, unsigned int rotation) +static bool rotation_is_valid(const struct intel_plane_state *plane_state) { - if (DISPLAY_VER(dev_priv) >= 9 && pixel_format == DRM_FORMAT_RGB565 && + struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev); + const struct drm_framebuffer *fb = plane_state->hw.fb; + unsigned int rotation = plane_state->hw.rotation; + + if (DISPLAY_VER(dev_priv) >= 9 && + fb->format->format == DRM_FORMAT_RGB565 && drm_rotation_90_or_270(rotation)) return false; else if (DISPLAY_VER(dev_priv) <= 4 && !IS_G4X(dev_priv) && @@ -656,10 +670,10 @@ static bool rotation_is_valid(struct drm_i915_private *dev_priv, * the X and Y offset registers. That's why we include the src x/y offsets * instead of just looking at the plane size. */ -static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) +static bool +intel_fbc_hw_tracking_covers_screen(const struct intel_plane_state *plane_state) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_fbc *fbc = &dev_priv->fbc; + struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev); unsigned int effective_w, effective_h, max_w, max_h; if (DISPLAY_VER(dev_priv) >= 10) { @@ -676,18 +690,20 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) max_h = 1536; } - intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w, - &effective_h); - effective_w += fbc->state_cache.plane.adjusted_x; - effective_h += fbc->state_cache.plane.adjusted_y; + effective_w = plane_state->view.color_plane[0].x + + (drm_rect_width(&plane_state->uapi.src) >> 16); + effective_h = plane_state->view.color_plane[0].y + + (drm_rect_height(&plane_state->uapi.src) >> 16); return effective_w <= max_w && effective_h <= max_h; } -static bool tiling_is_valid(struct drm_i915_private *dev_priv, - u64 modifier) +static bool tiling_is_valid(const struct intel_plane_state *plane_state) { - switch (modifier) { + struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev); + const struct drm_framebuffer *fb = plane_state->hw.fb; + + switch (fb->modifier) { case DRM_FORMAT_MOD_LINEAR: case I915_FORMAT_MOD_Y_TILED: return DISPLAY_VER(dev_priv) >= 9; @@ -707,15 +723,10 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, struct intel_fbc_state_cache *cache = &fbc->state_cache; struct drm_framebuffer *fb = plane_state->hw.fb; - cache->plane.visible = plane_state->uapi.visible; - if (!cache->plane.visible) + cache->no_fbc_reason = crtc_state->no_fbc_reason; + if (cache->no_fbc_reason) return; - cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags; - if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) - cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate; - - cache->plane.rotation = plane_state->hw.rotation; /* * Src coordinates are already rotated by 270 degrees for * the 90/270 degree plane rotation cases (to match the @@ -723,10 +734,6 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, */ cache->plane.src_w = drm_rect_width(&plane_state->uapi.src) >> 16; cache->plane.src_h = drm_rect_height(&plane_state->uapi.src) >> 16; - cache->plane.adjusted_x = plane_state->view.color_plane[0].x; - cache->plane.adjusted_y = plane_state->view.color_plane[0].y; - - cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode; cache->fb.format = fb->format; cache->fb.modifier = fb->modifier; @@ -749,8 +756,6 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, cache->fence_id = plane_state->vma->fence->id; else cache->fence_id = -1; - - cache->psr2_active = crtc_state->has_psr2; } static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv) @@ -784,6 +789,11 @@ static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv) { struct intel_fbc *fbc = &dev_priv->fbc; + if (!HAS_FBC(dev_priv)) { + fbc->no_fbc_reason = "unsupported by this chipset"; + return false; + } + if (intel_vgpu_active(dev_priv)) { fbc->no_fbc_reason = "VGPU is active"; return false; @@ -802,6 +812,114 @@ static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv) return true; } +static int intel_crtc_fbc_check(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_plane *plane = to_intel_plane(crtc->base.primary); + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + const struct intel_plane_state *plane_state = + intel_atomic_get_new_plane_state(state, plane); + const struct drm_framebuffer *fb; + + if (!plane->has_fbc) + return 0; + + if (!plane_state) + return 0; + + fb = plane_state->hw.fb; + + if (!plane_state->uapi.visible) { + crtc_state->no_fbc_reason = "plane not visible"; + return 0; + } + + if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { + crtc_state->no_fbc_reason = "interlaced mode"; + return 0; + } + + if (!intel_fbc_hw_tracking_covers_screen(plane_state)) { + crtc_state->no_fbc_reason = "plane too large"; + return 0; + } + + if (!pixel_format_is_valid(plane_state)) { + crtc_state->no_fbc_reason = "incompatible pixel format"; + return 0; + } + + if (!tiling_is_valid(plane_state)) { + crtc_state->no_fbc_reason = "incompatible tiling"; + return 0; + } + + if (!rotation_is_valid(plane_state)) { + crtc_state->no_fbc_reason = "incompatible rotation"; + return 0; + } + + if (!stride_is_valid(plane_state)) { + crtc_state->no_fbc_reason = "incompatible stride"; + return 0; + } + + if (plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && + plane_state->hw.fb->format->has_alpha) { + crtc_state->no_fbc_reason = "alpha blending enabled"; + return 0; + } + + /* + * Work around a problem on GEN9+ HW, where enabling FBC on a plane + * having a Y offset that isn't divisible by 4 causes FIFO underrun + * and screen flicker. + */ + if (DISPLAY_VER(dev_priv) >= 9 && + plane_state->view.color_plane[0].y & 3) { + crtc_state->no_fbc_reason = "plane start Y offset misaligned"; + return 0; + } + + /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */ + if (DISPLAY_VER(dev_priv) >= 11 && + (plane_state->view.color_plane[0].y + (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) { + crtc_state->no_fbc_reason = "plane end Y offset misaligned"; + return 0; + } + + /* + * Tigerlake is not supporting FBC with PSR2. + * Recommendation is to keep this combination disabled + * Bspec: 50422 HSD: 14010260002 + */ + if (IS_TIGERLAKE(dev_priv) && crtc_state->has_psr2) { + crtc_state->no_fbc_reason = "PSR2 enabled"; + return 0; + } + + /* WaFbcExceedCdClockThreshold:hsw,bdw */ + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { + const struct intel_cdclk_state *cdclk_state; + + cdclk_state = intel_atomic_get_cdclk_state(state); + if (IS_ERR(cdclk_state)) + return PTR_ERR(cdclk_state); + + if (crtc_state->pixel_rate > + cdclk_state->logical.cdclk * 95 / 100) { + crtc_state->no_fbc_reason = "pixel rate too high"; + return 0; + } + } + + crtc_state->no_fbc_reason = NULL; + + return 0; +} + static bool intel_fbc_can_activate(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -811,26 +929,8 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) if (!intel_fbc_can_enable(dev_priv)) return false; - if (!cache->plane.visible) { - fbc->no_fbc_reason = "primary plane not visible"; - return false; - } - - /* We don't need to use a state cache here since this information is - * global for all CRTC. - */ - if (fbc->underrun_detected) { - fbc->no_fbc_reason = "underrun detected"; - return false; - } - - if (cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) { - fbc->no_fbc_reason = "incompatible mode"; - return false; - } - - if (!intel_fbc_hw_tracking_covers_screen(crtc)) { - fbc->no_fbc_reason = "mode too large for compression"; + if (cache->no_fbc_reason) { + fbc->no_fbc_reason = cache->no_fbc_reason; return false; } @@ -852,41 +952,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) * rotation. */ if (DISPLAY_VER(dev_priv) < 9 && cache->fence_id < 0) { - fbc->no_fbc_reason = "framebuffer not tiled or fenced"; - return false; - } - - if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) { - fbc->no_fbc_reason = "pixel format is invalid"; - return false; - } - - if (!rotation_is_valid(dev_priv, cache->fb.format->format, - cache->plane.rotation)) { - fbc->no_fbc_reason = "rotation unsupported"; - return false; - } - - if (!tiling_is_valid(dev_priv, cache->fb.modifier)) { - fbc->no_fbc_reason = "tiling unsupported"; - return false; - } - - if (!stride_is_valid(dev_priv, cache->fb.modifier, cache->fb.stride)) { - fbc->no_fbc_reason = "framebuffer stride not supported"; - return false; - } - - if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && - cache->fb.format->has_alpha) { - fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC"; - return false; - } - - /* WaFbcExceedCdClockThreshold:hsw,bdw */ - if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && - cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) { - fbc->no_fbc_reason = "pixel rate is too big"; + fbc->no_fbc_reason = "framebuffer not fenced"; return false; } @@ -905,34 +971,6 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) return false; } - /* - * Work around a problem on GEN9+ HW, where enabling FBC on a plane - * having a Y offset that isn't divisible by 4 causes FIFO underrun - * and screen flicker. - */ - if (DISPLAY_VER(dev_priv) >= 9 && - (fbc->state_cache.plane.adjusted_y & 3)) { - fbc->no_fbc_reason = "plane Y offset is misaligned"; - return false; - } - - /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */ - if (DISPLAY_VER(dev_priv) >= 11 && - (cache->plane.src_h + cache->plane.adjusted_y) % 4) { - fbc->no_fbc_reason = "plane height + offset is non-modulo of 4"; - return false; - } - - /* - * Tigerlake is not supporting FBC with PSR2. - * Recommendation is to keep this combination disabled - * Bspec: 50422 HSD: 14010260002 - */ - if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) { - fbc->no_fbc_reason = "not supported with PSR2"; - return false; - } - return true; } @@ -963,8 +1001,6 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc, params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache); params->gen9_wa_cfb_stride = cache->gen9_wa_cfb_stride; - - params->plane_visible = cache->plane.visible; } static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state) @@ -978,7 +1014,7 @@ static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state) if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) return false; - if (!params->plane_visible) + if (fbc->no_fbc_reason) return false; if (!intel_fbc_can_activate(crtc)) @@ -1012,7 +1048,6 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state, intel_atomic_get_new_plane_state(state, plane); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_fbc *fbc = &dev_priv->fbc; - const char *reason = "update pending"; bool need_vblank_wait = false; if (!plane->has_fbc || !plane_state) @@ -1027,7 +1062,7 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state, fbc->flip_pending = true; if (!intel_fbc_can_flip_nuke(crtc_state)) { - intel_fbc_deactivate(dev_priv, reason); + intel_fbc_deactivate(dev_priv, "update pending"); /* * Display WA #1198: glk+ @@ -1063,6 +1098,7 @@ bool intel_fbc_pre_update(struct intel_atomic_state *state, static void __intel_fbc_disable(struct drm_i915_private *dev_priv) { struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_fbc_state_cache *cache = &fbc->state_cache; struct intel_crtc *crtc = fbc->crtc; drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock)); @@ -1074,6 +1110,7 @@ static void __intel_fbc_disable(struct drm_i915_private *dev_priv) __intel_fbc_cleanup_cfb(dev_priv); + fbc->no_fbc_reason = cache->no_fbc_reason; fbc->crtc = NULL; } @@ -1089,13 +1126,6 @@ static void __intel_fbc_post_update(struct intel_crtc *crtc) fbc->flip_pending = false; - if (!dev_priv->params.enable_fbc) { - intel_fbc_deactivate(dev_priv, "disabled at runtime per module param"); - __intel_fbc_disable(dev_priv); - - return; - } - intel_fbc_get_reg_params(crtc, &fbc->params); if (!intel_fbc_can_activate(crtc)) @@ -1189,75 +1219,23 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv, mutex_unlock(&fbc->lock); } -/** - * intel_fbc_choose_crtc - select a CRTC to enable FBC on - * @dev_priv: i915 device instance - * @state: the atomic state structure - * - * This function looks at the proposed state for CRTCs and planes, then chooses - * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to - * true. - * - * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe - * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc. - */ -void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, - struct intel_atomic_state *state) +int intel_fbc_atomic_check(struct intel_atomic_state *state) { - struct intel_fbc *fbc = &dev_priv->fbc; - struct intel_plane *plane; - struct intel_plane_state *plane_state; - bool crtc_chosen = false; + struct intel_crtc_state *crtc_state; + struct intel_crtc *crtc; int i; - mutex_lock(&fbc->lock); + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { + int ret; - /* Does this atomic commit involve the CRTC currently tied to FBC? */ - if (fbc->crtc && - !intel_atomic_get_new_crtc_state(state, fbc->crtc)) - goto out; - - if (!intel_fbc_can_enable(dev_priv)) - goto out; - - /* Simply choose the first CRTC that is compatible and has a visible - * plane. We could go for fancier schemes such as checking the plane - * size, but this would just affect the few platforms that don't tie FBC - * to pipe or plane A. */ - for_each_new_intel_plane_in_state(state, plane, plane_state, i) { - struct intel_crtc_state *crtc_state; - struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc); - - if (!plane->has_fbc) - continue; - - if (!plane_state->uapi.visible) - continue; - - crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - - crtc_state->enable_fbc = true; - crtc_chosen = true; - break; + ret = intel_crtc_fbc_check(state, crtc); + if (ret) + return ret; } - if (!crtc_chosen) - fbc->no_fbc_reason = "no suitable CRTC for FBC"; - -out: - mutex_unlock(&fbc->lock); + return 0; } -/** - * intel_fbc_enable: tries to enable FBC on the CRTC - * @crtc: the CRTC - * @state: corresponding &drm_crtc_state for @crtc - * - * This function checks if the given CRTC was chosen for FBC, then enables it if - * possible. Notice that it doesn't activate FBC. It is valid to call - * intel_fbc_enable multiple times for the same pipe without an - * intel_fbc_disable in the middle, as long as it is deactivated. - */ static void intel_fbc_enable(struct intel_atomic_state *state, struct intel_crtc *crtc) { @@ -1287,15 +1265,14 @@ static void intel_fbc_enable(struct intel_atomic_state *state, drm_WARN_ON(&dev_priv->drm, fbc->active); intel_fbc_update_state_cache(crtc, crtc_state, plane_state); - - /* FIXME crtc_state->enable_fbc lies :( */ - if (!cache->plane.visible) + if (cache->no_fbc_reason) { + fbc->no_fbc_reason = cache->no_fbc_reason; goto out; + } if (intel_fbc_alloc_cfb(dev_priv, intel_fbc_calculate_cfb_size(dev_priv, cache), plane_state->hw.fb->format->cpp[0])) { - cache->plane.visible = false; fbc->no_fbc_reason = "not enough stolen memory"; goto out; } @@ -1348,7 +1325,7 @@ void intel_fbc_update(struct intel_atomic_state *state, const struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - if (crtc_state->update_pipe && !crtc_state->enable_fbc) + if (crtc_state->update_pipe && crtc_state->no_fbc_reason) intel_fbc_disable(crtc); else intel_fbc_enable(state, crtc); diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h index b97d908738e6..c678b83f7509 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.h +++ b/drivers/gpu/drm/i915/display/intel_fbc.h @@ -16,8 +16,7 @@ struct intel_crtc; struct intel_crtc_state; struct intel_plane_state; -void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, - struct intel_atomic_state *state); +int intel_fbc_atomic_check(struct intel_atomic_state *state); bool intel_fbc_is_active(struct drm_i915_private *dev_priv); bool intel_fbc_pre_update(struct intel_atomic_state *state, struct intel_crtc *crtc); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 69e43bf91a15..cbe880477ee1 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -385,25 +385,8 @@ struct intel_fbc { */ struct intel_fbc_state_cache { struct { - unsigned int mode_flags; - u32 hsw_bdw_pixel_rate; - } crtc; - - struct { - unsigned int rotation; int src_w; int src_h; - bool visible; - /* - * Display surface base address adjustement for - * pageflips. Note that on gen4+ this only adjusts up - * to a tile, offsets within a tile are handled in - * the hw itself (with the TILEOFF register). - */ - int adjusted_x; - int adjusted_y; - - u16 pixel_blend_mode; } plane; struct { @@ -416,7 +399,7 @@ struct intel_fbc { u16 gen9_wa_cfb_stride; u16 interval; s8 fence_id; - bool psr2_active; + const char *no_fbc_reason; } state_cache; /* @@ -443,9 +426,7 @@ struct intel_fbc { u16 gen9_wa_cfb_stride; u16 interval; s8 fence_id; - bool plane_visible; } params; - const char *no_fbc_reason; }; From patchwork Wed Apr 14 02:23:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12201751 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84F0FC433B4 for ; Wed, 14 Apr 2021 02:23:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 432106120E for ; Wed, 14 Apr 2021 02:23:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 432106120E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DF2C46E8C0; Wed, 14 Apr 2021 02:23:33 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id B14FA6E8C2 for ; Wed, 14 Apr 2021 02:23:32 +0000 (UTC) IronPort-SDR: eysW0h09a8k+pgdvTOex61vbnzJE7t8w+lizoiRkp1u/v6yKj7je/qxpPkXLlJABU3zQM9UpJO u2SizEKA3urA== X-IronPort-AV: E=McAfee;i="6200,9189,9953"; a="174652211" X-IronPort-AV: E=Sophos;i="5.82,221,1613462400"; d="scan'208";a="174652211" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2021 19:23:32 -0700 IronPort-SDR: sqEIt+y/T0TgFjLG5+Q5fdzVG3hPWR5fwUUq5Y7bGLAzVlQVo4ziepyuDgYupyPqhTAuFVDzev Qa+epYgJg+wQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,221,1613462400"; d="scan'208";a="389237400" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga007.fm.intel.com with SMTP; 13 Apr 2021 19:23:30 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 14 Apr 2021 05:23:29 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Wed, 14 Apr 2021 05:23:08 +0300 Message-Id: <20210414022309.30898-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210414022309.30898-1-ville.syrjala@linux.intel.com> References: <20210414022309.30898-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 7/8] drm/i915: No FBC+double wide pipe X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä FBC and double wide pipe are mutually exclusive. Disable FBC when we have to resort to double wide. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_fbc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index a8565c58d1f1..48cddf70488f 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -841,6 +841,11 @@ static int intel_crtc_fbc_check(struct intel_atomic_state *state, return 0; } + if (crtc_state->double_wide) { + crtc_state->no_fbc_reason = "double wide pipe"; + return 0; + } + if (!intel_fbc_hw_tracking_covers_screen(plane_state)) { crtc_state->no_fbc_reason = "plane too large"; return 0; From patchwork Wed Apr 14 02:23:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12201753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74E63C433B4 for ; Wed, 14 Apr 2021 02:23:39 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3BDD96100B for ; Wed, 14 Apr 2021 02:23:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3BDD96100B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D0B416E42F; Wed, 14 Apr 2021 02:23:38 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id B26666E42F for ; Wed, 14 Apr 2021 02:23:37 +0000 (UTC) IronPort-SDR: CHwYHCDCr+MMxaafH3+5pdPMSa25rKU5SvZRpdZmIf8snZEfSoxzQeLPXDi0yrg1sWpgl0S15U u+xa8/k+uGNw== X-IronPort-AV: E=McAfee;i="6200,9189,9953"; a="181671861" X-IronPort-AV: E=Sophos;i="5.82,221,1613462400"; d="scan'208";a="181671861" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2021 19:23:36 -0700 IronPort-SDR: o5PrpZKYauPQf42UXeUkfZdkstU8v0mbWX9EtJRWbWSOc2HhSjZ4792TxoLdVPnL+SaZJQO8aN onNPUtgkVzxA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,221,1613462400"; d="scan'208";a="452238368" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga002.fm.intel.com with SMTP; 13 Apr 2021 19:23:33 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 14 Apr 2021 05:23:32 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Wed, 14 Apr 2021 05:23:09 +0300 Message-Id: <20210414022309.30898-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210414022309.30898-1-ville.syrjala@linux.intel.com> References: <20210414022309.30898-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 8/8] drm/i915: Pimp the FBC debugfs output X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Now that each pipe tracks its own no_fbc_reason we can print that out in debugfs, and we can also show which pipe is currently selected for FBC duty. Signed-off-by: Ville Syrjälä --- .../drm/i915/display/intel_display_debugfs.c | 50 +++++++++++++------ 1 file changed, 36 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 183c414d554a..26317e66cb95 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -38,15 +38,36 @@ static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) return 0; } +static bool i915_fbc_is_compressing(struct drm_i915_private *dev_priv) +{ + if (!intel_fbc_is_active(dev_priv)) + return false; + + if (DISPLAY_VER(dev_priv) >= 8) + return intel_de_read(dev_priv, IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK; + else if (DISPLAY_VER(dev_priv) >= 7) + return intel_de_read(dev_priv, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; + else if (DISPLAY_VER(dev_priv) >= 5) + return intel_de_read(dev_priv, ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK; + else if (IS_G4X(dev_priv)) + return intel_de_read(dev_priv, DPFC_STATUS) & DPFC_COMP_SEG_MASK; + else + return intel_de_read(dev_priv, FBC_STATUS) & + (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED); +} + static int i915_fbc_status(struct seq_file *m, void *unused) { struct drm_i915_private *dev_priv = node_to_i915(m->private); struct intel_fbc *fbc = &dev_priv->fbc; + struct intel_crtc *crtc; intel_wakeref_t wakeref; if (!HAS_FBC(dev_priv)) return -ENODEV; + drm_modeset_lock_all(&dev_priv->drm); + wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); mutex_lock(&fbc->lock); @@ -55,27 +76,28 @@ static int i915_fbc_status(struct seq_file *m, void *unused) else seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason); - if (intel_fbc_is_active(dev_priv)) { - u32 mask; + seq_printf(m, "Compressing: %s\n", yesno(i915_fbc_is_compressing(dev_priv))); - if (DISPLAY_VER(dev_priv) >= 8) - mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK; - else if (DISPLAY_VER(dev_priv) >= 7) - mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; - else if (DISPLAY_VER(dev_priv) >= 5) - mask = intel_de_read(dev_priv, ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK; - else if (IS_G4X(dev_priv)) - mask = intel_de_read(dev_priv, DPFC_STATUS) & DPFC_COMP_SEG_MASK; - else - mask = intel_de_read(dev_priv, FBC_STATUS) & - (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED); + for_each_intel_crtc(&dev_priv->drm, crtc) { + struct intel_plane *plane = to_intel_plane(crtc->base.primary); + const struct intel_crtc_state *crtc_state = + to_intel_crtc_state(crtc->base.state); - seq_printf(m, "Compressing: %s\n", yesno(mask)); + if (!plane->has_fbc) + continue; + + seq_printf(m, "%c [CRTC:%d:%s]/[PLANE:%d:%s]: %s\n", + fbc->crtc == crtc ? '*' : ' ', + crtc->base.base.id, crtc->base.name, + plane->base.base.id, plane->base.name, + crtc_state->no_fbc_reason ?: "FBC possible"); } mutex_unlock(&fbc->lock); intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); + drm_modeset_unlock_all(&dev_priv->drm); + return 0; }