From patchwork Thu Apr 15 16:34:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alessandro Di Federico X-Patchwork-Id: 12205859 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38EDAC433ED for ; Thu, 15 Apr 2021 17:25:53 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C5D3B610F7 for ; Thu, 15 Apr 2021 17:25:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C5D3B610F7 Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=nongnu.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:36910 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lX5kV-0003Dg-Sz for qemu-devel@archiver.kernel.org; Thu, 15 Apr 2021 13:25:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42060) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lX4xY-0004EC-JN for qemu-devel@nongnu.org; Thu, 15 Apr 2021 12:35:16 -0400 Received: from rev.ng ([5.9.113.41]:34061) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lX4xT-0006eM-F0 for qemu-devel@nongnu.org; Thu, 15 Apr 2021 12:35:16 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=2RwTHTorS670vO4eCktAe3M0cB7xAsEMv6yPznJKvhs=; b=ajXB4n4evChcoHb6ENkZ3Crtmm 2kylkTGYPBTHWOULjBGD6/6qXRKri/Uk+yXbWROI46Qyjvx23FvJ34cYDIxVJgI8ezzbDf3BDLuZ5 Prk/foIBpeumlhbOTl5n2znn3hngOkHXW3ZW59xaxBx7NACsB65/J8YxLgmgKCkQ+xV4=; To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng, nizzo@rev.ng, philmd@redhat.com, richard.henderson@linaro.org, Alessandro Di Federico Subject: [PATCH v4 01/12] tcg: expose TCGCond manipulation routines Date: Thu, 15 Apr 2021 18:34:44 +0200 Message-Id: <20210415163455.3839169-2-ale.qemu@rev.ng> In-Reply-To: <20210415163455.3839169-1-ale.qemu@rev.ng> References: <20210415163455.3839169-1-ale.qemu@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico X-Patchwork-Original-From: Alessandro Di Federico via From: Alessandro Di Federico From: Alessandro Di Federico This commit moves into a separate file routines used to manipulate TCGCond. These will be employed by the idef-parser. Signed-off-by: Alessandro Di Federico Signed-off-by: Paolo Montesel Reviewed-by: Richard Henderson --- include/tcg/tcg-cond.h | 101 +++++++++++++++++++++++++++++++++++++++++ include/tcg/tcg.h | 70 +--------------------------- 2 files changed, 102 insertions(+), 69 deletions(-) create mode 100644 include/tcg/tcg-cond.h diff --git a/include/tcg/tcg-cond.h b/include/tcg/tcg-cond.h new file mode 100644 index 0000000000..2a38a386d4 --- /dev/null +++ b/include/tcg/tcg-cond.h @@ -0,0 +1,101 @@ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2008 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef TCG_COND_H +#define TCG_COND_H + +/* + * Conditions. Note that these are laid out for easy manipulation by + * the functions below: + * bit 0 is used for inverting; + * bit 1 is signed, + * bit 2 is unsigned, + * bit 3 is used with bit 0 for swapping signed/unsigned. + */ +typedef enum { + /* non-signed */ + TCG_COND_NEVER = 0 | 0 | 0 | 0, + TCG_COND_ALWAYS = 0 | 0 | 0 | 1, + TCG_COND_EQ = 8 | 0 | 0 | 0, + TCG_COND_NE = 8 | 0 | 0 | 1, + /* signed */ + TCG_COND_LT = 0 | 0 | 2 | 0, + TCG_COND_GE = 0 | 0 | 2 | 1, + TCG_COND_LE = 8 | 0 | 2 | 0, + TCG_COND_GT = 8 | 0 | 2 | 1, + /* unsigned */ + TCG_COND_LTU = 0 | 4 | 0 | 0, + TCG_COND_GEU = 0 | 4 | 0 | 1, + TCG_COND_LEU = 8 | 4 | 0 | 0, + TCG_COND_GTU = 8 | 4 | 0 | 1, +} TCGCond; + +/* Invert the sense of the comparison. */ +static inline TCGCond tcg_invert_cond(TCGCond c) +{ + return (TCGCond)(c ^ 1); +} + +/* Swap the operands in a comparison. */ +static inline TCGCond tcg_swap_cond(TCGCond c) +{ + return c & 6 ? (TCGCond)(c ^ 9) : c; +} + +/* Create an "unsigned" version of a "signed" comparison. */ +static inline TCGCond tcg_unsigned_cond(TCGCond c) +{ + return c & 2 ? (TCGCond)(c ^ 6) : c; +} + +/* Create a "signed" version of an "unsigned" comparison. */ +static inline TCGCond tcg_signed_cond(TCGCond c) +{ + return c & 4 ? (TCGCond)(c ^ 6) : c; +} + +/* Must a comparison be considered unsigned? */ +static inline bool is_unsigned_cond(TCGCond c) +{ + return (c & 4) != 0; +} + +/* + * Create a "high" version of a double-word comparison. + * This removes equality from a LTE or GTE comparison. + */ +static inline TCGCond tcg_high_cond(TCGCond c) +{ + switch (c) { + case TCG_COND_GE: + case TCG_COND_LE: + case TCG_COND_GEU: + case TCG_COND_LEU: + return (TCGCond)(c ^ 8); + default: + return c; + } +} + +#endif /* TCG_COND_H */ diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 0f0695e90d..3dc468ebd8 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -34,6 +34,7 @@ #include "tcg/tcg-mo.h" #include "tcg-target.h" #include "qemu/int128.h" +#include "tcg/tcg-cond.h" /* XXX: make safe guess about sizes */ #define MAX_OP_PER_INSTR 266 @@ -407,75 +408,6 @@ typedef TCGv_ptr TCGv_env; /* Used to align parameters. See the comment before tcgv_i32_temp. */ #define TCG_CALL_DUMMY_ARG ((TCGArg)0) -/* Conditions. Note that these are laid out for easy manipulation by - the functions below: - bit 0 is used for inverting; - bit 1 is signed, - bit 2 is unsigned, - bit 3 is used with bit 0 for swapping signed/unsigned. */ -typedef enum { - /* non-signed */ - TCG_COND_NEVER = 0 | 0 | 0 | 0, - TCG_COND_ALWAYS = 0 | 0 | 0 | 1, - TCG_COND_EQ = 8 | 0 | 0 | 0, - TCG_COND_NE = 8 | 0 | 0 | 1, - /* signed */ - TCG_COND_LT = 0 | 0 | 2 | 0, - TCG_COND_GE = 0 | 0 | 2 | 1, - TCG_COND_LE = 8 | 0 | 2 | 0, - TCG_COND_GT = 8 | 0 | 2 | 1, - /* unsigned */ - TCG_COND_LTU = 0 | 4 | 0 | 0, - TCG_COND_GEU = 0 | 4 | 0 | 1, - TCG_COND_LEU = 8 | 4 | 0 | 0, - TCG_COND_GTU = 8 | 4 | 0 | 1, -} TCGCond; - -/* Invert the sense of the comparison. */ -static inline TCGCond tcg_invert_cond(TCGCond c) -{ - return (TCGCond)(c ^ 1); -} - -/* Swap the operands in a comparison. */ -static inline TCGCond tcg_swap_cond(TCGCond c) -{ - return c & 6 ? (TCGCond)(c ^ 9) : c; -} - -/* Create an "unsigned" version of a "signed" comparison. */ -static inline TCGCond tcg_unsigned_cond(TCGCond c) -{ - return c & 2 ? (TCGCond)(c ^ 6) : c; -} - -/* Create a "signed" version of an "unsigned" comparison. */ -static inline TCGCond tcg_signed_cond(TCGCond c) -{ - return c & 4 ? (TCGCond)(c ^ 6) : c; -} - -/* Must a comparison be considered unsigned? */ -static inline bool is_unsigned_cond(TCGCond c) -{ - return (c & 4) != 0; -} - -/* Create a "high" version of a double-word comparison. - This removes equality from a LTE or GTE comparison. */ -static inline TCGCond tcg_high_cond(TCGCond c) -{ - switch (c) { - case TCG_COND_GE: - case TCG_COND_LE: - case TCG_COND_GEU: - case TCG_COND_LEU: - return (TCGCond)(c ^ 8); - default: - return c; - } -} - typedef enum TCGTempVal { TEMP_VAL_DEAD, TEMP_VAL_REG, From patchwork Thu Apr 15 16:34:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alessandro Di Federico X-Patchwork-Id: 12205817 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E70FC433B4 for ; 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envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico X-Patchwork-Original-From: Alessandro Di Federico via From: Alessandro Di Federico From: Alessandro Di Federico Signed-off-by: Alessandro Di Federico Reviewed-by: Richard Henderson --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 36055f14c5..158badbd18 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -193,11 +193,19 @@ Hexagon TCG CPUs M: Taylor Simpson S: Supported F: target/hexagon/ +X: target/hexagon/idef-parser/ +X: target/hexagon/gen_idef_parser_funcs.py F: linux-user/hexagon/ F: tests/tcg/hexagon/ F: disas/hexagon.c F: default-configs/targets/hexagon-linux-user.mak +Hexagon idef-parser +M: Alessandro Di Federico +S: Supported +F: target/hexagon/idef-parser/ +F: target/hexagon/gen_idef_parser_funcs.py + HPPA (PA-RISC) TCG CPUs M: Richard Henderson S: Maintained From patchwork Thu Apr 15 16:34:46 2021 Content-Type: text/plain; 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bh=nnMa6nyW3qh00VjA+XvsAuyxMfPHoTfD0lPP+OlMkB0=; b=Ua1kuDrso/YLXS1dXYRxI4AmEi 7GHALtNJ1kOlwj9sS86Gw/CtZnl7EBf/bWZTtRtFbJvl67+8inGoO4jMkVjjqmAv1LK8irh2GN872 6cVRw3CsYgKuxXEm6mJKmhaWdctBhW+xHwpWqzraJ6EPjP6ZrKmzdY8bEmvlsABEt42Y=; To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng, nizzo@rev.ng, philmd@redhat.com, richard.henderson@linaro.org, Alessandro Di Federico Subject: [PATCH v4 03/12] target/hexagon: import README for idef-parser Date: Thu, 15 Apr 2021 18:34:46 +0200 Message-Id: <20210415163455.3839169-4-ale.qemu@rev.ng> In-Reply-To: <20210415163455.3839169-1-ale.qemu@rev.ng> References: <20210415163455.3839169-1-ale.qemu@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico X-Patchwork-Original-From: Alessandro Di Federico via From: Alessandro Di Federico From: Alessandro Di Federico Signed-off-by: Alessandro Di Federico --- target/hexagon/README | 5 + target/hexagon/idef-parser/README.rst | 447 ++++++++++++++++++++++++++ 2 files changed, 452 insertions(+) create mode 100644 target/hexagon/idef-parser/README.rst diff --git a/target/hexagon/README b/target/hexagon/README index b0b2435070..2f2814380c 100644 --- a/target/hexagon/README +++ b/target/hexagon/README @@ -23,6 +23,10 @@ Hexagon-specific code are encode*.def Encoding patterns for each instruction iclass.def Instruction class definitions used to determine legal VLIW slots for each instruction + qemu/target/hexagon/idef-parser + Parser that, given the high-level definitions of an instruction, + produces a C function generating equivalent tiny code instructions. + See README.rst. qemu/linux-user/hexagon Helpers for loading the ELF file and making Linux system calls, signals, etc @@ -43,6 +47,7 @@ header files in /target/hexagon gen_tcg_funcs.py -> tcg_funcs_generated.c.inc gen_tcg_func_table.py -> tcg_func_table_generated.c.inc gen_helper_funcs.py -> helper_funcs_generated.c.inc + gen_idef_parser_funcs.py -> idef_parser_input.h Qemu helper functions have 3 parts DEF_HELPER declaration indicates the signature of the helper diff --git a/target/hexagon/idef-parser/README.rst b/target/hexagon/idef-parser/README.rst new file mode 100644 index 0000000000..f4cb416e8b --- /dev/null +++ b/target/hexagon/idef-parser/README.rst @@ -0,0 +1,447 @@ +Hexagon ISA instruction definitions to tinycode generator compiler +------------------------------------------------------------------ + +idef-parser is a small compiler able to translate the Hexagon ISA description +language into tinycode generator code, that can be easily integrated into QEMU. + +Compilation Example +------------------- + +To better understand the scope of the idef-parser, we'll explore an applicative +example. Let's start by one of the simplest Hexagon instruction: the ``add``. + +The ISA description language represents the ``add`` instruction as +follows: + +.. code:: c + + A2_add(RdV, in RsV, in RtV) { + { RdV=RsV+RtV;} + } + +idef-parser will compile the above code into the following code: + +.. code:: c + + /* A2_add */ + void emit_A2_add(DisasContext *ctx, Insn *insn, Packet *pkt, TCGv_i32 RdV, + TCGv_i32 RsV, TCGv_i32 RtV) + /* { RdV=RsV+RtV;} */ + { + tcg_gen_movi_i32(RdV, 0); + TCGv_i32 tmp_0 = tcg_temp_new_i32(); + tcg_gen_add_i32(tmp_0, RsV, RtV); + tcg_gen_mov_i32(RdV, tmp_0); + tcg_temp_free_i32(tmp_0); + } + +The output of the compilation process will be a function, containing the +tinycode generator code, implementing the correct semantics. That function will +not access any global variable, because all the accessed data structures will be +passed explicitly as function parameters. Among the passed parameters we will +have TCGv (tinycode variables) representing the input and output registers of +the architecture, integers representing the immediates that come from the code, +and other data structures which hold information about the disassemblation +context (``DisasContext`` struct). + +Let's begin by describing the input code. The ``add`` instruction is associated +with a unique identifier, in this case ``A2_add``, which allows to distinguish +variants of the same instruction, and expresses the class to which the +instruction belongs, in this case ``A2`` corresponds to the Hexagon +``ALU32/ALU`` instruction subclass. + +After the instruction identifier, we have a series of parameters that represents +TCG variables that will be passed to the generated function. Parameters marked +with ``in`` are already initialized, while the others are output parameters. + +We will leverage this information to infer several information: + +- Fill in the output function signature with the correct TCGv registers +- Fill in the output function signature with the immediate integers +- Keep track of which registers, among the declared one, have been + initialized + +Let's now observe the actual instruction description code, in this case: + +.. code:: c + + { RdV=RsV+RtV;} + +This code is composed by a subset of the C syntax, and is the result of the +application of some macro definitions contained in the ``macros.h`` file. + +This file is used to reduce the complexity of the input language where complex +variants of similar constructs can be mapped to a unique primitive, so that the +idef-parser has to handle a lower number of computation primitives. + +As you may notice, the description code modifies the registers which have been +declared by the declaration statements. In this case all the three registers +will be declared, ``RsV`` and ``RtV`` will also be read and ``RdV`` will be +written. + +Now let's have a quick look at the generated code, line by line. + +:: + + tcg_gen_movi_i32(RdV, 0); + +This code starts by zero-initializing ``RdV``, since reading from that register +without initialization will cause a segmentation fault by QEMU. This is emitted +since a declaration of the ``RdV`` register was parsed, but we got no indication +that the variable has been initialized by the caller. + +:: + + TCGv_i32 tmp_0 = tcg_temp_new_i32(); + +Then we are declaring a temporary TCGv to hold the result from the sum +operation. + +:: + + tcg_gen_add_i32(tmp_0, RsV, RtV); + +Now we are actually generating the sum tinycode operator between the selected +registers, storing the result in the just declared temporary. + +:: + + tcg_gen_mov_i32(RdV, tmp_0); + +The result of the addition is now stored in the temporary, we move it into the +correct destination register. This might not seem an efficient code, but QEMU +will perform some tinycode optimization, reducing the unnecessary copy. + +:: + + tcg_temp_free_i32(tmp_0); + +Finally, we free the temporary we used to hold the addition result. + +Parser Structure +---------------- + +The idef-parser is built using the ``flex`` and ``bison``. + +``flex`` is used to split the input string into tokens, each described using a +regular expression. The token description is contained in the +``idef-parser.lex`` source file. The flex-generated scanner takes care also to +extract from the input text other meaningful information, e.g., the numerical +value in case of an immediate constant, and decorates the token with the +extracted information. + +``bison`` is used to generate the actual parser, starting from the parsing +description contained in the ``idef-parser.y`` file. The generated parser +executes the ``main`` function at the end of the ``idef-parser.y`` file, which +opens input and output files, creates the parsing context, and eventually calls +the ``yyparse()`` function, which starts the execution of the LALR(1) parser +(see `Wikipedia `__ for more +information about LALR parsing techniques). The LALR(1) parser, whenever it has +to shift a token, calls the ``yylex()`` function, which is defined by the +flex-generated code, and reads the input file returning the next scanned token. + +The tokens are mapped on the source language grammar, defined in the +``idef-parser.y`` file to build a unique syntactic tree, according to the +specified operator precedences and associativity rules. + +The grammar describes the whole file which contains the Hexagon instruction +descriptions, therefore it starts from the ``input`` nonterminal, which is a +list of instructions, each instruction is represented by the following grammar +rule, representing the structure of the input file shown above: + +:: + + instruction : INAME code + + code : LBR decls statements decls RBR + + statements : statements statement + | statement + + statement : control_statement + | rvalue SEMI + | code_block + | SEMI + + code_block : LBR statements RBR + | LBR RBR + +With this initial portion of the grammar we are defining the instruction +statements, which are enclosed by the declarations. Each statement can be a +``control_statement``, a code block, which is just a bracket-enclosed list of +statements, a ``SEMI``, which is a ``nop`` instruction, and an ``rvalue SEMI``. + +Expressions +~~~~~~~~~~~ + +``rvalue`` is the nonterminal representing expressions, which are everything +that could be assigned to a variable. ``rvalue SEMI`` can be a statement on its +own because the assign statement, just as in the C language, is itself an +expression. + +``rvalue``\ s can be registers, immediates, predicates, control registers, +variables, or any combination of other ``rvalue``\ s through operators. An +``rvalue`` can be either an immediate or a TCGv, the actual type is determined +by the ``t_hex_value.type`` field. In case it is an immediate, its combination +with other immediates can be performed at compile-time (constant folding), only +the result will be written into the code. If the ``rvalue`` instead is a TCGv, +the operations performed on it will have to be emitted as tinycode instructions, +therefore their result will be known only at runtime. An immediate can be copied +into a TCGv through the ``rvalue_materialize`` function, which allocates a +temporary TCGv and copies the value of the immediate in it. Each temporary +should be freed after that it is no more used, we usually free both operands of +each operator, in an SSA fashion. + +``lvalue``\ s instead represents all the variables which can be assigned to a +value, and are specialized into registers and variables: + +:: + + lvalue : REG + | VAR + +The effective assignment of ``lvalue``\ s is handled by the ``gen_assign()`` +function. + +Automatic Variables +~~~~~~~~~~~~~~~~~~~ + +The input code can contain implicitly declared automatic variables, which are +initialized with a value and then used. We performed a dedicated handling of +such variables, because they will be matched by a generic ``VARID`` token, which +will feature the variable name as a decoration. Each time that the variable is +found, we have to check if that's the first variable use, in that case we +declare a new automatic variable in the tinycode, which can be considered at all +effects as an immediate. Special care is taken to make sure that each variable +is declared only the first time it is seen. Furthermore the variable might +inherit some characteristics like the signedness and the bit width, which must +be propagated from the initialization of the variable to all the further uses of +the variable. + +The combination of ``rvalue``\ s are handled through the use of the +``gen_bin_op`` and ``gen_bin_cmp`` helper functions. These two functions handle +the appropriate compile-time or run-time emission of operations to perform the +required computation. + +Type System +~~~~~~~~~~~ + +idef-parser features a simple type system which is used to correctly implement +the signedness and bit width of the operations. + +The type of each ``rvalue`` is determined by two attributes: its bit width +(``unsigned bit_width``) and its signedness (``bool is_unsigned``). + +For each operation, the type of ``rvalue``\ s influence the way in which the +operands are handled and emitted. For example a right shift between signed +operators will be an algebraic shift, while one between unsigned operators will +be a logical shift. If one of the two operands is signed, and the other is +unsigned, the operation will be signed. + +The bit width also influences the outcome of the operations, in particular while +the input languages features a fine granularity type system, with types of 8, +16, 32, 64 (and more for vectorial instructions) bits, the tinycode only +features 32 and 64 bit widths. We propagate as much as possible the fine +granularity type, until the value has to be used inside an operation between +``rvalue``\ s; in that case if one of the two operands is greater than 32 bits +we promote the whole operation to 64 bit, taking care of properly extending the +two operands. Fortunately, the most critical instructions already feature +explicit casts and zero/sign extensions which are properly propagated down to +our parser. + +Control Statements +~~~~~~~~~~~~~~~~~~ + +``control_statement``\ s are all the statements which modify the order of +execution of the generated code according to input parameters. They are expanded +by the following grammar rule: + +:: + + control_statement : frame_check + | cancel_statement + | if_statement + | for_statement + | fpart1_statement + +``if_statement``\ s require the emission of labels and branch instructions which +effectively perform conditional jumps (``tcg_gen_brcondi``) according to the +value of an expression. All the predicated instructions, and in general all the +instructions where there could be alternative values assigned to an ``lvalue``, +like C-style ternary expressions: + +:: + + rvalue : rvalue QMARK rvalue COLON rvalue + +Are handled using the conditional move tinycode instruction +(``tcg_gen_movcond``), which avoids the additional complexity of managing labels +and jumps. + +Instead, regarding the ``for`` loops, exploiting the fact that they always +iterate on immediate values, therefore their iteration ranges are always known +at compile time, we implemented those emitting plain C ``for`` loops. This is +possible because the loops will be executed in the QEMU code, leading to the +consequential unrolling of the for loop, since the tinycode generator +instructions will be executed multiple times, and the respective generated +tinycode will represent the unrolled execution of the loop. + +Parsing Context +~~~~~~~~~~~~~~~ + +All the helper functions in ``idef-parser.y`` carry two fixed parameters, which +are the parsing context ``c`` and the ``YYLLOC`` location information. The +context is explicitly passed to all the functions because the parser we generate +is a reentrant one, meaning that it does not have any global variable, and +therefore the instruction compilation could easily be parallelized in the +future. Finally for each rule we propagate information about the location of the +involved tokens to generate a pretty error reporting, able to highlight the +portion of the input code which generated each error. + +Debugging +--------- + +Developing the idef-parser can lead to two types of errors: compile-time errors +and parsing errors. + +Compile-time errors in Bison-generated parsers are usually due to conflicts in +the described grammar. Conflicts forbid the grammar to produce a unique +derivation tree, thus must be solved (except for the dangling else problem, +which is marked as expected through the ``%expect 1`` Bison option). + +For solving conflicts you need a basic understanding of `shift-reduce conflicts +`__ +and `reduce-reduce conflicts +`__, +then, if you are using a Bison version > 3.7.1 you can ask Bison to generate +some counterexamples which highlight ambiguous derivations, passing the +``-Wcex`` option to Bison. In general shift/reduce conflicts are solved by +redesigning the grammar in an unambiguous way or by setting the token priority +correctly, while reduce/reduce conflicts are solved by redesigning the +interested part of the grammar. + +Run-time errors can be divided between lexing and parsing errors, lexing errors +are hard to detect, since the ``VAR`` token will catch everything which is not +catched by other tokens, but easy to fix, because most of the time a simple +regex editing will be enough. + +idef-parser features a fancy parsing error reporting scheme, which for each +parsing error reports the fragment of the input text which was involved in the +parsing rule that generated an error. + +Implementing an instruction goes through several sequential steps, here are some +suggestions to make each instruction proceed to the next step. + +- not-emitted + + Means that the parsing of the input code relative to that instruction failed, + this could be due to a lexical error or to some mismatch between the order of + valid tokens and a parser rule. You should check that tokens are correctly + identified and mapped, and that there is a rule matching the token sequence + that you need to parse. + +- emitted + + This instruction class contains all the instruction which are emitted but + fail to compile when included in QEMU. The compilation errors are shown by + the QEMU building process and will lead to fixing the bug. Most common + errors regard the mismatch of parameters for tinycode generator functions, + which boil down to errors in the idef-parser type system. + +- compiled + + These instruction generate valid tinycode generator code, which however fail + the QEMU or the harness tests, these cases must be handled manually by + looking into the failing tests and looking at the generated tinycode + generator instruction and at the generated tinycode itself. Tip: handle the + failing harness tests first, because they usually feature only a single + instruction, thus will require less execution trace navigation. If a + multi-threaded test fail, fixing all the other tests will be the easier + option, hoping that the multi-threaded one will be indirectly fixed. + +- tests-passed + + This is the final goal for each instruction, meaning that the instruction + passes the test suite. + +Another approach to fix QEMU system test, where many instructions might fail, is +to compare the execution trace of your implementation with the reference +implementations already present in QEMU. To do so you should obtain a QEMU build +where the instruction pass the test, and run it with the following command: + +:: + + sudo unshare -p sudo -u bash -c \ + 'env -i -d cpu ' + +And do the same for your implementation, the generated execution traces will be +inherently aligned and can be inspected for behavioral differences using the +``diff`` tool. + +Limitations and Future Development +---------------------------------- + +The main limitation of the current parser is given by the syntax-driven nature +of the Bison-generated parsers. This has the severe implication of only being +able to generate code in the order of evaluation of the various rules, without, +in any case, being able to backtrack and alter the generated code. + +An example limitation is highlighted by this statement of the input language: + +:: + + { (PsV==0xff) ? (PdV=0xff) : (PdV=0x00); } + +This ternary assignment, when written in this form requires us to emit some +proper control flow statements, which emit a jump to the first or to the second +code block, whose implementation is extremely convoluted, because when matching +the ternary assignment, the code evaluating the two assignments will be already +generated. + +Instead we pre-process that statement, making it become: + +:: + + { PdV = ((PsV==0xff)) ? 0xff : 0x00; } + +Which can be easily matched by the following parser rules: + +:: + + statement | rvalue SEMI + + rvalue : rvalue QMARK rvalue COLON rvalue + | rvalue EQ rvalue + | LPAR rvalue RPAR + | assign_statement + | IMM + + assign_statement : pre ASSIGN rvalue + +Another example that highlight the limitation of the flex/bison parser can be +found even in the add operation we already saw: + +:: + + TCGv_i32 tmp_0 = tcg_temp_new_i32(); + tcg_gen_add_i32(tmp_0, RsV, RtV); + tcg_gen_mov_i32(RdV, tmp_0); + +The fact that we cannot directly use ``RdV`` as the destination of the sum is a +consequence of the syntax-driven nature of the parser. In fact when we parse the +assignment, the ``rvalue`` token, representing the sum has already been reduced, +and thus its code emitted and unchangeable. We rely on the fact that QEMU will +optimize our code reducing the useless move operations and the relative +temporaries. + +A possible improvement of the parser regards the support for vectorial +instructions and floating point instructions, which will require the extension +of the scanner, the parser, and a partial re-design of the type system, allowing +to build the vectorial semantics over the available vectorial tinycode generator +primitives. + +A more radical improvement will use the parser, not to generate directly the +tinycode generator code, but to generate an intermediate representation like the +LLVM IR, which in turn could be compiled using the clang TCG backend. That code +could be furtherly optimized, overcoming the limitations of the syntax-driven +parsing and could lead to a more optimized generated code. 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dmarc=pass (p=none dis=none) header.from=nongnu.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:56936 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lX5gY-00080C-9g for qemu-devel@archiver.kernel.org; Thu, 15 Apr 2021 13:21:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42042) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lX4xY-0004DB-4U for qemu-devel@nongnu.org; Thu, 15 Apr 2021 12:35:16 -0400 Received: from rev.ng ([5.9.113.41]:60547) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lX4xT-0006eb-Q8 for qemu-devel@nongnu.org; Thu, 15 Apr 2021 12:35:15 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=m2yRXnIbNbZIWeyfV8xdgvOS2RzdG35bJ8KtiwrTQJs=; b=L3QRgFQA7WbPsY+gbJJb8vMOCu 9vBsTygkU4tpJuTasZPP8X6pcM8eVdGzQLLtC69vIeq9avbZr0ZTfD1azYBqseTODHXFTXmqCBHSp 7jUxB1ZnO5hR3/jsd8/vXZV1HwkrURnPlMJWHGoTlJHMVaIUbP3BrsLmwJvNug6IGe/I=; To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng, nizzo@rev.ng, philmd@redhat.com, richard.henderson@linaro.org, Alessandro Di Federico Subject: [PATCH v4 04/12] target/hexagon: make slot number an unsigned Date: Thu, 15 Apr 2021 18:34:47 +0200 Message-Id: <20210415163455.3839169-5-ale.qemu@rev.ng> In-Reply-To: <20210415163455.3839169-1-ale.qemu@rev.ng> References: <20210415163455.3839169-1-ale.qemu@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico X-Patchwork-Original-From: Alessandro Di Federico via From: Alessandro Di Federico From: Paolo Montesel Signed-off-by: Alessandro Di Federico Signed-off-by: Paolo Montesel Acked-by: Richard Henderson --- target/hexagon/genptr.c | 6 ++++-- target/hexagon/macros.h | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 7481f4c1dd..fd18aabe8d 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -33,7 +33,8 @@ static inline TCGv gen_read_preg(TCGv pred, uint8_t num) return pred; } -static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot) +static inline void gen_log_predicated_reg_write(int rnum, TCGv val, + unsigned slot) { TCGv one = tcg_const_tl(1); TCGv zero = tcg_const_tl(0); @@ -62,7 +63,8 @@ static inline void gen_log_reg_write(int rnum, TCGv val) #endif } -static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot) +static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, + unsigned slot) { TCGv val32 = tcg_temp_new(); TCGv one = tcg_const_tl(1); diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index cfcb8173ba..d9473c8823 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -154,7 +154,7 @@ #define LOAD_CANCEL(EA) do { CANCEL; } while (0) #ifdef QEMU_GENERATE -static inline void gen_pred_cancel(TCGv pred, int slot_num) +static inline void gen_pred_cancel(TCGv pred, unsigned slot_num) { TCGv slot_mask = tcg_const_tl(1 << slot_num); TCGv tmp = tcg_temp_new(); From patchwork Thu Apr 15 16:34:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alessandro Di Federico X-Patchwork-Id: 12205785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5448FC433B4 for ; Thu, 15 Apr 2021 16:54:26 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D33E961166 for ; Thu, 15 Apr 2021 16:54:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D33E961166 Authentication-Results: mail.kernel.org; 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bh=8kkGbIESYw21aMYRMMd2RPq99rDaSprGzjF3+F+2fVc=; b=oYOl5eRgSfM8LETP1jUHjgBQyS kkfywWjsEymupkNPL+WfF36b9K3z963Om7bmJrqLFy3T7/BGqCgcqZ4/g3QUXHKaZM4ckJRBckiXq 9aXAHQLRbHqKqtWyRdmW0JIs0KphcKNjQ+D8S2YRjadVT1Sw+SvF6IHkwcyWHDKOttCo=; To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng, nizzo@rev.ng, philmd@redhat.com, richard.henderson@linaro.org, Alessandro Di Federico Subject: [PATCH v4 05/12] target/hexagon: make helper functions non-static Date: Thu, 15 Apr 2021 18:34:48 +0200 Message-Id: <20210415163455.3839169-6-ale.qemu@rev.ng> In-Reply-To: <20210415163455.3839169-1-ale.qemu@rev.ng> References: <20210415163455.3839169-1-ale.qemu@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico X-Patchwork-Original-From: Alessandro Di Federico via From: Alessandro Di Federico From: Paolo Montesel Make certain helper functions non-static, making them available outside genptr.c. These functions are required by code generated by the idef-parser. Signed-off-by: Alessandro Di Federico Signed-off-by: Paolo Montesel Reviewed-by: Richard Henderson --- target/hexagon/genptr.c | 7 ++++--- target/hexagon/genptr.h | 6 ++++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index fd18aabe8d..1ddb4360f1 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -26,8 +26,9 @@ #include "translate.h" #include "macros.h" #include "gen_tcg.h" +#include "genptr.h" -static inline TCGv gen_read_preg(TCGv pred, uint8_t num) +TCGv gen_read_preg(TCGv pred, uint8_t num) { tcg_gen_mov_tl(pred, hex_pred[num]); return pred; @@ -54,7 +55,7 @@ static inline void gen_log_predicated_reg_write(int rnum, TCGv val, tcg_temp_free(slot_mask); } -static inline void gen_log_reg_write(int rnum, TCGv val) +void gen_log_reg_write(int rnum, TCGv val) { tcg_gen_mov_tl(hex_new_value[rnum], val); #if HEX_DEBUG @@ -118,7 +119,7 @@ static void gen_log_reg_write_pair(int rnum, TCGv_i64 val) #endif } -static inline void gen_log_pred_write(int pnum, TCGv val) +void gen_log_pred_write(int pnum, TCGv val) { TCGv zero = tcg_const_tl(0); TCGv base_val = tcg_temp_new(); diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index c158005d2a..e1dcd24b0e 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -19,7 +19,13 @@ #define HEXAGON_GENPTR_H #include "insn.h" +#include "tcg/tcg.h" +#include "translate.h" extern const SemanticInsn opcode_genptr[]; +TCGv gen_read_preg(TCGv pred, uint8_t num); +void gen_log_reg_write(int rnum, TCGv val); +void gen_log_pred_write(int pnum, TCGv val); + #endif From patchwork Thu Apr 15 16:34:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alessandro Di Federico X-Patchwork-Id: 12205799 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E6B2C433ED for ; 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Thu, 15 Apr 2021 12:35:17 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=de9d+sgUljmQznIzRM11ZJmmsY24Ut5GL4mk3Ee2im4=; b=Jc+i0r+nNC7W6bz1tZTCtB6ZUB UHeDFsBe0ucOqfBpdrlfVtUxXWjCMDgdyfYtDkmgI5dQy/PM3lv4FXlOb5hKVoh6XbjkcELUjKSMh pka4lKIJ+7V6fQi+T1Edn2pyLEhOQ9FUKsVMVlH6P+aMiLSSpnHvhCt+BDwNywTsY9QA=; To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng, nizzo@rev.ng, philmd@redhat.com, richard.henderson@linaro.org, Alessandro Di Federico Subject: [PATCH v4 06/12] target/hexagon: introduce new helper functions Date: Thu, 15 Apr 2021 18:34:49 +0200 Message-Id: <20210415163455.3839169-7-ale.qemu@rev.ng> In-Reply-To: <20210415163455.3839169-1-ale.qemu@rev.ng> References: <20210415163455.3839169-1-ale.qemu@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico X-Patchwork-Original-From: Alessandro Di Federico via From: Alessandro Di Federico From: Niccolò Izzo These helpers will be employed by the idef-parser generated code. Signed-off-by: Alessandro Di Federico Signed-off-by: Niccolò Izzo --- target/hexagon/genptr.c | 188 ++++++++++++++++++++++++++++++++++++++++ target/hexagon/genptr.h | 22 +++++ target/hexagon/macros.h | 9 ++ 3 files changed, 219 insertions(+) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 1ddb4360f1..024419bf39 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -28,6 +28,12 @@ #include "gen_tcg.h" #include "genptr.h" +TCGv gen_read_reg(TCGv result, int num) +{ + tcg_gen_mov_tl(result, hex_gpr[num]); + return result; +} + TCGv gen_read_preg(TCGv pred, uint8_t num) { tcg_gen_mov_tl(pred, hex_pred[num]); @@ -330,5 +336,187 @@ static inline void gen_store_conditional8(CPUHexagonState *env, tcg_gen_movi_tl(hex_llsc_addr, ~0); } +void gen_store32(TCGv vaddr, TCGv src, tcg_target_long width, unsigned slot) +{ + tcg_gen_mov_tl(hex_store_addr[slot], vaddr); + tcg_gen_movi_tl(hex_store_width[slot], width); + tcg_gen_mov_tl(hex_store_val32[slot], src); +} + +void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + unsigned slot) +{ + gen_store32(vaddr, src, 1, slot); + ctx->store_width[slot] = 1; +} + +void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + unsigned slot) +{ + gen_store32(vaddr, src, 2, slot); + ctx->store_width[slot] = 2; +} + +void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + unsigned slot) +{ + gen_store32(vaddr, src, 4, slot); + ctx->store_width[slot] = 4; +} + + +void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, DisasContext *ctx, + unsigned slot) +{ + tcg_gen_mov_tl(hex_store_addr[slot], vaddr); + tcg_gen_movi_tl(hex_store_width[slot], 8); + tcg_gen_mov_i64(hex_store_val64[slot], src); + ctx->store_width[slot] = 8; +} + +void gen_set_usr_field(int field, TCGv val) +{ + tcg_gen_deposit_tl(hex_gpr[HEX_REG_USR], hex_gpr[HEX_REG_USR], val, + reg_field_info[field].offset, + reg_field_info[field].width); +} + +void gen_set_usr_fieldi(int field, int x) +{ + TCGv val = tcg_const_tl(x); + gen_set_usr_field(field, val); + tcg_temp_free(val); +} + +void gen_write_new_pc(TCGv addr) +{ + /* If there are multiple branches in a packet, ignore the second one */ + TCGv zero = tcg_const_tl(0); + tcg_gen_movcond_tl(TCG_COND_NE, hex_next_PC, hex_branch_taken, zero, + hex_next_PC, addr); + tcg_gen_movi_tl(hex_branch_taken, 1); + tcg_temp_free(zero); +} + +void gen_sat_i32(TCGv dest, TCGv source, int width) +{ + TCGv max_val = tcg_const_i32((1 << (width - 1)) - 1); + TCGv min_val = tcg_const_i32(-(1 << (width - 1))); + tcg_gen_smin_tl(dest, source, max_val); + tcg_gen_smax_tl(dest, dest, min_val); + tcg_temp_free_i32(max_val); + tcg_temp_free_i32(min_val); +} + +void gen_sat_i32_ext(TCGv ovfl, TCGv dest, TCGv source, int width) +{ + gen_sat_i32(dest, source, width); + TCGv zero = tcg_const_i32(0); + TCGv one = tcg_const_i32(1); + tcg_gen_movcond_i32(TCG_COND_NE, ovfl, source, dest, one, zero); + tcg_temp_free_i32(zero); + tcg_temp_free_i32(one); +} + +void gen_satu_i32(TCGv dest, TCGv source, int width) +{ + TCGv max_val = tcg_const_i32((1 << width) - 1); + tcg_gen_movcond_i32(TCG_COND_GTU, dest, source, max_val, max_val, source); + TCGv_i32 zero = tcg_const_i32(0); + tcg_gen_movcond_i32(TCG_COND_LT, dest, source, zero, zero, dest); + tcg_temp_free_i32(max_val); + tcg_temp_free_i32(zero); +} + +void gen_satu_i32_ext(TCGv ovfl, TCGv dest, TCGv source, int width) +{ + gen_satu_i32(dest, source, width); + TCGv zero = tcg_const_i32(0); + TCGv one = tcg_const_i32(1); + tcg_gen_movcond_i32(TCG_COND_NE, ovfl, dest, source, one, zero); + tcg_temp_free_i32(zero); + tcg_temp_free_i32(one); +} + +void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width) +{ + TCGv_i64 max_val = tcg_const_i64((1 << (width - 1)) - 1); + TCGv_i64 min_val = tcg_const_i64(-(1 << (width - 1))); + tcg_gen_smin_i64(dest, source, max_val); + tcg_gen_smax_i64(dest, dest, min_val); + tcg_temp_free_i64(max_val); + tcg_temp_free_i64(min_val); +} + +void gen_sat_i64_ext(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width) +{ + gen_sat_i64(dest, source, width); + TCGv_i64 ovfl_64 = tcg_temp_new_i64(); + TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 one = tcg_const_i64(1); + tcg_gen_movcond_i64(TCG_COND_NE, ovfl_64, dest, source, one, zero); + tcg_gen_trunc_i64_tl(ovfl, ovfl_64); + tcg_temp_free_i64(ovfl_64); + tcg_temp_free_i64(zero); + tcg_temp_free_i64(one); +} + +void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width) +{ + TCGv_i64 max_val = tcg_const_i64((1 << width) - 1); + tcg_gen_movcond_i64(TCG_COND_GTU, dest, source, max_val, max_val, source); + TCGv_i64 zero = tcg_const_i64(0); + tcg_gen_movcond_i64(TCG_COND_LT, dest, source, zero, zero, dest); + tcg_temp_free_i64(max_val); + tcg_temp_free_i64(zero); +} + +void gen_satu_i64_ext(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width) +{ + gen_sat_i64(dest, source, width); + TCGv_i64 ovfl_64 = tcg_temp_new_i64(); + TCGv_i64 zero = tcg_const_i64(0); + TCGv_i64 one = tcg_const_i64(1); + tcg_gen_movcond_i64(TCG_COND_NE, ovfl_64, dest, source, one, zero); + tcg_gen_trunc_i64_tl(ovfl, ovfl_64); + tcg_temp_free_i64(ovfl_64); + tcg_temp_free_i64(zero); + tcg_temp_free_i64(one); +} + +void gen_fbrev(TCGv result, TCGv src) +{ + TCGv lo = tcg_temp_new(); + TCGv tmp1 = tcg_temp_new(); + TCGv tmp2 = tcg_temp_new(); + + /* Bit reversal of low 16 bits */ + tcg_gen_extract_tl(lo, src, 0, 16); + tcg_gen_andi_tl(tmp1, lo, 0xaaaa); + tcg_gen_shri_tl(tmp1, tmp1, 1); + tcg_gen_andi_tl(tmp2, lo, 0x5555); + tcg_gen_shli_tl(tmp2, tmp2, 1); + tcg_gen_or_tl(lo, tmp1, tmp2); + tcg_gen_andi_tl(tmp1, lo, 0xcccc); + tcg_gen_shri_tl(tmp1, tmp1, 2); + tcg_gen_andi_tl(tmp2, lo, 0x3333); + tcg_gen_shli_tl(tmp2, tmp2, 2); + tcg_gen_or_tl(lo, tmp1, tmp2); + tcg_gen_andi_tl(tmp1, lo, 0xf0f0); + tcg_gen_shri_tl(tmp1, tmp1, 4); + tcg_gen_andi_tl(tmp2, lo, 0x0f0f); + tcg_gen_shli_tl(tmp2, tmp2, 4); + tcg_gen_or_tl(lo, tmp1, tmp2); + tcg_gen_bswap16_tl(lo, lo); + + /* Final tweaks */ + tcg_gen_deposit_tl(result, src, lo, 0, 16); + tcg_gen_or_tl(result, result, lo); + + tcg_temp_free(lo); + tcg_temp_free(tmp1); + tcg_temp_free(tmp2); +} + #include "tcg_funcs_generated.c.inc" #include "tcg_func_table_generated.c.inc" diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index e1dcd24b0e..8ff74a4aa8 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -24,8 +24,30 @@ extern const SemanticInsn opcode_genptr[]; +TCGv gen_read_reg(TCGv result, int num); TCGv gen_read_preg(TCGv pred, uint8_t num); void gen_log_reg_write(int rnum, TCGv val); void gen_log_pred_write(int pnum, TCGv val); +void gen_store32(TCGv vaddr, TCGv src, tcg_target_long width, unsigned slot); +void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + unsigned slot); +void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + unsigned slot); +void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + unsigned slot); +void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, DisasContext *ctx, + unsigned slot); +void gen_write_new_pc(TCGv addr); +void gen_set_usr_field(int field, TCGv val); +void gen_set_usr_fieldi(int field, int x); +void gen_sat_i32(TCGv dest, TCGv source, int width); +void gen_sat_i32_ext(TCGv ovfl, TCGv dest, TCGv source, int width); +void gen_satu_i32(TCGv dest, TCGv source, int width); +void gen_satu_i32_ext(TCGv ovfl, TCGv dest, TCGv source, int width); +void gen_sat_i64(TCGv_i64 dest, TCGv_i64 source, int width); +void gen_sat_i64_ext(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width); +void gen_satu_i64(TCGv_i64 dest, TCGv_i64 source, int width); +void gen_satu_i64_ext(TCGv ovfl, TCGv_i64 dest, TCGv_i64 source, int width); +void gen_fbrev(TCGv result, TCGv src); #endif diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index d9473c8823..94357c3e42 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -149,7 +149,16 @@ #define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT) #endif +#ifdef QEMU_GENERATE +static inline void gen_cancel(unsigned slot) +{ + tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, 1 << slot); +} + +#define CANCEL gen_cancel(slot); +#else #define CANCEL cancel_slot(env, slot) +#endif #define LOAD_CANCEL(EA) do { CANCEL; } while (0) From patchwork Thu Apr 15 16:34:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alessandro Di Federico X-Patchwork-Id: 12205861 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADB94C433ED for ; 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envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico X-Patchwork-Original-From: Alessandro Di Federico via From: Alessandro Di Federico From: Paolo Montesel Signed-off-by: Alessandro Di Federico Signed-off-by: Paolo Montesel Reviewed-by: Richard Henderson --- target/hexagon/translate.c | 3 ++- target/hexagon/translate.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index eeaad5f8ba..30ff3c5d51 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -503,11 +503,12 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx) if (decode_packet(nwords, words, &pkt, false) > 0) { HEX_DEBUG_PRINT_PKT(&pkt); gen_start_packet(ctx, &pkt); + ctx->npc = ctx->base.pc_next + pkt.encod_pkt_size_in_bytes; for (i = 0; i < pkt.num_insns; i++) { gen_insn(env, ctx, &pkt.insn[i], &pkt); } gen_commit_packet(ctx, &pkt); - ctx->base.pc_next += pkt.encod_pkt_size_in_bytes; + ctx->base.pc_next = ctx->npc; } else { gen_exception(HEX_EXCP_INVALID_PACKET); ctx->base.is_jmp = DISAS_NORETURN; diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 938f7fbb9f..2195e20f4b 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -36,6 +36,7 @@ typedef struct DisasContext { int preg_log_idx; uint8_t store_width[STORES_MAX]; uint8_t s1_store_processed; + uint32_t npc; } DisasContext; static inline void ctx_log_reg_write(DisasContext *ctx, int rnum) From patchwork Thu Apr 15 16:34:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alessandro Di Federico X-Patchwork-Id: 12205789 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BF7DC433B4 for ; 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Thu, 15 Apr 2021 12:35:20 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=o7eOwTQaaCKTsZNaE/Q7xS097X+2rNgLIZreM2cWgvI=; b=uCiinyZA9YcRPGoonmbvqboZ2t jIOrwB9O3I3MYViASR9Em2Pft0GmSb20mx/lhyXxZSifL+xIg4DE2+us3Jc7Ld9q/fxRXAswnMsnP HwNqyP2rHA/28XXhRGDVPzOlnGVTkHYn+la0SWcIktXh7zV4ylLwlgW6MojiTxtTIKMI=; To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng, nizzo@rev.ng, philmd@redhat.com, richard.henderson@linaro.org, Alessandro Di Federico Subject: [PATCH v4 08/12] target/hexagon: prepare input for the idef-parser Date: Thu, 15 Apr 2021 18:34:51 +0200 Message-Id: <20210415163455.3839169-9-ale.qemu@rev.ng> In-Reply-To: <20210415163455.3839169-1-ale.qemu@rev.ng> References: <20210415163455.3839169-1-ale.qemu@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico X-Patchwork-Original-From: Alessandro Di Federico via From: Alessandro Di Federico From: Alessandro Di Federico Introduce infrastructure necessary to produce a file suitable for being parsed by the idef-parser. Signed-off-by: Alessandro Di Federico --- target/hexagon/gen_idef_parser_funcs.py | 114 ++++++++++++++++++ target/hexagon/idef-parser/macros.inc | 150 ++++++++++++++++++++++++ target/hexagon/idef-parser/prepare | 24 ++++ target/hexagon/meson.build | 17 +++ 4 files changed, 305 insertions(+) create mode 100644 target/hexagon/gen_idef_parser_funcs.py create mode 100644 target/hexagon/idef-parser/macros.inc create mode 100755 target/hexagon/idef-parser/prepare diff --git a/target/hexagon/gen_idef_parser_funcs.py b/target/hexagon/gen_idef_parser_funcs.py new file mode 100644 index 0000000000..7b8e0f6981 --- /dev/null +++ b/target/hexagon/gen_idef_parser_funcs.py @@ -0,0 +1,114 @@ +#!/usr/bin/env python3 + +## +## Copyright(c) 2019-2021 rev.ng Srls. All Rights Reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, see . +## + +import sys +import re +import string +from io import StringIO + +import hex_common + +## +## Generate code to be fed to the idef_parser +## +## Consider A2_add: +## +## Rd32=add(Rs32,Rt32), { RdV=RsV+RtV;} +## +## We produce: +## +## A2_add(RdV, in RsV, in RtV) { +## { RdV=RsV+RtV;} +## } +## +## A2_add represents the instruction tag. Then we have a list of TCGv +## that the code generated by the parser can expect in input. Some of +## them are inputs ("in" prefix), while some others are outputs. +## +def main(): + hex_common.read_semantics_file(sys.argv[1]) + hex_common.read_attribs_file(sys.argv[2]) + hex_common.read_overrides_file(sys.argv[3]) + hex_common.calculate_attribs() + tagregs = hex_common.get_tagregs() + tagimms = hex_common.get_tagimms() + + with open(sys.argv[4], 'w') as f: + f.write('#include "macros.inc"\n\n') + + for tag in hex_common.tags: + ## Skip the priv instructions + if ( "A_PRIV" in hex_common.attribdict[tag] ) : + continue + ## Skip the guest instructions + if ( "A_GUEST" in hex_common.attribdict[tag] ) : + continue + ## Skip instructions using switch + if ( tag in {'S4_vrcrotate_acc', 'S4_vrcrotate'} ) : + continue + ## Skip trap instructions + if ( tag in {'J2_trap0', 'J2_trap1'} ) : + continue + ## Skip 128-bit instructions + if ( tag in {'A7_croundd_ri', 'A7_croundd_rr'} ) : + continue + ## Skip other unsupported instructions + if ( tag.startswith('S2_cabacdecbin') ) : + continue + if ( tag.startswith('Y') ) : + continue + if ( tag.startswith('V6_') ) : + continue + if ( tag.startswith('F') ) : + continue + if ( tag.endswith('_locked') ) : + continue + + regs = tagregs[tag] + imms = tagimms[tag] + + arguments = [] + if hex_common.need_ea(tag): + arguments.append("EA") + + for regtype,regid,toss,numregs in regs: + prefix = "in " if hex_common.is_read(regid) else "" + + is_pair = hex_common.is_pair(regid) + is_single_old = (hex_common.is_single(regid) + and hex_common.is_old_val(regtype, regid, tag)) + is_single_new = (hex_common.is_single(regid) + and hex_common.is_new_val(regtype, regid, tag)) + + if is_pair or is_single_old: + arguments.append("%s%s%sV" % (prefix, regtype, regid)) + elif is_single_new: + arguments.append("%s%s%sN" % (prefix, regtype, regid)) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + + for immlett,bits,immshift in imms: + arguments.append(hex_common.imm_name(immlett)) + + f.write("%s(%s) {\n" % (tag, ", ".join(arguments))) + f.write(" %s\n" % hex_common.semdict[tag]) + f.write("}\n\n") + +if __name__ == "__main__": + main() diff --git a/target/hexagon/idef-parser/macros.inc b/target/hexagon/idef-parser/macros.inc new file mode 100644 index 0000000000..a0e16180c9 --- /dev/null +++ b/target/hexagon/idef-parser/macros.inc @@ -0,0 +1,150 @@ +/* + * Copyright(c) 2019-2021 rev.ng Srls. All Rights Reserved. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +/* Copy rules */ +#define fLSBOLD(VAL) (fGETBIT(0, VAL)) +#define fSATH(VAL) fSATN(16, VAL) +#define fSATUH(VAL) fSATUN(16, VAL) +#define fVSATH(VAL) fVSATN(16, VAL) +#define fVSATUH(VAL) fVSATUN(16, VAL) +#define fSATUB(VAL) fSATUN(8, VAL) +#define fSATB(VAL) fSATN(8, VAL) +#define fVSATUB(VAL) fVSATUN(8, VAL) +#define fVSATB(VAL) fVSATN(8, VAL) +#define fCALL(A) fWRITE_LR(fREAD_NPC()); fWRITE_NPC(A); +#define fCALLR(A) fWRITE_LR(fREAD_NPC()); fWRITE_NPC(A); +#define fCAST2_8s(A) fSXTN(16, 64, A) +#define fCAST2_8u(A) fZXTN(16, 64, A) +#define fCAST8S_16S(A) (fSXTN(64, 128, A)) +#define fCAST16S_8S(A) (fSXTN(128, 64, A)) +#define fVSATW(A) fVSATN(32, fCAST8_8s(A)) +#define fSATW(A) fSATN(32, fCAST8_8s(A)) +#define fVSAT(A) fVSATN(32, A) +#define fSAT(A) fSATN(32, A) + +/* Ease parsing */ +#define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00) +#define fREAD_GP() (Constant_extended ? (0) : GP) +#define fCLIP(DST, SRC, U) (DST = fMIN((1 << U) - 1, fMAX(SRC, -(1 << U)))) +#define fBIDIR_ASHIFTL(SRC, SHAMT, REGSTYPE) \ + ((SHAMT > 0) ? \ + (fCAST##REGSTYPE##s(SRC) << SHAMT) : \ + (fCAST##REGSTYPE##s(SRC) >> -SHAMT)) + +#define fBIDIR_LSHIFTL(SRC, SHAMT, REGSTYPE) \ + ((SHAMT > 0) ? \ + (fCAST##REGSTYPE##u(SRC) << SHAMT) : \ + (fCAST##REGSTYPE##u(SRC) >>> -SHAMT)) + +#define fBIDIR_ASHIFTR(SRC, SHAMT, REGSTYPE) \ + ((SHAMT > 0) ? \ + (fCAST##REGSTYPE##s(SRC) >> SHAMT) : \ + (fCAST##REGSTYPE##s(SRC) << -SHAMT)) + +#define fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE) \ + (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \ + : (fCAST##REGSTYPE(SRC) >> (SHAMT))) + +#define fBIDIR_LSHIFTR(SRC, SHAMT, REGSTYPE) \ + fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##u) + +#define fSATVALN(N, VAL) \ + fSET_OVERFLOW( \ + ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1) \ + ) + +#define fSAT_ORIG_SHL(A, ORIG_REG) \ + (((fCAST4s((fSAT(A)) ^ (fCAST4s(ORIG_REG)))) < 0) \ + ? fSATVALN(32, (fCAST4s(ORIG_REG))) \ + : ((((ORIG_REG) > 0) && ((A) == 0)) ? fSATVALN(32, (ORIG_REG)) \ + : fSAT(A))) + +#define fBIDIR_ASHIFTR_SAT(SRC, SHAMT, REGSTYPE) \ + (((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) \ + << ((-(SHAMT)) - 1)) << 1, (SRC)) \ + : (fCAST##REGSTYPE##s(SRC) >> (SHAMT))) + +#define fBIDIR_ASHIFTL_SAT(SRC, SHAMT, REGSTYPE) \ + (((SHAMT) < 0) \ + ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT)) - 1)) >> 1) \ + : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT), (SRC))) + +#define fEXTRACTU_BIDIR(INREG, WIDTH, OFFSET) \ + (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8))) + +#define fADDSAT64(DST, A, B) \ + __a = fCAST8u(A); \ + __b = fCAST8u(B); \ + __sum = __a + __b; \ + __xor = __a ^ __b; \ + __mask = fCAST8s(0x8000000000000000ULL); \ + if (((__a ^ __b) | ~(__a ^ __sum)) & __mask) { \ + DST = __sum; \ + } else { \ + DST = ((__sum & __mask) >> 63) + __mask; \ + fSET_OVERFLOW(); \ + } + +/* Negation operator */ +#define fLSBOLDNOT(VAL) fGETBIT(0, ~VAL) +#define fLSBNEWNOT(PNUM) (!fLSBNEW(PNUM)) +#define fLSBNEW0NOT (!fLSBNEW0) + +/* Assignments */ +#define fPCALIGN(IMM) (IMM = IMM & ~3) +#define fWRITE_LR(A) (LR = A) +#define fWRITE_FP(A) (FP = A) +#define fWRITE_SP(A) (SP = A) +#define fBRANCH(LOC, TYPE) (PC = LOC) +#define fJUMPR(REGNO, TARGET, TYPE) (PC = TARGET) +#define fWRITE_LOOP_REGS0(START, COUNT) SA0 = START; (LC0 = COUNT) +#define fWRITE_LOOP_REGS1(START, COUNT) SA1 = START; (LC1 = COUNT) +#define fWRITE_LC0(VAL) (LC0 = VAL) +#define fWRITE_LC1(VAL) (LC1 = VAL) +#define fSET_LPCFG(VAL) (USR.LPCFG = VAL) +#define fWRITE_P0(VAL) P0 = VAL; +#define fWRITE_P1(VAL) P1 = VAL; +#define fWRITE_P3(VAL) P3 = VAL; +#define fEA_RI(REG, IMM) (EA = REG + IMM) +#define fEA_RRs(REG, REG2, SCALE) (EA = REG + (REG2 << SCALE)) +#define fEA_IRs(IMM, REG, SCALE) (EA = IMM + (REG << SCALE)) +#define fEA_IMM(IMM) (EA = IMM) +#define fEA_REG(REG) (EA = REG) +#define fEA_BREVR(REG) (EA = fbrev(REG)) +#define fEA_GPI(IMM) (EA = fREAD_GP() + IMM) +#define fPM_I(REG, IMM) (REG = REG + IMM) +#define fPM_M(REG, MVAL) (REG = REG + MVAL) +#define fWRITE_NPC(VAL) (PC = VAL) + +/* Unary operators */ +#define fROUND(A) (A + 0x8000) + +/* Binary operators */ +#define fADD128(A, B) (A + B) +#define fSUB128(A, B) (A - B) +#define fSHIFTR128(A, B) (size8s_t) (A >> B) +#define fSHIFTL128(A, B) (A << B) +#define fAND128(A, B) (A & B) +#define fSCALE(N, A) (A << N) +#define fASHIFTR(SRC, SHAMT, REGSTYPE) (SRC >> SHAMT) +#define fLSHIFTR(SRC, SHAMT, REGSTYPE) (SRC >>> SHAMT) +#define fROTL(SRC, SHAMT, REGSTYPE) fROTL(SRC, SHAMT) +#define fASHIFTL(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) << SHAMT) + +/* Purge non-relavant parts */ +#define fHIDE(A) +#define fBRANCH_SPECULATE_STALL(A, B, C, D, E) diff --git a/target/hexagon/idef-parser/prepare b/target/hexagon/idef-parser/prepare new file mode 100755 index 0000000000..9b662dea18 --- /dev/null +++ b/target/hexagon/idef-parser/prepare @@ -0,0 +1,24 @@ +#!/bin/bash + +# +# Copyright(c) 2019-2021 rev.ng Srls. All Rights Reserved. +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . +# + +set -e +set -o pipefail + +# Run the preprocessor and drop comments +cpp "$@" | grep -v '^#' diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index bb0b4fb621..5949d079a5 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -20,6 +20,7 @@ hexagon_ss = ss.source_set() hex_common_py = 'hex_common.py' attribs_def = meson.current_source_dir() / 'attribs_def.h.inc' gen_tcg_h = meson.current_source_dir() / 'gen_tcg.h' +idef_parser_dir = meson.current_source_dir() / 'idef-parser' # # Step 1 @@ -176,4 +177,20 @@ hexagon_ss.add(files( 'conv_emu.c', )) +idef_parser_input_generated = custom_target( + 'idef_parser_input.h.inc', + output: 'idef_parser_input.h.inc', + depend_files: [hex_common_py], + command: [python, files('gen_idef_parser_funcs.py'), semantics_generated, attribs_def, gen_tcg_h, '@OUTPUT@'], +) + +idef_parser_input_generated_prep = custom_target( + 'idef_parser_input.preprocessed.h.inc', + output: 'idef_parser_input.preprocessed.h.inc', + input: idef_parser_input_generated, + capture: true, + depend_files: [hex_common_py], + command: [idef_parser_dir / 'prepare', '@INPUT@', '-I' + idef_parser_dir], +) + target_arch += {'hexagon': hexagon_ss} From patchwork Thu Apr 15 16:34:52 2021 Content-Type: text/plain; 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dmarc=pass (p=none dis=none) header.from=nongnu.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:56338 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lX5Oc-0001Om-3E for qemu-devel@archiver.kernel.org; Thu, 15 Apr 2021 13:03:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42154) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lX4xl-0004Kx-A3 for qemu-devel@nongnu.org; Thu, 15 Apr 2021 12:35:32 -0400 Received: from rev.ng ([5.9.113.41]:32787) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lX4xW-0006gE-Ct for qemu-devel@nongnu.org; Thu, 15 Apr 2021 12:35:28 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=aeIOArBBmeoTqsOuwjEMM5gghx/A82/c7Mqhyj14Xi4=; b=xjRv2q1r+zhsXEOddmG6qlFl72 P1NMpWhbL2+mkOFsiDVpdx35RmioqRgat/DG+12GUigX2Aj/1ysuPPnsYWKNzwf/+PILaZkzrYlVL r1m39cxGfn0tSaIE5gAEacY5tnfcjfXWys+G0wbGWYA8KdG27cSafhQlcAmrMMrkzTP4=; To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng, nizzo@rev.ng, philmd@redhat.com, richard.henderson@linaro.org, Alessandro Di Federico Subject: [PATCH v4 09/12] target/hexagon: import lexer for idef-parser Date: Thu, 15 Apr 2021 18:34:52 +0200 Message-Id: <20210415163455.3839169-10-ale.qemu@rev.ng> In-Reply-To: <20210415163455.3839169-1-ale.qemu@rev.ng> References: <20210415163455.3839169-1-ale.qemu@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico X-Patchwork-Original-From: Alessandro Di Federico via From: Alessandro Di Federico From: Paolo Montesel Signed-off-by: Alessandro Di Federico Signed-off-by: Paolo Montesel --- target/hexagon/idef-parser/idef-parser.h | 254 ++++++++ target/hexagon/idef-parser/idef-parser.lex | 611 ++++++++++++++++++ target/hexagon/meson.build | 4 + tests/docker/dockerfiles/alpine.docker | 1 + tests/docker/dockerfiles/centos7.docker | 1 + tests/docker/dockerfiles/centos8.docker | 1 + tests/docker/dockerfiles/debian10.docker | 1 + .../dockerfiles/fedora-i386-cross.docker | 1 + .../dockerfiles/fedora-win32-cross.docker | 1 + .../dockerfiles/fedora-win64-cross.docker | 1 + tests/docker/dockerfiles/fedora.docker | 1 + tests/docker/dockerfiles/opensuse-leap.docker | 1 + tests/docker/dockerfiles/ubuntu.docker | 1 + tests/docker/dockerfiles/ubuntu1804.docker | 1 + tests/docker/dockerfiles/ubuntu2004.docker | 3 +- 15 files changed, 882 insertions(+), 1 deletion(-) create mode 100644 target/hexagon/idef-parser/idef-parser.h create mode 100644 target/hexagon/idef-parser/idef-parser.lex diff --git a/target/hexagon/idef-parser/idef-parser.h b/target/hexagon/idef-parser/idef-parser.h new file mode 100644 index 0000000000..f9aaff71f6 --- /dev/null +++ b/target/hexagon/idef-parser/idef-parser.h @@ -0,0 +1,254 @@ +/* + * Copyright(c) 2019-2021 rev.ng Srls. All Rights Reserved. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef IDEF_PARSER_H +#define IDEF_PARSER_H + +#include +#include +#include +#include + +#define TCGV_NAME_SIZE 7 +#define MAX_WRITTEN_REGS 32 +#define OFFSET_STR_LEN 32 +#define ALLOC_LIST_LEN 32 +#define ALLOC_NAME_SIZE 32 +#define INIT_LIST_LEN 32 +#define OUT_BUF_LEN (1024 * 1024) +#define SIGNATURE_BUF_LEN (128 * 1024) +#define HEADER_BUF_LEN (128 * 1024) + +/* Variadic macros to wrap the buffer printing functions */ +#define EMIT(c, ...) \ + do { \ + g_string_append_printf((c)->out_str, __VA_ARGS__); \ + } while (0) + +#define EMIT_SIG(c, ...) \ + do { \ + g_string_append_printf((c)->signature_str, __VA_ARGS__); \ + } while (0) + +#define EMIT_HEAD(c, ...) \ + do { \ + g_string_append_printf((c)->header_str, __VA_ARGS__); \ + } while (0) + +/** + * Type of register, assigned to the HexReg.type field + */ +typedef enum {GENERAL_PURPOSE, CONTROL, MODIFIER, DOTNEW} RegType; + +/** + * Types of control registers, assigned to the HexReg.id field + */ +typedef enum {SP, FP, LR, GP, LC0, LC1, SA0, SA1} CregType; + +/** + * Identifier string of the control registers, indexed by the CregType enum + */ +extern const char *creg_str[]; + +/** + * Semantic record of the REG tokens, identifying registers + */ +typedef struct HexReg { + CregType id; /**< Identifier of the register */ + RegType type; /**< Type of the register */ + unsigned bit_width; /**< Bit width of the reg, 32 or 64 bits */ +} HexReg; + +/** + * Data structure, identifying a TCGv temporary value + */ +typedef struct HexTmp { + int index; /**< Index of the TCGv temporary value */ +} HexTmp; + +/** + * Enum of the possible immediated, an immediate is a value which is known + * at tinycode generation time, e.g. an integer value, not a TCGv + */ +enum ImmUnionTag {I, VARIABLE, VALUE, QEMU_TMP, IMM_PC, IMM_CONSTEXT}; + +/** + * Semantic record of the IMM token, identifying an immediate constant + */ +typedef struct HexImm { + union { + char id; /**< Identifier of the immediate */ + uint64_t value; /**< Immediate value (for VALUE type immediates) */ + uint64_t index; /**< Index of the immediate (for int temp vars) */ + }; + enum ImmUnionTag type; /**< Type of the immediate */ +} HexImm; + +/** + * Semantic record of the PRE token, identifying a predicate + */ +typedef struct HexPre { + char id; /**< Identifier of the predicate */ +} HexPre; + +/** + * Semantic record of the SAT token, identifying the saturate operator + */ +typedef struct HexSat { + bool set_overflow; /**< Set-overflow feature for the sat operator */ + bool is_unsigned; /**< Unsigned flag for the saturate operator */ +} HexSat; + +/** + * Semantic record of the CAST token, identifying the cast operator + */ +typedef struct HexCast { + int bit_width; /**< Bit width of the cast operator */ + bool is_unsigned; /**< Unsigned flag for the cast operator */ +} HexCast; + +/** + * Semantic record of the EXTRACT token, identifying the cast operator + */ +typedef struct HexExtract { + int bit_width; /**< Bit width of the extract operator */ + int storage_bit_width; /**< Actual bit width of the extract operator */ + bool is_unsigned; /**< Unsigned flag for the extract operator */ +} HexExtract; + +/** + * Semantic record of the MPY token, identifying the fMPY multiplication + * operator + */ +typedef struct HexMpy { + int first_bit_width; /**< Bit width of the first operand of fMPY op */ + int second_bit_width; /**< Bit width of the second operand of fMPY */ + bool first_unsigned; /**< Unsigned flag for the first operand of fMPY */ + bool second_unsigned; /**< Unsigned flag for second operand of fMPY */ +} HexMpy; + +/** + * Semantic record of the VARID token, identifying automatic variables + * of the input language + */ +typedef struct HexVar { + GString *name; /**< Name of the VARID automatic variable */ +} HexVar; + +/** + * Data structure uniquely identifying an automatic VARID variable, used for + * keeping track of declared variable, so that any variable is declared only + * once, and its properties are propagated through all the subsequent instances + * of that variable + */ +typedef struct Var { + GString *name; /**< Name of the VARID automatic variable */ + uint8_t bit_width; /**< Bit width of the VARID automatic variable */ + bool is_unsigned; /**< Unsigned flag for the VARID automatic var */ +} Var; + +/** + * Enum of the possible rvalue types, used in the HexValue.type field + */ +typedef enum RvalueUnionTag { + REGISTER, TEMP, IMMEDIATE, PREDICATE, VARID +} RvalueUnionTag; + +/** + * Semantic record of the rvalue token, identifying any numeric value, + * immediate or register based. The rvalue tokens are combined together + * through the use of several operators, to encode expressions + */ +typedef struct HexValue { + union { + HexReg reg; /**< rvalue of register type */ + HexTmp tmp; /**< rvalue of temporary type */ + HexImm imm; /**< rvalue of immediate type */ + HexPre pre; /**< rvalue of predicate type */ + HexVar var; /**< rvalue of automatic variable type */ + }; + RvalueUnionTag type; /**< Type of the rvalue */ + unsigned bit_width; /**< Bit width of the rvalue */ + bool is_unsigned; /**< Unsigned flag for the rvalue */ + bool is_dotnew; /**< rvalue of predicate type is dotnew? */ + bool is_manual; /**< Opt out of automatic freeing of params */ +} HexValue; + +/** + * State of ternary operator + */ +typedef enum TernaryState { IN_LEFT, IN_RIGHT } TernaryState; + +/** + * Data structure used to handle side effects inside ternary operators + */ +typedef struct Ternary { + TernaryState state; + HexValue cond; +} Ternary; + +/** + * Operator type, used for referencing the correct operator when calling the + * gen_bin_op() function, which in turn will generate the correct code to + * execute the operation between the two rvalues + */ +typedef enum OpType { + ADD_OP, SUB_OP, MUL_OP, ASL_OP, ASR_OP, LSR_OP, ANDB_OP, ORB_OP, + XORB_OP, ANDL_OP, MINI_OP, MAXI_OP, MOD_OP +} OpType; + +/** + * Data structure including instruction specific information, to be cleared + * out after the compilation of each instruction + */ +typedef struct Inst { + GString *name; /**< Name of the compiled instruction */ + char *code_begin; /**< Beginning of instruction input code */ + char *code_end; /**< End of instruction input code */ + int tmp_count; /**< Index of the last declared TCGv temp */ + int qemu_tmp_count; /**< Index of the last declared int temp */ + int if_count; /**< Index of the last declared if label */ + int error_count; /**< Number of generated errors */ + GArray *allocated; /**< Allocated VARID automatic vars */ + GArray *init_list; /**< List of initialized registers */ + GArray *strings; /**< Strings allocated by the instruction */ +} Inst; + +/** + * Data structure representing the whole translation context, which in a + * reentrant flex/bison parser just like ours is passed between the scanner + * and the parser, holding all the necessary information to perform the + * parsing, this data structure survives between the compilation of different + * instructions + * + */ +typedef struct Context { + void *scanner; /**< Reentrant parser state pointer */ + char *input_buffer; /**< Buffer containing the input code */ + GString *out_str; /**< String containing the output code */ + GString *signature_str; /**< String containing the signatures code */ + GString *header_str; /**< String containing the output code */ + FILE *defines_file; /**< FILE * of the generated header */ + FILE *output_file; /**< FILE * of the C output file */ + FILE *enabled_file; /**< FILE * of the list of enabled inst */ + GArray *ternary; /**< Array to track nesting of ternary ops */ + int total_insn; /**< Number of instructions in input file */ + int implemented_insn; /**< Instruction compiled without errors */ + Inst inst; /**< Parsing data of the current inst */ +} Context; + +#endif /* IDEF_PARSER_H */ diff --git a/target/hexagon/idef-parser/idef-parser.lex b/target/hexagon/idef-parser/idef-parser.lex new file mode 100644 index 0000000000..0d5f8e5b5c --- /dev/null +++ b/target/hexagon/idef-parser/idef-parser.lex @@ -0,0 +1,611 @@ +%option noyywrap noinput nounput +%option 8bit reentrant bison-bridge +%option warn nodefault +%option bison-locations + +%{ +/* + * Copyright(c) 2019-2021 rev.ng Srls. All Rights Reserved. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include +#include + +#include "idef-parser.h" +#include "idef-parser.tab.h" + +/* Keep track of scanner position for error message printout */ +#define YY_USER_ACTION yylloc->first_column = yylloc->last_column; \ + for (int i = 0; yytext[i] != '\0'; i++) { \ + yylloc->last_column++; \ + } + +/* Global Error Counter */ +int error_count; + +%} + +/* Definitions */ +DIGIT [0-9] +LOWER_ID [a-z] +UPPER_ID [A-Z] +ID LOWER_ID|UPPER_ID +INST_NAME [A-Z]+[0-9]_([A-Za-z]|[0-9]|_)+ +HEX_DIGIT [0-9a-fA-F] +REG_ID_32 e|s|d|t|u|v|x|y +REG_ID_64 ee|ss|dd|tt|uu|vv|xx|yy +SYS_ID_32 s|d +SYS_ID_64 ss|dd +LOWER_PRE d|s|t|u|v|e|x|x +IMM_ID r|s|S|u|U +VAR_ID [a-zA-Z_][a-zA-Z0-9_]* +SIGN_ID s|u + +/* Tokens */ +%% + +[ \t\f\v]+ { /* Ignore whitespaces. */ } +[\n\r]+ { /* Ignore newlines. */ } + +{INST_NAME} { yylval->string = g_string_new(yytext); + return INAME; } +"fFLOAT" | +"fUNFLOAT" | +"fDOUBLE" | +"fUNDOUBLE" | +"0.0" | +"0x1.0p52" | +"0x1.0p-52" { return FAIL; } +"R"{REG_ID_32}"V" { + yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = GENERAL_PURPOSE; + yylval->rvalue.reg.id = yytext[1]; + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + yylval->rvalue.is_dotnew = false; + return REG; } +"R"{REG_ID_32}"N" { + yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = DOTNEW; + yylval->rvalue.reg.id = yytext[1]; + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + yylval->rvalue.is_dotnew = true; + return REG; } +"R"{REG_ID_64}"V" { + yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = GENERAL_PURPOSE; + yylval->rvalue.reg.id = yytext[1]; + yylval->rvalue.reg.bit_width = 64; + yylval->rvalue.bit_width = 64; + yylval->rvalue.is_dotnew = false; + return REG; } +"R"{REG_ID_64}"N" { + yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = DOTNEW; + yylval->rvalue.reg.id = yytext[1]; + yylval->rvalue.reg.bit_width = 64; + yylval->rvalue.bit_width = 64; + yylval->rvalue.is_dotnew = true; + return REG; } +"MuV" { + yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = MODIFIER; + yylval->rvalue.reg.id = 'u'; + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + return REG; } +"C"{REG_ID_32}"V" { + yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = CONTROL; + yylval->rvalue.reg.id = yytext[1]; + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + yylval->rvalue.is_dotnew = false; + return REG; } +"C"{REG_ID_64}"V" { + yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = CONTROL; + yylval->rvalue.reg.id = yytext[1]; + yylval->rvalue.reg.bit_width = 64; + yylval->rvalue.bit_width = 64; + yylval->rvalue.is_dotnew = false; + return REG; } +{IMM_ID}"iV" { + yylval->rvalue.type = IMMEDIATE; + yylval->rvalue.is_unsigned = false; + yylval->rvalue.imm.type = VARIABLE; + yylval->rvalue.imm.id = yytext[0]; + yylval->rvalue.is_dotnew = false; + return IMM; } +"P"{LOWER_PRE}"V" { + yylval->rvalue.type = PREDICATE; + yylval->rvalue.pre.id = yytext[1]; + yylval->rvalue.bit_width = 32; + yylval->rvalue.is_dotnew = false; + return PRE; } +"P"{LOWER_PRE}"N" { + yylval->rvalue.type = PREDICATE; + yylval->rvalue.pre.id = yytext[1]; + yylval->rvalue.bit_width = 32; + yylval->rvalue.is_dotnew = true; + return PRE; } +"in R"{REG_ID_32}"V" { + yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = GENERAL_PURPOSE; + yylval->rvalue.reg.id = yytext[4]; + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + yylval->rvalue.is_dotnew = false; + return RREG; } +"in R"{REG_ID_64}"V" { + yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = GENERAL_PURPOSE; + yylval->rvalue.reg.id = yytext[4]; + yylval->rvalue.reg.bit_width = 64; + yylval->rvalue.bit_width = 64; + yylval->rvalue.is_dotnew = false; + return RREG; } +"in N"{REG_ID_32}"N" { + yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = DOTNEW; + yylval->rvalue.reg.id = yytext[4]; + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + yylval->rvalue.is_dotnew = true; + return RREG; } +"in N"{REG_ID_64}"N" { + yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = DOTNEW; + yylval->rvalue.reg.id = yytext[4]; + yylval->rvalue.reg.bit_width = 64; + yylval->rvalue.bit_width = 64; + yylval->rvalue.is_dotnew = true; + return RREG; } +"in P"{LOWER_PRE}"V" { + yylval->rvalue.type = PREDICATE; + yylval->rvalue.pre.id = yytext[4]; + yylval->rvalue.bit_width = 32; + yylval->rvalue.is_dotnew = false; + return RPRE; } +"in P"{LOWER_PRE}"N" { + yylval->rvalue.type = PREDICATE; + yylval->rvalue.pre.id = yytext[4]; + yylval->rvalue.bit_width = 32; + yylval->rvalue.is_dotnew = true; + return RPRE; } +"in MuV" { + yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = MODIFIER; + yylval->rvalue.reg.id = 'u'; + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + return RREG; } +"in C"{REG_ID_32}"V" { + yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = CONTROL; + yylval->rvalue.reg.id = yytext[4]; + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + yylval->rvalue.is_dotnew = false; + return RREG; } +"in C"{REG_ID_64}"V" { + yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = CONTROL; + yylval->rvalue.reg.id = yytext[4]; + yylval->rvalue.reg.bit_width = 64; + yylval->rvalue.bit_width = 64; + yylval->rvalue.is_dotnew = false; + return RREG; } +"fGEN_TCG_"{INST_NAME}"(" { return FWRAP; } +"IV1DEAD()" | +"fPAUSE(uiV);" { return ';'; } +"**" { return POW; } +"+=" { return INC; } +"-=" { return DEC; } +"++" { return PLUSPLUS; } +"&=" { return ANDA; } +"|=" { return ORA; } +"^=" { return XORA; } +"<<" { return ASL; } +">>" { return ASR; } +">>>" { return LSR; } +"==" { return EQ; } +"!=" { return NEQ; } +"<=" { return LTE; } +">=" { return GTE; } +"&&" { return ANDL; } +"||" { return ORL; } +"else" { return ELSE; } +"for" { return FOR; } +"fREAD_IREG" { return ICIRC; } +"fPART1" { return PART1; } +"if" { return IF; } +"fFRAME_SCRAMBLE" { return FSCR; } +"fFRAME_UNSCRAMBLE" { return FSCR; } +"fFRAMECHECK" { return FCHK; } +"Constant_extended" { return CONSTEXT; } +"fCL1_"{DIGIT} { return LOCNT; } +"fBREV_8" { return BREV_8; } +"fBREV_4" { return BREV_4; } +"fbrev" { return BREV; } +"fSXTN" { return SXT; } +"fZXTN" { return ZXT; } +"fDF_MAX" | +"fSF_MAX" | +"fMAX" { return MAX; } +"fDF_MIN" | +"fSF_MIN" | +"fMIN" { return MIN; } +"fABS" { return ABS; } +"fRNDN" { return ROUND; } +"fCRND" { return CROUND; } +"fCRNDN" { return CROUND; } +"fPM_CIRI" { return CIRCADD; } +"fPM_CIRR" { return CIRCADD; } +"fCOUNTONES_"{DIGIT} { return COUNTONES; } +"fSATN" { yylval->sat.set_overflow = true; + yylval->sat.is_unsigned = false; + return SAT; } +"fVSATN" { yylval->sat.set_overflow = false; + yylval->sat.is_unsigned = false; + return SAT; } +"fSATUN" { yylval->sat.set_overflow = false; + yylval->sat.is_unsigned = true; + return SAT; } +"fSE32_64" { yylval->cast.bit_width = 64; + yylval->cast.is_unsigned = false; + return CAST; } +"fCAST4_4u" { yylval->cast.bit_width = 32; + yylval->cast.is_unsigned = true; + return CAST; } +"fCAST4_8s" { yylval->cast.bit_width = 64; + yylval->cast.is_unsigned = false; + return CAST; } +"fCAST4_8u" { return CAST4_8U; } +"fCAST4u" { yylval->cast.bit_width = 32; + yylval->cast.is_unsigned = true; + return CAST; } +"fCAST4s" { yylval->cast.bit_width = 32; + yylval->cast.is_unsigned = false; + return CAST; } +"fCAST8_8u" { yylval->cast.bit_width = 64; + yylval->cast.is_unsigned = true; + return CAST; } +"fCAST8u" { yylval->cast.bit_width = 64; + yylval->cast.is_unsigned = true; + return CAST; } +"fCAST8s" { yylval->cast.bit_width = 64; + yylval->cast.is_unsigned = false; + return CAST; } +"fGETBIT" { yylval->extract.bit_width = 1; + yylval->extract.storage_bit_width = 1; + yylval->extract.is_unsigned = true; + return EXTRACT; } +"fGETBYTE" { yylval->extract.bit_width = 8; + yylval->extract.storage_bit_width = 8; + yylval->extract.is_unsigned = false; + return EXTRACT; } +"fGETUBYTE" { yylval->extract.bit_width = 8; + yylval->extract.storage_bit_width = 8; + yylval->extract.is_unsigned = true; + return EXTRACT; } +"fGETHALF" { yylval->extract.bit_width = 16; + yylval->extract.storage_bit_width = 16; + yylval->extract.is_unsigned = false; + return EXTRACT; } +"fGETUHALF" { yylval->extract.bit_width = 16; + yylval->extract.storage_bit_width = 16; + yylval->extract.is_unsigned = true; + return EXTRACT; } +"fGETWORD" { yylval->extract.bit_width = 32; + yylval->extract.storage_bit_width = 64; + yylval->extract.is_unsigned = false; + return EXTRACT; } +"fGETUWORD" { yylval->extract.bit_width = 32; + yylval->extract.storage_bit_width = 64; + yylval->extract.is_unsigned = true; + return EXTRACT; } +"fEXTRACTU_BITS" { return EXTBITS; } +"fEXTRACTU_RANGE" { return EXTRANGE; } +"fSETBIT" { yylval->cast.bit_width = 1; + yylval->cast.is_unsigned = false; + return DEPOSIT; } +"fSETBYTE" { yylval->cast.bit_width = 8; + yylval->cast.is_unsigned = false; + return DEPOSIT; } +"fSETHALF" { yylval->cast.bit_width = 16; + yylval->cast.is_unsigned = false; + return SETHALF; } +"fSETWORD" { yylval->cast.bit_width = 32; + yylval->cast.is_unsigned = false; + return DEPOSIT; } +"fINSERT_BITS" { return INSBITS; } +"fSETBITS" { return SETBITS; } +"fMPY8UU" { yylval->mpy.first_bit_width = 8; + yylval->mpy.second_bit_width = 8; + yylval->mpy.first_unsigned = true; + yylval->mpy.second_unsigned = true; + return MPY; } +"fMPY8US" { yylval->mpy.first_bit_width = 8; + yylval->mpy.second_bit_width = 8; + yylval->mpy.first_unsigned = true; + yylval->mpy.second_unsigned = false; + return MPY; } +"fMPY8SU" { yylval->mpy.first_bit_width = 8; + yylval->mpy.second_bit_width = 8; + yylval->mpy.first_unsigned = false; + yylval->mpy.second_unsigned = true; + return MPY; } +"fMPY8SS" { yylval->mpy.first_bit_width = 8; + yylval->mpy.second_bit_width = 8; + yylval->mpy.first_unsigned = false; + yylval->mpy.second_unsigned = false; + return MPY; } +"fMPY16UU" { yylval->mpy.first_bit_width = 16; + yylval->mpy.second_bit_width = 16; + yylval->mpy.first_unsigned = true; + yylval->mpy.second_unsigned = true; + return MPY; } +"fMPY16US" { yylval->mpy.first_bit_width = 16; + yylval->mpy.second_bit_width = 16; + yylval->mpy.first_unsigned = true; + yylval->mpy.second_unsigned = false; + return MPY; } +"fMPY16SU" { yylval->mpy.first_bit_width = 16; + yylval->mpy.second_bit_width = 16; + yylval->mpy.first_unsigned = false; + yylval->mpy.second_unsigned = true; + return MPY; } +"fMPY16SS" { yylval->mpy.first_bit_width = 16; + yylval->mpy.second_bit_width = 16; + yylval->mpy.first_unsigned = false; + yylval->mpy.second_unsigned = false; + return MPY; } +"fMPY32UU" { yylval->mpy.first_bit_width = 32; + yylval->mpy.second_bit_width = 32; + yylval->mpy.first_unsigned = true; + yylval->mpy.second_unsigned = true; + return MPY; } +"fMPY32US" { yylval->mpy.first_bit_width = 32; + yylval->mpy.second_bit_width = 32; + yylval->mpy.first_unsigned = true; + yylval->mpy.second_unsigned = false; + return MPY; } +"fMPY32SU" { yylval->mpy.first_bit_width = 32; + yylval->mpy.second_bit_width = 32; + yylval->mpy.first_unsigned = false; + yylval->mpy.second_unsigned = true; + return MPY; } +"fSFMPY" | +"fMPY32SS" { yylval->mpy.first_bit_width = 32; + yylval->mpy.second_bit_width = 32; + yylval->mpy.first_unsigned = false; + yylval->mpy.second_unsigned = false; + return MPY; } +"fMPY3216SS" { yylval->mpy.first_bit_width = 32; + yylval->mpy.second_bit_width = 16; + yylval->mpy.first_unsigned = false; + yylval->mpy.second_unsigned = false; + return MPY; } +"fMPY3216SU" { yylval->mpy.first_bit_width = 32; + yylval->mpy.second_bit_width = 16; + yylval->mpy.first_unsigned = false; + yylval->mpy.second_unsigned = true; + return MPY; } +"fNEWREG" | +"fNEWREG_ST" | +"fIMMEXT" | +"fMUST_IMMEXT" | +"fCAST2_2s" | +"fCAST2_2u" | +"fCAST4_4s" | +"fCAST8_8s" | +"fZE8_16" | +"fSE8_16" | +"fZE16_32" | +"fSE16_32" | +"fZE32_64" | +"fPASS" | +"fECHO" { return IDENTITY; } +"(size8"[us]"_t)" { yylval->cast.bit_width = 8; + yylval->cast.is_unsigned = ((yytext[6]) == 'u'); + return CAST; } +"(size16"[us]"_t)" { yylval->cast.bit_width = 16; + yylval->cast.is_unsigned = ((yytext[7]) == 'u'); + return CAST; } +"(int)" { yylval->cast.bit_width = 32; + yylval->cast.is_unsigned = false; + return CAST; } +"(unsigned int)" { yylval->cast.bit_width = 32; + yylval->cast.is_unsigned = true; + return CAST; } +"fREAD_PC()" | +"PC" { return PC; } +"fREAD_NPC()" | +"NPC" { return NPC; } +"fGET_LPCFG" | +"USR.LPCFG" { return LPCFG; } +"LOAD_CANCEL(EA)" | +"STORE_CANCEL(EA)" | +"CANCEL" { return CANCEL; } +"N"{LOWER_ID} { yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = GENERAL_PURPOSE; + yylval->rvalue.reg.id = yytext[1]; + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + return REG; } +"N"{LOWER_ID}"N" { yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = DOTNEW; + yylval->rvalue.reg.id = yytext[1]; + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + return REG; } +[rR]{DIGIT}+ { yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = GENERAL_PURPOSE; + yylval->rvalue.reg.id = atoi(yytext + 1); + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + return REG; } +"fREAD_SP()" | +"SP" { yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = CONTROL; + yylval->rvalue.reg.id = SP; + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + return REG; } +"fREAD_FP()" | +"FP" { yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = CONTROL; + yylval->rvalue.reg.id = FP; + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + return REG; } +"fREAD_LR()" | +"LR" { yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = CONTROL; + yylval->rvalue.reg.id = LR; + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + return REG; } +"GP" { yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = CONTROL; + yylval->rvalue.reg.id = GP; + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + return REG; } +"fREAD_LC"[01] { yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = CONTROL; + yylval->rvalue.reg.id = LC0 + (yytext[8] - '0'); + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + return REG; } +"LC"[01] { yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = CONTROL; + yylval->rvalue.reg.id = LC0 + (yytext[2] - '0'); + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + return REG; } +"fREAD_SA"[01] { yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = CONTROL; + yylval->rvalue.reg.id = SA0 + (yytext[8] - '0'); + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + return REG; } +"SA"[01] { yylval->rvalue.type = REGISTER; + yylval->rvalue.reg.type = CONTROL; + yylval->rvalue.reg.id = SA0 + (yytext[2] - '0'); + yylval->rvalue.reg.bit_width = 32; + yylval->rvalue.bit_width = 32; + return REG; } +"MuN" { return MUN; } +"fREAD_P0()" { yylval->rvalue.type = PREDICATE; + yylval->rvalue.pre.id = '0'; + yylval->rvalue.bit_width = 32; + return PRE; } +[pP]{DIGIT} { yylval->rvalue.type = PREDICATE; + yylval->rvalue.pre.id = yytext[1]; + yylval->rvalue.bit_width = 32; + return PRE; } +"fLSBNEW(P"{LOWER_PRE}"N)" { yylval->rvalue.type = PREDICATE; + yylval->rvalue.pre.id = yytext[9]; + yylval->rvalue.bit_width = 32; + yylval->rvalue.is_dotnew = true; + return PRE; } +"fLSBNEW0" { yylval->rvalue.type = PREDICATE; + yylval->rvalue.pre.id = '0'; + yylval->rvalue.bit_width = 32; + yylval->rvalue.is_dotnew = true; + return PRE; } +"fLSBNEW1" { yylval->rvalue.type = PREDICATE; + yylval->rvalue.pre.id = '1'; + yylval->rvalue.bit_width = 32; + yylval->rvalue.is_dotnew = true; + return PRE; } +"fLSBNEW1NOT" { yylval->rvalue.type = PREDICATE; + yylval->rvalue.pre.id = '1'; + yylval->rvalue.bit_width = 32; + yylval->rvalue.is_dotnew = true; + return PRE; } +"N" { yylval->rvalue.type = IMMEDIATE; + yylval->rvalue.bit_width = 32; + yylval->rvalue.imm.type = VARIABLE; + yylval->rvalue.imm.id = 'N'; + return IMM; } +"i" { yylval->rvalue.type = IMMEDIATE; + yylval->rvalue.bit_width = 32; + yylval->rvalue.imm.type = I; + return IMM; } +{SIGN_ID} { yylval->is_unsigned = (yytext[0] == 'u'); + return SIGN; + } +"fSF_BIAS()" { yylval->rvalue.type = IMMEDIATE; + yylval->rvalue.bit_width = 32; + yylval->rvalue.is_unsigned = false; + yylval->rvalue.imm.type = VALUE; + yylval->rvalue.imm.value = 127; + return IMM; } +{DIGIT}+ { yylval->rvalue.type = IMMEDIATE; + yylval->rvalue.bit_width = 64; + yylval->rvalue.is_unsigned = false; + yylval->rvalue.imm.type = VALUE; + yylval->rvalue.imm.value = atoi(yytext); + return IMM; } +{DIGIT}+"LL" { yylval->rvalue.type = IMMEDIATE; + yylval->rvalue.bit_width = 64; + yylval->rvalue.is_unsigned = false; + yylval->rvalue.imm.type = VALUE; + yylval->rvalue.imm.value = strtoll(yytext, NULL, 10); + return IMM; } +"0x"{HEX_DIGIT}+ { yylval->rvalue.type = IMMEDIATE; + yylval->rvalue.bit_width = 32; + yylval->rvalue.is_unsigned = false; + yylval->rvalue.imm.type = VALUE; + yylval->rvalue.imm.value = strtoul(yytext, NULL, 16); + return IMM; } +"0x"{HEX_DIGIT}+"LL" { yylval->rvalue.type = IMMEDIATE; + yylval->rvalue.bit_width = 64; + yylval->rvalue.is_unsigned = false; + yylval->rvalue.imm.type = VALUE; + yylval->rvalue.imm.value = strtoll(yytext, NULL, 16); + return IMM; } +"0x"{HEX_DIGIT}+"ULL" { yylval->rvalue.type = IMMEDIATE; + yylval->rvalue.bit_width = 64; + yylval->rvalue.is_unsigned = true; + yylval->rvalue.imm.type = VALUE; + yylval->rvalue.imm.value = strtoull(yytext, + NULL, + 16); + return IMM; } +"fCONSTLL" { return CONSTLL; } +"fCONSTULL" { return CONSTULL; } +"fLOAD" { return LOAD; } +"fSTORE" { return STORE; } +"fROTL" { return ROTL; } +"fSET_OVERFLOW" { return SETOVF; } +"fDEINTERLEAVE" { return DEINTERLEAVE; } +"fINTERLEAVE" { return INTERLEAVE; } +"fCARRY_FROM_ADD" { return CARRY_FROM_ADD; } +{VAR_ID} { /* Variable name, we adopt the C names convention */ + yylval->rvalue.type = VARID; + yylval->rvalue.var.name = g_string_new(yytext); + /* Default types are int */ + yylval->rvalue.bit_width = 32; + return VAR; } +"fHINTJR(RsV)" { /* Emit no token */ } +. { return yytext[0]; } + +%% diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index 5949d079a5..1bdf988269 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -193,4 +193,8 @@ idef_parser_input_generated_prep = custom_target( command: [idef_parser_dir / 'prepare', '@INPUT@', '-I' + idef_parser_dir], ) +flex = generator(find_program('flex'), + output: ['@BASENAME@.yy.c', '@BASENAME@.yy.h'], + arguments: ['-o', '@OUTPUT0@', '--header-file=@OUTPUT1@', '@INPUT@']) + target_arch += {'hexagon': hexagon_ss} diff --git a/tests/docker/dockerfiles/alpine.docker b/tests/docker/dockerfiles/alpine.docker index d63a269aef..1120e8555d 100644 --- a/tests/docker/dockerfiles/alpine.docker +++ b/tests/docker/dockerfiles/alpine.docker @@ -11,6 +11,7 @@ ENV PACKAGES \ binutils \ coreutils \ curl-dev \ + flex \ g++ \ gcc \ git \ diff --git a/tests/docker/dockerfiles/centos7.docker b/tests/docker/dockerfiles/centos7.docker index 75fdb53c7c..95966ea7e6 100644 --- a/tests/docker/dockerfiles/centos7.docker +++ b/tests/docker/dockerfiles/centos7.docker @@ -10,6 +10,7 @@ ENV PACKAGES \ ccache \ csnappy-devel \ dbus-daemon \ + flex \ gcc-c++ \ gcc \ gettext \ diff --git a/tests/docker/dockerfiles/centos8.docker b/tests/docker/dockerfiles/centos8.docker index a8c6c528b0..6ea9cf8b5a 100644 --- a/tests/docker/dockerfiles/centos8.docker +++ b/tests/docker/dockerfiles/centos8.docker @@ -7,6 +7,7 @@ ENV PACKAGES \ bzip2-devel \ dbus-daemon \ diffutils \ + flex \ gcc \ gcc-c++ \ genisoimage \ diff --git a/tests/docker/dockerfiles/debian10.docker b/tests/docker/dockerfiles/debian10.docker index d034acbd25..97ec6d5637 100644 --- a/tests/docker/dockerfiles/debian10.docker +++ b/tests/docker/dockerfiles/debian10.docker @@ -23,6 +23,7 @@ RUN apt update && \ ccache \ clang \ dbus \ + flex \ gdb-multiarch \ gettext \ git \ diff --git a/tests/docker/dockerfiles/fedora-i386-cross.docker b/tests/docker/dockerfiles/fedora-i386-cross.docker index 966072c08e..9703b7ec78 100644 --- a/tests/docker/dockerfiles/fedora-i386-cross.docker +++ b/tests/docker/dockerfiles/fedora-i386-cross.docker @@ -3,6 +3,7 @@ ENV PACKAGES \ bzip2 \ diffutils \ findutils \ + flex \ gcc \ git \ libtasn1-devel.i686 \ diff --git a/tests/docker/dockerfiles/fedora-win32-cross.docker b/tests/docker/dockerfiles/fedora-win32-cross.docker index 81b5659e9c..2018dcabe5 100644 --- a/tests/docker/dockerfiles/fedora-win32-cross.docker +++ b/tests/docker/dockerfiles/fedora-win32-cross.docker @@ -6,6 +6,7 @@ ENV PACKAGES \ bzip2 \ diffutils \ findutils \ + flex \ gcc \ gettext \ git \ diff --git a/tests/docker/dockerfiles/fedora-win64-cross.docker b/tests/docker/dockerfiles/fedora-win64-cross.docker index bcb428e724..b05e4cbcc6 100644 --- a/tests/docker/dockerfiles/fedora-win64-cross.docker +++ b/tests/docker/dockerfiles/fedora-win64-cross.docker @@ -6,6 +6,7 @@ ENV PACKAGES \ bzip2 \ diffutils \ findutils \ + flex \ gcc \ gettext \ git \ diff --git a/tests/docker/dockerfiles/fedora.docker b/tests/docker/dockerfiles/fedora.docker index 915fdc1845..5d3f49936b 100644 --- a/tests/docker/dockerfiles/fedora.docker +++ b/tests/docker/dockerfiles/fedora.docker @@ -14,6 +14,7 @@ ENV PACKAGES \ device-mapper-multipath-devel \ diffutils \ findutils \ + flex \ gcc \ gcc-c++ \ genisoimage \ diff --git a/tests/docker/dockerfiles/opensuse-leap.docker b/tests/docker/dockerfiles/opensuse-leap.docker index 0e64893e4a..ce1db959a2 100644 --- a/tests/docker/dockerfiles/opensuse-leap.docker +++ b/tests/docker/dockerfiles/opensuse-leap.docker @@ -6,6 +6,7 @@ ENV PACKAGES \ brlapi-devel \ bzip2 \ cyrus-sasl-devel \ + flex \ gcc \ gcc-c++ \ mkisofs \ diff --git a/tests/docker/dockerfiles/ubuntu.docker b/tests/docker/dockerfiles/ubuntu.docker index b5ef7a8198..e2f55eb892 100644 --- a/tests/docker/dockerfiles/ubuntu.docker +++ b/tests/docker/dockerfiles/ubuntu.docker @@ -14,6 +14,7 @@ ENV PACKAGES \ ccache \ clang \ dbus \ + flex \ gcc \ gettext \ git \ diff --git a/tests/docker/dockerfiles/ubuntu1804.docker b/tests/docker/dockerfiles/ubuntu1804.docker index 9b0a19ba5e..2068118180 100644 --- a/tests/docker/dockerfiles/ubuntu1804.docker +++ b/tests/docker/dockerfiles/ubuntu1804.docker @@ -2,6 +2,7 @@ FROM ubuntu:18.04 ENV PACKAGES \ ccache \ clang \ + flex \ gcc \ gettext \ git \ diff --git a/tests/docker/dockerfiles/ubuntu2004.docker b/tests/docker/dockerfiles/ubuntu2004.docker index 9750016e51..13d43a7b90 100644 --- a/tests/docker/dockerfiles/ubuntu2004.docker +++ b/tests/docker/dockerfiles/ubuntu2004.docker @@ -1,8 +1,9 @@ FROM ubuntu:20.04 -ENV PACKAGES flex bison \ +ENV PACKAGES bison \ bsdmainutils \ ccache \ clang-10\ + flex \ gcc \ gcovr \ genisoimage \ From patchwork Thu Apr 15 16:34:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alessandro Di Federico X-Patchwork-Id: 12205807 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27D23C433B4 for ; Thu, 15 Apr 2021 17:03:49 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org 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v4 10/12] target/hexagon: import parser for idef-parser Date: Thu, 15 Apr 2021 18:34:53 +0200 Message-Id: <20210415163455.3839169-11-ale.qemu@rev.ng> In-Reply-To: <20210415163455.3839169-1-ale.qemu@rev.ng> References: <20210415163455.3839169-1-ale.qemu@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico X-Patchwork-Original-From: Alessandro Di Federico via From: Alessandro Di Federico From: Paolo Montesel Signed-off-by: Alessandro Di Federico Signed-off-by: Paolo Montesel --- target/hexagon/idef-parser/idef-parser.y | 947 +++++++ target/hexagon/idef-parser/parser-helpers.c | 2374 +++++++++++++++++ target/hexagon/idef-parser/parser-helpers.h | 347 +++ target/hexagon/meson.build | 26 +- tests/docker/dockerfiles/alpine.docker | 1 + tests/docker/dockerfiles/centos7.docker | 1 + tests/docker/dockerfiles/centos8.docker | 1 + tests/docker/dockerfiles/debian10.docker | 2 + .../dockerfiles/fedora-i386-cross.docker | 2 + .../dockerfiles/fedora-win32-cross.docker | 2 + .../dockerfiles/fedora-win64-cross.docker | 2 + tests/docker/dockerfiles/fedora.docker | 1 + tests/docker/dockerfiles/opensuse-leap.docker | 1 + tests/docker/dockerfiles/ubuntu.docker | 2 + tests/docker/dockerfiles/ubuntu1804.docker | 2 + tests/docker/dockerfiles/ubuntu2004.docker | 4 +- 16 files changed, 3713 insertions(+), 2 deletions(-) create mode 100644 target/hexagon/idef-parser/idef-parser.y create mode 100644 target/hexagon/idef-parser/parser-helpers.c create mode 100644 target/hexagon/idef-parser/parser-helpers.h diff --git a/target/hexagon/idef-parser/idef-parser.y b/target/hexagon/idef-parser/idef-parser.y new file mode 100644 index 0000000000..dbfc9572f9 --- /dev/null +++ b/target/hexagon/idef-parser/idef-parser.y @@ -0,0 +1,947 @@ +%{ +/* + * Copyright(c) 2019-2021 rev.ng Srls. All Rights Reserved. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "idef-parser.h" +#include "parser-helpers.h" +#include "idef-parser.tab.h" +#include "idef-parser.yy.h" + +/* Uncomment this to disable yyasserts */ +/* #define NDEBUG */ + +#define ERR_LINE_CONTEXT 40 + +%} + +%lex-param {void *scanner} +%parse-param {void *scanner} +%parse-param {Context *c} + +%define parse.error verbose +%define parse.lac full +%define api.pure full + +%locations + +%union { + GString *string; + HexValue rvalue; + HexSat sat; + HexCast cast; + HexExtract extract; + HexMpy mpy; + bool is_unsigned; + int index; +} + +/* Tokens */ +%start input + +%expect 1 + +%token INAME DREG DIMM DPRE DEA RREG WREG FREG FIMM RPRE WPRE FPRE FWRAP FEA VAR +%token POW ABS CROUND ROUND CIRCADD COUNTONES INC DEC ANDA ORA XORA PLUSPLUS ASL +%token ASR LSR EQ NEQ LTE GTE MIN MAX ANDL ORL FOR ICIRC IF MUN FSCR FCHK SXT +%token ZXT CONSTEXT LOCNT BREV SIGN LOAD STORE CONSTLL CONSTULL PC NPC LPCFG +%token CANCEL IDENTITY PART1 BREV_4 BREV_8 ROTL INSBITS SETBITS EXTBITS EXTRANGE +%token CAST4_8U SETOVF FAIL DEINTERLEAVE INTERLEAVE CARRY_FROM_ADD + +%token REG IMM PRE +%token ELSE +%token MPY +%token SAT +%token CAST DEPOSIT SETHALF +%token EXTRACT +%type INAME +%type rvalue lvalue VAR assign_statement var +%type DREG DIMM DPRE RREG RPRE FAIL +%type if_stmt IF +%type SIGN + +/* Operator Precedences */ +%left MIN MAX +%left '(' +%left ',' +%left '=' +%right CIRCADD +%right INC DEC ANDA ORA XORA +%left '?' ':' +%left ORL +%left ANDL +%left '|' +%left '^' ANDOR +%left '&' +%left EQ NEQ +%left '<' '>' LTE GTE +%left ASL ASR LSR +%right ABS +%left '-' '+' +%left POW +%left '*' '/' '%' MPY +%right '~' '!' +%left '[' +%right CAST +%right LOCNT BREV + +/* Bison Grammar */ +%% + +/* Input file containing the description of each hexagon instruction */ +input : instructions + { + YYACCEPT; + } + ; + +instructions : instruction instructions + | %empty + ; + +instruction : INAME + { + gen_inst(c, $1); + } + arguments + { + gen_inst_args(c, &@1); + } + code + { + gen_inst_code(c, &@1); + } + | error /* Recover gracefully after instruction compilation error */ + { + free_instruction(c); + } + ; + +arguments : '(' ')' + | '(' argument_list ')'; + +argument_list : decl ',' argument_list + | decl + ; + +var : VAR + { + track_string(c, $1.var.name); + $$ = $1; + } + ; + +/* Return the modified registers list */ +code : '{' statements '}' + { + c->inst.code_begin = c->input_buffer + @2.first_column; + c->inst.code_end = c->input_buffer + @2.last_column - 1; + } + | '{' + { + /* Nop */ + } + '}' + ; + +decl : REG + { + emit_arg(c, &@1, &$1); + /* Enqueue register into initialization list */ + g_array_append_val(c->inst.init_list, $1); + } + | IMM + { + EMIT_SIG(c, ", int %ciV", $1.imm.id); + } + | PRE + { + emit_arg(c, &@1, &$1); + /* Enqueue predicate into initialization list */ + g_array_append_val(c->inst.init_list, $1); + } + | var + { + yyassert(c, &@1, !strcmp($1.var.name->str, "EA"), + "Unknown argument variable!"); + } + | RREG + { + emit_arg(c, &@1, &$1); + } + | WREG + | FREG + | FIMM + | RPRE + { + emit_arg(c, &@1, &$1); + } + | WPRE + | FPRE + | FEA + ; + +code_block : '{' statements '}' + | '{' '}' + ; + +/* A list of one or more statements */ +statements : statements statement + | statement + ; + +/* Statements can be assignment (rvalue ';'), control or memory statements */ +statement : control_statement + | rvalue ';' + { + rvalue_free(c, &@1, &$1); + } + | code_block + | ';' + ; + +assign_statement : lvalue '=' rvalue + { + @1.last_column = @3.last_column; + gen_assign(c, &@1, &$1, &$3); + $$ = $1; + } + | lvalue INC rvalue + { + @1.last_column = @3.last_column; + HexValue tmp = gen_bin_op(c, &@1, ADD_OP, &$1, &$3); + gen_assign(c, &@1, &$1, &tmp); + $$ = $1; + } + | lvalue DEC rvalue + { + @1.last_column = @3.last_column; + HexValue tmp = gen_bin_op(c, &@1, SUB_OP, &$1, &$3); + gen_assign(c, &@1, &$1, &tmp); + $$ = $1; + } + | lvalue ANDA rvalue + { + @1.last_column = @3.last_column; + HexValue tmp = gen_bin_op(c, &@1, ANDB_OP, &$1, &$3); + gen_assign(c, &@1, &$1, &tmp); + $$ = $1; + } + | lvalue ORA rvalue + { + @1.last_column = @3.last_column; + HexValue tmp = gen_bin_op(c, &@1, ORB_OP, &$1, &$3); + gen_assign(c, &@1, &$1, &tmp); + $$ = $1; + } + | lvalue XORA rvalue + { + @1.last_column = @3.last_column; + HexValue tmp = gen_bin_op(c, &@1, XORB_OP, &$1, &$3); + gen_assign(c, &@1, &$1, &tmp); + $$ = $1; + } + | PRE '=' rvalue + { + @1.last_column = @3.last_column; + gen_pre_assign(c, &@1, &$1, &$3); + } + | IMM '=' rvalue + { + @1.last_column = @3.last_column; + yyassert(c, &@1, $3.type == IMMEDIATE, + "Cannot assign non-immediate to immediate!"); + yyassert(c, &@1, $1.imm.type == VARIABLE, + "Cannot assign to non-variable!"); + /* Assign to the function argument */ + OUT(c, &@1, &$1, " = ", &$3, ";\n"); + $$ = $1; + } + | PC '=' rvalue + { + @1.last_column = @3.last_column; + yyassert(c, &@1, c->ternary->len == 0, + "Assignment side-effect not modeled!"); + $3 = rvalue_truncate(c, &@1, &$3); + $3 = rvalue_materialize(c, &@1, &$3); + OUT(c, &@1, "gen_write_new_pc(", &$3, ");\n"); + rvalue_free(c, &@1, &$3); /* Free temporary value */ + } + | LOAD '(' IMM ',' IMM ',' SIGN ',' var ',' lvalue ')' + { + @1.last_column = @12.last_column; + yyassert(c, &@1, c->ternary->len == 0, + "Assignment side-effect not modeled!"); + gen_load(c, &@1, &$3, &$5, $7, &$9, &$11); + } + | STORE '(' IMM ',' IMM ',' var ',' rvalue ')' + /* Store primitive */ + { + @1.last_column = @10.last_column; + yyassert(c, &@1, c->ternary->len == 0, + "Assignment side-effect not modeled!"); + gen_store(c, &@1, &$3, &$5, &$7, &$9); + } + | LPCFG '=' rvalue + { + @1.last_column = @3.last_column; + yyassert(c, &@1, c->ternary->len == 0, + "Assignment side-effect not modeled!"); + $3 = rvalue_truncate(c, &@1, &$3); + $3 = rvalue_materialize(c, &@1, &$3); + OUT(c, &@1, "SET_USR_FIELD(USR_LPCFG, ", &$3, ");\n"); + rvalue_free(c, &@1, &$3); + } + | DEPOSIT '(' rvalue ',' rvalue ',' rvalue ')' + { + @1.last_column = @8.last_column; + yyassert(c, &@1, c->ternary->len == 0, + "Assignment side-effect not modeled!"); + gen_deposit_op(c, &@1, &$5, &$7, &$3, &$1); + } + | SETHALF '(' rvalue ',' lvalue ',' rvalue ')' + { + @1.last_column = @8.last_column; + yyassert(c, &@1, c->ternary->len == 0, + "Assignment side-effect not modeled!"); + gen_sethalf(c, &@1, &$1, &$3, &$5, &$7); + } + | SETBITS '(' rvalue ',' rvalue ',' rvalue ',' rvalue ')' + { + @1.last_column = @10.last_column; + yyassert(c, &@1, c->ternary->len == 0, + "Assignment side-effect not modeled!"); + gen_setbits(c, &@1, &$3, &$5, &$7, &$9); + } + | INSBITS '(' lvalue ',' rvalue ',' rvalue ',' rvalue ')' + { + @1.last_column = @10.last_column; + yyassert(c, &@1, c->ternary->len == 0, + "Assignment side-effect not modeled!"); + gen_rdeposit_op(c, &@1, &$3, &$9, &$7, &$5); + } + | IDENTITY '(' rvalue ')' + { + @1.last_column = @4.last_column; + $$ = $3; + } + ; + +control_statement : frame_check + | cancel_statement + | if_statement + | for_statement + | fpart1_statement + ; + +frame_check : FCHK '(' rvalue ',' rvalue ')' ';' + { + rvalue_free(c, &@1, &$3); + rvalue_free(c, &@1, &$5); + } + ; + +cancel_statement : CANCEL + { + OUT(c, &@1, "gen_cancel(insn->slot);\n"); + } + ; + +if_statement : if_stmt + { + /* Fix else label */ + OUT(c, &@1, "gen_set_label(if_label_", &$1, ");\n"); + } + | if_stmt ELSE + { + @1.last_column = @2.last_column; + $2 = gen_if_else(c, &@1, $1); + } + statement + { + OUT(c, &@1, "gen_set_label(if_label_", &$2, ");\n"); + } + ; + +for_statement : FOR '(' IMM '=' IMM ';' IMM '<' IMM ';' IMM PLUSPLUS ')' + { + @1.last_column = @13.last_column; + OUT(c, &@1, "for (int ", &$3, " = ", &$5, "; ", + &$7, " < ", &$9); + OUT(c, &@1, "; ", &$11, "++) {\n"); + } + code_block + { + OUT(c, &@1, "}\n"); + } + | FOR '(' IMM '=' IMM ';' IMM '<' IMM ';' IMM INC IMM ')' + { + @1.last_column = @14.last_column; + OUT(c, &@1, "for (int ", &$3, " = ", &$5, "; ", + &$7, " < ", &$9); + OUT(c, &@1, "; ", &$11, " += ", &$13, ") {\n"); + } + code_block + { + OUT(c, &@1, "}\n"); + } + ; + +fpart1_statement : PART1 + { + OUT(c, &@1, "if (insn->part1) {\n"); + } + '(' statements ')' + { + @1.last_column = @3.last_column; + OUT(c, &@1, "return; }\n"); + } + ; + +if_stmt : IF '(' rvalue ')' + { + @1.last_column = @3.last_column; + $1 = gen_if_cond(c, &@1, &$3); + } + statement + { + $$ = $1; + } + ; + +rvalue : FAIL + { + yyassert(c, &@1, false, "Encountered a FAIL token as rvalue.\n"); + } + | assign_statement + | REG + { + if ($1.reg.type == CONTROL) { + $$ = gen_read_creg(c, &@1, &$1); + } else { + $$ = $1; + } + } + | IMM + { + $$ = $1; + } + | CONSTLL '(' IMM ')' + { + $3.is_unsigned = false; + $3.bit_width = 64; + $$ = $3; + } + | CONSTULL '(' IMM ')' + { + $3.is_unsigned = true; + $3.bit_width = 64; + $$ = $3; + } + | PRE + { + $$ = gen_rvalue_pre(c, &@1, &$1); + } + | PC + { + /* Read PC from the CR */ + $$ = gen_tmp(c, &@1, 32); + OUT(c, &@1, "tcg_gen_movi_i32(", &$$, ", ctx->base.pc_next);\n"); + } + | NPC + { + /* NPC is only read from CALLs, so we can hardcode it + at translation time */ + $$ = gen_tmp(c, &@1, 32); + OUT(c, &@1, "tcg_gen_movi_i32(", &$$, ", ctx->npc);\n"); + } + | CONSTEXT + { + HexValue rvalue; + rvalue.type = IMMEDIATE; + rvalue.imm.type = IMM_CONSTEXT; + rvalue.is_unsigned = true; + rvalue.is_dotnew = false; + rvalue.is_manual = false; + $$ = rvalue; + } + | var + { + $$ = gen_rvalue_var(c, &@1, &$1); + } + | MPY '(' rvalue ',' rvalue ')' + { + @1.last_column = @6.last_column; + $$ = gen_rvalue_mpy(c, &@1, &$1, &$3, &$5); + } + | rvalue '+' rvalue + { + @1.last_column = @3.last_column; + $$ = gen_bin_op(c, &@1, ADD_OP, &$1, &$3); + } + | rvalue '-' rvalue + { + @1.last_column = @3.last_column; + $$ = gen_bin_op(c, &@1, SUB_OP, &$1, &$3); + } + | rvalue '*' rvalue + { + @1.last_column = @3.last_column; + $$ = gen_bin_op(c, &@1, MUL_OP, &$1, &$3); + } + | rvalue POW rvalue + { + @1.last_column = @3.last_column; + $$ = gen_rvalue_pow(c, &@1, &$1, &$3); + } + | rvalue '%' rvalue + { + @1.last_column = @3.last_column; + $$ = gen_bin_op(c, &@1, MOD_OP, &$1, &$3); + } + | rvalue ASL rvalue + { + @1.last_column = @3.last_column; + $$ = gen_bin_op(c, &@1, ASL_OP, &$1, &$3); + } + | rvalue ASR rvalue + { + @1.last_column = @3.last_column; + if ($1.is_unsigned) { + $$ = gen_bin_op(c, &@1, LSR_OP, &$1, &$3); + } else { + $$ = gen_bin_op(c, &@1, ASR_OP, &$1, &$3); + } + } + | rvalue LSR rvalue + { + @1.last_column = @3.last_column; + $$ = gen_bin_op(c, &@1, LSR_OP, &$1, &$3); + } + | rvalue '&' rvalue + { + @1.last_column = @3.last_column; + $$ = gen_bin_op(c, &@1, ANDB_OP, &$1, &$3); + } + | rvalue '|' rvalue + { + @1.last_column = @3.last_column; + $$ = gen_bin_op(c, &@1, ORB_OP, &$1, &$3); + } + | rvalue '^' rvalue + { + @1.last_column = @3.last_column; + $$ = gen_bin_op(c, &@1, XORB_OP, &$1, &$3); + } + | rvalue ANDL rvalue + { + @1.last_column = @3.last_column; + $$ = gen_bin_op(c, &@1, ANDL_OP, &$1, &$3); + } + | MIN '(' rvalue ',' rvalue ')' + { + @1.last_column = @3.last_column; + $$ = gen_bin_op(c, &@1, MINI_OP, &$3, &$5); + } + | MAX '(' rvalue ',' rvalue ')' + { + @1.last_column = @3.last_column; + $$ = gen_bin_op(c, &@1, MAXI_OP, &$3, &$5); + } + | '~' rvalue + { + @1.last_column = @2.last_column; + $$ = gen_rvalue_not(c, &@1, &$2); + } + | '!' rvalue + { + @1.last_column = @2.last_column; + $$ = gen_rvalue_notl(c, &@1, &$2); + } + | SAT '(' IMM ',' rvalue ')' + { + @1.last_column = @6.last_column; + $$ = gen_rvalue_sat(c, &@1, &$1, &$3, &$5); + } + | CAST rvalue + { + @1.last_column = @2.last_column; + /* Assign target signedness */ + $2.is_unsigned = $1.is_unsigned; + $$ = gen_cast_op(c, &@1, &$2, $1.bit_width); + $$.is_unsigned = $1.is_unsigned; + } + | rvalue '[' rvalue ']' + { + @1.last_column = @4.last_column; + if ($3.type == IMMEDIATE) { + $$ = gen_tmp(c, &@1, $1.bit_width); + OUT(c, &@1, "tcg_gen_extract_i", &$$.bit_width, "("); + OUT(c, &@1, &$$, ", ", &$1, ", ", &$3, ", 1);\n"); + } else { + HexValue one = gen_imm_value(c, &@1, 1, $3.bit_width); + HexValue tmp = gen_bin_op(c, &@1, ASR_OP, &$1, &$3); + $$ = gen_bin_op(c, &@1, ANDB_OP, &tmp, &one); + } + } + | rvalue EQ rvalue + { + @1.last_column = @3.last_column; + $$ = gen_bin_cmp(c, &@1, TCG_COND_EQ, &$1, &$3); + } + | rvalue NEQ rvalue + { + @1.last_column = @3.last_column; + $$ = gen_bin_cmp(c, &@1, TCG_COND_NE, &$1, &$3); + } + | rvalue '<' rvalue + { + @1.last_column = @3.last_column; + if ($1.is_unsigned || $3.is_unsigned) { + $$ = gen_bin_cmp(c, &@1, TCG_COND_LTU, &$1, &$3); + } else { + $$ = gen_bin_cmp(c, &@1, TCG_COND_LT, &$1, &$3); + } + } + | rvalue '>' rvalue + { + @1.last_column = @3.last_column; + if ($1.is_unsigned || $3.is_unsigned) { + $$ = gen_bin_cmp(c, &@1, TCG_COND_GTU, &$1, &$3); + } else { + $$ = gen_bin_cmp(c, &@1, TCG_COND_GT, &$1, &$3); + } + } + | rvalue LTE rvalue + { + @1.last_column = @3.last_column; + if ($1.is_unsigned || $3.is_unsigned) { + $$ = gen_bin_cmp(c, &@1, TCG_COND_LEU, &$1, &$3); + } else { + $$ = gen_bin_cmp(c, &@1, TCG_COND_LE, &$1, &$3); + } + } + | rvalue GTE rvalue + { + @1.last_column = @3.last_column; + if ($1.is_unsigned || $3.is_unsigned) { + $$ = gen_bin_cmp(c, &@1, TCG_COND_GEU, &$1, &$3); + } else { + $$ = gen_bin_cmp(c, &@1, TCG_COND_GE, &$1, &$3); + } + } + | rvalue '?' + { + $1.is_manual = true; + Ternary t = {0}; + t.state = IN_LEFT; + t.cond = $1; + g_array_append_val(c->ternary, t); + } + rvalue ':' + { + Ternary *t = &g_array_index(c->ternary, Ternary, + c->ternary->len - 1); + t->state = IN_RIGHT; + } + rvalue + { + @1.last_column = @5.last_column; + $$ = gen_rvalue_ternary(c, &@1, &$1, &$4, &$7); + } + | FSCR '(' rvalue ')' + { + @1.last_column = @4.last_column; + $$ = gen_rvalue_fscr(c, &@1, &$3); + } + | SXT '(' rvalue ',' IMM ',' rvalue ')' + { + @1.last_column = @8.last_column; + yyassert(c, &@1, $5.type == IMMEDIATE && + $5.imm.type == VALUE, + "SXT expects immediate values\n"); + $5.imm.value = 64; + $$ = gen_extend_op(c, &@1, &$3, &$5, &$7, false); + } + | ZXT '(' rvalue ',' IMM ',' rvalue ')' + { + @1.last_column = @8.last_column; + yyassert(c, &@1, $5.type == IMMEDIATE && + $5.imm.type == VALUE, + "ZXT expects immediate values\n"); + $$ = gen_extend_op(c, &@1, &$3, &$5, &$7, true); + } + | '(' rvalue ')' + { + $$ = $2; + } + | ABS rvalue + { + @1.last_column = @2.last_column; + $$ = gen_rvalue_abs(c, &@1, &$2); + } + | CROUND '(' rvalue ',' rvalue ')' + { + @1.last_column = @6.last_column; + $$ = gen_convround_n(c, &@1, &$3, &$5); + } + | CROUND '(' rvalue ')' + { + @1.last_column = @4.last_column; + $$ = gen_convround(c, &@1, &$3); + } + | ROUND '(' rvalue ',' rvalue ')' + { + @1.last_column = @6.last_column; + $$ = gen_round(c, &@1, &$3, &$5); + } + | '-' rvalue + { + @1.last_column = @2.last_column; + $$ = gen_rvalue_neg(c, &@1, &$2); + } + | ICIRC '(' rvalue ')' ASL IMM + { + @1.last_column = @6.last_column; + $$ = gen_tmp(c, &@1, 32); + OUT(c, &@1, "gen_read_ireg(", &$$, ", ", &$3, ", ", &$6, ");\n"); + rvalue_free(c, &@1, &$3); + } + | CIRCADD '(' rvalue ',' rvalue ',' rvalue ')' + { + @1.last_column = @8.last_column; + gen_circ_op(c, &@1, &$3, &$5, &$7); + } + | LOCNT '(' rvalue ')' + { + @1.last_column = @4.last_column; + /* Leading ones count */ + $$ = gen_locnt_op(c, &@1, &$3); + } + | COUNTONES '(' rvalue ')' + { + @1.last_column = @4.last_column; + /* Ones count */ + $$ = gen_ctpop_op(c, &@1, &$3); + } + | LPCFG + { + $$ = gen_tmp_value(c, &@1, "0", 32); + OUT(c, &@1, "tcg_gen_extract_tl(", &$$, + ", hex_gpr[HEX_REG_USR], "); + OUT(c, &@1, "reg_field_info[USR_LPCFG].offset, "); + OUT(c, &@1, "reg_field_info[USR_LPCFG].width);\n"); + } + | EXTRACT '(' rvalue ',' rvalue ')' + { + @1.last_column = @6.last_column; + $$ = gen_extract_op(c, &@1, &$5, &$3, &$1); + } + | EXTBITS '(' rvalue ',' rvalue ',' rvalue ')' + { + @1.last_column = @8.last_column; + yyassert(c, &@1, $5.type == IMMEDIATE && + $5.imm.type == VALUE && + $7.type == IMMEDIATE && + $7.imm.type == VALUE, + "Range extract needs immediate values!\n"); + $$ = gen_rextract_op(c, &@1, &$3, $7.imm.value, $5.imm.value); + } + | EXTRANGE '(' rvalue ',' rvalue ',' rvalue ')' + { + @1.last_column = @8.last_column; + yyassert(c, &@1, $5.type == IMMEDIATE && + $5.imm.type == VALUE && + $7.type == IMMEDIATE && + $7.imm.type == VALUE, + "Range extract needs immediate values!\n"); + $$ = gen_rextract_op(c, + &@1, + &$3, + $7.imm.value, + $5.imm.value - $7.imm.value + 1); + } + | CAST4_8U '(' rvalue ')' + { + @1.last_column = @4.last_column; + $$ = rvalue_truncate(c, &@1, &$3); + $$.is_unsigned = true; + $$ = rvalue_materialize(c, &@1, &$$); + $$ = rvalue_extend(c, &@1, &$$); + } + | BREV '(' rvalue ')' + { + @1.last_column = @4.last_column; + $$ = gen_rvalue_brev(c, &@1, &$3); + } + | BREV_4 '(' rvalue ')' + { + @1.last_column = @4.last_column; + $$ = gen_fbrev_4(c, &@1, &$3); + } + | BREV_8 '(' rvalue ')' + { + @1.last_column = @4.last_column; + $$ = gen_fbrev_8(c, &@1, &$3); + } + | ROTL '(' rvalue ',' rvalue ')' + { + @1.last_column = @6.last_column; + $$ = gen_rotl(c, &@1, &$3, &$5); + } + | SETOVF '(' ')' + { + @1.last_column = @3.last_column; + HexValue ovfl = gen_imm_value(c, &@1, 1, 32); + gen_set_overflow(c, &@1, &ovfl); + } + | SETOVF '(' rvalue ')' + { + /* Convenience fSET_OVERFLOW with pass-through */ + @1.last_column = @3.last_column; + HexValue ovfl = gen_imm_value(c, &@1, 1, 32); + gen_set_overflow(c, &@1, &ovfl); + $$ = $3; + } + | DEINTERLEAVE '(' rvalue ')' + { + @1.last_column = @4.last_column; + $$ = gen_deinterleave(c, &@1, &$3); + } + | INTERLEAVE '(' rvalue ',' rvalue ')' + { + @1.last_column = @6.last_column; + $$ = gen_interleave(c, &@1, &$3, &$5); + } + | CARRY_FROM_ADD '(' rvalue ',' rvalue ',' rvalue ')' + { + @1.last_column = @8.last_column; + $$ = gen_carry_from_add(c, &@1, &$3, &$5, &$7); + } + ; + +lvalue : FAIL + { + @1.last_column = @1.last_column; + yyassert(c, &@1, false, "Encountered a FAIL token as lvalue.\n"); + } + | REG + { + $$ = $1; + } + | var + { + $$ = $1; + } + ; + +%% + +int main(int argc, char **argv) +{ + if (argc != 5) { + fprintf(stderr, + "Semantics: Hexagon ISA to tinycode generator compiler\n\n"); + fprintf(stderr, + "Usage: ./semantics IDEFS EMITTER_C EMITTER_H " + "ENABLED_INSTRUCTIONS_LIST\n"); + return 1; + } + + enum { + ARG_INDEX_ARGV0 = 0, + ARG_INDEX_IDEFS, + ARG_INDEX_EMITTER_C, + ARG_INDEX_EMITTER_H, + ARG_INDEX_ENABLED_INSTRUCTIONS_LIST + }; + + FILE *enabled_file = fopen(argv[ARG_INDEX_ENABLED_INSTRUCTIONS_LIST], "w"); + + FILE *output_file = fopen(argv[ARG_INDEX_EMITTER_C], "w"); + fputs("#include \"qemu/osdep.h\"\n", output_file); + fputs("#include \"qemu/log.h\"\n", output_file); + fputs("#include \"cpu.h\"\n", output_file); + fputs("#include \"internal.h\"\n", output_file); + fputs("#include \"tcg/tcg-op.h\"\n", output_file); + fputs("#include \"insn.h\"\n", output_file); + fputs("#include \"opcodes.h\"\n", output_file); + fputs("#include \"translate.h\"\n", output_file); + fputs("#define QEMU_GENERATE\n", output_file); + fputs("#include \"genptr.h\"\n", output_file); + fputs("#include \"tcg/tcg.h\"\n", output_file); + fputs("#include \"macros.h\"\n", output_file); + fprintf(output_file, "#include \"%s\"\n", argv[ARG_INDEX_EMITTER_H]); + + FILE *defines_file = fopen(argv[ARG_INDEX_EMITTER_H], "w"); + assert(defines_file != NULL); + fputs("#ifndef HEX_EMITTER_H\n", defines_file); + fputs("#define HEX_EMITTER_H\n", defines_file); + fputs("\n", defines_file); + fputs("#include \"insn.h\"\n\n", defines_file); + + /* Parser input file */ + Context context = { 0 }; + context.defines_file = defines_file; + context.output_file = output_file; + context.enabled_file = enabled_file; + /* Initialize buffers */ + context.out_str = g_string_new(NULL); + context.signature_str = g_string_new(NULL); + context.header_str = g_string_new(NULL); + context.ternary = g_array_new(FALSE, TRUE, sizeof(Ternary)); + /* Read input file */ + FILE *input_file = fopen(argv[ARG_INDEX_IDEFS], "r"); + fseek(input_file, 0L, SEEK_END); + long input_size = ftell(input_file); + context.input_buffer = (char *) calloc(input_size + 1, sizeof(char)); + fseek(input_file, 0L, SEEK_SET); + size_t read_chars = fread(context.input_buffer, + sizeof(char), + input_size, + input_file); + if (read_chars != input_size) { + fprintf(stderr, "Error: an error occurred while reading input file!\n"); + return -1; + } + yylex_init(&context.scanner); + YY_BUFFER_STATE buffer; + buffer = yy_scan_string(context.input_buffer, context.scanner); + /* Start the parsing procedure */ + yyparse(context.scanner, &context); + if (context.implemented_insn != context.total_insn) { + fprintf(stderr, + "Warning: %d/%d meta instructions have been implemented!\n", + context.implemented_insn, + context.total_insn); + } + fputs("#endif " START_COMMENT " HEX_EMITTER_h " END_COMMENT "\n", + defines_file); + /* Cleanup */ + yy_delete_buffer(buffer, context.scanner); + yylex_destroy(context.scanner); + free(context.input_buffer); + g_string_free(context.out_str, TRUE); + g_string_free(context.signature_str, TRUE); + g_string_free(context.header_str, TRUE); + g_array_free(context.ternary, TRUE); + fclose(output_file); + fclose(input_file); + fclose(defines_file); + fclose(enabled_file); + + return 0; +} diff --git a/target/hexagon/idef-parser/parser-helpers.c b/target/hexagon/idef-parser/parser-helpers.c new file mode 100644 index 0000000000..d6f8de14e3 --- /dev/null +++ b/target/hexagon/idef-parser/parser-helpers.c @@ -0,0 +1,2374 @@ +/* + * Copyright(c) 2019-2021 rev.ng Srls. All Rights Reserved. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "idef-parser.h" +#include "parser-helpers.h" +#include "idef-parser.tab.h" +#include "idef-parser.yy.h" + +const char *creg_str[] = {"HEX_REG_SP", "HEX_REG_FP", "HEX_REG_LR", + "HEX_REG_GP", "HEX_REG_LC0", "HEX_REG_LC1", + "HEX_REG_SA0", "HEX_REG_SA1"}; + +void yyerror(YYLTYPE *locp, + yyscan_t scanner __attribute__((unused)), + Context *c, + const char *s) +{ + const char *code_ptr = c->input_buffer; + + fprintf(stderr, "WARNING (%s): '%s'\n", c->inst.name->str, s); + + fprintf(stderr, "Problematic range: "); + for (int i = locp->first_column; i < locp->last_column; i++) { + if (code_ptr[i] != '\n') { + fprintf(stderr, "%c", code_ptr[i]); + } + } + fprintf(stderr, "\n"); + + for (int i = 0; + i < 80 && + code_ptr[locp->first_column - 10 + i] != '\0' && + code_ptr[locp->first_column - 10 + i] != '\n'; + i++) { + fprintf(stderr, "%c", code_ptr[locp->first_column - 10 + i]); + } + fprintf(stderr, "\n"); + for (int i = 0; i < 9; i++) { + fprintf(stderr, " "); + } + fprintf(stderr, "^"); + for (int i = 0; i < (locp->last_column - locp->first_column) - 1; i++) { + fprintf(stderr, "~"); + } + fprintf(stderr, "\n"); + c->inst.error_count++; +} + +bool is_direct_predicate(HexValue *value) +{ + return value->pre.id >= '0' && value->pre.id <= '3'; + +} + +bool is_inside_ternary(Context *c) +{ + return c->ternary->len > 0; +} + +/* Print functions */ +void str_print(Context *c, YYLTYPE *locp, const char *string) +{ + EMIT(c, "%s", string); +} + + +void uint64_print(Context *c, YYLTYPE *locp, uint64_t *num) +{ + EMIT(c, "%" PRIu64, *num); +} + +void int_print(Context *c, YYLTYPE *locp, int *num) +{ + EMIT(c, "%d", *num); +} + +void uint_print(Context *c, YYLTYPE *locp, unsigned *num) +{ + EMIT(c, "%u", *num); +} + +void tmp_print(Context *c, YYLTYPE *locp, HexTmp *tmp) +{ + EMIT(c, "tmp_%d", tmp->index); +} + +void pre_print(Context *c, YYLTYPE *locp, HexPre *pre, bool is_dotnew) +{ + char suffix = is_dotnew ? 'N' : 'V'; + EMIT(c, "P%c%c", pre->id, suffix); +} + +void reg_compose(Context *c, YYLTYPE *locp, HexReg *reg, char reg_id[5]) +{ + switch (reg->type) { + case GENERAL_PURPOSE: + reg_id[0] = 'R'; + break; + case CONTROL: + reg_id[0] = 'C'; + break; + case MODIFIER: + reg_id[0] = 'M'; + break; + case DOTNEW: + /* The DOTNEW case is managed by the upper level function */ + break; + } + switch (reg->bit_width) { + case 32: + reg_id[1] = reg->id; + reg_id[2] = 'V'; + break; + case 64: + reg_id[1] = reg->id; + reg_id[2] = reg->id; + reg_id[3] = 'V'; + break; + default: + yyassert(c, locp, false, "Unhandled register bit width!\n"); + } +} + +void reg_print(Context *c, YYLTYPE *locp, HexReg *reg) +{ + if (reg->type == DOTNEW) { + EMIT(c, "N%cN", reg->id); + } else { + char reg_id[5] = { 0 }; + reg_compose(c, locp, reg, reg_id); + EMIT(c, "%s", reg_id); + } +} + +void imm_print(Context *c, YYLTYPE *locp, HexImm *imm) +{ + switch (imm->type) { + case I: + EMIT(c, "i"); + break; + case VARIABLE: + EMIT(c, "%ciV", imm->id); + break; + case VALUE: + EMIT(c, "((int64_t)%" PRIu64 "ULL)", (int64_t)imm->value); + break; + case QEMU_TMP: + EMIT(c, "qemu_tmp_%" PRIu64, imm->index); + break; + case IMM_PC: + EMIT(c, "dc->pc"); + break; + case IMM_CONSTEXT: + EMIT(c, "insn->extension_valid"); + break; + default: + yyassert(c, locp, false, "Cannot print this expression!"); + } +} + +void var_print(Context *c, YYLTYPE *locp, HexVar *var) +{ + EMIT(c, "%s", var->name->str); +} + +void rvalue_out(Context *c, YYLTYPE *locp, void *pointer) +{ + HexValue *rvalue = (HexValue *) pointer; + switch (rvalue->type) { + case REGISTER: + reg_print(c, locp, &rvalue->reg); + break; + case TEMP: + tmp_print(c, locp, &rvalue->tmp); + break; + case IMMEDIATE: + imm_print(c, locp, &rvalue->imm); + break; + case VARID: + var_print(c, locp, &rvalue->var); + break; + case PREDICATE: + pre_print(c, locp, &rvalue->pre, rvalue->is_dotnew); + break; + default: + yyassert(c, locp, false, "Cannot print this expression!"); + } +} + +void out_assert(Context *c, YYLTYPE *locp, + void *dummy __attribute__((unused))) { + abort(); + yyassert(c, locp, false, "Unhandled print type!"); +} + +/* Copy output code buffer */ +void commit(Context *c) +{ + /* Emit instruction pseudocode */ + EMIT_SIG(c, "\n" START_COMMENT " "); + for (char *x = c->inst.code_begin; x < c->inst.code_end; x++) { + EMIT_SIG(c, "%c", *x); + } + EMIT_SIG(c, " " END_COMMENT "\n"); + + /* Commit instruction code to output file */ + fwrite(c->signature_str->str, sizeof(char), c->signature_str->len, + c->output_file); + fwrite(c->header_str->str, sizeof(char), c->header_str->len, + c->output_file); + fwrite(c->out_str->str, sizeof(char), c->out_str->len, + c->output_file); + + fwrite(c->signature_str->str, sizeof(char), c->signature_str->len, + c->defines_file); + fprintf(c->defines_file, ";\n"); +} + +static HexValue get_ternary_cond(Context *c, YYLTYPE *locp) +{ + yyassert(c, locp, is_inside_ternary(c), "unexisting condition"); + Ternary *t = &g_array_index(c->ternary, Ternary, 0); + HexValue cond = t->cond; + if (t->state == IN_RIGHT) { + cond = gen_rvalue_notl(c, locp, &cond); + } + for (unsigned i = 1; i < c->ternary->len; ++i) { + Ternary *right = &g_array_index(c->ternary, Ternary, i); + HexValue other = right->cond; + /* Invert condition if we are on the right side */ + if (right->state == IN_RIGHT) { + other = gen_rvalue_notl(c, locp, &other); + } + cond = gen_bin_op(c, locp, ANDL_OP, &cond, &other); + } + return cond; +} + +/* Temporary values creation */ +HexValue gen_tmp(Context *c, YYLTYPE *locp, int bit_width) +{ + HexValue rvalue; + rvalue.type = TEMP; + bit_width = (bit_width == 64) ? 64 : 32; + rvalue.bit_width = bit_width; + rvalue.is_unsigned = false; + rvalue.is_dotnew = false; + rvalue.is_manual = false; + rvalue.tmp.index = c->inst.tmp_count; + OUT(c, locp, "TCGv_i", &bit_width, " tmp_", &c->inst.tmp_count, + " = tcg_temp_local_new_i", &bit_width, "();\n"); + c->inst.tmp_count++; + return rvalue; +} + +HexValue gen_tmp_value(Context *c, + YYLTYPE *locp, + const char *value, + int bit_width) +{ + HexValue rvalue; + rvalue.type = TEMP; + rvalue.bit_width = bit_width; + rvalue.is_unsigned = false; + rvalue.is_dotnew = false; + rvalue.is_manual = false; + rvalue.tmp.index = c->inst.tmp_count; + OUT(c, locp, "TCGv_i", &bit_width, " tmp_", &c->inst.tmp_count, + " = tcg_const_i", &bit_width, "(", value, ");\n"); + c->inst.tmp_count++; + return rvalue; +} + +HexValue gen_imm_value(Context *c __attribute__((unused)), + YYLTYPE *locp, + int value, + int bit_width) +{ + HexValue rvalue; + rvalue.type = IMMEDIATE; + rvalue.bit_width = bit_width; + rvalue.is_unsigned = false; + rvalue.is_dotnew = false; + rvalue.is_manual = false; + rvalue.imm.type = VALUE; + rvalue.imm.value = value; + return rvalue; +} + +void rvalue_free(Context *c, YYLTYPE *locp, HexValue *rvalue) +{ + if (rvalue->type == TEMP && !rvalue->is_manual) { + const char *bit_suffix = (rvalue->bit_width == 64) ? "i64" : "i32"; + OUT(c, locp, "tcg_temp_free_", bit_suffix, "(", rvalue, ");\n"); + } +} + +static void rvalue_free_manual(Context *c, YYLTYPE *locp, HexValue *rvalue) +{ + rvalue->is_manual = false; + rvalue_free(c, locp, rvalue); +} + +HexValue rvalue_materialize(Context *c, YYLTYPE *locp, HexValue *rvalue) +{ + if (rvalue->type == IMMEDIATE) { + HexValue tmp = gen_tmp(c, locp, rvalue->bit_width); + tmp.is_unsigned = rvalue->is_unsigned; + const char *bit_suffix = (rvalue->bit_width == 64) ? "i64" : "i32"; + OUT(c, locp, "tcg_gen_movi_", bit_suffix, + "(", &tmp, ", ", rvalue, ");\n"); + rvalue_free(c, locp, rvalue); + return tmp; + } + return *rvalue; +} + +HexValue rvalue_extend(Context *c, YYLTYPE *locp, HexValue *rvalue) +{ + if (rvalue->type == IMMEDIATE) { + HexValue res = *rvalue; + res.bit_width = 64; + return res; + } else { + if (rvalue->bit_width == 32) { + HexValue res = gen_tmp(c, locp, 64); + const char *sign_suffix = (rvalue->is_unsigned) ? "u" : ""; + OUT(c, locp, "tcg_gen_ext", sign_suffix, + "_i32_i64(", &res, ", ", rvalue, ");\n"); + rvalue_free(c, locp, rvalue); + return res; + } + } + return *rvalue; +} + +HexValue rvalue_truncate(Context *c, YYLTYPE *locp, HexValue *rvalue) +{ + if (rvalue->type == IMMEDIATE) { + HexValue res = *rvalue; + res.bit_width = 32; + return res; + } else { + if (rvalue->bit_width == 64) { + HexValue res = gen_tmp(c, locp, 32); + OUT(c, locp, "tcg_gen_trunc_i64_tl(", &res, ", ", rvalue, ");\n"); + rvalue_free(c, locp, rvalue); + return res; + } + } + return *rvalue; +} + +int find_variable(Context *c, YYLTYPE *locp, HexValue *varid) +{ + for (int i = 0; i < c->inst.allocated->len; i++) { + Var *curr = &g_array_index(c->inst.allocated, Var, i); + if (g_string_equal(varid->var.name, curr->name)) { + return i; + } + } + return -1; +} + +void varid_allocate(Context *c, + YYLTYPE *locp, + HexValue *varid, + int width, + bool is_unsigned) +{ + varid->bit_width = width; + const char *bit_suffix = width == 64 ? "64" : "32"; + int index = find_variable(c, locp, varid); + bool found = index != -1; + if (found) { + Var *other = &g_array_index(c->inst.allocated, Var, index); + varid->var.name = other->name; + varid->bit_width = other->bit_width; + varid->is_unsigned = other->is_unsigned; + } else { + EMIT_HEAD(c, "TCGv_i%s %s", bit_suffix, varid->var.name->str); + EMIT_HEAD(c, " = tcg_temp_local_new_i%s();\n", bit_suffix); + Var new_var = { + .name = varid->var.name, + .bit_width = width, + .is_unsigned = is_unsigned, + }; + g_array_append_val(c->inst.allocated, new_var); + } +} + +void ea_free(Context *c, YYLTYPE *locp) +{ + OUT(c, locp, "tcg_temp_free(EA);\n"); +} + +enum OpTypes { + IMM_IMM = 0, + IMM_REG = 1, + REG_IMM = 2, + REG_REG = 3, +}; + +HexValue gen_bin_cmp(Context *c, + YYLTYPE *locp, + TCGCond type, + HexValue *op1_ptr, + HexValue *op2_ptr) +{ + HexValue op1 = *op1_ptr; + HexValue op2 = *op2_ptr; + enum OpTypes op_types = (op1.type != IMMEDIATE) << 1 + | (op2.type != IMMEDIATE); + + /* Find bit width of the two operands, if at least one is 64 bit use a */ + /* 64bit operation, eventually extend 32bit operands. */ + bool op_is64bit = op1.bit_width == 64 || op2.bit_width == 64; + const char *bit_suffix = op_is64bit ? "i64" : "i32"; + int bit_width = (op_is64bit) ? 64 : 32; + if (op_is64bit) { + switch (op_types) { + case IMM_IMM: + break; + case IMM_REG: + op2 = rvalue_extend(c, locp, &op2); + break; + case REG_IMM: + op1 = rvalue_extend(c, locp, &op1); + break; + case REG_REG: + op1 = rvalue_extend(c, locp, &op1); + op2 = rvalue_extend(c, locp, &op2); + break; + } + } + + HexValue res = gen_tmp(c, locp, bit_width); + + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "tcg_gen_movi_", bit_suffix, + "(", &res, ", ", &op1, " == ", &op2, ");\n"); + break; + case IMM_REG: + { + HexValue swp = op2; + op2 = op1; + op1 = swp; + /* Swap comparison direction */ + type = tcg_swap_cond(type); + } + /* fallthrough */ + case REG_IMM: + OUT(c, locp, "tcg_gen_setcondi_", bit_suffix, "("); + OUT(c, locp, cond_to_str(type), ", ", &res, ", ", &op1, ", ", &op2, + ");\n"); + break; + case REG_REG: + OUT(c, locp, "tcg_gen_setcond_", bit_suffix, "("); + OUT(c, locp, cond_to_str(type), ", ", &res, ", ", &op1, ", ", &op2, + ");\n"); + break; + default: + fprintf(stderr, "Error in evalutating immediateness!"); + abort(); + } + + /* Free operands */ + rvalue_free(c, locp, &op1); + rvalue_free(c, locp, &op2); + + return res; +} + +static void gen_simple_op(Context *c, YYLTYPE *locp, unsigned bit_width, + const char *bit_suffix, HexValue *res, + enum OpTypes op_types, HexValue *op1, + HexValue *op2, + const char *imm_imm, + const char *imm_reg, + const char *reg_imm, + const char *reg_reg + ) { + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int", &bit_width, "_t ", res, + " = ", op1, imm_imm, op2, ";\n"); + break; + case IMM_REG: + OUT(c, locp, imm_reg, bit_suffix, + "(", res, ", ", op2, ", (int64_t)", op1, ");\n"); + break; + case REG_IMM: + OUT(c, locp, reg_imm, bit_suffix, + "(", res, ", ", op1, ", (int64_t)", op2, ");\n"); + break; + case REG_REG: + OUT(c, locp, reg_reg, bit_suffix, + "(", res, ", ", op1, ", ", op2, ");\n"); + break; + } + rvalue_free(c, locp, op1); + rvalue_free(c, locp, op2); +} + +static void gen_sub_op(Context *c, YYLTYPE *locp, unsigned bit_width, + const char *bit_suffix, HexValue *res, + enum OpTypes op_types, HexValue *op1, HexValue *op2) +{ + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int", &bit_width, "_t ", res, + " = ", op1, " - ", op2, ";\n"); + break; + case IMM_REG: + OUT(c, locp, "tcg_gen_subfi_", bit_suffix, + "(", res, ", ", op1, ", ", op2, ");\n"); + break; + case REG_IMM: + OUT(c, locp, "tcg_gen_subi_", bit_suffix, + "(", res, ", ", op1, ", ", op2, ");\n"); + break; + case REG_REG: + OUT(c, locp, "tcg_gen_sub_", bit_suffix, + "(", res, ", ", op1, ", ", op2, ");\n"); + break; + } + rvalue_free(c, locp, op1); + rvalue_free(c, locp, op2); +} + +static void gen_asl_op(Context *c, YYLTYPE *locp, unsigned bit_width, + bool op_is64bit, const char *bit_suffix, HexValue *res, + enum OpTypes op_types, HexValue *op1_ptr, + HexValue *op2_ptr) +{ + HexValue op1 = *op1_ptr; + HexValue op2 = *op2_ptr; + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int", &bit_width, "_t ", res, + " = ", &op1, " << ", &op2, ";\n"); + break; + case REG_IMM: + { + OUT(c, locp, "if (", &op2, " >= ", &bit_width, ") {\n"); + OUT(c, locp, "tcg_gen_movi_", bit_suffix, "(", res, ", 0);\n"); + OUT(c, locp, "} else {\n"); + OUT(c, locp, "tcg_gen_shli_", bit_suffix, + "(", res, ", ", &op1, ", ", &op2, ");\n"); + OUT(c, locp, "}\n"); + } + break; + case IMM_REG: + op1.bit_width = bit_width; + op1 = rvalue_materialize(c, locp, &op1); + /* Fallthrough */ + case REG_REG: + OUT(c, locp, "tcg_gen_shl_", bit_suffix, + "(", res, ", ", &op1, ", ", &op2, ");\n"); + break; + } + if (op_types == IMM_REG || op_types == REG_REG) { + /* Handle left shift by 64/32 which hexagon-sim expects to clear out */ + /* register */ + HexValue edge = gen_imm_value(c, locp, bit_width, bit_width); + edge = rvalue_materialize(c, locp, &edge); + HexValue zero = gen_tmp_value(c, locp, "0", bit_width); + if (op_is64bit) { + op2 = rvalue_extend(c, locp, &op2); + } + op1 = rvalue_materialize(c, locp, &op1); + op2 = rvalue_materialize(c, locp, &op2); + OUT(c, locp, "tcg_gen_movcond_i", &bit_width); + OUT(c, locp, "(TCG_COND_GEU, ", res, ", ", &op2, ", ", &edge); + OUT(c, locp, ", ", &zero, ", ", res, ");\n"); + rvalue_free(c, locp, &edge); + rvalue_free(c, locp, &zero); + } + rvalue_free(c, locp, &op1); + rvalue_free(c, locp, &op2); +} + +static void gen_asr_op(Context *c, YYLTYPE *locp, unsigned bit_width, + bool op_is64bit, const char *bit_suffix, HexValue *res, + enum OpTypes op_types, HexValue *op1_ptr, + HexValue *op2_ptr) +{ + HexValue op1 = *op1_ptr; + HexValue op2 = *op2_ptr; + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int", &bit_width, "_t ", res, + " = ", &op1, " >> ", &op2, ";\n"); + break; + case REG_IMM: + OUT(c, locp, "{\nint", &bit_width, "_t shift = ", &op2, ";\n"); + OUT(c, locp, "if (", &op2, " >= ", &bit_width, ") {\n"); + OUT(c, locp, " shift = ", &bit_width, " - 1;\n"); + OUT(c, locp, "}\n"); + OUT(c, locp, "tcg_gen_sari_", bit_suffix, + "(", res, ", ", &op1, ", shift);\n}\n"); + break; + case IMM_REG: + op1 = rvalue_materialize(c, locp, &op1); + /* Fallthrough */ + case REG_REG: + OUT(c, locp, "tcg_gen_sar_", bit_suffix, + "(", res, ", ", &op1, ", ", &op2, ");\n"); + break; + } + if (op_types == IMM_REG || op_types == REG_REG) { + /* Handle right shift by values >= bit_width */ + HexValue edge = gen_imm_value(c, locp, bit_width, bit_width); + edge = rvalue_materialize(c, locp, &edge); + HexValue tmp = gen_tmp(c, locp, bit_width); + HexValue zero = gen_tmp_value(c, locp, "0", bit_width); + if (op_is64bit) { + op2 = rvalue_extend(c, locp, &op2); + } + op1 = rvalue_materialize(c, locp, &op1); + op2 = rvalue_materialize(c, locp, &op2); + + const char *offset = op_is64bit ? "63" : "31"; + OUT(c, locp, "tcg_gen_extract_", bit_suffix, "(", + &tmp, ", ", &op1, ", ", offset, ", 1);\n"); + OUT(c, locp, "tcg_gen_sub_", bit_suffix, "(", + &tmp, ", ", &zero, ", ", &tmp, ");\n"); + OUT(c, locp, "tcg_gen_movcond_i", &bit_width); + OUT(c, locp, "(TCG_COND_GEU, ", res, ", ", &op2, ", ", &edge); + OUT(c, locp, ", ", &tmp, ", ", res, ");\n"); + rvalue_free(c, locp, &edge); + rvalue_free(c, locp, &tmp); + rvalue_free(c, locp, &zero); + } + rvalue_free(c, locp, &op1); + rvalue_free(c, locp, &op2); +} + +static void gen_lsr_op(Context *c, YYLTYPE *locp, unsigned bit_width, + bool op_is64bit, const char *bit_suffix, HexValue *res, + enum OpTypes op_types, HexValue *op1_ptr, + HexValue *op2_ptr) +{ + HexValue op1 = *op1_ptr; + HexValue op2 = *op2_ptr; + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int", &bit_width, "_t ", + res, " = ", &op1, " >> ", &op2, ";\n"); + break; + case REG_IMM: + OUT(c, locp, "if (", &op2, " >= ", &bit_width, ") {\n"); + OUT(c, locp, "tcg_gen_movi_", bit_suffix, "(", res, ", 0);\n"); + OUT(c, locp, "} else {\n"); + OUT(c, locp, "tcg_gen_shri_", bit_suffix, + "(", res, ", ", &op1, ", ", &op2, ");\n"); + OUT(c, locp, "}\n"); + break; + case IMM_REG: + op1 = rvalue_materialize(c, locp, &op1); + /* Fallthrough */ + case REG_REG: + OUT(c, locp, "tcg_gen_shr_", bit_suffix, + "(", res, ", ", &op1, ", ", &op2, ");\n"); + break; + } + if (op_types == IMM_REG || op_types == REG_REG) { + /* Handle right shift by values >= bit_width */ + HexValue edge = gen_imm_value(c, locp, bit_width, bit_width); + edge = rvalue_materialize(c, locp, &edge); + HexValue zero = gen_tmp_value(c, locp, "0", bit_width); + if (op_is64bit) { + op2 = rvalue_extend(c, locp, &op2); + } + op1 = rvalue_materialize(c, locp, &op1); + op2 = rvalue_materialize(c, locp, &op2); + OUT(c, locp, "tcg_gen_movcond_i", &bit_width); + OUT(c, locp, "(TCG_COND_GEU, ", res, ", ", &op2, ", ", &edge); + OUT(c, locp, ", ", &zero, ", ", res, ");\n"); + rvalue_free(c, locp, &edge); + rvalue_free(c, locp, &zero); + } + rvalue_free(c, locp, &op1); + rvalue_free(c, locp, &op2); +} + +static void gen_andl_op(Context *c, YYLTYPE *locp, unsigned bit_width, + const char *bit_suffix, HexValue *res, + enum OpTypes op_types, HexValue *op1, HexValue *op2) +{ + HexValue zero, tmp1, tmp2; + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int", &bit_width, "_t ", + res, " = ", op1, " && ", op2, ";\n"); + break; + case IMM_REG: + zero = gen_tmp_value(c, locp, "0", 32); + tmp2 = gen_bin_cmp(c, locp, TCG_COND_NE, op2, &zero); + OUT(c, locp, "tcg_gen_andi_", bit_suffix, + "(", res, ", ", op1, " != 0 , ", &tmp2, ");\n"); + rvalue_free(c, locp, &tmp2); + break; + case REG_IMM: + zero = gen_tmp_value(c, locp, "0", 32); + tmp1 = gen_bin_cmp(c, locp, TCG_COND_NE, op1, &zero); + OUT(c, locp, "tcg_gen_andi_", bit_suffix, + "(", res, ", ", &tmp1, ", ", op2, " != 0);\n"); + rvalue_free(c, locp, &tmp1); + break; + case REG_REG: + zero = gen_tmp_value(c, locp, "0", 32); + zero.is_manual = true; + tmp1 = gen_bin_cmp(c, locp, TCG_COND_NE, op1, &zero); + tmp2 = gen_bin_cmp(c, locp, TCG_COND_NE, op2, &zero); + OUT(c, locp, "tcg_gen_and_", bit_suffix, + "(", res, ", ", &tmp1, ", ", &tmp2, ");\n"); + rvalue_free_manual(c, locp, &zero); + rvalue_free(c, locp, &tmp1); + rvalue_free(c, locp, &tmp2); + break; + } +} + +static void gen_mini_op(Context *c, YYLTYPE *locp, unsigned bit_width, + HexValue *res, enum OpTypes op_types, + HexValue *op1_ptr, HexValue *op2_ptr) +{ + HexValue op1 = *op1_ptr; + HexValue op2 = *op2_ptr; + const char *min = res->is_unsigned ? "tcg_gen_umin" : "tcg_gen_smin"; + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int", &bit_width, "_t ", res, " = (", &op1, " <= "); + OUT(c, locp, &op2, ") ? ", &op1, " : ", &op2, ";\n"); + break; + case IMM_REG: + op1.bit_width = bit_width; + op1 = rvalue_materialize(c, locp, &op1); + OUT(c, locp, min, "_i", &bit_width, "("); + OUT(c, locp, res, ", ", &op1, ", ", &op2, ");\n"); + break; + case REG_IMM: + op2.bit_width = bit_width; + op2 = rvalue_materialize(c, locp, &op2); + /* Fallthrough */ + case REG_REG: + OUT(c, locp, min, "_i", &bit_width, "("); + OUT(c, locp, res, ", ", &op1, ", ", &op2, ");\n"); + break; + } + rvalue_free(c, locp, &op1); + rvalue_free(c, locp, &op2); +} + +static void gen_maxi_op(Context *c, YYLTYPE *locp, unsigned bit_width, + HexValue *res, enum OpTypes op_types, + HexValue *op1_ptr, HexValue *op2_ptr) +{ + HexValue op1 = *op1_ptr; + HexValue op2 = *op2_ptr; + const char *min = res->is_unsigned ? "tcg_gen_umax" : "tcg_gen_smax"; + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int", &bit_width, "_t ", res, " = (", &op1, " <= "); + OUT(c, locp, &op2, ") ? ", &op2, " : ", &op1, ";\n"); + break; + case IMM_REG: + op1.bit_width = bit_width; + op1 = rvalue_materialize(c, locp, &op1); + OUT(c, locp, min, "_i", &bit_width, "("); + OUT(c, locp, res, ", ", &op1, ", ", &op2, ");\n"); + break; + case REG_IMM: + op2.bit_width = bit_width; + op2 = rvalue_materialize(c, locp, &op2); + /* Fallthrough */ + case REG_REG: + OUT(c, locp, min, "_i", &bit_width, "("); + OUT(c, locp, res, ", ", &op1, ", ", &op2, ");\n"); + break; + } + rvalue_free(c, locp, &op1); + rvalue_free(c, locp, &op2); +} + +static void gen_mod_op(Context *c, YYLTYPE *locp, HexValue *res, + enum OpTypes op_types, HexValue *op1, HexValue *op2) +{ + switch (op_types) { + case IMM_IMM: + OUT(c, locp, "int64_t ", res, " = ", op1, " % ", op2, ";\n"); + break; + case IMM_REG: + case REG_IMM: + case REG_REG: + OUT(c, locp, "gen_helper_mod(", + res, ", ", op1, ", ", op2, ");\n"); + break; + } + rvalue_free(c, locp, op1); + rvalue_free(c, locp, op2); +} + +/* Code generation functions */ +HexValue gen_bin_op(Context *c, + YYLTYPE *locp, + OpType type, + HexValue *operand1, + HexValue *operand2) +{ + /* Replicate operands to avoid side effects */ + HexValue op1 = *operand1; + HexValue op2 = *operand2; + + /* Enforce variables' size */ + if (op1.type == VARID) { + int index = find_variable(c, locp, &op1); + yyassert(c, locp, c->inst.allocated->len > 0, + "Variable in bin_op must exist!\n"); + op1.bit_width = g_array_index(c->inst.allocated, Var, index).bit_width; + } + if (op2.type == VARID) { + int index = find_variable(c, locp, &op2); + yyassert(c, locp, c->inst.allocated->len > 0, + "Variable in bin_op must exist!\n"); + op2.bit_width = g_array_index(c->inst.allocated, Var, index).bit_width; + } + + enum OpTypes op_types = (op1.type != IMMEDIATE) << 1 + | (op2.type != IMMEDIATE); + + /* Find bit width of the two operands, if at least one is 64 bit use a */ + /* 64bit operation, eventually extend 32bit operands. */ + bool op_is64bit = op1.bit_width == 64 || op2.bit_width == 64; + /* Shift greater than 32 are 64 bits wide */ + if (type == ASL_OP && op2.type == IMMEDIATE && + op2.imm.type == VALUE && op2.imm.value >= 32) + op_is64bit = true; + const char *bit_suffix = op_is64bit ? "i64" : "i32"; + int bit_width = (op_is64bit) ? 64 : 32; + /* Handle bit width */ + if (op_is64bit) { + switch (op_types) { + case IMM_IMM: + break; + case IMM_REG: + op2 = rvalue_extend(c, locp, &op2); + break; + case REG_IMM: + op1 = rvalue_extend(c, locp, &op1); + break; + case REG_REG: + op1 = rvalue_extend(c, locp, &op1); + op2 = rvalue_extend(c, locp, &op2); + break; + } + } + HexValue res; + if (op_types != IMM_IMM) { + res = gen_tmp(c, locp, bit_width); + } else { + res.type = IMMEDIATE; + res.is_dotnew = false; + res.is_manual = false; + res.imm.type = QEMU_TMP; + res.imm.index = c->inst.qemu_tmp_count; + res.bit_width = bit_width; + } + /* Handle signedness, if both unsigned -> result is unsigned, else signed */ + res.is_unsigned = op1.is_unsigned && op2.is_unsigned; + + switch (type) { + case ADD_OP: + gen_simple_op(c, locp, bit_width, bit_suffix, &res, + op_types, &op1, &op2, + " + ", + "tcg_gen_addi_", + "tcg_gen_addi_", + "tcg_gen_add_"); + break; + case SUB_OP: + gen_sub_op(c, locp, bit_width, bit_suffix, &res, op_types, &op1, &op2); + break; + case MUL_OP: + gen_simple_op(c, locp, bit_width, bit_suffix, &res, + op_types, &op1, &op2, + " * ", + "tcg_gen_muli_", + "tcg_gen_muli_", + "tcg_gen_mul_"); + break; + case ASL_OP: + gen_asl_op(c, locp, bit_width, op_is64bit, bit_suffix, &res, op_types, + &op1, &op2); + break; + case ASR_OP: + gen_asr_op(c, locp, bit_width, op_is64bit, bit_suffix, &res, op_types, + &op1, &op2); + break; + case LSR_OP: + gen_lsr_op(c, locp, bit_width, op_is64bit, bit_suffix, &res, op_types, + &op1, &op2); + break; + case ANDB_OP: + gen_simple_op(c, locp, bit_width, bit_suffix, &res, + op_types, &op1, &op2, + " & ", + "tcg_gen_andi_", + "tcg_gen_andi_", + "tcg_gen_and_"); + break; + case ORB_OP: + gen_simple_op(c, locp, bit_width, bit_suffix, &res, + op_types, &op1, &op2, + " | ", + "tcg_gen_ori_", + "tcg_gen_ori_", + "tcg_gen_or_"); + break; + case XORB_OP: + gen_simple_op(c, locp, bit_width, bit_suffix, &res, + op_types, &op1, &op2, + " ^ ", + "tcg_gen_xori_", + "tcg_gen_xori_", + "tcg_gen_xor_"); + break; + case ANDL_OP: + gen_andl_op(c, locp, bit_width, bit_suffix, &res, op_types, &op1, &op2); + break; + case MINI_OP: + gen_mini_op(c, locp, bit_width, &res, op_types, &op1, &op2); + break; + case MAXI_OP: + gen_maxi_op(c, locp, bit_width, &res, op_types, &op1, &op2); + break; + case MOD_OP: + gen_mod_op(c, locp, &res, op_types, &op1, &op2); + break; + } + if (op_types == IMM_IMM) { + c->inst.qemu_tmp_count++; + } + return res; +} + +HexValue gen_cast_op(Context *c, + YYLTYPE *locp, + HexValue *source, + unsigned target_width) { + if (source->bit_width == target_width) { + return *source; + } else if (source->type == IMMEDIATE) { + HexValue res = *source; + res.bit_width = target_width; + return res; + } else { + HexValue res = gen_tmp(c, locp, target_width); + /* Truncate */ + if (source->bit_width > target_width) { + OUT(c, locp, "tcg_gen_trunc_i64_tl(", &res, ", ", source, ");\n"); + } else { + if (source->is_unsigned) { + /* Extend unsigned */ + OUT(c, locp, "tcg_gen_extu_i32_i64(", + &res, ", ", source, ");\n"); + } else { + /* Extend signed */ + OUT(c, locp, "tcg_gen_ext_i32_i64(", + &res, ", ", source, ");\n"); + } + } + rvalue_free(c, locp, source); + return res; + } +} + +HexValue gen_extend_op(Context *c, + YYLTYPE *locp, + HexValue *src_width_ptr, + HexValue *dst_width_ptr, + HexValue *value_ptr, + bool is_unsigned) { + HexValue src_width = *src_width_ptr; + HexValue dst_width = *dst_width_ptr; + HexValue value = *value_ptr; + src_width = rvalue_extend(c, locp, &src_width); + value = rvalue_extend(c, locp, &value); + src_width = rvalue_materialize(c, locp, &src_width); + value = rvalue_materialize(c, locp, &value); + + HexValue res = gen_tmp(c, locp, 64); + HexValue shift = gen_tmp_value(c, locp, "64", 64); + HexValue zero = gen_tmp_value(c, locp, "0", 64); + OUT(c, locp, "tcg_gen_sub_i64(", + &shift, ", ", &shift, ", ", &src_width, ");\n"); + if (is_unsigned) { + HexValue mask = gen_tmp_value(c, locp, "0xffffffffffffffff", 64); + OUT(c, locp, "tcg_gen_shr_i64(", + &mask, ", ", &mask, ", ", &shift, ");\n"); + OUT(c, locp, "tcg_gen_and_i64(", + &res, ", ", &value, ", ", &mask, ");\n"); + rvalue_free(c, locp, &mask); + } else { + OUT(c, locp, "tcg_gen_shl_i64(", + &res, ", ", &value, ", ", &shift, ");\n"); + OUT(c, locp, "tcg_gen_sar_i64(", + &res, ", ", &res, ", ", &shift, ");\n"); + } + OUT(c, locp, "tcg_gen_movcond_i64(TCG_COND_EQ, ", &res, ", "); + OUT(c, locp, &src_width, ", ", &zero, ", ", &zero, ", ", &res, ");\n"); + + rvalue_free(c, locp, &src_width); + rvalue_free(c, locp, &dst_width); + rvalue_free(c, locp, &value); + rvalue_free(c, locp, &shift); + rvalue_free(c, locp, &zero); + + res.is_unsigned = is_unsigned; + return res; +} + +void gen_rdeposit_op(Context *c, + YYLTYPE *locp, + HexValue *dest, + HexValue *value, + HexValue *begin, + HexValue *width) +{ + HexValue dest_m = *dest; + dest_m.is_manual = true; + + HexValue value_m = rvalue_extend(c, locp, value); + HexValue begin_m = rvalue_extend(c, locp, begin); + HexValue width_orig = *width; + width_orig.is_manual = true; + HexValue width_m = rvalue_extend(c, locp, &width_orig); + width_m = rvalue_materialize(c, locp, &width_m); + + HexValue mask = gen_tmp_value(c, locp, "0xffffffffffffffffUL", 64); + mask.is_unsigned = true; + HexValue k64 = gen_tmp_value(c, locp, "64", 64); + k64 = gen_bin_op(c, locp, SUB_OP, &k64, &width_m); + mask = gen_bin_op(c, locp, LSR_OP, &mask, &k64); + begin_m.is_manual = true; + mask = gen_bin_op(c, locp, ASL_OP, &mask, &begin_m); + mask.is_manual = true; + value_m = gen_bin_op(c, locp, ASL_OP, &value_m, &begin_m); + value_m = gen_bin_op(c, locp, ANDB_OP, &value_m, &mask); + + OUT(c, locp, "tcg_gen_not_i64(", &mask, ", ", &mask, ");\n"); + mask.is_manual = false; + HexValue res = gen_bin_op(c, locp, ANDB_OP, &dest_m, &mask); + res = gen_bin_op(c, locp, ORB_OP, &res, &value_m); + + if (dest->bit_width != res.bit_width) { + res = rvalue_truncate(c, locp, &res); + } + + HexValue zero = gen_tmp_value(c, locp, "0", res.bit_width); + OUT(c, locp, "tcg_gen_movcond_i", &res.bit_width, "(TCG_COND_NE, ", dest); + OUT(c, locp, ", ", &width_orig, ", ", &zero, ", ", &res, ", ", dest, + ");\n"); + + rvalue_free(c, locp, &zero); + rvalue_free(c, locp, width); + rvalue_free(c, locp, &res); +} + +void gen_deposit_op(Context *c, + YYLTYPE *locp, + HexValue *dest, + HexValue *value, + HexValue *index, + HexCast *cast) +{ + yyassert(c, locp, index->type == IMMEDIATE, + "Deposit index must be immediate!\n"); + HexValue value_m = *value; + int bit_width = (dest->bit_width == 64) ? 64 : 32; + int width = cast->bit_width; + /* If the destination value is 32, truncate the value, otherwise extend */ + if (dest->bit_width != value->bit_width) { + if (bit_width == 32) { + value_m = rvalue_truncate(c, locp, &value_m); + } else { + value_m = rvalue_extend(c, locp, &value_m); + } + } + value_m = rvalue_materialize(c, locp, &value_m); + OUT(c, locp, "tcg_gen_deposit_i", &bit_width, "(", dest, ", ", dest, ", "); + OUT(c, locp, &value_m, ", ", index, " * ", &width, ", ", &width, ");\n"); + rvalue_free(c, locp, index); + rvalue_free(c, locp, &value_m); +} + +HexValue gen_rextract_op(Context *c, + YYLTYPE *locp, + HexValue *source, + int begin, + int width) { + int bit_width = (source->bit_width == 64) ? 64 : 32; + HexValue res = gen_tmp(c, locp, bit_width); + OUT(c, locp, "tcg_gen_extract_i", &bit_width, "(", &res); + OUT(c, locp, ", ", source, ", ", &begin, ", ", &width, ");\n"); + rvalue_free(c, locp, source); + return res; +} + +HexValue gen_extract_op(Context *c, + YYLTYPE *locp, + HexValue *source, + HexValue *index, + HexExtract *extract) { + yyassert(c, locp, index->type == IMMEDIATE, + "Extract index must be immediate!\n"); + int bit_width = (source->bit_width == 64) ? 64 : 32; + const char *sign_prefix = (extract->is_unsigned) ? "" : "s"; + int width = extract->bit_width; + HexValue res = gen_tmp(c, locp, bit_width); + res.is_unsigned = extract->is_unsigned; + OUT(c, locp, "tcg_gen_", sign_prefix, "extract_i", &bit_width, + "(", &res, ", ", source); + OUT(c, locp, ", ", index, " * ", &width, ", ", &width, ");\n"); + + /* Some extract operations have bit_width != storage_bit_width */ + if (extract->storage_bit_width > bit_width) { + HexValue tmp = gen_tmp(c, locp, extract->storage_bit_width); + tmp.is_unsigned = extract->is_unsigned; + if (extract->is_unsigned) { + /* Extend unsigned */ + OUT(c, locp, "tcg_gen_extu_i32_i64(", + &tmp, ", ", &res, ");\n"); + } else { + /* Extend signed */ + OUT(c, locp, "tcg_gen_ext_i32_i64(", + &tmp, ", ", &res, ");\n"); + } + rvalue_free(c, locp, &res); + res = tmp; + } + + rvalue_free(c, locp, source); + rvalue_free(c, locp, index); + return res; +} + +HexValue gen_read_creg(Context *c, YYLTYPE *locp, HexValue *reg) +{ + yyassert(c, locp, reg->type == REGISTER, "reg must be a register!"); + if (reg->reg.id < 'a') { + HexValue tmp = gen_tmp_value(c, locp, "0", 32); + const char *id = creg_str[(uint8_t)reg->reg.id]; + OUT(c, locp, "READ_REG(", &tmp, ", ", id, ");\n"); + rvalue_free(c, locp, reg); + return tmp; + } + return *reg; +} + +void gen_write_creg(Context *c, + YYLTYPE *locp, + HexValue *reg, + HexValue *value) +{ + yyassert(c, locp, reg->type == REGISTER, "reg must be a register!"); + HexValue value_m = *value; + value_m = rvalue_truncate(c, locp, &value_m); + value_m = rvalue_materialize(c, locp, &value_m); + OUT(c, + locp, + "gen_log_reg_write(", creg_str[(uint8_t)reg->reg.id], ", ", + &value_m, ");\n"); + OUT(c, + locp, + "ctx_log_reg_write(ctx, ", creg_str[(uint8_t)reg->reg.id], ");\n"); + rvalue_free(c, locp, reg); + rvalue_free(c, locp, &value_m); +} + +void gen_assign(Context *c, + YYLTYPE *locp, + HexValue *dest, + HexValue *value) +{ + yyassert(c, + locp, + !is_inside_ternary(c) + || !(dest->type == REGISTER && dest->reg.type == CONTROL), + "control assign in ternary"); + + HexValue value_m = *value; + if (dest->type == REGISTER && + dest->reg.type == CONTROL && dest->reg.id < 'a') { + gen_write_creg(c, locp, dest, &value_m); + return; + } + /* Create (if not present) and assign to temporary variable */ + if (dest->type == VARID) { + varid_allocate(c, locp, dest, value_m.bit_width, value_m.is_unsigned); + } + int bit_width = dest->bit_width == 64 ? 64 : 32; + if (bit_width != value_m.bit_width) { + if (bit_width == 64) { + value_m = rvalue_extend(c, locp, &value_m); + } else { + value_m = rvalue_truncate(c, locp, &value_m); + } + } + if (is_inside_ternary(c)) { + value_m = rvalue_materialize(c, locp, &value_m); + HexValue cond = get_ternary_cond(c, locp); + if (cond.bit_width != bit_width) { + if (cond.bit_width == 64) { + cond = rvalue_truncate(c, locp, &cond); + } else { + cond = rvalue_extend(c, locp, &cond); + } + } + HexValue zero = gen_tmp_value(c, locp, "0", bit_width); + OUT(c, locp, "tcg_gen_movcond_i", &bit_width, "(TCG_COND_NE, ", dest); + OUT(c, locp, ", ", &cond, ", ", &zero, ", "); + OUT(c, locp, &value_m, ", ", dest, ");\n"); + rvalue_free(c, locp, &cond); + rvalue_free(c, locp, &zero); + } else { + if (value_m.type == IMMEDIATE) { + OUT(c, locp, "tcg_gen_movi_i", &bit_width, + "(", dest, ", ", &value_m, ");\n"); + } else { + OUT(c, locp, "tcg_gen_mov_i", &bit_width, + "(", dest, ", ", &value_m, ");\n"); + } + } + rvalue_free(c, locp, &value_m); +} + +HexValue gen_convround(Context *c, + YYLTYPE *locp, + HexValue *source) +{ + HexValue src = *source; + src.is_manual = true; + + unsigned bit_width = src.bit_width; + const char *size = (bit_width == 32) ? "32" : "64"; + HexValue res = gen_tmp(c, locp, bit_width); + HexValue mask = gen_tmp_value(c, locp, "0x3", bit_width); + mask.is_manual = true; + HexValue and = gen_bin_op(c, locp, ANDB_OP, &src, &mask); + HexValue one = gen_tmp_value(c, locp, "1", bit_width); + HexValue src_p1 = gen_bin_op(c, locp, ADD_OP, &src, &one); + + OUT(c, locp, "tcg_gen_movcond_i", size, "(TCG_COND_EQ, ", &res); + OUT(c, locp, ", ", &and, ", ", &mask, ", "); + OUT(c, locp, &src_p1, ", ", &src, ");\n"); + + /* Free src but use the original `is_manual` value */ + rvalue_free(c, locp, source); + + /* Free the rest of the values */ + rvalue_free_manual(c, locp, &mask); + rvalue_free(c, locp, &and); + rvalue_free(c, locp, &src_p1); + + return res; +} + +static HexValue gen_convround_n_a(Context *c, + YYLTYPE *locp, + HexValue *a, + HexValue *n) +{ + HexValue res = gen_tmp(c, locp, 64); + OUT(c, locp, "tcg_gen_ext_i32_i64(", &res, ", ", a, ");\n"); + return res; +} + +static HexValue gen_convround_n_b(Context *c, + YYLTYPE *locp, + HexValue *a, + HexValue *n) +{ + HexValue res = gen_tmp(c, locp, 64); + OUT(c, locp, "tcg_gen_ext_i32_i64(", &res, ", ", a, ");\n"); + + HexValue one = gen_tmp_value(c, locp, "1", 32); + HexValue tmp = gen_tmp(c, locp, 32); + HexValue tmp_64 = gen_tmp(c, locp, 64); + + OUT(c, locp, "tcg_gen_shl_i32(", &tmp); + OUT(c, locp, ", ", &one, ", ", n, ");\n"); + OUT(c, locp, "tcg_gen_and_i32(", &tmp); + OUT(c, locp, ", ", &tmp, ", ", a, ");\n"); + OUT(c, locp, "tcg_gen_shri_i32(", &tmp); + OUT(c, locp, ", ", &tmp, ", 1);\n"); + OUT(c, locp, "tcg_gen_ext_i32_i64(", &tmp_64, ", ", &tmp, ");\n"); + OUT(c, locp, "tcg_gen_add_i64(", &res); + OUT(c, locp, ", ", &res, ", ", &tmp_64, ");\n"); + + rvalue_free(c, locp, &one); + rvalue_free(c, locp, &tmp); + rvalue_free(c, locp, &tmp_64); + + return res; +} + +static HexValue gen_convround_n_c(Context *c, + YYLTYPE *locp, + HexValue *a, + HexValue *n) +{ + HexValue res = gen_tmp(c, locp, 64); + OUT(c, locp, "tcg_gen_ext_i32_i64(", &res, ", ", a, ");\n"); + + HexValue one = gen_tmp_value(c, locp, "1", 32); + HexValue tmp = gen_tmp(c, locp, 32); + HexValue tmp_64 = gen_tmp(c, locp, 64); + + OUT(c, locp, "tcg_gen_subi_i32(", &tmp); + OUT(c, locp, ", ", n, ", 1);\n"); + OUT(c, locp, "tcg_gen_shl_i32(", &tmp); + OUT(c, locp, ", ", &one, ", ", &tmp, ");\n"); + OUT(c, locp, "tcg_gen_ext_i32_i64(", &tmp_64, ", ", &tmp, ");\n"); + OUT(c, locp, "tcg_gen_add_i64(", &res); + OUT(c, locp, ", ", &res, ", ", &tmp_64, ");\n"); + + rvalue_free(c, locp, &one); + rvalue_free(c, locp, &tmp); + rvalue_free(c, locp, &tmp_64); + + return res; +} + +HexValue gen_convround_n(Context *c, + YYLTYPE *locp, + HexValue *source_ptr, + HexValue *bit_pos_ptr) +{ + /* If input is 64 bit cast it to 32 */ + HexValue source = gen_cast_op(c, locp, source_ptr, 32); + HexValue bit_pos = gen_cast_op(c, locp, bit_pos_ptr, 32); + + source = rvalue_materialize(c, locp, &source); + bit_pos = rvalue_materialize(c, locp, &bit_pos); + + HexValue r1 = gen_convround_n_a(c, locp, &source, &bit_pos); + HexValue r2 = gen_convround_n_b(c, locp, &source, &bit_pos); + HexValue r3 = gen_convround_n_c(c, locp, &source, &bit_pos); + + HexValue l_32 = gen_tmp_value(c, locp, "1", 32); + + HexValue cond = gen_tmp(c, locp, 32); + HexValue cond_64 = gen_tmp(c, locp, 64); + HexValue mask = gen_tmp(c, locp, 32); + HexValue n_64 = gen_tmp(c, locp, 64); + HexValue res = gen_tmp(c, locp, 64); + HexValue zero = gen_tmp_value(c, locp, "0", 64); + + OUT(c, locp, "tcg_gen_sub_i32(", &mask); + OUT(c, locp, ", ", &bit_pos, ", ", &l_32, ");\n"); + OUT(c, locp, "tcg_gen_shl_i32(", &mask); + OUT(c, locp, ", ", &l_32, ", ", &mask, ");\n"); + OUT(c, locp, "tcg_gen_sub_i32(", &mask); + OUT(c, locp, ", ", &mask, ", ", &l_32, ");\n"); + OUT(c, locp, "tcg_gen_and_i32(", &cond); + OUT(c, locp, ", ", &source, ", ", &mask, ");\n"); + OUT(c, locp, "tcg_gen_extu_i32_i64(", &cond_64, ", ", &cond, ");\n"); + OUT(c, locp, "tcg_gen_ext_i32_i64(", &n_64, ", ", &bit_pos, ");\n"); + + OUT(c, locp, "tcg_gen_movcond_i64"); + OUT(c, locp, "(TCG_COND_EQ, ", &res, ", ", &cond_64, ", ", &zero); + OUT(c, locp, ", ", &r2, ", ", &r3, ");\n"); + + OUT(c, locp, "tcg_gen_movcond_i64"); + OUT(c, locp, "(TCG_COND_EQ, ", &res, ", ", &n_64, ", ", &zero); + OUT(c, locp, ", ", &r1, ", ", &res, ");\n"); + + OUT(c, locp, "tcg_gen_shr_i64(", &res); + OUT(c, locp, ", ", &res, ", ", &n_64, ");\n"); + + rvalue_free(c, locp, &source); + rvalue_free(c, locp, &bit_pos); + + rvalue_free(c, locp, &r1); + rvalue_free(c, locp, &r2); + rvalue_free(c, locp, &r3); + + rvalue_free(c, locp, &cond); + rvalue_free(c, locp, &cond_64); + rvalue_free(c, locp, &l_32); + rvalue_free(c, locp, &mask); + rvalue_free(c, locp, &n_64); + rvalue_free(c, locp, &zero); + + res = rvalue_truncate(c, locp, &res); + return res; +} + +HexValue gen_round(Context *c, + YYLTYPE *locp, + HexValue *source, + HexValue *position) { + yyassert(c, locp, source->bit_width <= 32, + "fRNDN not implemented for bit widths > 32!"); + + HexValue src = *source; + HexValue pos = *position; + + HexValue src_width = gen_imm_value(c, locp, src.bit_width, 32); + HexValue dst_width = gen_imm_value(c, locp, 64, 32); + HexValue a = gen_extend_op(c, locp, &src_width, &dst_width, &src, false); + + src_width = gen_imm_value(c, locp, 5, 32); + dst_width = gen_imm_value(c, locp, 64, 32); + HexValue b = gen_extend_op(c, locp, &src_width, &dst_width, &pos, true); + + /* Disable auto-free of values used more than once */ + a.is_manual = true; + b.is_manual = true; + + HexValue res = gen_tmp(c, locp, 64); + + HexValue one = gen_tmp_value(c, locp, "1", 64); + HexValue n_m1 = gen_bin_op(c, locp, SUB_OP, &b, &one); + one = gen_tmp_value(c, locp, "1", 64); + HexValue shifted = gen_bin_op(c, locp, ASL_OP, &one, &n_m1); + HexValue sum = gen_bin_op(c, locp, ADD_OP, &shifted, &a); + + HexValue zero = gen_tmp_value(c, locp, "0", 64); + OUT(c, locp, "tcg_gen_movcond_i64"); + OUT(c, locp, "(TCG_COND_EQ, ", &res, ", ", &b, ", ", &zero); + OUT(c, locp, ", ", &a, ", ", &sum, ");\n"); + + rvalue_free_manual(c, locp, &a); + rvalue_free_manual(c, locp, &b); + rvalue_free(c, locp, &zero); + rvalue_free(c, locp, &sum); + + return res; +} + +/* Circular addressing mode with auto-increment */ +void gen_circ_op(Context *c, + YYLTYPE *locp, + HexValue *addr, + HexValue *increment, + HexValue *modifier) { + HexValue increment_m = *increment; + HexValue cs = gen_tmp(c, locp, 32); + increment_m = rvalue_materialize(c, locp, &increment_m); + OUT(c, locp, "READ_REG(", &cs, ", HEX_REG_CS0 + MuN);\n"); + OUT(c, + locp, + "gen_helper_fcircadd(", + addr, + ", ", + addr, + ", ", + &increment_m, + ", ", + modifier); + OUT(c, locp, ", ", &cs, ");\n"); + rvalue_free(c, locp, &increment_m); + rvalue_free(c, locp, modifier); + rvalue_free(c, locp, &cs); +} + +HexValue gen_locnt_op(Context *c, YYLTYPE *locp, HexValue *source) +{ + HexValue source_m = *source; + const char *bit_suffix = source->bit_width == 64 ? "64" : "32"; + HexValue res = gen_tmp(c, locp, source->bit_width == 64 ? 64 : 32); + res.type = TEMP; + source_m = rvalue_materialize(c, locp, &source_m); + OUT(c, locp, "tcg_gen_not_i", bit_suffix, "(", + &res, ", ", &source_m, ");\n"); + OUT(c, locp, "tcg_gen_clzi_i", bit_suffix, "(", &res, ", ", &res, ", "); + OUT(c, locp, bit_suffix, ");\n"); + rvalue_free(c, locp, &source_m); + return res; +} + +HexValue gen_ctpop_op(Context *c, YYLTYPE *locp, HexValue *source) +{ + HexValue source_m = *source; + const char *bit_suffix = source_m.bit_width == 64 ? "64" : "32"; + HexValue res = gen_tmp(c, locp, source_m.bit_width == 64 ? 64 : 32); + res.type = TEMP; + source_m = rvalue_materialize(c, locp, &source_m); + OUT(c, locp, "tcg_gen_ctpop_i", bit_suffix, + "(", &res, ", ", &source_m, ");\n"); + rvalue_free(c, locp, &source_m); + return res; +} + +HexValue gen_fbrev_4(Context *c, YYLTYPE *locp, HexValue *source) +{ + HexValue source_m = *source; + + HexValue res = gen_tmp(c, locp, 32); + HexValue tmp1 = gen_tmp(c, locp, 32); + HexValue tmp2 = gen_tmp(c, locp, 32); + + source_m = rvalue_materialize(c, locp, &source_m); + source_m = rvalue_truncate(c, locp, &source_m); + + OUT(c, locp, "tcg_gen_mov_tl(", &res, ", ", &source_m, ");\n"); + OUT(c, locp, "tcg_gen_andi_tl(", &tmp1, ", ", &res, ", 0xaaaaaaaa);\n"); + OUT(c, locp, "tcg_gen_shri_tl(", &tmp1, ", ", &tmp1, ", 1);\n"); + OUT(c, locp, "tcg_gen_andi_tl(", &tmp2, ", ", &res, ", 0x55555555);\n"); + OUT(c, locp, "tcg_gen_shli_tl(", &tmp2, ", ", &tmp2, ", 1);\n"); + OUT(c, locp, "tcg_gen_or_tl(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"); + OUT(c, locp, "tcg_gen_andi_tl(", &tmp1, ", ", &res, ", 0xcccccccc);\n"); + OUT(c, locp, "tcg_gen_shri_tl(", &tmp1, ", ", &tmp1, ", 2);\n"); + OUT(c, locp, "tcg_gen_andi_tl(", &tmp2, ", ", &res, ", 0x33333333);\n"); + OUT(c, locp, "tcg_gen_shli_tl(", &tmp2, ", ", &tmp2, ", 2);\n"); + OUT(c, locp, "tcg_gen_or_tl(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"); + OUT(c, locp, "tcg_gen_andi_tl(", &tmp1, ", ", &res, ", 0xf0f0f0f0);\n"); + OUT(c, locp, "tcg_gen_shri_tl(", &tmp1, ", ", &tmp1, ", 4);\n"); + OUT(c, locp, "tcg_gen_andi_tl(", &tmp2, ", ", &res, ", 0x0f0f0f0f);\n"); + OUT(c, locp, "tcg_gen_shli_tl(", &tmp2, ", ", &tmp2, ", 4);\n"); + OUT(c, locp, "tcg_gen_or_tl(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"); + OUT(c, locp, "tcg_gen_bswap32_tl(", &res, ", ", &res, ");\n"); + + rvalue_free(c, locp, &tmp1); + rvalue_free(c, locp, &tmp2); + rvalue_free(c, locp, &source_m); + + return res; +} + +HexValue gen_fbrev_8(Context *c, YYLTYPE *locp, HexValue *source) +{ + HexValue source_m = *source; + + source_m = rvalue_extend(c, locp, &source_m); + source_m = rvalue_materialize(c, locp, &source_m); + + HexValue res = gen_tmp(c, locp, 64); + HexValue tmp1 = gen_tmp(c, locp, 64); + HexValue tmp2 = gen_tmp(c, locp, 64); + + OUT(c, locp, "tcg_gen_mov_i64(", + &res, ", ", &source_m, ");\n"); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp1, ", ", &res, ", 0xaaaaaaaaaaaaaaaa);\n"); + OUT(c, locp, "tcg_gen_shri_i64(", + &tmp1, ", ", &tmp1, ", 1);\n"); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp2, ", ", &res, ", 0x5555555555555555);\n"); + OUT(c, locp, "tcg_gen_shli_i64(", + &tmp2, ", ", &tmp2, ", 1);\n"); + OUT(c, locp, "tcg_gen_or_i64(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp1, ", ", &res, ", 0xcccccccccccccccc);\n"); + OUT(c, locp, "tcg_gen_shri_i64(", + &tmp1, ", ", &tmp1, ", 2);\n"); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp2, ", ", &res, ", 0x3333333333333333);\n"); + OUT(c, locp, "tcg_gen_shli_i64(", + &tmp2, ", ", &tmp2, ", 2);\n"); + OUT(c, locp, "tcg_gen_or_i64(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp1, ", ", &res, ", 0xf0f0f0f0f0f0f0f0);\n"); + OUT(c, locp, "tcg_gen_shri_i64(", + &tmp1, ", ", &tmp1, ", 4);\n"); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp2, ", ", &res, ", 0x0f0f0f0f0f0f0f0f);\n"); + OUT(c, locp, "tcg_gen_shli_i64(", + &tmp2, ", ", &tmp2, ", 4);\n"); + OUT(c, locp, "tcg_gen_or_i64(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp1, ", ", &res, ", 0xff00ff00ff00ff00);\n"); + OUT(c, locp, "tcg_gen_shri_i64(", + &tmp1, ", ", &tmp1, ", 8);\n"); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp2, ", ", &res, ", 0x00ff00ff00ff00ff);\n"); + OUT(c, locp, "tcg_gen_shli_i64(", + &tmp2, ", ", &tmp2, ", 8);\n"); + OUT(c, locp, "tcg_gen_or_i64(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp1, ", ", &res, ", 0xffff0000ffff0000);\n"); + OUT(c, locp, "tcg_gen_shri_i64(", + &tmp1, ", ", &tmp1, ", 16);\n"); + OUT(c, locp, "tcg_gen_andi_i64(", + &tmp2, ", ", &res, ", 0x0000ffff0000ffff);\n"); + OUT(c, locp, "tcg_gen_shli_i64(", + &tmp2, ", ", &tmp2, ", 16);\n"); + OUT(c, locp, "tcg_gen_or_i64(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"); + OUT(c, locp, "tcg_gen_shri_i64(", &tmp1, ", ", &res, ", 32);\n"); + OUT(c, locp, "tcg_gen_shli_i64(", &tmp2, ", ", &res, ", 32);\n"); + OUT(c, locp, "tcg_gen_or_i64(", &res, ", ", &tmp1, ", ", &tmp2, ");\n"); + + rvalue_free(c, locp, &tmp1); + rvalue_free(c, locp, &tmp2); + rvalue_free(c, locp, &source_m); + + return res; +} + +HexValue gen_rotl(Context *c, YYLTYPE *locp, HexValue *source, HexValue *n) +{ + HexValue amount = *n; + amount = rvalue_materialize(c, locp, &amount); + const char *suffix = source->bit_width == 64 ? "i64" : "i32"; + + HexValue res = gen_tmp(c, locp, source->bit_width); + res.is_unsigned = source->is_unsigned; + OUT(c, locp, "tcg_gen_rotl_", suffix, "(", + &res, ", ", source, ", ", &amount, ");\n"); + rvalue_free(c, locp, source); + rvalue_free(c, locp, &amount); + + return res; +} + +const char *INTERLEAVE_MASKS[6] = { + "0x5555555555555555ULL", + "0x3333333333333333ULL", + "0x0f0f0f0f0f0f0f0fULL", + "0x00ff00ff00ff00ffULL", + "0x0000ffff0000ffffULL", + "0x00000000ffffffffULL", +}; + +HexValue gen_deinterleave(Context *c, YYLTYPE *locp, HexValue *mixed) +{ + HexValue src = rvalue_extend(c, locp, mixed); + + HexValue a = gen_tmp(c, locp, 64); + a.is_unsigned = true; + HexValue b = gen_tmp(c, locp, 64); + b.is_unsigned = true; + + const char **masks = INTERLEAVE_MASKS; + + OUT(c, locp, "tcg_gen_shri_i64(", &a, ", ", &src, ", 1);\n"); + OUT(c, locp, "tcg_gen_andi_i64(", &a, ", ", &a, ", ", masks[0], ");\n"); + OUT(c, locp, "tcg_gen_andi_i64(", &b, ", ", &src, ", ", masks[0], ");\n"); + + HexValue res = gen_tmp(c, locp, 64); + res.is_unsigned = true; + + unsigned shift = 1; + for (unsigned i = 1; i < 6; ++i) { + OUT(c, locp, "tcg_gen_shri_i64(", &res, ", ", &b, ", ", &shift, ");\n"); + OUT(c, locp, "tcg_gen_or_i64(", &b, ", ", &res, ", ", &b, ");\n"); + OUT(c, locp, "tcg_gen_andi_i64(", &b, ", ", &b, ", ", masks[i], ");\n"); + OUT(c, locp, "tcg_gen_shri_i64(", &res, ", ", &a, ", ", &shift, ");\n"); + OUT(c, locp, "tcg_gen_or_i64(", &a, ", ", &res, ", ", &a, ");\n"); + OUT(c, locp, "tcg_gen_andi_i64(", &a, ", ", &a, ", ", masks[i], ");\n"); + shift <<= 1; + } + + OUT(c, locp, "tcg_gen_shli_i64(", &a, ", ", &a, ", 32);\n"); + OUT(c, locp, "tcg_gen_or_i64(", &res, ", ", &a, ", ", &b, ");\n"); + + rvalue_free(c, locp, &a); + rvalue_free(c, locp, &b); + + return res; +} + +HexValue gen_interleave(Context *c, + YYLTYPE *locp, + HexValue *odd, + HexValue *even) +{ + HexValue a = rvalue_truncate(c, locp, odd); + a.is_unsigned = true; + HexValue b = rvalue_truncate(c, locp, even); + a.is_unsigned = true; + + a = rvalue_extend(c, locp, &a); + b = rvalue_extend(c, locp, &b); + + HexValue res = gen_tmp(c, locp, 64); + res.is_unsigned = true; + + const char **masks = INTERLEAVE_MASKS; + + unsigned shift = 16; + for (int i = 4; i >= 0; --i) { + OUT(c, locp, "tcg_gen_shli_i64(", &res, ", ", &a, ", ", &shift, ");\n"); + OUT(c, locp, "tcg_gen_or_i64(", &a, ", ", &res, ", ", &a, ");\n"); + OUT(c, locp, "tcg_gen_andi_i64(", &a, ", ", &a, ", ", masks[i], ");\n"); + OUT(c, locp, "tcg_gen_shli_i64(", &res, ", ", &b, ", ", &shift, ");\n"); + OUT(c, locp, "tcg_gen_or_i64(", &b, ", ", &res, ", ", &b, ");\n"); + OUT(c, locp, "tcg_gen_andi_i64(", &b, ", ", &b, ", ", masks[i], ");\n"); + shift >>= 1; + } + + OUT(c, locp, "tcg_gen_shli_i64(", &a, ", ", &a, ", 1);\n"); + OUT(c, locp, "tcg_gen_or_i64(", &res, ", ", &a, ", ", &b, ");\n"); + + rvalue_free(c, locp, &a); + rvalue_free(c, locp, &b); + + return res; +} + +HexValue gen_carry_from_add(Context *c, + YYLTYPE *locp, + HexValue *op1, + HexValue *op2, + HexValue *op3) +{ + HexValue opa = rvalue_materialize(c, locp, op1); + HexValue opb = rvalue_materialize(c, locp, op2); + HexValue opc = rvalue_materialize(c, locp, op3); + opc = rvalue_extend(c, locp, &opc); + + HexValue zero = gen_tmp_value(c, locp, "0", 64); + HexValue res = gen_tmp(c, locp, 64); + HexValue cf = gen_tmp(c, locp, 64); + OUT(c, locp, "tcg_gen_add2_i64(", &res, ", ", &cf, ", ", &opa, ", ", &zero); + OUT(c, locp, ", ", &opc, ", ", &zero, ");\n"); + OUT(c, locp, "tcg_gen_add2_i64(", &res, ", ", &cf, ", ", &res, ", ", &cf); + OUT(c, locp, ", ", &opb, ", ", &zero, ");\n"); + + rvalue_free(c, locp, &opa); + rvalue_free(c, locp, &opb); + rvalue_free(c, locp, &opc); + rvalue_free(c, locp, &zero); + rvalue_free(c, locp, &res); + return cf; +} + +void gen_inst(Context *c, GString *iname) +{ + c->total_insn++; + c->inst.name = iname; + c->inst.allocated = g_array_new(FALSE, FALSE, sizeof(Var)); + c->inst.init_list = g_array_new(FALSE, FALSE, sizeof(HexValue)); + c->inst.strings = g_array_new(FALSE, FALSE, sizeof(GString *)); + EMIT_SIG(c, "void emit_%s(DisasContext *ctx, Insn *insn, Packet *pkt", + c->inst.name->str); +} + +void gen_inst_args(Context *c, YYLTYPE *locp) +{ + EMIT_SIG(c, ")"); + EMIT_HEAD(c, "{\n"); + + /* Initialize declared but uninitialized registers, but only for */ + /* non-conditional instructions */ + for (int i = 0; i < c->inst.init_list->len; i++) { + HexValue *reg = &g_array_index(c->inst.init_list, HexValue, i); + if (reg->type == REGISTER || reg->type == PREDICATE) { + OUT(c, locp, "tcg_gen_movi_i", ®->bit_width, "(", + reg, ", 0);\n"); + } + } +} + +void gen_inst_code(Context *c, YYLTYPE *locp) +{ + if (c->inst.error_count != 0) { + fprintf(stderr, + "Parsing of instruction %s generated %d errors!\n", + c->inst.name->str, + c->inst.error_count); + } else { + free_variables(c, locp); + c->implemented_insn++; + fprintf(c->enabled_file, "%s\n", c->inst.name->str); + emit_footer(c); + commit(c); + } + free_instruction(c); +} + +void gen_pre_assign(Context *c, YYLTYPE *locp, HexValue *lp, HexValue *rp) +{ + bool is_direct = is_direct_predicate(lp); + char pre_id[2] = " "; + pre_id[0] = lp->pre.id; + /* Extract predicate TCGv */ + if (is_direct) { + *lp = gen_tmp_value(c, locp, "0", 32); + } + HexValue r = rvalue_materialize(c, locp, rp); + r = rvalue_truncate(c, locp, &r); + /* Extract first 8 bits, and store new predicate value */ + if (is_inside_ternary(c)) { + yyassert(c, locp, !is_direct, "direct pre assign inside ternary op"); + HexValue tmp = gen_tmp(c, locp, r.bit_width); + HexValue cond = get_ternary_cond(c, locp); + HexValue zero = gen_tmp_value(c, locp, "0", r.bit_width); + OUT(c, locp, "tcg_gen_mov_i32(", &tmp, ", ", &r, ");\n"); + OUT(c, locp, "tcg_gen_andi_i32(", &tmp, ", ", &tmp, ", 0xff);\n"); + OUT(c, locp, "tcg_gen_movcond_i", &r.bit_width); + OUT(c, locp, "(TCG_COND_NE, ", lp, ", ", &cond, ", ", &zero); + OUT(c, locp, ", ", &tmp, ", ", lp, ");\n"); + rvalue_free(c, locp, &tmp); + rvalue_free(c, locp, &cond); + rvalue_free(c, locp, &zero); + } else { + OUT(c, locp, "tcg_gen_mov_i32(", lp, ", ", &r, ");\n"); + OUT(c, locp, "tcg_gen_andi_i32(", lp, ", ", lp, ", 0xff);\n"); + } + if (is_direct) { + OUT(c, locp, "gen_log_pred_write(", pre_id, ", ", lp, ");\n"); + OUT(c, locp, "ctx_log_pred_write(ctx, ", pre_id, ");\n"); + rvalue_free(c, locp, lp); + } + rvalue_free(c, locp, &r); /* Free temporary value */ +} + +void gen_load(Context *c, YYLTYPE *locp, HexValue *num, HexValue *size, + bool is_unsigned, HexValue *ea, HexValue *dst) +{ + /* Memop width is specified in the load macro */ + int bit_width = (size->imm.value > 4) ? 64 : 32; + const char *sign_suffix = (size->imm.value > 4) + ? "" + : ((is_unsigned) ? "u" : "s"); + char size_suffix[4] = { 0 }; + /* Create temporary variable (if not present) */ + if (dst->type == VARID) { + /* TODO: this is a common pattern, the parser should be varid-aware. */ + varid_allocate(c, locp, dst, bit_width, is_unsigned); + } + snprintf(size_suffix, 4, "%" PRIu64, size->imm.value * 8); + if (bit_width == 32) { + *dst = rvalue_truncate(c, locp, dst); + } else { + *dst = rvalue_extend(c, locp, dst); + } + int var_id = find_variable(c, locp, ea); + yyassert(c, locp, var_id != -1, "Load variable must exist!\n"); + /* We need to enforce the variable size */ + ea->bit_width = g_array_index(c->inst.allocated, Var, var_id).bit_width; + if (ea->bit_width != 32) { + *ea = rvalue_truncate(c, locp, ea); + } + OUT(c, locp, "if (insn->slot == 0 && pkt->pkt_has_store_s1) {\n"); + OUT(c, locp, "process_store(ctx, pkt, 1);\n"); + OUT(c, locp, "}\n"); + OUT(c, locp, "tcg_gen_qemu_ld", size_suffix, sign_suffix); + OUT(c, locp, "(", dst, ", ", ea, ", 0);\n"); + /* If the var in EA was truncated it is now a tmp HexValue, so free it. */ + rvalue_free(c, locp, ea); +} + +void gen_store(Context *c, YYLTYPE *locp, HexValue *num, HexValue *size, + HexValue *ea, HexValue *src) +{ + /* Memop width is specified in the store macro */ + int mem_width = size->imm.value; + /* Adjust operand bit width to memop bit width */ + if (mem_width < 8) { + *src = rvalue_truncate(c, locp, src); + } else { + *src = rvalue_extend(c, locp, src); + } + assert(ea->type == VARID); + int var_id = find_variable(c, locp, ea); + yyassert(c, locp, var_id != -1, "Load variable must exist!\n"); + /* We need to enforce the variable size */ + ea->bit_width = g_array_index(c->inst.allocated, Var, var_id).bit_width; + if (ea->bit_width != 32) { + *ea = rvalue_truncate(c, locp, ea); + } + *src = rvalue_materialize(c, locp, src); + OUT(c, locp, "gen_store", &mem_width, "(cpu_env, ", ea, ", ", src); + OUT(c, locp, ", ctx, insn->slot);\n"); + rvalue_free(c, locp, src); + /* If the var in ea was truncated it is now a tmp HexValue, so free it. */ + rvalue_free(c, locp, ea); +} + +void gen_sethalf(Context *c, YYLTYPE *locp, HexCast *sh, HexValue *n, + HexValue *dst, HexValue *val) +{ + yyassert(c, locp, n->type == IMMEDIATE, + "Deposit index must be immediate!\n"); + if (dst->type == VARID) { + int var_id = find_variable(c, locp, dst); + if (var_id == -1) { + HexValue zero = gen_imm_value(c, locp, 0, 64); + zero.is_unsigned = true; + dst->bit_width = 64; + gen_assign(c, locp, dst, &zero); + } else { + /* We need to enforce the variable size (default is 32) */ + dst->bit_width = g_array_index(c->inst.allocated, + Var, + var_id).bit_width; + } + } + gen_deposit_op(c, locp, dst, val, n, sh); +} + +void gen_setbits(Context *c, YYLTYPE *locp, HexValue *hi, HexValue *lo, + HexValue *dst, HexValue *val) +{ + yyassert(c, locp, hi->type == IMMEDIATE && + hi->imm.type == VALUE && + lo->type == IMMEDIATE && + lo->imm.type == VALUE, + "Range deposit needs immediate values!\n"); + + *val = rvalue_truncate(c, locp, val); + unsigned len = hi->imm.value + 1 - lo->imm.value; + HexValue tmp = gen_tmp(c, locp, 32); + OUT(c, locp, "tcg_gen_neg_i32(", &tmp, ", ", val, ");\n"); + OUT(c, locp, "tcg_gen_deposit_i32(", dst, ", ", dst, ", ", &tmp, ", "); + OUT(c, locp, lo, ", ", &len, ");\n"); + + rvalue_free(c, locp, &tmp); + rvalue_free(c, locp, hi); + rvalue_free(c, locp, lo); + rvalue_free(c, locp, val); +} + +int gen_if_cond(Context *c, YYLTYPE *locp, HexValue *cond) +{ + /* Generate an end label, if false branch to that label */ + OUT(c, locp, "TCGLabel *if_label_", &c->inst.if_count, + " = gen_new_label();\n"); + *cond = rvalue_materialize(c, locp, cond); + const char *bit_suffix = (cond->bit_width == 64) ? "i64" : "i32"; + OUT(c, locp, "tcg_gen_brcondi_", bit_suffix, "(TCG_COND_EQ, ", cond, + ", 0, if_label_", &c->inst.if_count, ");\n"); + rvalue_free(c, locp, cond); + return c->inst.if_count++; +} + +int gen_if_else(Context *c, YYLTYPE *locp, int index) +{ + /* Generate label to jump if else is not verified */ + OUT(c, locp, "TCGLabel *if_label_", &c->inst.if_count, + " = gen_new_label();\n"); + int if_index = c->inst.if_count; + c->inst.if_count++; + /* Jump out of the else statement */ + OUT(c, locp, "tcg_gen_br(if_label_", &if_index, ");\n"); + /* Fix the else label */ + OUT(c, locp, "gen_set_label(if_label_", &index, ");\n"); + return if_index; +} + +HexValue gen_rvalue_pre(Context *c, YYLTYPE *locp, HexValue *pre) +{ + if (is_direct_predicate(pre)) { + bool is_dotnew = pre->is_dotnew; + char predicate_id[2] = { pre->pre.id, '\0' }; + char *pre_str = (char *) &predicate_id; + *pre = gen_tmp_value(c, locp, "0", 32); + if (is_dotnew) { + OUT(c, locp, "tcg_gen_mov_i32(", pre, ", hex_new_pred_value["); + OUT(c, locp, pre_str, "]);\n"); + } else { + OUT(c, locp, "gen_read_preg(", pre, ", ", pre_str, ");\n"); + } + } + return *pre; +} + +HexValue gen_rvalue_var(Context *c, YYLTYPE *locp, HexValue *var) +{ + /* Assign correct bit width and signedness */ + bool found = false; + for (int i = 0; i < c->inst.allocated->len; i++) { + Var *other = &g_array_index(c->inst.allocated, Var, i); + if (g_string_equal(var->var.name, other->name)) { + found = true; + other->name = var->var.name; + var->bit_width = other->bit_width; + var->is_unsigned = other->is_unsigned; + break; + } + } + yyassert(c, locp, found, "Undefined symbol!\n"); + return *var; +} + +HexValue gen_rvalue_mpy(Context *c, YYLTYPE *locp, HexMpy *mpy, HexValue *a, + HexValue *b) +{ + a->is_unsigned = mpy->first_unsigned; + b->is_unsigned = mpy->second_unsigned; + *a = gen_cast_op(c, locp, a, mpy->first_bit_width * 2); + /* Handle fMPTY3216.. */ + if (mpy->first_bit_width == 32) { + *b = gen_cast_op(c, locp, b, 64); + } else { + *b = gen_cast_op(c, locp, b, mpy->second_bit_width * 2); + } + HexValue ret = gen_bin_op(c, locp, MUL_OP, a, b); + /* Handle special cases required by the language */ + if (mpy->first_bit_width == 16 && mpy->second_bit_width == 16) { + HexValue src_width = gen_imm_value(c, locp, 32, 32); + HexValue dst_width = gen_imm_value(c, locp, 64, 32); + ret = gen_extend_op(c, locp, &src_width, &dst_width, &ret, + mpy->first_unsigned && mpy->second_unsigned); + } + return ret; +} + +HexValue gen_rvalue_pow(Context *c, YYLTYPE *locp, HexValue *l, HexValue *r) +{ + /* We assume that this is a shorthand for a shift */ + yyassert(c, locp, l->type == IMMEDIATE && r->imm.value == 2, + "Exponentiation is not a left shift!\n"); + HexValue one = gen_imm_value(c, locp, 1, 32); + HexValue shift = gen_bin_op(c, locp, SUB_OP, r, &one); + HexValue res = gen_bin_op(c, locp, ASL_OP, l, &shift); + rvalue_free(c, locp, &one); + rvalue_free(c, locp, &shift); + return res; +} + +HexValue gen_rvalue_not(Context *c, YYLTYPE *locp, HexValue *v) +{ + const char *bit_suffix = (v->bit_width == 64) ? "i64" : "i32"; + int bit_width = (v->bit_width == 64) ? 64 : 32; + HexValue res; + res.is_unsigned = v->is_unsigned; + res.is_dotnew = false; + res.is_manual = false; + if (v->type == IMMEDIATE) { + res.type = IMMEDIATE; + res.imm.type = QEMU_TMP; + res.imm.index = c->inst.qemu_tmp_count; + OUT(c, locp, "int", &bit_width, "_t ", &res, " = ~", v, ";\n"); + c->inst.qemu_tmp_count++; + } else { + res = gen_tmp(c, locp, bit_width); + OUT(c, locp, "tcg_gen_not_", bit_suffix, "(", &res, + ", ", v, ");\n"); + rvalue_free(c, locp, v); + } + return res; +} + +HexValue gen_rvalue_notl(Context *c, YYLTYPE *locp, HexValue *v) +{ + const char *bit_suffix = (v->bit_width == 64) ? "i64" : "i32"; + int bit_width = (v->bit_width == 64) ? 64 : 32; + HexValue res; + res.is_unsigned = v->is_unsigned; + res.is_dotnew = false; + res.is_manual = false; + if (v->type == IMMEDIATE) { + res.type = IMMEDIATE; + res.imm.type = QEMU_TMP; + res.imm.index = c->inst.qemu_tmp_count; + OUT(c, locp, "int", &bit_width, "_t ", &res, " = !", v, ";\n"); + c->inst.qemu_tmp_count++; + } else { + res = gen_tmp(c, locp, bit_width); + HexValue zero = gen_tmp_value(c, locp, "0", bit_width); + HexValue one = gen_tmp_value(c, locp, "0xff", bit_width); + OUT(c, locp, "tcg_gen_movcond_", bit_suffix); + OUT(c, locp, "(TCG_COND_EQ, ", &res, ", ", v, ", ", &zero); + OUT(c, locp, ", ", &one, ", ", &zero, ");\n"); + rvalue_free(c, locp, v); + rvalue_free(c, locp, &zero); + rvalue_free(c, locp, &one); + } + return res; +} + +void gen_set_overflow(Context *c, YYLTYPE *locp, HexValue *vp) +{ + HexValue v = *vp; + + HexValue ovfl = gen_tmp(c, locp, 32); + ovfl.is_unsigned = true; + OUT(c, locp, "GET_USR_FIELD(USR_OVF, ", &ovfl, ");\n"); + + if (is_inside_ternary(c)) { + /* Inside ternary operator, need to take care of the side-effect */ + HexValue cond = get_ternary_cond(c, locp); + v = rvalue_materialize(c, locp, &v); + bool is_64bit = cond.bit_width == 64; + unsigned bit_width = cond.bit_width; + if (is_64bit) { + ovfl = rvalue_extend(c, locp, &ovfl); + v = rvalue_extend(c, locp, &v); + } + HexValue tmp = gen_tmp_value(c, locp, "0", cond.bit_width); + OUT(c, locp, "tcg_gen_movcond_i", &bit_width, + "(TCG_COND_NE, ", &tmp, ", ", &cond); + OUT(c, locp, ", ", &tmp, ", ", &v, ", ", &tmp, ");\n"); + OUT(c, locp, "tcg_gen_or_i", &bit_width, "(", + &ovfl, ", ", &ovfl, ", ", &tmp, ");\n"); + if (is_64bit) { + ovfl = rvalue_truncate(c, locp, &ovfl); + } + rvalue_free(c, locp, &tmp); + rvalue_free(c, locp, &cond); + } else { + if (v.type == IMMEDIATE) { + OUT(c, locp, "tcg_gen_ori_i32(", + &ovfl, ", ", &ovfl, ", ", &v, ");\n"); + } else { + OUT(c, locp, "tcg_gen_or_i32(", + &ovfl, ", ", &ovfl, ", ", &v, ");\n"); + } + } + + OUT(c, locp, "SET_USR_FIELD(USR_OVF, ", &ovfl, ");\n"); + + rvalue_free(c, locp, &ovfl); + rvalue_free(c, locp, &v); +} + +HexValue gen_rvalue_sat(Context *c, YYLTYPE *locp, HexSat *sat, HexValue *n, + HexValue *v) +{ + if (sat->set_overflow) { + yyassert(c, locp, n->imm.value < v->bit_width, "To compute overflow, " + "source width must be greater than saturation width!"); + } + HexValue res = gen_tmp(c, locp, v->bit_width); + const char *bit_suffix = (v->bit_width == 64) ? "i64" : "i32"; + const char *unsigned_str = (sat->is_unsigned) ? "u" : ""; + if (sat->set_overflow) { + HexValue ovfl = gen_tmp(c, locp, 32); + OUT(c, locp, "gen_sat", unsigned_str, "_", bit_suffix, "_ext("); + OUT(c, locp, &ovfl, ", ", &res, ", ", v, ", ", &n->imm.value, ");\n"); + gen_set_overflow(c, locp, &ovfl); + } else { + OUT(c, locp, "gen_sat", unsigned_str, "_", bit_suffix, "(", &res, ", "); + OUT(c, locp, v, ", ", &n->imm.value, ");\n"); + } + res.is_unsigned = sat->is_unsigned; + rvalue_free(c, locp, v); + return res; +} + +HexValue gen_rvalue_fscr(Context *c, YYLTYPE *locp, HexValue *v) +{ + HexValue key = gen_tmp(c, locp, 64); + HexValue res = gen_tmp(c, locp, 64); + *v = rvalue_extend(c, locp, v); + HexValue frame_key = gen_tmp(c, locp, 32); + OUT(c, locp, "READ_REG(", &frame_key, ", HEX_REG_FRAMEKEY);\n"); + OUT(c, locp, "tcg_gen_concat_i32_i64(", + &key, ", ", &frame_key, ", ", &frame_key, ");\n"); + OUT(c, locp, "tcg_gen_xor_i64(", &res, ", ", v, ", ", &key, ");\n"); + rvalue_free(c, locp, &key); + rvalue_free(c, locp, &frame_key); + rvalue_free(c, locp, v); + return res; +} + +HexValue gen_rvalue_abs(Context *c, YYLTYPE *locp, HexValue *v) +{ + const char *bit_suffix = (v->bit_width == 64) ? "i64" : "i32"; + int bit_width = (v->bit_width == 64) ? 64 : 32; + HexValue res; + res.is_unsigned = v->is_unsigned; + res.is_dotnew = false; + res.is_manual = false; + if (v->type == IMMEDIATE) { + res.type = IMMEDIATE; + res.imm.type = QEMU_TMP; + res.imm.index = c->inst.qemu_tmp_count; + OUT(c, locp, "int", &bit_width, "_t ", &res, " = abs(", v, ");\n"); + c->inst.qemu_tmp_count++; + } else { + res = gen_tmp(c, locp, bit_width); + HexValue zero = gen_tmp_value(c, locp, "0", bit_width); + OUT(c, locp, "tcg_gen_neg_", bit_suffix, "(", &res, ", ", v, ");\n"); + OUT(c, locp, "tcg_gen_movcond_i", &bit_width); + OUT(c, locp, "(TCG_COND_GT, ", &res, ", ", v, ", ", &zero); + OUT(c, locp, ", ", v, ", ", &res, ");\n"); + rvalue_free(c, locp, &zero); + rvalue_free(c, locp, v); + } + return res; +} + +HexValue gen_rvalue_neg(Context *c, YYLTYPE *locp, HexValue *v) +{ + const char *bit_suffix = (v->bit_width == 64) ? "i64" : "i32"; + int bit_width = (v->bit_width == 64) ? 64 : 32; + HexValue res; + res.is_unsigned = v->is_unsigned; + res.is_dotnew = false; + res.is_manual = false; + if (v->type == IMMEDIATE) { + res.type = IMMEDIATE; + res.imm.type = QEMU_TMP; + res.imm.index = c->inst.qemu_tmp_count; + OUT(c, locp, "int", &bit_width, "_t ", &res, " = -", v, ";\n"); + c->inst.qemu_tmp_count++; + } else { + res = gen_tmp(c, locp, bit_width); + OUT(c, locp, "tcg_gen_neg_", bit_suffix, "(", &res, ", ", v, ");\n"); + rvalue_free(c, locp, v); + } + return res; +} + +HexValue gen_rvalue_brev(Context *c, YYLTYPE *locp, HexValue *v) +{ + yyassert(c, locp, v->bit_width <= 32, + "fbrev not implemented for 64-bit integers!"); + HexValue res = gen_tmp(c, locp, v->bit_width); + *v = rvalue_materialize(c, locp, v); + OUT(c, locp, "gen_fbrev(", &res, ", ", v, ");\n"); + rvalue_free(c, locp, v); + return res; +} + +HexValue gen_rvalue_ternary(Context *c, YYLTYPE *locp, HexValue *cond, + HexValue *t, HexValue *e) { + bool is_64bit = (t->bit_width == 64) || (e->bit_width == 64); + int bit_width = (is_64bit) ? 64 : 32; + if (is_64bit) { + *cond = rvalue_extend(c, locp, cond); + *t = rvalue_extend(c, locp, t); + *e = rvalue_extend(c, locp, e); + } else { + *cond = rvalue_truncate(c, locp, cond); + } + *cond = rvalue_materialize(c, locp, cond); + *t = rvalue_materialize(c, locp, t); + *e = rvalue_materialize(c, locp, e); + HexValue res = gen_tmp(c, locp, bit_width); + HexValue zero = gen_tmp_value(c, locp, "0", bit_width); + + OUT(c, locp, "tcg_gen_movcond_i", &bit_width); + OUT(c, locp, "(TCG_COND_NE, ", &res, ", ", cond, ", ", &zero); + OUT(c, locp, ", ", t, ", ", e, ");\n"); + + assert(c->ternary->len > 0); + Ternary *ternary = &g_array_index(c->ternary, Ternary, c->ternary->len - 1); + rvalue_free_manual(c, locp, &ternary->cond); + g_array_remove_index(c->ternary, c->ternary->len - 1); + + rvalue_free(c, locp, &zero); + rvalue_free(c, locp, cond); + rvalue_free(c, locp, t); + rvalue_free(c, locp, e); + return res; +} + +const char *cond_to_str(TCGCond cond) +{ + switch (cond) { + case TCG_COND_NEVER: + return "TCG_COND_NEVER"; + case TCG_COND_ALWAYS: + return "TCG_COND_ALWAYS"; + case TCG_COND_EQ: + return "TCG_COND_EQ"; + case TCG_COND_NE: + return "TCG_COND_NE"; + case TCG_COND_LT: + return "TCG_COND_LT"; + case TCG_COND_GE: + return "TCG_COND_GE"; + case TCG_COND_LE: + return "TCG_COND_LE"; + case TCG_COND_GT: + return "TCG_COND_GT"; + case TCG_COND_LTU: + return "TCG_COND_LTU"; + case TCG_COND_GEU: + return "TCG_COND_GEU"; + case TCG_COND_LEU: + return "TCG_COND_LEU"; + case TCG_COND_GTU: + return "TCG_COND_GTU"; + default: + abort(); + } +} + +void emit_arg(Context *c, YYLTYPE *locp, HexValue *arg) +{ + switch (arg->type) { + case REGISTER: + if (arg->reg.type == DOTNEW) { + EMIT_SIG(c, ", TCGv N%cN", arg->reg.id); + } else { + bool is64 = (arg->bit_width == 64); + const char *type = is64 ? "TCGv_i64" : "TCGv_i32"; + char reg_id[5] = { 0 }; + reg_compose(c, locp, &(arg->reg), reg_id); + EMIT_SIG(c, ", %s %s", type, reg_id); + /* MuV register requires also MuN to provide its index */ + if (arg->reg.type == MODIFIER) { + EMIT_SIG(c, ", int MuN"); + } + } + break; + case PREDICATE: + { + char suffix = arg->is_dotnew ? 'N' : 'V'; + EMIT_SIG(c, ", TCGv P%c%c", arg->pre.id, suffix); + } + break; + default: + { + fprintf(stderr, "emit_arg got unsupported argument!"); + abort(); + } + } +} + +void emit_footer(Context *c) +{ + EMIT(c, "}\n"); + EMIT(c, "\n"); +} + +void track_string(Context *c, GString *s) +{ + g_array_append_val(c->inst.strings, s); +} + +void free_variables(Context *c, YYLTYPE *locp) +{ + for (unsigned i = 0; i < c->inst.allocated->len; ++i) { + Var *var = &g_array_index(c->inst.allocated, Var, i); + const char *suffix = var->bit_width == 64 ? "i64" : "i32"; + OUT(c, locp, "tcg_temp_free_", suffix, "(", var->name->str, ");\n"); + } +} + +void free_instruction(Context *c) +{ + assert(c->ternary->len == 0); + /* Free the strings */ + g_string_truncate(c->signature_str, 0); + g_string_truncate(c->out_str, 0); + g_string_truncate(c->header_str, 0); + /* Free strings allocated by the instruction */ + for (int i = 0; i < c->inst.strings->len; i++) { + g_string_free(g_array_index(c->inst.strings, GString*, i), TRUE); + } + g_array_free(c->inst.strings, TRUE); + /* Free INAME token value */ + g_string_free(c->inst.name, TRUE); + /* Free variables and registers */ + g_array_free(c->inst.allocated, TRUE); + g_array_free(c->inst.init_list, TRUE); + /* Initialize instruction-specific portion of the context */ + memset(&(c->inst), 0, sizeof(Inst)); +} diff --git a/target/hexagon/idef-parser/parser-helpers.h b/target/hexagon/idef-parser/parser-helpers.h new file mode 100644 index 0000000000..fec3ad7819 --- /dev/null +++ b/target/hexagon/idef-parser/parser-helpers.h @@ -0,0 +1,347 @@ +/* + * Copyright(c) 2019-2021 rev.ng Srls. All Rights Reserved. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef PARSER_HELPERS_H +#define PARSER_HELPERS_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "qemu/compiler.h" +#include "tcg/tcg-cond.h" + +#include "idef-parser.tab.h" +#include "idef-parser.yy.h" +#include "idef-parser.h" + +/* Decomment this to disable yyasserts */ +/* #define NDEBUG */ + +#define ERR_LINE_CONTEXT 40 + +#define START_COMMENT "/" "*" +#define END_COMMENT "*" "/" + +void yyerror(YYLTYPE *locp, + yyscan_t scanner __attribute__((unused)), + Context *c, + const char *s); + +#ifndef NDEBUG +#define yyassert(context, locp, condition, msg) \ + if (!(condition)) { \ + yyerror(locp, (context)->scanner, (context), (msg)); \ + } +#endif + +bool is_direct_predicate(HexValue *value); + +/* Print functions */ +void str_print(Context *c, YYLTYPE *locp, const char *string); + +void uint64_print(Context *c, YYLTYPE *locp, uint64_t *num); + +void int_print(Context *c, YYLTYPE *locp, int *num); + +void uint_print(Context *c, YYLTYPE *locp, unsigned *num); + +void tmp_print(Context *c, YYLTYPE *locp, HexTmp *tmp); + +void pre_print(Context *c, YYLTYPE *locp, HexPre *pre, bool is_dotnew); + +void reg_compose(Context *c, YYLTYPE *locp, HexReg *reg, char reg_id[5]); + +void reg_print(Context *c, YYLTYPE *locp, HexReg *reg); + +void imm_print(Context *c, YYLTYPE *locp, HexImm *imm); + +void var_print(Context *c, YYLTYPE *locp, HexVar *var); + +void rvalue_out(Context *c, YYLTYPE *locp, void *pointer); + +void out_assert(Context *c, YYLTYPE *locp, void *dummy); + +/* Copy output code buffer into stdout */ +void commit(Context *c); + +#define OUT_IMPL(c, locp, x) \ + QEMU_GENERIC(typeof(*x), \ + (char, str_print), \ + (uint64_t, uint64_print), \ + (int, int_print), \ + (unsigned, uint_print), \ + (HexValue, rvalue_out), \ + out_assert \ + )(c, locp, x); \ + +/* Make a FOREACH macro */ +#define FE_1(c, locp, WHAT, X) WHAT(c, locp, X) +#define FE_2(c, locp, WHAT, X, ...) \ + WHAT(c, locp, X)FE_1(c, locp, WHAT, __VA_ARGS__) +#define FE_3(c, locp, WHAT, X, ...) \ + WHAT(c, locp, X)FE_2(c, locp, WHAT, __VA_ARGS__) +#define FE_4(c, locp, WHAT, X, ...) \ + WHAT(c, locp, X)FE_3(c, locp, WHAT, __VA_ARGS__) +#define FE_5(c, locp, WHAT, X, ...) \ + WHAT(c, locp, X)FE_4(c, locp, WHAT, __VA_ARGS__) +#define FE_6(c, locp, WHAT, X, ...) \ + WHAT(c, locp, X)FE_5(c, locp, WHAT, __VA_ARGS__) +#define FE_7(c, locp, WHAT, X, ...) \ + WHAT(c, locp, X)FE_6(c, locp, WHAT, __VA_ARGS__) +#define FE_8(c, locp, WHAT, X, ...) \ + WHAT(c, locp, X)FE_7(c, locp, WHAT, __VA_ARGS__) +#define FE_9(c, locp, WHAT, X, ...) \ + WHAT(c, locp, X)FE_8(c, locp, WHAT, __VA_ARGS__) +/* repeat as needed */ + +#define GET_MACRO(_1, _2, _3, _4, _5, _6, _7, _8, _9, NAME, ...) NAME + +#define FOR_EACH(c, locp, action, ...) \ + do { \ + GET_MACRO(__VA_ARGS__, \ + FE_9, \ + FE_8, \ + FE_7, \ + FE_6, \ + FE_5, \ + FE_4, \ + FE_3, \ + FE_2, \ + FE_1)(c, locp, action, \ + __VA_ARGS__) \ + } while (0) + +#define OUT(c, locp, ...) FOR_EACH((c), (locp), OUT_IMPL, __VA_ARGS__) + +const char *cmp_swap(Context *c, YYLTYPE *locp, const char *type); + +/* Temporary values creation */ +HexValue gen_tmp(Context *c, YYLTYPE *locp, int bit_width); + +HexValue gen_tmp_value(Context *c, + YYLTYPE *locp, + const char *value, + int bit_width); + +HexValue gen_imm_value(Context *c __attribute__((unused)), + YYLTYPE *locp, + int value, + int bit_width); + +void rvalue_free(Context *c, YYLTYPE *locp, HexValue *rvalue); + +HexValue rvalue_materialize(Context *c, YYLTYPE *locp, HexValue *rvalue); + +HexValue rvalue_extend(Context *c, YYLTYPE *locp, HexValue *rvalue); + +HexValue rvalue_truncate(Context *c, YYLTYPE *locp, HexValue *rvalue); + +int find_variable(Context *c, YYLTYPE *locp, HexValue *varid); + +void varid_allocate(Context *c, + YYLTYPE *locp, + HexValue *varid, + int width, + bool is_unsigned); + +void ea_free(Context *c, YYLTYPE *locp); + +HexValue gen_bin_cmp(Context *c, + YYLTYPE *locp, + TCGCond type, + HexValue *op1_ptr, + HexValue *op2_ptr); + +/* Code generation functions */ +HexValue gen_bin_op(Context *c, + YYLTYPE *locp, + OpType type, + HexValue *operand1, + HexValue *operand2); + +HexValue gen_cast_op(Context *c, + YYLTYPE *locp, + HexValue *source, + unsigned target_width); + +HexValue gen_extend_op(Context *c, + YYLTYPE *locp, + HexValue *src_width_ptr, + HexValue *dst_width_ptr, + HexValue *value_ptr, + bool is_unsigned); + +void gen_rdeposit_op(Context *c, + YYLTYPE *locp, + HexValue *dest, + HexValue *value, + HexValue *begin, + HexValue *width); + +void gen_deposit_op(Context *c, + YYLTYPE *locp, + HexValue *dest, + HexValue *value, + HexValue *index, + HexCast *cast); + +HexValue gen_rextract_op(Context *c, + YYLTYPE *locp, + HexValue *source, + int begin, + int width); + +HexValue gen_extract_op(Context *c, + YYLTYPE *locp, + HexValue *source, + HexValue *index, + HexExtract *extract); + +HexValue gen_read_creg(Context *c, YYLTYPE *locp, HexValue *reg); + +void gen_write_creg(Context *c, + YYLTYPE *locp, + HexValue *reg, + HexValue *value); + +void gen_assign(Context *c, + YYLTYPE *locp, + HexValue *dest, + HexValue *value); + +HexValue gen_convround(Context *c, + YYLTYPE *locp, + HexValue *source); + +HexValue gen_round(Context *c, + YYLTYPE *locp, + HexValue *source, + HexValue *position); + +HexValue gen_convround_n(Context *c, + YYLTYPE *locp, + HexValue *source_ptr, + HexValue *bit_pos_ptr); + +/* Circular addressing mode with auto-increment */ +void gen_circ_op(Context *c, + YYLTYPE *locp, + HexValue *addr, + HexValue *increment, + HexValue *modifier); + +HexValue gen_locnt_op(Context *c, YYLTYPE *locp, HexValue *source); + +HexValue gen_ctpop_op(Context *c, YYLTYPE *locp, HexValue *source); + +HexValue gen_fbrev_4(Context *c, YYLTYPE *locp, HexValue *source); + +HexValue gen_fbrev_8(Context *c, YYLTYPE *locp, HexValue *source); + +HexValue gen_rotl(Context *c, YYLTYPE *locp, HexValue *source, HexValue *n); + +HexValue gen_deinterleave(Context *c, YYLTYPE *locp, HexValue *mixed); + +HexValue gen_interleave(Context *c, + YYLTYPE *locp, + HexValue *odd, + HexValue *even); + +HexValue gen_carry_from_add(Context *c, + YYLTYPE *locp, + HexValue *op1, + HexValue *op2, + HexValue *op3); + +void gen_inst(Context *c, GString *iname); + +void gen_inst_args(Context *c, YYLTYPE *locp); + +void gen_inst_code(Context *c, YYLTYPE *locp); + +void gen_pre_assign(Context *c, YYLTYPE *locp, HexValue *lp, HexValue *rp); + +void gen_load(Context *c, YYLTYPE *locp, HexValue *num, HexValue *size, + bool is_unsigned, HexValue *ea, HexValue *dst); + +void gen_store(Context *c, YYLTYPE *locp, HexValue *num, HexValue *size, + HexValue *ea, HexValue *src); + +void gen_sethalf(Context *c, YYLTYPE *locp, HexCast *sh, HexValue *n, + HexValue *dst, HexValue *val); + +void gen_setbits(Context *c, YYLTYPE *locp, HexValue *hi, HexValue *lo, + HexValue *dst, HexValue *val); + +int gen_if_cond(Context *c, YYLTYPE *locp, HexValue *cond); + +int gen_if_else(Context *c, YYLTYPE *locp, int index); + +HexValue gen_rvalue_pre(Context *c, YYLTYPE *locp, HexValue *pre); + +HexValue gen_rvalue_var(Context *c, YYLTYPE *locp, HexValue *var); + +HexValue gen_rvalue_mpy(Context *c, YYLTYPE *locp, HexMpy *mpy, HexValue *a, + HexValue *b); + +HexValue gen_rvalue_pow(Context *c, YYLTYPE *locp, HexValue *l, HexValue *r); + +HexValue gen_rvalue_not(Context *c, YYLTYPE *locp, HexValue *v); + +HexValue gen_rvalue_notl(Context *c, YYLTYPE *locp, HexValue *v); + +HexValue gen_rvalue_sat(Context *c, YYLTYPE *locp, HexSat *sat, HexValue *n, + HexValue *v); + +HexValue gen_rvalue_ternary(Context *c, YYLTYPE *locp, HexValue *cond, + HexValue *t, HexValue *e); + +HexValue gen_rvalue_fscr(Context *c, YYLTYPE *locp, HexValue *v); + +HexValue gen_rvalue_abs(Context *c, YYLTYPE *locp, HexValue *v); + +HexValue gen_rvalue_neg(Context *c, YYLTYPE *locp, HexValue *v); + +HexValue gen_rvalue_brev(Context *c, YYLTYPE *locp, HexValue *v); + +void gen_set_overflow(Context *c, YYLTYPE *locp, HexValue *vp); + +HexValue gen_rvalue_ternary(Context *c, YYLTYPE *locp, HexValue *cond, + HexValue *t, HexValue *e); + +const char *cond_to_str(TCGCond cond); + +void emit_header(Context *c); + +void emit_arg(Context *c, YYLTYPE *locp, HexValue *arg); + +void emit_footer(Context *c); + +void track_string(Context *c, GString *s); + +void free_variables(Context *c, YYLTYPE *locp); + +void free_instruction(Context *c); + +#endif /* PARSER_HELPERS_h */ diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index 1bdf988269..abd931d636 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -184,7 +184,7 @@ idef_parser_input_generated = custom_target( command: [python, files('gen_idef_parser_funcs.py'), semantics_generated, attribs_def, gen_tcg_h, '@OUTPUT@'], ) -idef_parser_input_generated_prep = custom_target( +preprocessed_idef_parser_input_generated = custom_target( 'idef_parser_input.preprocessed.h.inc', output: 'idef_parser_input.preprocessed.h.inc', input: idef_parser_input_generated, @@ -197,4 +197,28 @@ flex = generator(find_program('flex'), output: ['@BASENAME@.yy.c', '@BASENAME@.yy.h'], arguments: ['-o', '@OUTPUT0@', '--header-file=@OUTPUT1@', '@INPUT@']) +bison = generator(find_program('bison'), + output: ['@BASENAME@.tab.c', '@BASENAME@.tab.h'], + arguments: ['@INPUT@', '--defines=@OUTPUT1@', '--output=@OUTPUT0@']) + +glib_dep = dependency('glib-2.0', native: true) + +idef_parser = executable('idef-parser', + [flex.process(idef_parser_dir / 'idef-parser.lex'), + bison.process(idef_parser_dir / 'idef-parser.y'), + idef_parser_dir / 'parser-helpers.c'], + include_directories: ['idef-parser', '../../include/'], + dependencies: [glib_dep], + native: true) + +idef_generated_tcg = custom_target( + 'idef-generated-tcg', + output: ['idef-generated-emitter.c', + 'idef-generated-emitter.h.inc', + 'idef-generated-enabled-instructions'], + input: preprocessed_idef_parser_input_generated, + depend_files: [hex_common_py], + command: [idef_parser, '@INPUT@', '@OUTPUT0@', '@OUTPUT1@', '@OUTPUT2@'], +) + target_arch += {'hexagon': hexagon_ss} diff --git a/tests/docker/dockerfiles/alpine.docker b/tests/docker/dockerfiles/alpine.docker index 1120e8555d..04a85afe3b 100644 --- a/tests/docker/dockerfiles/alpine.docker +++ b/tests/docker/dockerfiles/alpine.docker @@ -9,6 +9,7 @@ ENV PACKAGES \ alsa-lib-dev \ bash \ binutils \ + bison \ coreutils \ curl-dev \ flex \ diff --git a/tests/docker/dockerfiles/centos7.docker b/tests/docker/dockerfiles/centos7.docker index 95966ea7e6..33c38dc35b 100644 --- a/tests/docker/dockerfiles/centos7.docker +++ b/tests/docker/dockerfiles/centos7.docker @@ -5,6 +5,7 @@ RUN yum -y update # Please keep this list sorted alphabetically ENV PACKAGES \ + bison \ bzip2 \ bzip2-devel \ ccache \ diff --git a/tests/docker/dockerfiles/centos8.docker b/tests/docker/dockerfiles/centos8.docker index 6ea9cf8b5a..4f37198cb6 100644 --- a/tests/docker/dockerfiles/centos8.docker +++ b/tests/docker/dockerfiles/centos8.docker @@ -3,6 +3,7 @@ FROM centos:8.3.2011 RUN dnf -y update ENV PACKAGES \ SDL2-devel \ + bison \ bzip2 \ bzip2-devel \ dbus-daemon \ diff --git a/tests/docker/dockerfiles/debian10.docker b/tests/docker/dockerfiles/debian10.docker index 97ec6d5637..bb04ea9f6e 100644 --- a/tests/docker/dockerfiles/debian10.docker +++ b/tests/docker/dockerfiles/debian10.docker @@ -17,6 +17,7 @@ RUN apt update && \ DEBIAN_FRONTEND=noninteractive apt install -yy eatmydata && \ DEBIAN_FRONTEND=noninteractive eatmydata \ apt install -y --no-install-recommends \ + bison \ bc \ build-essential \ ca-certificates \ @@ -27,6 +28,7 @@ RUN apt update && \ gdb-multiarch \ gettext \ git \ + libglib2.0-dev \ libncurses5-dev \ ninja-build \ pkg-config \ diff --git a/tests/docker/dockerfiles/fedora-i386-cross.docker b/tests/docker/dockerfiles/fedora-i386-cross.docker index 9703b7ec78..ba8165dc0d 100644 --- a/tests/docker/dockerfiles/fedora-i386-cross.docker +++ b/tests/docker/dockerfiles/fedora-i386-cross.docker @@ -1,11 +1,13 @@ FROM fedora:33 ENV PACKAGES \ + bison \ bzip2 \ diffutils \ findutils \ flex \ gcc \ git \ + glib2-devel \ libtasn1-devel.i686 \ libzstd-devel.i686 \ make \ diff --git a/tests/docker/dockerfiles/fedora-win32-cross.docker b/tests/docker/dockerfiles/fedora-win32-cross.docker index 2018dcabe5..98b525258b 100644 --- a/tests/docker/dockerfiles/fedora-win32-cross.docker +++ b/tests/docker/dockerfiles/fedora-win32-cross.docker @@ -2,6 +2,7 @@ FROM fedora:33 # Please keep this list sorted alphabetically ENV PACKAGES \ + bison \ bc \ bzip2 \ diffutils \ @@ -10,6 +11,7 @@ ENV PACKAGES \ gcc \ gettext \ git \ + glib2-devel \ hostname \ make \ meson \ diff --git a/tests/docker/dockerfiles/fedora-win64-cross.docker b/tests/docker/dockerfiles/fedora-win64-cross.docker index b05e4cbcc6..f28cc3d02f 100644 --- a/tests/docker/dockerfiles/fedora-win64-cross.docker +++ b/tests/docker/dockerfiles/fedora-win64-cross.docker @@ -2,6 +2,7 @@ FROM fedora:33 # Please keep this list sorted alphabetically ENV PACKAGES \ + bison \ bc \ bzip2 \ diffutils \ @@ -9,6 +10,7 @@ ENV PACKAGES \ flex \ gcc \ gettext \ + glib2-devel \ git \ hostname \ make \ diff --git a/tests/docker/dockerfiles/fedora.docker b/tests/docker/dockerfiles/fedora.docker index 5d3f49936b..a6714ec2e2 100644 --- a/tests/docker/dockerfiles/fedora.docker +++ b/tests/docker/dockerfiles/fedora.docker @@ -2,6 +2,7 @@ FROM fedora:33 # Please keep this list sorted alphabetically ENV PACKAGES \ + bison \ bc \ brlapi-devel \ bzip2 \ diff --git a/tests/docker/dockerfiles/opensuse-leap.docker b/tests/docker/dockerfiles/opensuse-leap.docker index ce1db959a2..debdb029c1 100644 --- a/tests/docker/dockerfiles/opensuse-leap.docker +++ b/tests/docker/dockerfiles/opensuse-leap.docker @@ -3,6 +3,7 @@ FROM opensuse/leap:15.2 # Please keep this list sorted alphabetically ENV PACKAGES \ bc \ + bison \ brlapi-devel \ bzip2 \ cyrus-sasl-devel \ diff --git a/tests/docker/dockerfiles/ubuntu.docker b/tests/docker/dockerfiles/ubuntu.docker index e2f55eb892..1609af3c4f 100644 --- a/tests/docker/dockerfiles/ubuntu.docker +++ b/tests/docker/dockerfiles/ubuntu.docker @@ -11,6 +11,7 @@ FROM ubuntu:20.04 ENV PACKAGES \ + bison \ ccache \ clang \ dbus \ @@ -30,6 +31,7 @@ ENV PACKAGES \ libepoxy-dev \ libfdt-dev \ libgbm-dev \ + libglib2.0-dev \ libgnutls28-dev \ libgtk-3-dev \ libibverbs-dev \ diff --git a/tests/docker/dockerfiles/ubuntu1804.docker b/tests/docker/dockerfiles/ubuntu1804.docker index 2068118180..18f9261ad5 100644 --- a/tests/docker/dockerfiles/ubuntu1804.docker +++ b/tests/docker/dockerfiles/ubuntu1804.docker @@ -1,5 +1,6 @@ FROM ubuntu:18.04 ENV PACKAGES \ + bison \ ccache \ clang \ flex \ @@ -18,6 +19,7 @@ ENV PACKAGES \ libepoxy-dev \ libfdt-dev \ libgbm-dev \ + libglib2.0-dev \ libgtk-3-dev \ libibverbs-dev \ libiscsi-dev \ diff --git a/tests/docker/dockerfiles/ubuntu2004.docker b/tests/docker/dockerfiles/ubuntu2004.docker index 13d43a7b90..4c01e0cbef 100644 --- a/tests/docker/dockerfiles/ubuntu2004.docker +++ b/tests/docker/dockerfiles/ubuntu2004.docker @@ -1,5 +1,6 @@ FROM ubuntu:20.04 -ENV PACKAGES bison \ +ENV PACKAGES \ + bison \ bsdmainutils \ ccache \ clang-10\ @@ -21,6 +22,7 @@ ENV PACKAGES bison \ libepoxy-dev \ libfdt-dev \ libgbm-dev \ + libglib2.0-dev \ libgtk-3-dev \ libibverbs-dev \ libiscsi-dev \ From patchwork Thu Apr 15 16:34:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alessandro Di Federico X-Patchwork-Id: 12205811 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham 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33rATpvhRNMLH0+9ITbmRCCDH4TPnlYm+IQgtV0QwAxkHHJM3og2mtoQlgkFtrIAVy6k=; To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng, nizzo@rev.ng, philmd@redhat.com, richard.henderson@linaro.org, Alessandro Di Federico Subject: [PATCH v4 11/12] target/hexagon: call idef-parser functions Date: Thu, 15 Apr 2021 18:34:54 +0200 Message-Id: <20210415163455.3839169-12-ale.qemu@rev.ng> In-Reply-To: <20210415163455.3839169-1-ale.qemu@rev.ng> References: <20210415163455.3839169-1-ale.qemu@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico X-Patchwork-Original-From: Alessandro Di Federico via From: Alessandro Di Federico From: Alessandro Di Federico Extend gen_tcg_funcs.py in order to emit calls to the functions emitted by the idef-parser, if available. Signed-off-by: Alessandro Di Federico --- target/hexagon/gen_tcg_funcs.py | 28 ++++++++++++++++++++++++++-- target/hexagon/hex_common.py | 10 ++++++++++ target/hexagon/meson.build | 22 +++++++++++++--------- 3 files changed, 49 insertions(+), 11 deletions(-) diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py index db9f663a77..5980dab8ee 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -394,7 +394,29 @@ def gen_tcg_func(f, tag, regs, imms): if (hex_common.is_read(regid)): genptr_src_read_opn(f,regtype,regid,tag) - if ( hex_common.skip_qemu_helper(tag) ): + if hex_common.is_idef_parser_enabled(tag): + declared = [] + ## Handle registers + for regtype,regid,toss,numregs in regs: + if (hex_common.is_pair(regid) + or (hex_common.is_single(regid) + and hex_common.is_old_val(regtype, regid, tag))): + declared.append("%s%sV" % (regtype, regid)) + if regtype == "M": + declared.append("%s%sN" % (regtype, regid)) + elif hex_common.is_new_val(regtype, regid, tag): + declared.append("%s%sN" % (regtype,regid)) + else: + print("Bad register parse: ",regtype,regid,toss,numregs) + + ## Handle immediates + for immlett,bits,immshift in imms: + declared.append(hex_common.imm_name(immlett)) + + arguments = ", ".join(["ctx", "insn", "pkt"] + declared) + f.write(" emit_%s(%s);\n" % (tag, arguments)) + + elif ( hex_common.skip_qemu_helper(tag) ): f.write(" fGEN_TCG_%s(%s);\n" % (tag, hex_common.semdict[tag])) else: ## Generate the call to the helper @@ -455,12 +477,14 @@ def main(): hex_common.read_attribs_file(sys.argv[2]) hex_common.read_overrides_file(sys.argv[3]) hex_common.calculate_attribs() + hex_common.read_idef_parser_enabled_file(sys.argv[4]) tagregs = hex_common.get_tagregs() tagimms = hex_common.get_tagimms() - with open(sys.argv[4], 'w') as f: + with open(sys.argv[5], 'w') as f: f.write("#ifndef HEXAGON_TCG_FUNCS_H\n") f.write("#define HEXAGON_TCG_FUNCS_H\n\n") + f.write("#include \"idef-generated-emitter.h.inc\"\n\n") for tag in hex_common.tags: ## Skip the priv instructions diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index b3b534057d..648ad29e94 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -28,6 +28,7 @@ attribinfo = {} # Register information and misc tags = [] # list of all tags overrides = {} # tags with helper overrides +idef_parser_enabled = {} # tags enabled for idef-parser # We should do this as a hash for performance, # but to keep order let's keep it as a list. @@ -201,6 +202,9 @@ def need_ea(tag): def skip_qemu_helper(tag): return tag in overrides.keys() +def is_idef_parser_enabled(tag): + return tag in idef_parser_enabled + def imm_name(immlett): return "%siV" % immlett @@ -232,3 +236,9 @@ def read_overrides_file(name): continue tag = overridere.findall(line)[0] overrides[tag] = True + +def read_idef_parser_enabled_file(name): + global idef_parser_enabled + with open(name, "r") as idef_parser_enabled_file: + lines = idef_parser_enabled_file.read().strip().split("\n") + idef_parser_enabled = set(lines) diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index abd931d636..7f30237e59 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -69,15 +69,6 @@ helper_protos_generated = custom_target( ) hexagon_ss.add(helper_protos_generated) -tcg_funcs_generated = custom_target( - 'tcg_funcs_generated.c.inc', - output: 'tcg_funcs_generated.c.inc', - depends: [semantics_generated], - depend_files: [hex_common_py, attribs_def, gen_tcg_h], - command: [python, files('gen_tcg_funcs.py'), semantics_generated, attribs_def, gen_tcg_h, '@OUTPUT@'], -) -hexagon_ss.add(tcg_funcs_generated) - tcg_func_table_generated = custom_target( 'tcg_func_table_generated.c.inc', output: 'tcg_func_table_generated.c.inc', @@ -221,4 +212,17 @@ idef_generated_tcg = custom_target( command: [idef_parser, '@INPUT@', '@OUTPUT0@', '@OUTPUT1@', '@OUTPUT2@'], ) +idef_generated_list = idef_generated_tcg[2].full_path() + +hexagon_ss.add(idef_generated_tcg) + +tcg_funcs_generated = custom_target( + 'tcg_funcs_generated.c.inc', + output: 'tcg_funcs_generated.c.inc', + depends: [semantics_generated, idef_generated_tcg], + depend_files: [hex_common_py, attribs_def, gen_tcg_h], + command: [python, files('gen_tcg_funcs.py'), semantics_generated, attribs_def, gen_tcg_h, idef_generated_list, '@OUTPUT@'], +) +hexagon_ss.add(tcg_funcs_generated) + target_arch += {'hexagon': hexagon_ss} From patchwork Thu Apr 15 16:34:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alessandro Di Federico X-Patchwork-Id: 12205801 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, 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(envelope-from ) id 1lX5JV-00068I-F0 for qemu-devel@archiver.kernel.org; Thu, 15 Apr 2021 12:57:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42146) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lX4xf-0004Ke-Fw for qemu-devel@nongnu.org; Thu, 15 Apr 2021 12:35:27 -0400 Received: from rev.ng ([5.9.113.41]:36245) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lX4xa-0006gO-VD for qemu-devel@nongnu.org; Thu, 15 Apr 2021 12:35:23 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=F3rOoAwEptGDRgqIt9tnoJolggTgyWJSZISJCB7EnDM=; b=QXipnrMVFaAOCchyVNu6iL4A/8 WJIS2+peiFjCizyU6AxrUX3bvHekFFfv904SUm8kOpVrrJp9RWd9CGTdNsWFFr9kYw6ovtexGc2Sy cgs3mGG011FbqlBDWvBiHb2XbRIQgbjkiEOQ7xLNwLI1gfBpI4wHGAUjN6vZQB/VISNs=; To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng, nizzo@rev.ng, philmd@redhat.com, richard.henderson@linaro.org, Alessandro Di Federico Subject: [PATCH v4 12/12] target/hexagon: import additional tests Date: Thu, 15 Apr 2021 18:34:55 +0200 Message-Id: <20210415163455.3839169-13-ale.qemu@rev.ng> In-Reply-To: <20210415163455.3839169-1-ale.qemu@rev.ng> References: <20210415163455.3839169-1-ale.qemu@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico X-Patchwork-Original-From: Alessandro Di Federico via From: Alessandro Di Federico From: Niccolò Izzo Signed-off-by: Alessandro Di Federico Signed-off-by: Niccolò Izzo --- tests/tcg/hexagon/Makefile.target | 36 ++++++++++++++++- tests/tcg/hexagon/crt.S | 28 +++++++++++++ tests/tcg/hexagon/test_abs.S | 20 ++++++++++ tests/tcg/hexagon/test_add.S | 20 ++++++++++ tests/tcg/hexagon/test_andp.S | 23 +++++++++++ tests/tcg/hexagon/test_bitcnt.S | 42 ++++++++++++++++++++ tests/tcg/hexagon/test_bitsplit.S | 25 ++++++++++++ tests/tcg/hexagon/test_call.S | 63 ++++++++++++++++++++++++++++++ tests/tcg/hexagon/test_clobber.S | 35 +++++++++++++++++ tests/tcg/hexagon/test_cmp.S | 34 ++++++++++++++++ tests/tcg/hexagon/test_cmpy.S | 31 +++++++++++++++ tests/tcg/hexagon/test_djump.S | 24 ++++++++++++ tests/tcg/hexagon/test_dotnew.S | 39 ++++++++++++++++++ tests/tcg/hexagon/test_dstore.S | 29 ++++++++++++++ tests/tcg/hexagon/test_ext.S | 18 +++++++++ tests/tcg/hexagon/test_fibonacci.S | 33 ++++++++++++++++ tests/tcg/hexagon/test_hello.S | 21 ++++++++++ tests/tcg/hexagon/test_hl.S | 19 +++++++++ tests/tcg/hexagon/test_hwloops.S | 25 ++++++++++++ tests/tcg/hexagon/test_jmp.S | 25 ++++++++++++ tests/tcg/hexagon/test_lsr.S | 39 ++++++++++++++++++ tests/tcg/hexagon/test_mpyi.S | 20 ++++++++++ tests/tcg/hexagon/test_overflow.S | 63 ++++++++++++++++++++++++++++++ tests/tcg/hexagon/test_packet.S | 26 ++++++++++++ tests/tcg/hexagon/test_reorder.S | 31 +++++++++++++++ tests/tcg/hexagon/test_round.S | 31 +++++++++++++++ tests/tcg/hexagon/test_vavgw.S | 33 ++++++++++++++++ tests/tcg/hexagon/test_vcmpb.S | 32 +++++++++++++++ tests/tcg/hexagon/test_vcmpw.S | 29 ++++++++++++++ tests/tcg/hexagon/test_vcmpy.S | 50 ++++++++++++++++++++++++ tests/tcg/hexagon/test_vlsrw.S | 23 +++++++++++ tests/tcg/hexagon/test_vmaxh.S | 37 ++++++++++++++++++ tests/tcg/hexagon/test_vminh.S | 37 ++++++++++++++++++ tests/tcg/hexagon/test_vpmpyh.S | 30 ++++++++++++++ tests/tcg/hexagon/test_vspliceb.S | 33 ++++++++++++++++ 35 files changed, 1103 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/hexagon/crt.S create mode 100644 tests/tcg/hexagon/test_abs.S create mode 100644 tests/tcg/hexagon/test_add.S create mode 100644 tests/tcg/hexagon/test_andp.S create mode 100644 tests/tcg/hexagon/test_bitcnt.S create mode 100644 tests/tcg/hexagon/test_bitsplit.S create mode 100644 tests/tcg/hexagon/test_call.S create mode 100644 tests/tcg/hexagon/test_clobber.S create mode 100644 tests/tcg/hexagon/test_cmp.S create mode 100644 tests/tcg/hexagon/test_cmpy.S create mode 100644 tests/tcg/hexagon/test_djump.S create mode 100644 tests/tcg/hexagon/test_dotnew.S create mode 100644 tests/tcg/hexagon/test_dstore.S create mode 100644 tests/tcg/hexagon/test_ext.S create mode 100644 tests/tcg/hexagon/test_fibonacci.S create mode 100644 tests/tcg/hexagon/test_hello.S create mode 100644 tests/tcg/hexagon/test_hl.S create mode 100644 tests/tcg/hexagon/test_hwloops.S create mode 100644 tests/tcg/hexagon/test_jmp.S create mode 100644 tests/tcg/hexagon/test_lsr.S create mode 100644 tests/tcg/hexagon/test_mpyi.S create mode 100644 tests/tcg/hexagon/test_overflow.S create mode 100644 tests/tcg/hexagon/test_packet.S create mode 100644 tests/tcg/hexagon/test_reorder.S create mode 100644 tests/tcg/hexagon/test_round.S create mode 100644 tests/tcg/hexagon/test_vavgw.S create mode 100644 tests/tcg/hexagon/test_vcmpb.S create mode 100644 tests/tcg/hexagon/test_vcmpw.S create mode 100644 tests/tcg/hexagon/test_vcmpy.S create mode 100644 tests/tcg/hexagon/test_vlsrw.S create mode 100644 tests/tcg/hexagon/test_vmaxh.S create mode 100644 tests/tcg/hexagon/test_vminh.S create mode 100644 tests/tcg/hexagon/test_vpmpyh.S create mode 100644 tests/tcg/hexagon/test_vspliceb.S diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile.target index 616af697fe..b5323cba05 100644 --- a/tests/tcg/hexagon/Makefile.target +++ b/tests/tcg/hexagon/Makefile.target @@ -32,7 +32,7 @@ CFLAGS += -Wno-incompatible-pointer-types -Wno-undefined-internal HEX_SRC=$(SRC_PATH)/tests/tcg/hexagon VPATH += $(HEX_SRC) -first: $(HEX_SRC)/first.S +%: $(HEX_SRC)/%.S $(HEX_SRC)/crt.S $(CC) -static -mv67 -nostdlib $^ -o $@ HEX_TESTS = first @@ -43,4 +43,38 @@ HEX_TESTS += mem_noshuf HEX_TESTS += atomics HEX_TESTS += fpstuff +HEX_TESTS += test_abs +HEX_TESTS += test_add +HEX_TESTS += test_andp +HEX_TESTS += test_bitcnt +HEX_TESTS += test_bitsplit +HEX_TESTS += test_call +HEX_TESTS += test_clobber +HEX_TESTS += test_cmp +HEX_TESTS += test_cmpy +HEX_TESTS += test_djump +HEX_TESTS += test_dotnew +HEX_TESTS += test_dstore +HEX_TESTS += test_ext +HEX_TESTS += test_fibonacci +HEX_TESTS += test_hello +HEX_TESTS += test_hl +HEX_TESTS += test_hwloops +HEX_TESTS += test_jmp +HEX_TESTS += test_lsr +HEX_TESTS += test_mpyi +HEX_TESTS += test_overflow +HEX_TESTS += test_packet +HEX_TESTS += test_reorder +HEX_TESTS += test_round +HEX_TESTS += test_vavgw +HEX_TESTS += test_vcmpb +HEX_TESTS += test_vcmpw +HEX_TESTS += test_vcmpy +HEX_TESTS += test_vlsrw +HEX_TESTS += test_vmaxh +HEX_TESTS += test_vminh +HEX_TESTS += test_vpmpyh +HEX_TESTS += test_vspliceb + TESTS += $(HEX_TESTS) diff --git a/tests/tcg/hexagon/crt.S b/tests/tcg/hexagon/crt.S new file mode 100644 index 0000000000..2c10577470 --- /dev/null +++ b/tests/tcg/hexagon/crt.S @@ -0,0 +1,28 @@ +#define SYS_exit_group 94 + + .text + .globl init +init: + { + allocframe(r29,#0):raw + } + { + r0=#256 + } + { + dealloc_return + } + + .space 240 + + .globl pass +pass: + r0 = #0 + r6 = #SYS_exit_group + trap0(#1) + + .globl fail +fail: + r0 = #1 + r6 = #SYS_exit_group + trap0(#1) diff --git a/tests/tcg/hexagon/test_abs.S b/tests/tcg/hexagon/test_abs.S new file mode 100644 index 0000000000..880b2886b5 --- /dev/null +++ b/tests/tcg/hexagon/test_abs.S @@ -0,0 +1,20 @@ +/* Purpose: test example, verify the soundness of the abs operation */ + + .text + .globl _start + +_start: + { + call init + } + { + r1=#-2 + r2=#2 + } + { + r3=abs(r1) + } + { + p0 = cmp.eq(r3, r2); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_add.S b/tests/tcg/hexagon/test_add.S new file mode 100644 index 0000000000..e8de34520f --- /dev/null +++ b/tests/tcg/hexagon/test_add.S @@ -0,0 +1,20 @@ +/* Purpose: test example, verify the soundness of the add operation */ + + .text + .globl _start + +_start: + { + call init + } + { + r1=#0 + r2=#0 + } + { + r3=add(r1,r2) + } + { + p0 = cmp.eq(r3, #0); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_andp.S b/tests/tcg/hexagon/test_andp.S new file mode 100644 index 0000000000..3c4aa8b2ae --- /dev/null +++ b/tests/tcg/hexagon/test_andp.S @@ -0,0 +1,23 @@ +/* Purpose: test a multiple predicate AND combination */ + + .text + .globl _start + +_start: + { + r1+=sub(r2,r3) + call init + } + { + r0=#0 + r1=#1 + } + { + p0=cmp.gt(r0,r1) + p0=cmp.gt(r0,r1) + p0=cmp.gt(r1,r0) + } + { + if (!p0) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_bitcnt.S b/tests/tcg/hexagon/test_bitcnt.S new file mode 100644 index 0000000000..df77fe61e2 --- /dev/null +++ b/tests/tcg/hexagon/test_bitcnt.S @@ -0,0 +1,42 @@ +/* Purpose: test example, verify the soundness of the cl[01] operations + * + * the number 0x000001aa has 23 leading zeroes + * they become 55 when considered as 64 bit register + * and it has 1 trailing zero + */ + .text + .globl _start + +_start: + { + call init + } + { + r0=#426 + r1=#0 + } + { + r2=cl0(r0) + } + { + p0 = cmp.eq(r2, #23); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + r2=cl0(r1:0) + } + { + p0 = cmp.eq(r2, #55); if (p0.new) jump:t test3 + jump fail + } + +test3: + { + r2=ct0(r0) + } + { + p0 = cmp.eq(r2, #1); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_bitsplit.S b/tests/tcg/hexagon/test_bitsplit.S new file mode 100644 index 0000000000..787cce72e4 --- /dev/null +++ b/tests/tcg/hexagon/test_bitsplit.S @@ -0,0 +1,25 @@ +/* Purpose: test example, verify the soundness of the bitsplit operation */ + + .text + .globl _start + +_start: + { + call init + } + { + r1=#187 + } + { + r3:2=bitsplit(r1, #3) + } + { + p0 = cmp.eq(r2, #3); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + p0 = cmp.eq(r3, #23); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_call.S b/tests/tcg/hexagon/test_call.S new file mode 100644 index 0000000000..53a2450522 --- /dev/null +++ b/tests/tcg/hexagon/test_call.S @@ -0,0 +1,63 @@ +/* Purpose: test function calls and duplex instructions. + * The string "Hello there, I'm a test string!" with the first letter replaced + * with a capital L should be printed out. + */ + + .text + .globl test +test: + { + jumpr r31 + memb(r0+#0)=#76 + } +.Lfunc_end0: +.Ltmp0: + .size test, .Ltmp0-test + + .globl _start +_start: + { + call init + } + { + call test + r0=##dummy_buffer + allocframe(#0) + } + { + call write + } + { + jump pass + } + { + r31:30=deallocframe(r30):raw + } +.Lfunc_end1: +.Ltmp1: + .size _start, .Ltmp1-_start +write: + { + r2=##dummy_buffer + } + { r0=r2; } + { + r2=#256 + } + { r1=r2; } + { trap0(#7); } + { + jumpr r31 + } +.Lfunc_end2: +.Ltmp2: + .size write, .Ltmp2-write + + .type dummy_buffer,@object + .data + .globl dummy_buffer + .p2align 3 +dummy_buffer: + .string "Hello there, I'm a test string!\n" + .space 223 + .size dummy_buffer, 256 diff --git a/tests/tcg/hexagon/test_clobber.S b/tests/tcg/hexagon/test_clobber.S new file mode 100644 index 0000000000..198817ebd5 --- /dev/null +++ b/tests/tcg/hexagon/test_clobber.S @@ -0,0 +1,35 @@ +/* Purpose: demonstrate the succesful operation of the register save mechanism, + * in which the caller saves the registers that will be clobbered, and restores + * them after the call. + */ + + .text + .globl _start + +_start: + { + call init + } + { + r16=#47 + r17=#155 + } + { + memd(r29+#-16)=r17:16; allocframe(#8) + } + { + r16=#255 + r17=#42 + } + { + r17:16=memd(r29+#0); deallocframe + } + { + r3=add(r16,r17) + } + { + p0 = cmp.eq(r3, #202); if (p0.new) jump:t pass + } + { + jump fail + } diff --git a/tests/tcg/hexagon/test_cmp.S b/tests/tcg/hexagon/test_cmp.S new file mode 100644 index 0000000000..31ee9565fe --- /dev/null +++ b/tests/tcg/hexagon/test_cmp.S @@ -0,0 +1,34 @@ +/* Purpose: test a signed and unsigned comparison */ + + .text + .globl _start + +_start: + { + call init + } + { + jump signed + } + + .globl signed +signed: + { + r0=#-2 + r1=#0 + } + { + p0 = cmp.lt(r0, r1); if (p0.new) jump:t unsigned + jump fail + } + + .globl unsigned +unsigned: + { + r0=#-2 + r1=#0 + } + { + p0 = cmp.gtu(r0, r1); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_cmpy.S b/tests/tcg/hexagon/test_cmpy.S new file mode 100644 index 0000000000..0b3dfb95de --- /dev/null +++ b/tests/tcg/hexagon/test_cmpy.S @@ -0,0 +1,31 @@ +/* Purpose: test example, verify the soundness of the cmpy operation + * + * 3j+5 * 2j+4 = 22j+14 + * + * the complex multiply between 0x00030005 and 0x00020004 is 0x000000160000000e + */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=#196613 + r1=#131076 + } + { + r3:2=cmpy(r0, r1):sat + } + { + p0 = cmp.eq(r2, #14); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + p0 = cmp.eq(r3, #22); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_djump.S b/tests/tcg/hexagon/test_djump.S new file mode 100644 index 0000000000..dbad7eb0a1 --- /dev/null +++ b/tests/tcg/hexagon/test_djump.S @@ -0,0 +1,24 @@ +/* Purpose: show dual jumps actually work. This program features a packet where + * two jumps should (in theory) be performed if !P0. However, we correctly + * handle the situation by performing only the first one and ignoring the second + * one. This can be verified by checking that the CPU dump contains 0xDEADBEEF + * in R2. + */ + + .text + .globl _start + +_start: + { + call init + } + { + r1 = #255; + } + { + p0 = r1; + } + { + if (p0) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_dotnew.S b/tests/tcg/hexagon/test_dotnew.S new file mode 100644 index 0000000000..3897c6bc96 --- /dev/null +++ b/tests/tcg/hexagon/test_dotnew.S @@ -0,0 +1,39 @@ +/* Purpose: test the .new operator while performing memory stores. + * In the final CPU dump R0 should contain 3, R1 should contain 2 and R2 should + * contain 1. + */ + .text + .globl _start + +_start: + { + call init + } + { + r0=#1 + memw(sp+#0)=r0.new + } + { + r1=#2 + memw(sp+#4)=r1.new + } + { + r2=#3 + memw(sp+#8)=r2.new + } + { + r0=memw(sp+#8) + } + { + r1=memw(sp+#4) + } + { + r2=memw(sp+#0) + } + { + r3=mpyi(r1,r2) + } + { + p0 = cmp.eq(r3, #2); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_dstore.S b/tests/tcg/hexagon/test_dstore.S new file mode 100644 index 0000000000..62c4301eb1 --- /dev/null +++ b/tests/tcg/hexagon/test_dstore.S @@ -0,0 +1,29 @@ +/* Purpose: test dual stores correctness. + * In this example the values 1 and 2 are both written on the top of the stack + * in a single packet. + * The value is then read back in R3, which should contain only the latest value + * written (2). + */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=#1 + r1=#2 + } + { + memw(sp+#0)=r0 + memw(sp+#0)=r1 + } + { + r3=memw(sp+#0) + } + { + p0 = cmp.eq(r3, #2); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_ext.S b/tests/tcg/hexagon/test_ext.S new file mode 100644 index 0000000000..0f6e21593a --- /dev/null +++ b/tests/tcg/hexagon/test_ext.S @@ -0,0 +1,18 @@ +/* Purpose: test immediate extender instructions. + * In the CPU dump R0 should contain 0xDEADBEEF. + */ + + .text + .globl _start + +_start: + { + call init + } + { + r2=##-559038737 + } + { + p0 = cmp.eq(r2, ##-559038737); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_fibonacci.S b/tests/tcg/hexagon/test_fibonacci.S new file mode 100644 index 0000000000..41cb1517cb --- /dev/null +++ b/tests/tcg/hexagon/test_fibonacci.S @@ -0,0 +1,33 @@ +/* Purpose: computes the Fibonacci series up to a constant number. */ + + .text + .globl _start + +_start: + { + call init + } + { + r2=#100 + } + { + p0=cmp.gt(r2,#0); if (!p0.new) jump:nt .LBB0_3 + } + { + r3=#0 + r4=#1 + } +.LBB0_2: + { + r5=r4 + } + { + p0=cmp.gt(r2,r5); if (p0.new) jump:nt .LBB0_2 + r4=add(r3,r4) + r3=r5 + } +.LBB0_3: + { + p0 = cmp.eq(r3, #144); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_hello.S b/tests/tcg/hexagon/test_hello.S new file mode 100644 index 0000000000..89c7da677f --- /dev/null +++ b/tests/tcg/hexagon/test_hello.S @@ -0,0 +1,21 @@ +/* Purpose: simple hello world program. */ + + .text + .globl _start + +_start: + { + call init + } + { r0=#4; } + { + r1=##.L.str + } + { trap0(#0); } + { + jump pass + } + +.L.str: + .string "Hello world!\n" + .size .L.str, 14 diff --git a/tests/tcg/hexagon/test_hl.S b/tests/tcg/hexagon/test_hl.S new file mode 100644 index 0000000000..217b3143e2 --- /dev/null +++ b/tests/tcg/hexagon/test_hl.S @@ -0,0 +1,19 @@ +/* Purpose: test example, verify the soundness of the high/low assignment */ + + .text + .globl _start + +_start: + { + call init + } + { + r0.H=#42 + } + { + r0.L=#69 + } + { + p0 = cmp.eq(r0, #2752581); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_hwloops.S b/tests/tcg/hexagon/test_hwloops.S new file mode 100644 index 0000000000..8337083d8e --- /dev/null +++ b/tests/tcg/hexagon/test_hwloops.S @@ -0,0 +1,25 @@ +/* Purpose: simple C Program to test hardware loops. + * It should print numbersfrom 0 to 9. + */ + + .text + .globl _start + +_start: + { + call init + } + { + loop0(.LBB0_1,#10) + r2=#0 + } +.Ltmp0: +.LBB0_1: + { + r2=add(r2,#1) + nop + }:endloop0 + { + p0 = cmp.eq(r2, #10); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_jmp.S b/tests/tcg/hexagon/test_jmp.S new file mode 100644 index 0000000000..9bf6ea34e5 --- /dev/null +++ b/tests/tcg/hexagon/test_jmp.S @@ -0,0 +1,25 @@ +/* Purpose: test example, verify the soundness of the add operation */ + + .text + .globl _start + +_start: + { + call init + } + { + r1=#0 + r2=#0 + } + { + r3=add(r1,r2) + } + { + p0 = cmp.eq(r3, #0) + } + { + if (p0) jump:t pass + } + { + jump fail + } diff --git a/tests/tcg/hexagon/test_lsr.S b/tests/tcg/hexagon/test_lsr.S new file mode 100644 index 0000000000..202eb4aec7 --- /dev/null +++ b/tests/tcg/hexagon/test_lsr.S @@ -0,0 +1,39 @@ +/* Purpose: test the soundness of the lsr operation */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=#-56984 + r1=#2147483647 + } + { + r2=#0x19 + } + { + r0&=lsr(r1, r2) + } + { + p0 = cmp.eq(r0, #0x28); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + r0=#0x0000000a + r1=#0x00000000 + } + { + r2=#-1 + } + { + r1:0=lsl(r1:0, r2) + } + { + p0 = cmp.eq(r0, #0x5); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_mpyi.S b/tests/tcg/hexagon/test_mpyi.S new file mode 100644 index 0000000000..b8e0d50b68 --- /dev/null +++ b/tests/tcg/hexagon/test_mpyi.S @@ -0,0 +1,20 @@ +/* Purpose: test a simple multiplication operation */ + + .text + .globl _start + +_start: + { + call init + } + { + r1=#4 + r2=#6 + } + { + r3=mpyi(r1,r2) + } + { + p0 = cmp.eq(r3, #24); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_overflow.S b/tests/tcg/hexagon/test_overflow.S new file mode 100644 index 0000000000..9e2a235616 --- /dev/null +++ b/tests/tcg/hexagon/test_overflow.S @@ -0,0 +1,63 @@ +// Purpose: test example, verify the soundness of the overflow bit +// +// a right shift with negative amount should make r0 saturate, setting the +// overflow bit + + .text + .globl _start + +_start: + { + call init + } + { + r0=#0x10000000 + r1=#-2 + } + { + r2=asr(r0, r1):sat + } + { + r4=USR + } + { + r5=and(r4,#1) + } + { + p0 = cmp.eq(r5, #0); if (p0.new) jump:t check_ovfl + jump fail + } +check_ovfl: + { + r1=#-3 + } + { + r2=asr(r0, r1):sat + } + { + r4=USR + } + { + r5=and(r4,#1) + } + { + p0 = cmp.eq(r5, #1); if (p0.new) jump:t check_sticky + jump fail + } +check_sticky: + { + r1=#-2 + } + { + r2=asr(r0, r1):sat + } + { + r4=USR + } + { + r5=and(r4,#1) + } + { + p0 = cmp.eq(r5, #1); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_packet.S b/tests/tcg/hexagon/test_packet.S new file mode 100644 index 0000000000..d26e284be9 --- /dev/null +++ b/tests/tcg/hexagon/test_packet.S @@ -0,0 +1,26 @@ +/* Purpose: test that writes of a register in a packet are performed only after + * that packet has finished its execution. + */ + + .text + .globl _start + +_start: + { + call init + } + { + r2=#4 + r3=#6 + } + { + memw(sp+#0)=r2 + } + { + r3=memw(sp+#0) + r0=add(r2,r3) + } + { + p0 = cmp.eq(r0, #10); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_reorder.S b/tests/tcg/hexagon/test_reorder.S new file mode 100644 index 0000000000..508d5302f9 --- /dev/null +++ b/tests/tcg/hexagon/test_reorder.S @@ -0,0 +1,31 @@ +/* Purpose: demonstrate handling of .new uses appearing before the associated + * definition. + * Here we perform a jump that skips the code resetting R2 from 0xDEADBEEF to 0, + * only if P0.new is true, but P0 is assigned to 1 (R4) in the next instruction + * in the packet. + * A successful run of the program will show R2 retaining the 0xDEADBEEF value + * in the CPU dump. + */ + + .text + .globl _start + +_start: + { + call init + } + { r2=#-559038737 } + { r4=#1 } + { + if (p0.new) jump:nt skip + p0=r4; + } + +fallthrough: + { r2=#0 } + +skip: + { + p0 = cmp.eq(r2, #-559038737); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_round.S b/tests/tcg/hexagon/test_round.S new file mode 100644 index 0000000000..2becd62c4c --- /dev/null +++ b/tests/tcg/hexagon/test_round.S @@ -0,0 +1,31 @@ +/* Purpose: test example, verify the soundness of the cround operation + * 106 = 0b1101010 with the comma at third digit is 12.5 which is crounded to 12 + * but rounded to 13 + */ + + .text + .globl _start + +_start: + { + call init + } + { + r1=#200 + } + { + r2=round(r1, #4) + } + { + p0 = cmp.eq(r2, #13); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + r2=cround(r1, #4) + } + { + p0 = cmp.eq(r2, #12); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_vavgw.S b/tests/tcg/hexagon/test_vavgw.S new file mode 100644 index 0000000000..8f67238900 --- /dev/null +++ b/tests/tcg/hexagon/test_vavgw.S @@ -0,0 +1,33 @@ +/* Purpose: test example, verify the soundness of the vavgw operation + * + * 0x00030001 averaged with 0x00010003 results 0x00020002 + */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=#3 + r1=#1 + } + { + r2=#1 + r3=#3 + } + { + r1:0=vavgw(r1:0, r3:2):crnd + } + { + p0 = cmp.eq(r0, #2); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + p0 = cmp.eq(r1, #2); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_vcmpb.S b/tests/tcg/hexagon/test_vcmpb.S new file mode 100644 index 0000000000..3c6700a63a --- /dev/null +++ b/tests/tcg/hexagon/test_vcmpb.S @@ -0,0 +1,32 @@ +/* Purpose: test example, verify the soundness of the vector compare bytes + * operation + * + * Vector word comparison between 0x1234567887654321 and 0x1234567800000000 + * should result in 0x11110000 + */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=#305419896 + r1=#-2023406815 + } + { + r2=#305419896 + r3=#0 + } + { + p2=vcmpb.eq(r1:0, r3:2) + } + { + r4=p2 + } + { + p0 = cmp.eq(r4, #15); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_vcmpw.S b/tests/tcg/hexagon/test_vcmpw.S new file mode 100644 index 0000000000..112f08c92f --- /dev/null +++ b/tests/tcg/hexagon/test_vcmpw.S @@ -0,0 +1,29 @@ +/* Purpose: test example, verify the soundness of the vector compare words + * operation + * + * Vector word comparison between 0x1234567887654321 and 0x1234567800000000 + * should result in 0x11110000 + */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=#305419896 + r1=#-2023406815 + } + { + r2=#305419896 + r3=#0 + } + { + p2=vcmpw.eq(r1:0, r3:2) + } + { + if (p2) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_vcmpy.S b/tests/tcg/hexagon/test_vcmpy.S new file mode 100644 index 0000000000..df379f9186 --- /dev/null +++ b/tests/tcg/hexagon/test_vcmpy.S @@ -0,0 +1,50 @@ +/* Purpose: test example, verify the soundness of the vcmpy operation + * this operation is a complex multiply and accumulate on vectors of two values + * + * (3j+5 * 2j+4) + (4j+6 * 5j+2) = 22j+14 + * + * the complex multiply between 0x00030005 and 0x00020004 is 0x000000160000000e + * the complex multiply between 0x00040006 and 0x00050002 is 0x000000160000000e + */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=#196613 + r1=#131076 + } + { + r2=#262150 + r3=#327682 + } + { + r5:4=vcmpyr(r1:0, r3:2):sat + r7:6=vcmpyi(r1:0, r3:2):sat + } + { + p0 = cmp.eq(r4, #18); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + p0 = cmp.eq(r5, #-2); if (p0.new) jump:t test3 + jump fail + } + +test3: + { + p0 = cmp.eq(r6, #38); if (p0.new) jump:t test4 + jump fail + } + +test4: + { + p0 = cmp.eq(r7, #24); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_vlsrw.S b/tests/tcg/hexagon/test_vlsrw.S new file mode 100644 index 0000000000..962ec99543 --- /dev/null +++ b/tests/tcg/hexagon/test_vlsrw.S @@ -0,0 +1,23 @@ +/* Purpose: test the soundness of the vlsrw operation */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=#0x00000001 + r1=#0x00000001 + } + { + r1:0=vlsrw(r1:0, #1) + } + { + r0 = add(r0, r1) + } + { + p0 = cmp.eq(r0, #0); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_vmaxh.S b/tests/tcg/hexagon/test_vmaxh.S new file mode 100644 index 0000000000..1fce935e35 --- /dev/null +++ b/tests/tcg/hexagon/test_vmaxh.S @@ -0,0 +1,37 @@ +/* Purpose: test example, verify the soundness of the vrmaxh operation + * + * the maximum between 0x0002000300010005 and 0x0003000200020007 is + * 0x0003000300020007. + * + * r1=0x00010003 r0=0x00010005 r3=0x00030002 r2=0x00020007 + * result: r1=0x00030003 r0=0x00020007 + */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=#65541 + r1=#65539 + } + { + r2=#131079 + r3=#196610 + } + { + r1:0=vmaxh(r1:0, r3:2) + } + { + p0 = cmp.eq(r0, #131079); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + p0 = cmp.eq(r1, #196611); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_vminh.S b/tests/tcg/hexagon/test_vminh.S new file mode 100644 index 0000000000..6c6d18c673 --- /dev/null +++ b/tests/tcg/hexagon/test_vminh.S @@ -0,0 +1,37 @@ +/* Purpose: test example, verify the soundness of the vrmaxh operation + * + * the minimum between 0x0002000300010005 and 0x0003000200020007 is + * 0x0003000300020007 + * + * r1=0x00010003 r0=0x00010005 r3=0x00030002 r2=0x00020007 + * result: r1=0x00010002 r0=0x00010005 + */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=#65541 + r1=#65539 + } + { + r2=#131079 + r3=#196610 + } + { + r1:0=vminh(r1:0, r3:2) + } + { + p0 = cmp.eq(r0, #65541); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + p0 = cmp.eq(r1, #65538); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_vpmpyh.S b/tests/tcg/hexagon/test_vpmpyh.S new file mode 100644 index 0000000000..942d691da4 --- /dev/null +++ b/tests/tcg/hexagon/test_vpmpyh.S @@ -0,0 +1,30 @@ +/* Purpose: test example, verify the soundness of the vpmpyh operator + * + * 0x01020304 vector polynomial multiplied with 0x04030201 results + * 0x000400060b060b04 + */ + + .text + .globl _start + +_start: + { + call init + } + { + r0=#16909060 + r1=#67305985 + } + { + r1:0=vpmpyh(r0, r1) + } + { + p0 = cmp.eq(r0, #184945412); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + p0 = cmp.eq(r1, #262150); if (p0.new) jump:t pass + jump fail + } diff --git a/tests/tcg/hexagon/test_vspliceb.S b/tests/tcg/hexagon/test_vspliceb.S new file mode 100644 index 0000000000..bae2a9c163 --- /dev/null +++ b/tests/tcg/hexagon/test_vspliceb.S @@ -0,0 +1,33 @@ +/* Purpose: test example, verify the soundness of the vspliceb operation + * the operation is a binary splice of two 64bit operators + * + * vspliceb(0xffffffffffffffff,0x0000000000000000,5) = 0x000000000000001f + */ + .text + .globl _start + +_start: + { + call init + } + { + r0=#-1 + r1=#-1 + } + { + r2=#0 + r3=#0 + } + { + r5:4=vspliceb(r1:0, r3:2, #5) + } + { + p0 = cmp.eq(r4, #-1); if (p0.new) jump:t test2 + jump fail + } + +test2: + { + p0 = cmp.eq(r5, #255); if (p0.new) jump:t pass + jump fail + }