From patchwork Thu Aug 2 14:10:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Merello X-Patchwork-Id: 10553655 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 16A6615E9 for ; Thu, 2 Aug 2018 14:10:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 069F52C0F6 for ; Thu, 2 Aug 2018 14:10:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 037142C0E0; Thu, 2 Aug 2018 14:10:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E1AD42C10A for ; Thu, 2 Aug 2018 14:10:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732255AbeHBQBm (ORCPT ); Thu, 2 Aug 2018 12:01:42 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:36732 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732141AbeHBQBm (ORCPT ); Thu, 2 Aug 2018 12:01:42 -0400 Received: by mail-wr1-f66.google.com with SMTP id h9-v6so2299429wro.3; Thu, 02 Aug 2018 07:10:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=NPisTIUxEJWllPtVLNR+w7rnRDOVuscZpqNlMO4PTg8=; b=qVQHkycNLclULwTXiDeJPxKYdPwDoM0UCfDyc2FdD0++BxTwl3kSb0MOnH3uMV4qdb qKSg4R4VcVDls2VmQa17AB0GIPU4kR0WnMIHsrILlUejoJtzWE7DpbJtmvJKWPpuhNgD NZvBx4xIM5oPTXPzV7A0+RGCTBOrEcbh6+w8XleP2HpUi+iA7T8VOv8DmZWLlSmR5fm+ p2sI7LkpQBEuKX5SzcbcLIBwwEYY+wEOPczGVpF5fePlrEB2ryXoTIQnivUT/KeevhMy U+MBnFD6S8HA8AuEPfDy/JeRmB+HG4jvn2Dhj7VyczHejMAjIMnMeynJK18PRFtVau23 zWzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=NPisTIUxEJWllPtVLNR+w7rnRDOVuscZpqNlMO4PTg8=; b=CEE6lv0Bfoa3QsIHRiZwyH66WG8jk26tnBdYmtfWgdVIN47LgL0YPQpTk3wRsh2SUs U2NPocMlmsQAebH1lpi0zYvBNKeuP6Crqrqy71z4EwYL5HfQDRzvEbo9lMo08nObFA14 RTq5ZPBQnQuOB4Yi1EHYCWP8XJGeB4/3O0zlJciUiStdXZcABjt41bUGLKMuCMXb3PAa eSyAFfgPsHgb5jSl89i8C8tgH05IeM7g7oxTc1VRHK2wSdTW+nW0pPL58xwIv4zRFzTP POZgue0apKmPof/8VVNsIY3P2kZyVj6XuzVSijPYDRbScIBHGgTsZ8TVF/I20EzbcQoz VA+w== X-Gm-Message-State: AOUpUlE8DTwYYBvZYk6T/ZKh6DcerPGs+vrvY+Y0LurvAbInbSOyTp2w TEzdDHqB6qJykJZyRbgTYiQ= X-Google-Smtp-Source: AAOMgpcPYdK2+JgAvUBhf8b+RM5WPAVCDoisie/8hbPiagqA9l6iXr0W0pVcjCKD7MFAGWxM0/GluQ== X-Received: by 2002:adf:bc03:: with SMTP id s3-v6mr2262503wrg.211.1533219018243; Thu, 02 Aug 2018 07:10:18 -0700 (PDT) Received: from NewMoon.iit.local ([90.147.180.254]) by smtp.gmail.com with ESMTPSA id d78-v6sm3392310wma.37.2018.08.02.07.10.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 02 Aug 2018 07:10:17 -0700 (PDT) From: Andrea Merello To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: v4-000linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello Subject: [PATCH v4 1/7] dmaengine: xilinx_dma: commonize DMA copy size calculation Date: Thu, 2 Aug 2018 16:10:06 +0200 Message-Id: <20180802141012.19970-1-andrea.merello@gmail.com> X-Mailer: git-send-email 2.17.1 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch removes a bit of duplicated code by introducing a new function that implements calculations for DMA copy size. Suggested-by: Vinod Koul Signed-off-by: Andrea Merello --- Changes in v4: - introduce this patch in the patch series --- drivers/dma/xilinx/xilinx_dma.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 27b523530c4a..a3aaa0e34cc7 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -952,6 +952,19 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) return 0; } +/** + * xilinx_dma_calc_copysize - Calculate the amount of data to copy + * @size: Total data that needs to be copied + * @done: Amount of data that has been already copied + * + * Return: Amount of data that has to be copied + */ +static int xilinx_dma_calc_copysize(int size, int done) +{ + return min_t(size_t, size - done, + XILINX_DMA_MAX_TRANS_LEN); +} + /** * xilinx_dma_tx_status - Get DMA transaction status * @dchan: DMA channel @@ -1791,8 +1804,8 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( * Calculate the maximum number of bytes to transfer, * making sure it is less than the hw limit */ - copy = min_t(size_t, sg_dma_len(sg) - sg_used, - XILINX_DMA_MAX_TRANS_LEN); + copy = xilinx_dma_calc_copysize(sg_dma_len(sg), + sg_used); hw = &segment->hw; /* Fill in the descriptor */ @@ -1896,8 +1909,7 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( * Calculate the maximum number of bytes to transfer, * making sure it is less than the hw limit */ - copy = min_t(size_t, period_len - sg_used, - XILINX_DMA_MAX_TRANS_LEN); + copy = xilinx_dma_calc_copysize(period_len, sg_used); hw = &segment->hw; xilinx_axidma_buf(chan, hw, buf_addr, sg_used, period_len * i); From patchwork Thu Aug 2 14:10:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Merello X-Patchwork-Id: 10553665 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 57D65174A for ; Thu, 2 Aug 2018 14:10:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3EB182C0E5 for ; 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Thu, 02 Aug 2018 07:10:19 -0700 (PDT) Received: from NewMoon.iit.local ([90.147.180.254]) by smtp.gmail.com with ESMTPSA id d78-v6sm3392310wma.37.2018.08.02.07.10.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 02 Aug 2018 07:10:18 -0700 (PDT) From: Andrea Merello To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: v4-000linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello Subject: [PATCH v4 2/7] dmaengine: xilinx_dma: in axidma slave_sg and dma_cylic mode align split descriptors Date: Thu, 2 Aug 2018 16:10:07 +0200 Message-Id: <20180802141012.19970-2-andrea.merello@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180802141012.19970-1-andrea.merello@gmail.com> References: <20180802141012.19970-1-andrea.merello@gmail.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Whenever a single or cyclic transaction is prepared, the driver could eventually split it over several SG descriptors in order to deal with the HW maximum transfer length. This could end up in DMA operations starting from a misaligned address. This seems fatal for the HW if DRE is not enabled. This patch eventually adjusts the transfer size in order to make sure all operations start from an aligned address. Cc: Radhey Shyam Pandey Signed-off-by: Andrea Merello Reviewed-by: Radhey Shyam Pandey --- Changes in v2: - don't introduce copy_mask field, rather rely on already-esistent copy_align field. Suggested by Radhey Shyam Pandey - reword title Changes in v3: - fix bug introduced in v2: wrong copy size when DRE is enabled - use implementation suggested by Radhey Shyam Pandey Changes in v4: - rework on the top of 1/6 --- drivers/dma/xilinx/xilinx_dma.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index a3aaa0e34cc7..aaa6de8a70e4 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -954,15 +954,28 @@ static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) /** * xilinx_dma_calc_copysize - Calculate the amount of data to copy + * @chan: Driver specific DMA channel * @size: Total data that needs to be copied * @done: Amount of data that has been already copied * * Return: Amount of data that has to be copied */ -static int xilinx_dma_calc_copysize(int size, int done) +static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan, + int size, int done) { - return min_t(size_t, size - done, + size_t copy = min_t(size_t, size - done, XILINX_DMA_MAX_TRANS_LEN); + + if ((copy + done < size) && + chan->xdev->common.copy_align) { + /* + * If this is not the last descriptor, make sure + * the next one will be properly aligned + */ + copy = rounddown(copy, + (1 << chan->xdev->common.copy_align)); + } + return copy; } /** @@ -1804,7 +1817,7 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( * Calculate the maximum number of bytes to transfer, * making sure it is less than the hw limit */ - copy = xilinx_dma_calc_copysize(sg_dma_len(sg), + copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg), sg_used); hw = &segment->hw; @@ -1909,7 +1922,8 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( * Calculate the maximum number of bytes to transfer, * making sure it is less than the hw limit */ - copy = xilinx_dma_calc_copysize(period_len, sg_used); + copy = xilinx_dma_calc_copysize(chan, + period_len, sg_used); hw = &segment->hw; xilinx_axidma_buf(chan, hw, buf_addr, sg_used, period_len * i); From patchwork Thu Aug 2 14:10:08 2018 Content-Type: text/plain; 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Thu, 02 Aug 2018 07:10:19 -0700 (PDT) From: Andrea Merello To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: v4-000linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello Subject: [PATCH v4 3/7] dt-bindings: dmaengine: xilinx_dma: add optional xlnx,sg-length-width property Date: Thu, 2 Aug 2018 16:10:08 +0200 Message-Id: <20180802141012.19970-3-andrea.merello@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180802141012.19970-1-andrea.merello@gmail.com> References: <20180802141012.19970-1-andrea.merello@gmail.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The width of the "length register" cannot be autodetected, and it is now specified with a DT property. Add DOC for it. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Radhey Shyam Pandey Signed-off-by: Andrea Merello Reviewed-by: Radhey Shyam Pandey --- Changes in v2: - change property name - property is now optional - cc DT maintainer Changes in v3: - reword - cc DT maintainerS and ML Changes in v4: - specify the unit, the valid range and the default value --- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index a2b8bfaec43c..aec4a41a03ae 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -41,6 +41,10 @@ Optional properties: - xlnx,include-sg: Tells configured for Scatter-mode in the hardware. Optional properties for AXI DMA: +- xlnx,sg-length-width: Should be set to the width in bits of the length + register as configured in h/w. Takes values {8...26}. If the property + is missing or invalid then the default value 23 is used. This is the + maximum value that is supported by all IP versions. - xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware. Optional properties for VDMA: - xlnx,flush-fsync: Tells which channel to Flush on Frame sync. From patchwork Thu Aug 2 14:10:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Merello X-Patchwork-Id: 10553663 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9788B174A for ; Thu, 2 Aug 2018 14:10:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 867D92C12A for ; Thu, 2 Aug 2018 14:10:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 83FB22C128; Thu, 2 Aug 2018 14:10:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C16C12C12A for ; Thu, 2 Aug 2018 14:10:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732538AbeHBQBr (ORCPT ); Thu, 2 Aug 2018 12:01:47 -0400 Received: from mail-wr1-f67.google.com ([209.85.221.67]:36740 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732533AbeHBQBq (ORCPT ); Thu, 2 Aug 2018 12:01:46 -0400 Received: by mail-wr1-f67.google.com with SMTP id h9-v6so2299647wro.3; Thu, 02 Aug 2018 07:10:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6U8OjZp1aNLtxv3SHkdF70T4ai4ppTPufaREl0hEaVo=; b=NC7NwQxTv0HljieeseJTwhkdZgSd7mFTuT/xOu07kdZm8AjMdqDjyRwHt16Yl2/Tv4 +iL8EewGXE+KsdsNAQIm2fxUoom+y3uL2VoBe5jitGO0mAW9pg1cTgAh2pJhci1x71hl /QA4d4+OzKs/bIBDzkXqFcyTlaWF6XFCcTHYEyJ7zXmmM5QAOtJxazh/8Y0ggK8VsBqp Hwa8ah6BmUh1jEFyZ7pIAsEko18hLGGNE3axqmEyoqoCsAWc8QmSTG/oONCsRcDBoJ+r qlS6XDDXPhoAD/tRx3d+sTmgxKWCR1/zfW8+gTcwS2OxCI3FtTk7+k0zgFNtiQnPxWDC Yz7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6U8OjZp1aNLtxv3SHkdF70T4ai4ppTPufaREl0hEaVo=; b=StWdRpF7YIzfJRbTbrMV5+n6G+v2WBC1gwfG3845tOTk9IV1vsUmrf8mMpvapSNsGo xwcHbsRf6HV8ZR21s2IU1DTZNLa4S8ci0oSal+1cAbN6ywTG2o04IGUeZ9VJWBqx5bNw oMEJeTCFRzrRTUyBZe1MP56vdPXJ9xUc6q03eJXmaZmfV7AmGlW8I0rKe7kOzhgDkzA8 GUmRcmEbohWdwqmM/ibNp2UQ8AFULHH4TGnKYOXZkSEnr52X7u+2LDcFF1jINzvVwJzr Dl2ShI/7HGgWUEzZ2tKsd+NPxhnUHEVsjRyaR+kUia0JwNjkQQXaWRc9gLscxvZRh8JO htzw== X-Gm-Message-State: AOUpUlEWtSBvX6eMSASiTxTAJLD1f6Our7JhQOdK0PLywfCjSZN91os5 q51L/XSGx5CRolq2w1zJRoc= X-Google-Smtp-Source: AAOMgpfs/l3B2fdbgBOhmC40D/qnZ7aT0hCkuYpGzyHiSgivo/tFd4eZu0062KOn5Yfi1Wvj+jLKUQ== X-Received: by 2002:adf:fec8:: with SMTP id q8-v6mr2192742wrs.164.1533219022144; Thu, 02 Aug 2018 07:10:22 -0700 (PDT) Received: from NewMoon.iit.local ([90.147.180.254]) by smtp.gmail.com with ESMTPSA id d78-v6sm3392310wma.37.2018.08.02.07.10.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 02 Aug 2018 07:10:21 -0700 (PDT) From: Andrea Merello To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: v4-000linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello Subject: [PATCH v4 4/7] dmaengine: xilinx_dma: program hardware supported buffer length Date: Thu, 2 Aug 2018 16:10:09 +0200 Message-Id: <20180802141012.19970-4-andrea.merello@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180802141012.19970-1-andrea.merello@gmail.com> References: <20180802141012.19970-1-andrea.merello@gmail.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Radhey Shyam Pandey AXI-DMA IP supports configurable (c_sg_length_width) buffer length register width, hence read buffer length (xlnx,sg-length-width) DT property and ensure that driver doesn't program buffer length exceeding the supported limit. For VDMA and CDMA there is no change. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Signed-off-by: Radhey Shyam Pandey Signed-off-by: Michal Simek Signed-off-by: Andrea Merello [rebase, reword] --- Changes in v2: - drop original patch and replace with the one in Xilinx tree Changes in v3: - cc DT maintainers/ML Changes in v4: - upper bound for the property should be 26, not 23 - add warn for width > 23 as per xilinx original patch - rework due to changes introduced in 1/6 --- drivers/dma/xilinx/xilinx_dma.c | 36 +++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index aaa6de8a70e4..b17f24e4ec35 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -158,7 +158,9 @@ #define XILINX_DMA_REG_BTT 0x28 /* AXI DMA Specific Masks/Bit fields */ -#define XILINX_DMA_MAX_TRANS_LEN GENMASK(22, 0) +#define XILINX_DMA_MAX_TRANS_LEN_MIN 8 +#define XILINX_DMA_MAX_TRANS_LEN_MAX 23 +#define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26 #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16) #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4) #define XILINX_DMA_CR_COALESCE_SHIFT 16 @@ -418,6 +420,7 @@ struct xilinx_dma_config { * @rxs_clk: DMA s2mm stream clock * @nr_channels: Number of channels DMA device supports * @chan_id: DMA channel identifier + * @max_buffer_len: Max buffer length */ struct xilinx_dma_device { void __iomem *regs; @@ -437,6 +440,7 @@ struct xilinx_dma_device { struct clk *rxs_clk; u32 nr_channels; u32 chan_id; + u32 max_buffer_len; }; /* Macros */ @@ -964,7 +968,7 @@ static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan, int size, int done) { size_t copy = min_t(size_t, size - done, - XILINX_DMA_MAX_TRANS_LEN); + chan->xdev->max_buffer_len); if ((copy + done < size) && chan->xdev->common.copy_align) { @@ -1011,7 +1015,7 @@ static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan, list_for_each_entry(segment, &desc->segments, node) { hw = &segment->hw; residue += (hw->control - hw->status) & - XILINX_DMA_MAX_TRANS_LEN; + chan->xdev->max_buffer_len; } } spin_unlock_irqrestore(&chan->lock, flags); @@ -1263,7 +1267,7 @@ static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan) /* Start the transfer */ dma_ctrl_write(chan, XILINX_DMA_REG_BTT, - hw->control & XILINX_DMA_MAX_TRANS_LEN); + hw->control & chan->xdev->max_buffer_len); } list_splice_tail_init(&chan->pending_list, &chan->active_list); @@ -1366,7 +1370,7 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) /* Start the transfer */ dma_ctrl_write(chan, XILINX_DMA_REG_BTT, - hw->control & XILINX_DMA_MAX_TRANS_LEN); + hw->control & chan->xdev->max_buffer_len); } list_splice_tail_init(&chan->pending_list, &chan->active_list); @@ -1727,7 +1731,7 @@ xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst, struct xilinx_cdma_tx_segment *segment; struct xilinx_cdma_desc_hw *hw; - if (!len || len > XILINX_DMA_MAX_TRANS_LEN) + if (!len || len > chan->xdev->max_buffer_len) return NULL; desc = xilinx_dma_alloc_tx_descriptor(chan); @@ -2596,7 +2600,7 @@ static int xilinx_dma_probe(struct platform_device *pdev) struct xilinx_dma_device *xdev; struct device_node *child, *np = pdev->dev.of_node; struct resource *io; - u32 num_frames, addr_width; + u32 num_frames, addr_width, len_width; int i, err; /* Allocate and initialize the DMA engine structure */ @@ -2628,8 +2632,24 @@ static int xilinx_dma_probe(struct platform_device *pdev) /* Retrieve the DMA engine properties from the device tree */ xdev->has_sg = of_property_read_bool(node, "xlnx,include-sg"); - if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) + xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0); + + if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { xdev->mcdma = of_property_read_bool(node, "xlnx,mcdma"); + if (!of_property_read_u32(node, "xlnx,sg-length-width", + &len_width)) { + if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN || + len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) { + dev_warn(xdev->dev, + "invalid xlnx,sg-length-width property value. Using default width\n"); + } else { + if (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX) + dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n"); + xdev->max_buffer_len = + GENMASK(len_width - 1, 0); + } + } + } if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { err = of_property_read_u32(node, "xlnx,num-fstores", From patchwork Thu Aug 2 14:10:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Merello X-Patchwork-Id: 10553661 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D62FF15A6 for ; Thu, 2 Aug 2018 14:10:45 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C38392C13F for ; Thu, 2 Aug 2018 14:10:45 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C1D5E2C149; Thu, 2 Aug 2018 14:10:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 33EEE2C146 for ; Thu, 2 Aug 2018 14:10:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732560AbeHBQBs (ORCPT ); Thu, 2 Aug 2018 12:01:48 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:35596 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732231AbeHBQBr (ORCPT ); Thu, 2 Aug 2018 12:01:47 -0400 Received: by mail-wm0-f66.google.com with SMTP id o18-v6so2756537wmc.0; Thu, 02 Aug 2018 07:10:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AQDlM29x6ygdS9Pi8RFktUUJqAuke0GTAHr2//YIM4A=; b=foRxSGO0M7a6KElsDaOL9oUpKUQtz4wSDl+JmEJTAXjHbI3yL0Ngofv5XqHHrjDg2G eKdF7Nbjl8qrlV7Mqy9jDgeY6agxQTj1JXtrmrYFgvHku/XiF430bfBVUj+s9ezgmlJZ pTGFbTp+rKsmnJ0j0Sqd+gDGAj2/EoD2DEB67j54KCih8VtfFzs3TaRStZEZ/UqlMCOQ 4pxBvlM0cVGgkg2oujnI8aD3TPrVkvYe+S9UdtNhdJdkGumeV7L5QH50BN57Lfju5edr 1cBvVH/1LZSPwqOCfmAbmfngETZQQxosTJfyRQRsuDhshTuRC3EQBN+tOgU156Vg8r4Y BDWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AQDlM29x6ygdS9Pi8RFktUUJqAuke0GTAHr2//YIM4A=; b=DsHt1cOvRVvg7nklawP5RooynsD42yL/XeOBr8Uq7RjxuBwB5GiSoQCypKf4Poi5IQ rPkXM5YoWWFOkSeE/ZY/cLHSRXi5gn6ZAjSDj9NeccZ7cNFwkVdkXSt7b5rHEX1kUb+Q 26HwrpOXTmeEokXyxJiA9vphj/OW/Np+fw0SRdT/X92VETB7BjKV9uaq7k73CI/MTAaS dALgMTZ2PqnwfzvOVGxo2326kr+PprxPnYjme1TW2u1LQ5pG8NacV6vTNgcL0B/F6xz/ G3659WlwZ8l0ruUYR06uzhxenns9dXkoAWBVybKE4mIWyCqfk+u+8WVMyDDFfZfbaCaZ RgfA== X-Gm-Message-State: AOUpUlEGShkBqgn0UKrk7dzgIHqQ9RmrfoWz5FPiPH5MN2EowCH8UzyT R0F0cHx/+4gH+OgQyhdaLZxRcbYQDuw= X-Google-Smtp-Source: AAOMgpcTKRBUMWzVHcrVqu5ub15Jig4lnbDbN0jtTtJc7//BKU/OUlYio+dpTVp/egLC6sGHUwkDKQ== X-Received: by 2002:a1c:6c14:: with SMTP id h20-v6mr2218384wmc.138.1533219023425; Thu, 02 Aug 2018 07:10:23 -0700 (PDT) Received: from NewMoon.iit.local ([90.147.180.254]) by smtp.gmail.com with ESMTPSA id d78-v6sm3392310wma.37.2018.08.02.07.10.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 02 Aug 2018 07:10:22 -0700 (PDT) From: Andrea Merello To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: v4-000linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello Subject: [PATCH v4 5/7] dmaengine: xilinx_dma: autodetect whether the HW supports scatter-gather Date: Thu, 2 Aug 2018 16:10:10 +0200 Message-Id: <20180802141012.19970-5-andrea.merello@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180802141012.19970-1-andrea.merello@gmail.com> References: <20180802141012.19970-1-andrea.merello@gmail.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The AXIDMA and CDMA HW can be either direct-access or scatter-gather version. These are SW incompatible. The driver can handle both versions: a DT property was used to tell the driver whether to assume the HW is in scatter-gather mode. This patch makes the driver to autodetect this information. The DT property is not required anymore. No changes for VDMA. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Radhey Shyam Pandey Signed-off-by: Andrea Merello Reviewed-by: Radhey Shyam Pandey --- Changes in v2: - autodetect only in !VDMA case Changes in v3: - cc DT maintainers/ML Changes in v4: - fix typos in commit message --- drivers/dma/xilinx/xilinx_dma.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index b17f24e4ec35..78d0f2f8225e 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -86,6 +86,7 @@ #define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6) #define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5) #define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4) +#define XILINX_DMA_DMASR_SG_MASK BIT(3) #define XILINX_DMA_DMASR_IDLE BIT(1) #define XILINX_DMA_DMASR_HALTED BIT(0) #define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24) @@ -407,7 +408,6 @@ struct xilinx_dma_config { * @dev: Device Structure * @common: DMA device structure * @chan: Driver specific DMA channel - * @has_sg: Specifies whether Scatter-Gather is present or not * @mcdma: Specifies whether Multi-Channel is present or not * @flush_on_fsync: Flush on frame sync * @ext_addr: Indicates 64 bit addressing is supported by dma device @@ -427,7 +427,6 @@ struct xilinx_dma_device { struct device *dev; struct dma_device common; struct xilinx_dma_chan *chan[XILINX_DMA_MAX_CHANS_PER_DEVICE]; - bool has_sg; bool mcdma; u32 flush_on_fsync; bool ext_addr; @@ -2400,7 +2399,6 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, chan->dev = xdev->dev; chan->xdev = xdev; - chan->has_sg = xdev->has_sg; chan->desc_pendingcount = 0x0; chan->ext_addr = xdev->ext_addr; /* This variable ensures that descriptors are not @@ -2493,6 +2491,15 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, chan->stop_transfer = xilinx_dma_stop_transfer; } + /* check if SG is enabled (only for AXIDMA and CDMA) */ + if (xdev->dma_config->dmatype != XDMA_TYPE_VDMA) { + if (dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) & + XILINX_DMA_DMASR_SG_MASK) + chan->has_sg = true; + dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id, + chan->has_sg ? "enabled" : "disabled"); + } + /* Initialize the tasklet */ tasklet_init(&chan->tasklet, xilinx_dma_do_tasklet, (unsigned long)chan); @@ -2631,7 +2638,6 @@ static int xilinx_dma_probe(struct platform_device *pdev) return PTR_ERR(xdev->regs); /* Retrieve the DMA engine properties from the device tree */ - xdev->has_sg = of_property_read_bool(node, "xlnx,include-sg"); xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0); if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { From patchwork Thu Aug 2 14:10:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Merello X-Patchwork-Id: 10553657 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6903415A6 for ; Thu, 2 Aug 2018 14:10:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 543E52C110 for ; Thu, 2 Aug 2018 14:10:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 489902C0A1; Thu, 2 Aug 2018 14:10:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B89AB2C130 for ; Thu, 2 Aug 2018 14:10:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732579AbeHBQBt (ORCPT ); Thu, 2 Aug 2018 12:01:49 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:53581 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732533AbeHBQBt (ORCPT ); Thu, 2 Aug 2018 12:01:49 -0400 Received: by mail-wm0-f67.google.com with SMTP id s9-v6so2688141wmh.3; Thu, 02 Aug 2018 07:10:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OFumUdGhZ7/Qo2AF6h3QVzXCRrFVnDrRwV2P55v4HHw=; b=hovCdr6bLm8TVWK0kHNpxnn89wuopWV6lIn6LDgsezkq27AUiCy7HZbs+XPWJkjVYx gqdjG83yAZN61ra0sWZoHUhd3+6Lh6i3hvq9vInPkIyVOlLw6zWpDJ6CX21VAqxMCPjg HkHDXD4JIMOQvWmMSyvMyFanuCE5JvSZvQfJW81S3k3HlqLEkDpIdPLtGuYmfxCQwPbz bUMCebnR6n1ti9EeWOcn7DWuEiQo5Xrm1D9G3EFpoUFSYJhUHAs+xfFShJdWvmFNUmQQ fA27bytWg0PoeAW+M3J1woYl93UVg39dyruCG5KRXdtDS4KQCJiTN+pElddRXa3Zn7+t q9sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OFumUdGhZ7/Qo2AF6h3QVzXCRrFVnDrRwV2P55v4HHw=; b=j6JvXUQMopc+eDYx6+dFpFtQNbIZFki1Dk29XPsV+DPsYH79rP+RkXAbBD61o+Nb22 59p51QzFgR3xXqBt2p8DgZshitslRXfB/eq7FsI9jM1jBvw7V63XVBwLH4ozXdq5529C eACRPmMLvvEl4E0U148bQePKLYHzVIM3hMBw/4PdYw8ARePcY7NNML1Qu7udnX6pKO4V ywS/wIMVpKkwfj4K6BO12L3fXpB4SUXp5KNdV7xX11Bmqfhr+PLswaBR4ger1f42ywvw YrSkTqgwZW0/wnAzMSBQcEx9oWoRAYF7vkOEXjG/WgRCNLOv2mO3BbpLXfCKS+H+GDlM g0fg== X-Gm-Message-State: AOUpUlFICKiqDwZdiuaqLVQMzyyguixJSug27KgH0fpmWOpe7VcoKnnK u3A6+9llf6H2FDct+y4KA98= X-Google-Smtp-Source: AAOMgpdyoZdKqc7ohkKhpoBeOYM5vOxXsdCI9oH9ErfvQ7HlkLtn+f1uZBSMu0O/Tcx8KAns2AexTA== X-Received: by 2002:a1c:3b54:: with SMTP id i81-v6mr2198153wma.143.1533219024796; Thu, 02 Aug 2018 07:10:24 -0700 (PDT) Received: from NewMoon.iit.local ([90.147.180.254]) by smtp.gmail.com with ESMTPSA id d78-v6sm3392310wma.37.2018.08.02.07.10.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 02 Aug 2018 07:10:23 -0700 (PDT) From: Andrea Merello To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: v4-000linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello Subject: [PATCH v4 6/7] dt-bindings: dmaengine: xilinx_dma: drop has-sg property Date: Thu, 2 Aug 2018 16:10:11 +0200 Message-Id: <20180802141012.19970-6-andrea.merello@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180802141012.19970-1-andrea.merello@gmail.com> References: <20180802141012.19970-1-andrea.merello@gmail.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This property is not needed anymore, because the driver now autodetects it. Delete references in documentation. Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Radhey Shyam Pandey Signed-off-by: Andrea Merello Reviewed-by: Radhey Shyam Pandey Reviewed-by: Rob Herring --- Changes in v2: - cc DT maintainer Changes in v3: - cc DT maintainerS/ML Changes in v4: None --- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 3 --- 1 file changed, 3 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index aec4a41a03ae..3051bc3713c6 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -37,9 +37,6 @@ Required properties: Required properties for VDMA: - xlnx,num-fstores: Should be the number of framebuffers as configured in h/w. -Optional properties: -- xlnx,include-sg: Tells configured for Scatter-mode in - the hardware. Optional properties for AXI DMA: - xlnx,sg-length-width: Should be set to the width in bits of the length register as configured in h/w. Takes values {8...26}. If the property From patchwork Thu Aug 2 14:10:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Merello X-Patchwork-Id: 10553659 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 418FE15A6 for ; Thu, 2 Aug 2018 14:10:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2FBDC2C137 for ; Thu, 2 Aug 2018 14:10:37 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2D5152C0AA; Thu, 2 Aug 2018 14:10:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 881852C13E for ; Thu, 2 Aug 2018 14:10:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732533AbeHBQBw (ORCPT ); Thu, 2 Aug 2018 12:01:52 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:55325 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732231AbeHBQBv (ORCPT ); Thu, 2 Aug 2018 12:01:51 -0400 Received: by mail-wm0-f65.google.com with SMTP id f21-v6so2678843wmc.5; Thu, 02 Aug 2018 07:10:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=S8SsR4dVdv/4wZtJLFjZ6eGrkCyYWI+YHEF2LPUUXRw=; b=cCoY8ViYeYEKuWFtYnZiXHjUKxCHN7Lco6eB00/SwPSoYkdWTv2ezY0ZAPBCIZ1EXM sgtPS/rQ0INqUkIgB6QUxM7JoU3STX1jkX0JsVJuGJIlSibBOWW9hv0mM81jFCD1muTx dyKwJ3qg5VVjjAw/jmlfvairTVcvvIZj8iBPwQUcyQ4+DbDQTM2RfoxyyfPLETcfmYls zoG3NCNwHQCZHHMMTzisa5SnR7CqerYL4Zq4KCsTYIbEgaCGMlgi2rOozAzvwX5zSDyO w8295+ktryYS+Qvv3BVcccGfkHmkxqCethP35lpeJN8w57XvODuPFoev4lT+2t7dDPpd 5rNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=S8SsR4dVdv/4wZtJLFjZ6eGrkCyYWI+YHEF2LPUUXRw=; b=oovZ7QG9xPmoaJpJyvOgRWNzJKbDAg7mwPzNgLNY++KpImf5t/CXGW1ay6ku6JHHkn 1rCQ3k4bnDHQMZHEw42vbOBxMnYKRCQxu+Uo/T5UDH8V4FP74b0lV+MGBIQ0h+hBy0N8 3w1/uqWjN4MxwCcGtjOKzhXr5CtO4PFaPFFcSFJaO72CqOsYjlYcvUxghbGCo/8ZbvbI Hjad7Io68/x5rT8PR16lPmMb/ZCmoKv2ST0feCBxwumVpySsF84/XYTMLf+kE8uwBo1O k0IqKXtKpL0q+3IOW4KGpMcD+nU45UJ4Ryzr8EFDz1QBTbKQHyCpNxEmjFkbH2t0GKi5 LR4g== X-Gm-Message-State: AOUpUlEoVt5d561XBCB9maB1QYv2MmfiJrRf+dsC4GXSP8rSrVT4QUbZ rOx0QdYRVjo4rNJamd/vsGU= X-Google-Smtp-Source: AAOMgpegeRYi5FPkVKWuQmFKPuFnKjsK589XEoSFhU0j9YYAkUmwdDZWWNcFB6TfnN0twXU98KmPvA== X-Received: by 2002:a1c:2142:: with SMTP id h63-v6mr2253193wmh.51.1533219026555; Thu, 02 Aug 2018 07:10:26 -0700 (PDT) Received: from NewMoon.iit.local ([90.147.180.254]) by smtp.gmail.com with ESMTPSA id d78-v6sm3392310wma.37.2018.08.02.07.10.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 02 Aug 2018 07:10:25 -0700 (PDT) From: Andrea Merello To: vkoul@kernel.org, dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, dmaengine@vger.kernel.org Cc: v4-000linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, radhey.shyam.pandey@xilinx.com, Andrea Merello Subject: [PATCH v4 7/7] dmaengine: xilinx_dma: Drop SG support for VDMA IP Date: Thu, 2 Aug 2018 16:10:12 +0200 Message-Id: <20180802141012.19970-7-andrea.merello@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180802141012.19970-1-andrea.merello@gmail.com> References: <20180802141012.19970-1-andrea.merello@gmail.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP xilinx_vdma_start_transfer() is used only for VDMA IP, still it contains conditional code on has_sg variable. has_sg is set only whenever the HW does support SG mode, that is never true for VDMA IP. This patch drops the never-taken branches. Signed-off-by: Andrea Merello --- Changes in V4: introduced this patch in series --- drivers/dma/xilinx/xilinx_dma.c | 84 +++++++++++++-------------------- 1 file changed, 32 insertions(+), 52 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 78d0f2f8225e..07ceadef0a00 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1093,6 +1093,8 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) struct xilinx_dma_tx_descriptor *desc, *tail_desc; u32 reg, j; struct xilinx_vdma_tx_segment *tail_segment; + struct xilinx_vdma_tx_segment *segment, *last = NULL; + int i = 0; /* This function was invoked with lock held */ if (chan->err) @@ -1112,14 +1114,6 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) tail_segment = list_last_entry(&tail_desc->segments, struct xilinx_vdma_tx_segment, node); - /* - * If hardware is idle, then all descriptors on the running lists are - * done, start new transfers - */ - if (chan->has_sg) - dma_ctrl_write(chan, XILINX_DMA_REG_CURDESC, - desc->async_tx.phys); - /* Configure the hardware using info in the config structure */ reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); @@ -1128,15 +1122,11 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) else reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN; - /* - * With SG, start with circular mode, so that BDs can be fetched. - * In direct register mode, if not parking, enable circular mode - */ - if (chan->has_sg || !config->park) - reg |= XILINX_DMA_DMACR_CIRC_EN; - + /* If not parking, enable circular mode */ if (config->park) reg &= ~XILINX_DMA_DMACR_CIRC_EN; + else + reg |= XILINX_DMA_DMACR_CIRC_EN; dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); @@ -1158,48 +1148,38 @@ static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) return; /* Start the transfer */ - if (chan->has_sg) { - dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC, - tail_segment->phys); - list_splice_tail_init(&chan->pending_list, &chan->active_list); - chan->desc_pendingcount = 0; - } else { - struct xilinx_vdma_tx_segment *segment, *last = NULL; - int i = 0; - - if (chan->desc_submitcount < chan->num_frms) - i = chan->desc_submitcount; - - list_for_each_entry(segment, &desc->segments, node) { - if (chan->ext_addr) - vdma_desc_write_64(chan, - XILINX_VDMA_REG_START_ADDRESS_64(i++), - segment->hw.buf_addr, - segment->hw.buf_addr_msb); - else - vdma_desc_write(chan, + if (chan->desc_submitcount < chan->num_frms) + i = chan->desc_submitcount; + + list_for_each_entry(segment, &desc->segments, node) { + if (chan->ext_addr) + vdma_desc_write_64(chan, + XILINX_VDMA_REG_START_ADDRESS_64(i++), + segment->hw.buf_addr, + segment->hw.buf_addr_msb); + else + vdma_desc_write(chan, XILINX_VDMA_REG_START_ADDRESS(i++), segment->hw.buf_addr); - last = segment; - } - - if (!last) - return; + last = segment; + } - /* HW expects these parameters to be same for one transaction */ - vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); - vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, - last->hw.stride); - vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); + if (!last) + return; - chan->desc_submitcount++; - chan->desc_pendingcount--; - list_del(&desc->node); - list_add_tail(&desc->node, &chan->active_list); - if (chan->desc_submitcount == chan->num_frms) - chan->desc_submitcount = 0; - } + /* HW expects these parameters to be same for one transaction */ + vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); + vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, + last->hw.stride); + vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); + + chan->desc_submitcount++; + chan->desc_pendingcount--; + list_del(&desc->node); + list_add_tail(&desc->node, &chan->active_list); + if (chan->desc_submitcount == chan->num_frms) + chan->desc_submitcount = 0; chan->idle = false; }