From patchwork Fri Apr 16 17:10:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12208291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 022C8C43460 for ; Fri, 16 Apr 2021 17:10:21 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AF504610CB for ; Fri, 16 Apr 2021 17:10:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AF504610CB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BAC186E1D6; Fri, 16 Apr 2021 17:10:19 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id D07C86E1B5 for ; Fri, 16 Apr 2021 17:10:17 +0000 (UTC) IronPort-SDR: NkCPh+xMYChRe0WpH5tMablZGBxaFmW7+uaISF5QAX7qB5aDO51We36UWXEwf0vFx2jSxfM6Gl +Yu8KbYxsBTw== X-IronPort-AV: E=McAfee;i="6200,9189,9956"; a="259027546" X-IronPort-AV: E=Sophos;i="5.82,226,1613462400"; d="scan'208";a="259027546" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2021 10:10:17 -0700 IronPort-SDR: thwEZXmcx0+ZCOASJyo9PyWFbZ//F+YCvm6i+d5BskGGvo257tVpHZZnyc8GRJF2sa0B5K1vzI chSa19w+PMeQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,226,1613462400"; d="scan'208";a="419177753" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga008.fm.intel.com with SMTP; 16 Apr 2021 10:10:15 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 16 Apr 2021 20:10:14 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 16 Apr 2021 20:10:04 +0300 Message-Id: <20210416171011.19012-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210416171011.19012-1-ville.syrjala@linux.intel.com> References: <20210416171011.19012-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/8] drm/i915: Collect dbuf device info into a sub-struct X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Collect the related dbuf information into a struct. Signed-off-by: Ville Syrjälä --- .../gpu/drm/i915/display/intel_display_power.c | 4 ++-- drivers/gpu/drm/i915/i915_pci.c | 16 ++++++++-------- drivers/gpu/drm/i915/intel_device_info.h | 6 ++++-- drivers/gpu/drm/i915/intel_pm.c | 14 +++++++------- 4 files changed, 21 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 0af1dee1ac95..0e433a0e1fce 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4777,7 +4777,7 @@ static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv, void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, u8 req_slices) { - int num_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices; + int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices; struct i915_power_domains *power_domains = &dev_priv->power_domains; enum dbuf_slice slice; @@ -4825,7 +4825,7 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv) { - const int num_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices; + int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices; enum dbuf_slice slice; for (slice = DBUF_S1; slice < (DBUF_S1 + num_slices); slice++) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 44e7b94db63d..484d2633894a 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -647,8 +647,8 @@ static const struct intel_device_info chv_info = { .has_gt_uc = 1, \ .display.has_hdcp = 1, \ .display.has_ipc = 1, \ - .ddb_size = 896, \ - .num_supported_dbuf_slices = 1 + .dbuf.size = 896, \ + .dbuf.num_slices = 1 #define SKL_PLATFORM \ GEN9_FEATURES, \ @@ -683,7 +683,7 @@ static const struct intel_device_info skl_gt4_info = { #define GEN9_LP_FEATURES \ GEN(9), \ .is_lp = 1, \ - .num_supported_dbuf_slices = 1, \ + .dbuf.num_slices = 1, \ .display.has_hotplug = 1, \ .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ @@ -720,14 +720,14 @@ static const struct intel_device_info skl_gt4_info = { static const struct intel_device_info bxt_info = { GEN9_LP_FEATURES, PLATFORM(INTEL_BROXTON), - .ddb_size = 512, + .dbuf.size = 512, }; static const struct intel_device_info glk_info = { GEN9_LP_FEATURES, PLATFORM(INTEL_GEMINILAKE), .display.ver = 10, - .ddb_size = 1024, + .dbuf.size = 1024, GLK_COLORS, }; @@ -790,7 +790,7 @@ static const struct intel_device_info cml_gt2_info = { #define GEN10_FEATURES \ GEN9_FEATURES, \ GEN(10), \ - .ddb_size = 1024, \ + .dbuf.size = 1024, \ .display.has_dsc = 1, \ .has_coherent_ggtt = false, \ GLK_COLORS @@ -830,8 +830,8 @@ static const struct intel_device_info cnl_info = { [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ }, \ GEN(11), \ - .ddb_size = 2048, \ - .num_supported_dbuf_slices = 2, \ + .dbuf.size = 2048, \ + .dbuf.num_slices = 2, \ .has_logical_ring_elsq = 1, \ .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 } diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 8ab4fa6c7fdd..74591e4f9c44 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -196,8 +196,10 @@ struct intel_device_info { #undef DEFINE_FLAG } display; - u16 ddb_size; /* in blocks */ - u8 num_supported_dbuf_slices; /* number of DBuf slices */ + struct { + u16 size; /* in blocks */ + u8 num_slices; + } dbuf; /* Register offsets for the various display pipes and transcoders */ int pipe_offsets[I915_MAX_TRANSCODERS]; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index eaf4c072ade0..ced1eb32cb78 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3637,10 +3637,10 @@ bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv) u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv) { int i; - int max_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices; + int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices; u8 enabled_slices_mask = 0; - for (i = 0; i < max_slices; i++) { + for (i = 0; i < num_slices; i++) { if (intel_uncore_read(&dev_priv->uncore, DBUF_CTL_S(i)) & DBUF_POWER_STATE) enabled_slices_mask |= BIT(i); } @@ -4030,7 +4030,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state) static int intel_dbuf_size(struct drm_i915_private *dev_priv) { - int ddb_size = INTEL_INFO(dev_priv)->ddb_size; + int ddb_size = INTEL_INFO(dev_priv)->dbuf.size; drm_WARN_ON(&dev_priv->drm, ddb_size == 0); @@ -4043,7 +4043,7 @@ static int intel_dbuf_size(struct drm_i915_private *dev_priv) static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv) { return intel_dbuf_size(dev_priv) / - INTEL_INFO(dev_priv)->num_supported_dbuf_slices; + INTEL_INFO(dev_priv)->dbuf.num_slices; } static void @@ -4070,8 +4070,8 @@ u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv, { u32 slice_mask = 0; u16 ddb_size = intel_dbuf_size(dev_priv); - u16 num_supported_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices; - u16 slice_size = ddb_size / num_supported_slices; + int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices; + u16 slice_size = ddb_size / num_slices; u16 start_slice; u16 end_slice; @@ -5828,7 +5828,7 @@ skl_compute_ddb(struct intel_atomic_state *state) "Enabled dbuf slices 0x%x -> 0x%x (out of %d dbuf slices)\n", old_dbuf_state->enabled_slices, new_dbuf_state->enabled_slices, - INTEL_INFO(dev_priv)->num_supported_dbuf_slices); + INTEL_INFO(dev_priv)->dbuf.num_slices); } for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { From patchwork Fri Apr 16 17:10:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12208293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ACA67C433B4 for ; Fri, 16 Apr 2021 17:10:23 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 73712610CB for ; Fri, 16 Apr 2021 17:10:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 73712610CB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 156026E1E9; Fri, 16 Apr 2021 17:10:23 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id DB3AD6E1E9 for ; Fri, 16 Apr 2021 17:10:21 +0000 (UTC) IronPort-SDR: fIz/CHIkO9AHN/lbuCyt11gHKUJtbZAvwXccD1Nh3tzKvfPbjX+e5/cutO7mIT5rlu4Xrv/XQI EdALiSmKDCuA== X-IronPort-AV: E=McAfee;i="6200,9189,9956"; a="195096716" X-IronPort-AV: E=Sophos;i="5.82,226,1613462400"; d="scan'208";a="195096716" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2021 10:10:20 -0700 IronPort-SDR: 5NmzeixOGX1uKCYxHcIm9gFez3q6gHpN2JT3UaBka/PdpLOXSw5zxUz2Gf24SY53cOK7gt+0WH 6sIbu3bG1PAQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,226,1613462400"; d="scan'208";a="425660862" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga008.jf.intel.com with SMTP; 16 Apr 2021 10:10:18 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 16 Apr 2021 20:10:17 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 16 Apr 2021 20:10:05 +0300 Message-Id: <20210416171011.19012-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210416171011.19012-1-ville.syrjala@linux.intel.com> References: <20210416171011.19012-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/8] drm/i915: Handle dbuf bypass path allocation earlier X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä We always reserve the same 4 dbuf blocks for the bypass path allocation, so might as well do that when declaring the dbuf size. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_pci.c | 8 ++++---- drivers/gpu/drm/i915/intel_pm.c | 9 +-------- 2 files changed, 5 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 484d2633894a..981d12702c49 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -647,7 +647,7 @@ static const struct intel_device_info chv_info = { .has_gt_uc = 1, \ .display.has_hdcp = 1, \ .display.has_ipc = 1, \ - .dbuf.size = 896, \ + .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \ .dbuf.num_slices = 1 #define SKL_PLATFORM \ @@ -720,14 +720,14 @@ static const struct intel_device_info skl_gt4_info = { static const struct intel_device_info bxt_info = { GEN9_LP_FEATURES, PLATFORM(INTEL_BROXTON), - .dbuf.size = 512, + .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ \ }; static const struct intel_device_info glk_info = { GEN9_LP_FEATURES, PLATFORM(INTEL_GEMINILAKE), .display.ver = 10, - .dbuf.size = 1024, + .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \ GLK_COLORS, }; @@ -790,7 +790,7 @@ static const struct intel_device_info cml_gt2_info = { #define GEN10_FEATURES \ GEN9_FEATURES, \ GEN(10), \ - .dbuf.size = 1024, \ + .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \ .display.has_dsc = 1, \ .has_coherent_ggtt = false, \ GLK_COLORS diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ced1eb32cb78..8d6ee5ad761e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4030,14 +4030,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state) static int intel_dbuf_size(struct drm_i915_private *dev_priv) { - int ddb_size = INTEL_INFO(dev_priv)->dbuf.size; - - drm_WARN_ON(&dev_priv->drm, ddb_size == 0); - - if (DISPLAY_VER(dev_priv) < 11) - return ddb_size - 4; /* 4 blocks for bypass path allocation */ - - return ddb_size; + return INTEL_INFO(dev_priv)->dbuf.size; } static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv) From patchwork Fri Apr 16 17:10:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12208295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF6D1C433ED for ; Fri, 16 Apr 2021 17:10:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6F9B16109F for ; Fri, 16 Apr 2021 17:10:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6F9B16109F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1F88A6EC7C; Fri, 16 Apr 2021 17:10:28 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 67CD96EC7C for ; Fri, 16 Apr 2021 17:10:26 +0000 (UTC) IronPort-SDR: a/mpBN/v+wHCC5DxOUgN6mvAHshWuH51T+RmCBdkU0+aIG05k4jaPfNj84WQ3h0cW1vx1WScnO O5f46JzYtzxw== X-IronPort-AV: E=McAfee;i="6200,9189,9956"; a="191881024" X-IronPort-AV: E=Sophos;i="5.82,226,1613462400"; d="scan'208";a="191881024" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2021 10:10:25 -0700 IronPort-SDR: tCBvZXmidIcPecsQeyvIGNmhAXBLD9bQQiVB8SR8Uf4x4/5W3vHIf9g6s15i5VZcXXc++rTtye bh7fTsK4bt9g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,226,1613462400"; d="scan'208";a="462020450" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga001.jf.intel.com with SMTP; 16 Apr 2021 10:10:21 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 16 Apr 2021 20:10:20 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 16 Apr 2021 20:10:06 +0300 Message-Id: <20210416171011.19012-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210416171011.19012-1-ville.syrjala@linux.intel.com> References: <20210416171011.19012-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/8] drm/i915: Store dbuf slice mask in device info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Let's just store the dbuf slice information as a bitmask in the device info. Makes life a little easier later. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display_power.c | 4 ++-- drivers/gpu/drm/i915/i915_pci.c | 6 +++--- drivers/gpu/drm/i915/intel_device_info.h | 2 +- drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++---- drivers/gpu/drm/i915/intel_pm.h | 1 + 5 files changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 0e433a0e1fce..0435103082eb 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4777,7 +4777,7 @@ static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv, void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, u8 req_slices) { - int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices; + int num_slices = intel_dbuf_num_slices(dev_priv); struct i915_power_domains *power_domains = &dev_priv->power_domains; enum dbuf_slice slice; @@ -4825,7 +4825,7 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv) { - int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices; + int num_slices = intel_dbuf_num_slices(dev_priv); enum dbuf_slice slice; for (slice = DBUF_S1; slice < (DBUF_S1 + num_slices); slice++) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 981d12702c49..15eb078fe6bb 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -648,7 +648,7 @@ static const struct intel_device_info chv_info = { .display.has_hdcp = 1, \ .display.has_ipc = 1, \ .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \ - .dbuf.num_slices = 1 + .dbuf.slice_mask = BIT(DBUF_S1) #define SKL_PLATFORM \ GEN9_FEATURES, \ @@ -683,7 +683,7 @@ static const struct intel_device_info skl_gt4_info = { #define GEN9_LP_FEATURES \ GEN(9), \ .is_lp = 1, \ - .dbuf.num_slices = 1, \ + .dbuf.slice_mask = BIT(DBUF_S1), \ .display.has_hotplug = 1, \ .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \ .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \ @@ -831,7 +831,7 @@ static const struct intel_device_info cnl_info = { }, \ GEN(11), \ .dbuf.size = 2048, \ - .dbuf.num_slices = 2, \ + .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \ .has_logical_ring_elsq = 1, \ .color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 } diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 74591e4f9c44..6aefe4fde197 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -198,7 +198,7 @@ struct intel_device_info { struct { u16 size; /* in blocks */ - u8 num_slices; + u8 slice_mask; } dbuf; /* Register offsets for the various display pipes and transcoders */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 8d6ee5ad761e..88eb54241b9f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3637,7 +3637,7 @@ bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv) u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv) { int i; - int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices; + int num_slices = intel_dbuf_num_slices(dev_priv); u8 enabled_slices_mask = 0; for (i = 0; i < num_slices; i++) { @@ -4033,10 +4033,15 @@ static int intel_dbuf_size(struct drm_i915_private *dev_priv) return INTEL_INFO(dev_priv)->dbuf.size; } +int intel_dbuf_num_slices(struct drm_i915_private *dev_priv) +{ + return hweight8(INTEL_INFO(dev_priv)->dbuf.slice_mask); +} + static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv) { return intel_dbuf_size(dev_priv) / - INTEL_INFO(dev_priv)->dbuf.num_slices; + intel_dbuf_num_slices(dev_priv); } static void @@ -4063,7 +4068,7 @@ u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv, { u32 slice_mask = 0; u16 ddb_size = intel_dbuf_size(dev_priv); - int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices; + int num_slices = intel_dbuf_num_slices(dev_priv); u16 slice_size = ddb_size / num_slices; u16 start_slice; u16 end_slice; @@ -5821,7 +5826,7 @@ skl_compute_ddb(struct intel_atomic_state *state) "Enabled dbuf slices 0x%x -> 0x%x (out of %d dbuf slices)\n", old_dbuf_state->enabled_slices, new_dbuf_state->enabled_slices, - INTEL_INFO(dev_priv)->dbuf.num_slices); + intel_dbuf_num_slices(dev_priv)); } for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index 669c8d505677..7dc11dec8984 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -38,6 +38,7 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv); void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv); void skl_wm_get_hw_state(struct drm_i915_private *dev_priv); u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv); +int intel_dbuf_num_slices(struct drm_i915_private *dev_priv); void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, struct skl_ddb_entry *ddb_y, struct skl_ddb_entry *ddb_uv); From patchwork Fri Apr 16 17:10:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12208297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03B42C43461 for ; Fri, 16 Apr 2021 17:10:32 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C51A96109F for ; Fri, 16 Apr 2021 17:10:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C51A96109F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 78B1D6EC88; Fri, 16 Apr 2021 17:10:31 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6B7036EC88 for ; Fri, 16 Apr 2021 17:10:30 +0000 (UTC) IronPort-SDR: F9dOb8O3+OXa2WETGqrKo9m09Cu2VkI4EcPtYiSWxIlilCkjbqOd9h33LgKPzkqBQyYm36tyjQ kE+W5QDrS3qg== X-IronPort-AV: E=McAfee;i="6200,9189,9956"; a="215609219" X-IronPort-AV: E=Sophos;i="5.82,226,1613462400"; d="scan'208";a="215609219" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2021 10:10:29 -0700 IronPort-SDR: t/iZuxG1ezhWPaGtTRINM39kx5Dr+IUHgtGW3d8v0JU4ywISIzG324nq6f+qQlGdDT/Fh93E6B Gr03QLu52rPg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,226,1613462400"; d="scan'208";a="522764596" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by fmsmga001.fm.intel.com with SMTP; 16 Apr 2021 10:10:26 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 16 Apr 2021 20:10:24 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 16 Apr 2021 20:10:07 +0300 Message-Id: <20210416171011.19012-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210416171011.19012-1-ville.syrjala@linux.intel.com> References: <20210416171011.19012-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/8] drm/i915: Use intel_dbuf_slice_size() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Use intel_dbuf_slice_size() instead of hand rolling it. Also clean up some of the types. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 88eb54241b9f..38e2ba45bfd8 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4066,12 +4066,9 @@ skl_ddb_entry_for_slices(struct drm_i915_private *dev_priv, u8 slice_mask, u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv, const struct skl_ddb_entry *entry) { - u32 slice_mask = 0; - u16 ddb_size = intel_dbuf_size(dev_priv); - int num_slices = intel_dbuf_num_slices(dev_priv); - u16 slice_size = ddb_size / num_slices; - u16 start_slice; - u16 end_slice; + int slice_size = intel_dbuf_slice_size(dev_priv); + enum dbuf_slice start_slice, end_slice; + u8 slice_mask = 0; if (!skl_ddb_entry_size(entry)) return 0; From patchwork Fri Apr 16 17:10:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12208299 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C0CBC433B4 for ; Fri, 16 Apr 2021 17:10:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 51DAA61073 for ; Fri, 16 Apr 2021 17:10:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 51DAA61073 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 032376EC7A; Fri, 16 Apr 2021 17:10:34 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 15AD56EC7A for ; Fri, 16 Apr 2021 17:10:32 +0000 (UTC) IronPort-SDR: bdkWOZ/PNaiMKhVgzyEZ3PlefE1EWmF4bTQ+45rv9spvwJyW4XFdDgbdkahrdxjyU005+eZhLU pOmaDGk5b9oQ== X-IronPort-AV: E=McAfee;i="6200,9189,9956"; a="182196985" X-IronPort-AV: E=Sophos;i="5.82,226,1613462400"; d="scan'208";a="182196985" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2021 10:10:32 -0700 IronPort-SDR: YmocjL9TCP8yfZWlfbZNdn/3BCiASpHnt93Pq88/c7Q+iDr7M6Mchol2Do1CM2rmiVFMx9f49H OFDZLWPr3jJQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,226,1613462400"; d="scan'208";a="399966189" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga002.jf.intel.com with SMTP; 16 Apr 2021 10:10:30 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 16 Apr 2021 20:10:29 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 16 Apr 2021 20:10:08 +0300 Message-Id: <20210416171011.19012-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210416171011.19012-1-ville.syrjala@linux.intel.com> References: <20210416171011.19012-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/8] drm/i915: Use intel_de_rmw() for DBUF_POWER_REQUEST X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Use intel_de_rmw() instead of hand rolling it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display_power.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 0435103082eb..528fbede0ee7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4757,14 +4757,9 @@ static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv, { i915_reg_t reg = DBUF_CTL_S(slice); bool state; - u32 val; - val = intel_de_read(dev_priv, reg); - if (enable) - val |= DBUF_POWER_REQUEST; - else - val &= ~DBUF_POWER_REQUEST; - intel_de_write(dev_priv, reg, val); + intel_de_rmw(dev_priv, reg, DBUF_POWER_REQUEST, + enable ? DBUF_POWER_REQUEST : 0); intel_de_posting_read(dev_priv, reg); udelay(10); From patchwork Fri Apr 16 17:10:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12208301 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8022C433ED for ; Fri, 16 Apr 2021 17:10:37 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8FA1961073 for ; Fri, 16 Apr 2021 17:10:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8FA1961073 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3A7B56EC89; Fri, 16 Apr 2021 17:10:37 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 518716EC89 for ; Fri, 16 Apr 2021 17:10:36 +0000 (UTC) IronPort-SDR: XmzwEhxJFua7PEp2HAXxdMaFDXM343qiOg0uVtoqXnG5vMIom7rw6h72i/ips9C5sxPu6DJuwx 7OzqniTPxScA== X-IronPort-AV: E=McAfee;i="6200,9189,9956"; a="182197002" X-IronPort-AV: E=Sophos;i="5.82,226,1613462400"; d="scan'208";a="182197002" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2021 10:10:35 -0700 IronPort-SDR: PkJfWBIvMgN6Mpol2ya5J5SiVmntmR9OFsZzWtjwdhtFaTt/Dj6zQi+sFAyQO9Evk+MrwwcLPq A2okSdk9vPwg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,226,1613462400"; d="scan'208";a="451518108" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by FMSMGA003.fm.intel.com with SMTP; 16 Apr 2021 10:10:33 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 16 Apr 2021 20:10:32 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 16 Apr 2021 20:10:09 +0300 Message-Id: <20210416171011.19012-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210416171011.19012-1-ville.syrjala@linux.intel.com> References: <20210416171011.19012-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 6/8] drm/i915: Polish for_each_dbuf_slice() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Now that we have the dbuf slice mask stored in the device info let's use it for for_each_dbuf_slice_in_mask*(). With this we cal also rip out intel_dbuf_size() and intel_dbuf_num_slices(). Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_bw.c | 11 +++--- drivers/gpu/drm/i915/display/intel_display.h | 9 ++--- .../drm/i915/display/intel_display_power.c | 13 ++++--- drivers/gpu/drm/i915/intel_pm.c | 34 +++++++------------ 4 files changed, 29 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 20dbc3759d27..969169743630 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -390,7 +390,6 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) const struct intel_crtc_state *crtc_state; struct intel_crtc *crtc; int max_bw = 0; - int slice_id; enum pipe pipe; int i; @@ -418,6 +417,7 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) &crtc_state->wm.skl.plane_ddb_uv[plane_id]; unsigned int data_rate = crtc_state->data_rate[plane_id]; unsigned int dbuf_mask = 0; + enum dbuf_slice slice; dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, plane_alloc); dbuf_mask |= skl_ddb_dbuf_slice_mask(dev_priv, uv_plane_alloc); @@ -435,8 +435,8 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) * pessimistic, which shouldn't pose any significant * problem anyway. */ - for_each_dbuf_slice_in_mask(slice_id, dbuf_mask) - crtc_bw->used_bw[slice_id] += data_rate; + for_each_dbuf_slice_in_mask(dev_priv, slice, dbuf_mask) + crtc_bw->used_bw[slice] += data_rate; } } @@ -445,10 +445,11 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) for_each_pipe(dev_priv, pipe) { struct intel_dbuf_bw *crtc_bw; + enum dbuf_slice slice; crtc_bw = &new_bw_state->dbuf_bw[pipe]; - for_each_dbuf_slice(slice_id) { + for_each_dbuf_slice(dev_priv, slice) { /* * Current experimental observations show that contrary * to BSpec we get underruns once we exceed 64 * CDCLK @@ -457,7 +458,7 @@ int skl_bw_calc_min_cdclk(struct intel_atomic_state *state) * bumped up all the time we calculate CDCLK according * to this formula for overall bw consumed by slices. */ - max_bw += crtc_bw->used_bw[slice_id]; + max_bw += crtc_bw->used_bw[slice]; } } diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 105294ec2dcc..b68bcd502206 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -188,12 +188,13 @@ enum plane_id { for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ for_each_if((__crtc)->plane_ids_mask & BIT(__p)) -#define for_each_dbuf_slice_in_mask(__slice, __mask) \ +#define for_each_dbuf_slice(__dev_priv, __slice) \ for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \ - for_each_if((BIT(__slice)) & (__mask)) + for_each_if(INTEL_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice)) -#define for_each_dbuf_slice(__slice) \ - for_each_dbuf_slice_in_mask(__slice, BIT(I915_MAX_DBUF_SLICES) - 1) +#define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \ + for_each_dbuf_slice((__dev_priv), (__slice)) \ + for_each_if((__mask) & BIT(__slice)) enum port { PORT_NONE = -1, diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 528fbede0ee7..0fb4864a191a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4772,13 +4772,13 @@ static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv, void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, u8 req_slices) { - int num_slices = intel_dbuf_num_slices(dev_priv); struct i915_power_domains *power_domains = &dev_priv->power_domains; + u8 slice_mask = INTEL_INFO(dev_priv)->dbuf.slice_mask; enum dbuf_slice slice; - drm_WARN(&dev_priv->drm, req_slices & ~(BIT(num_slices) - 1), - "Invalid set of dbuf slices (0x%x) requested (num dbuf slices %d)\n", - req_slices, num_slices); + drm_WARN(&dev_priv->drm, req_slices & ~slice_mask, + "Invalid set of dbuf slices (0x%x) requested (total dbuf slices 0x%x)\n", + req_slices, slice_mask); drm_dbg_kms(&dev_priv->drm, "Updating dbuf slices to 0x%x\n", req_slices); @@ -4792,7 +4792,7 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, */ mutex_lock(&power_domains->lock); - for (slice = DBUF_S1; slice < num_slices; slice++) + for_each_dbuf_slice(dev_priv, slice) gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice)); dev_priv->dbuf.enabled_slices = req_slices; @@ -4820,10 +4820,9 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv) { - int num_slices = intel_dbuf_num_slices(dev_priv); enum dbuf_slice slice; - for (slice = DBUF_S1; slice < (DBUF_S1 + num_slices); slice++) + for_each_dbuf_slice(dev_priv, slice) intel_de_rmw(dev_priv, DBUF_CTL_S(slice), DBUF_TRACKER_STATE_SERVICE_MASK, DBUF_TRACKER_STATE_SERVICE(8)); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 38e2ba45bfd8..155f41ed9dee 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3636,16 +3636,16 @@ bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv) u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv) { - int i; - int num_slices = intel_dbuf_num_slices(dev_priv); - u8 enabled_slices_mask = 0; + u8 enabled_slices = 0; + enum dbuf_slice slice; - for (i = 0; i < num_slices; i++) { - if (intel_uncore_read(&dev_priv->uncore, DBUF_CTL_S(i)) & DBUF_POWER_STATE) - enabled_slices_mask |= BIT(i); + for_each_dbuf_slice(dev_priv, slice) { + if (intel_uncore_read(&dev_priv->uncore, + DBUF_CTL_S(slice)) & DBUF_POWER_STATE) + enabled_slices |= BIT(slice); } - return enabled_slices_mask; + return enabled_slices; } /* @@ -4028,20 +4028,10 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state) return 0; } -static int intel_dbuf_size(struct drm_i915_private *dev_priv) -{ - return INTEL_INFO(dev_priv)->dbuf.size; -} - -int intel_dbuf_num_slices(struct drm_i915_private *dev_priv) -{ - return hweight8(INTEL_INFO(dev_priv)->dbuf.slice_mask); -} - static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv) { - return intel_dbuf_size(dev_priv) / - intel_dbuf_num_slices(dev_priv); + return INTEL_INFO(dev_priv)->dbuf.size / + hweight8(INTEL_INFO(dev_priv)->dbuf.slice_mask); } static void @@ -4060,7 +4050,7 @@ skl_ddb_entry_for_slices(struct drm_i915_private *dev_priv, u8 slice_mask, ddb->end = fls(slice_mask) * slice_size; WARN_ON(ddb->start >= ddb->end); - WARN_ON(ddb->end > intel_dbuf_size(dev_priv)); + WARN_ON(ddb->end > INTEL_INFO(dev_priv)->dbuf.size); } u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv, @@ -5820,10 +5810,10 @@ skl_compute_ddb(struct intel_atomic_state *state) return ret; drm_dbg_kms(&dev_priv->drm, - "Enabled dbuf slices 0x%x -> 0x%x (out of %d dbuf slices)\n", + "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x)\n", old_dbuf_state->enabled_slices, new_dbuf_state->enabled_slices, - intel_dbuf_num_slices(dev_priv)); + INTEL_INFO(dev_priv)->dbuf.slice_mask); } for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { From patchwork Fri Apr 16 17:10:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12208303 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4464C433B4 for ; Fri, 16 Apr 2021 17:10:41 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4D0A96109F for ; Fri, 16 Apr 2021 17:10:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4D0A96109F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BFFFC6EC8C; Fri, 16 Apr 2021 17:10:40 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 38DBE6EC8A for ; Fri, 16 Apr 2021 17:10:39 +0000 (UTC) IronPort-SDR: /bRbKeySD6XwHK5QxLPSg3B18+t8Zm5W8A31qYh4Imo014mTtfO1hWgPHz7kIlJ4LynZ2PbhG1 eimmerBxNS2A== X-IronPort-AV: E=McAfee;i="6200,9189,9956"; a="174563919" X-IronPort-AV: E=Sophos;i="5.82,226,1613462400"; d="scan'208";a="174563919" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2021 10:10:38 -0700 IronPort-SDR: sFojulemVVUVwuWbYlvEaERP7WkJbHNEOumUfNjyGj65qIHyU4xn05uPZcV4BXtmbv6ydjHYv0 CLKUtZcvl9IA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,226,1613462400"; d="scan'208";a="384377453" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga006.jf.intel.com with SMTP; 16 Apr 2021 10:10:36 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 16 Apr 2021 20:10:35 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 16 Apr 2021 20:10:10 +0300 Message-Id: <20210416171011.19012-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210416171011.19012-1-ville.syrjala@linux.intel.com> References: <20210416171011.19012-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 7/8] drm/i915: Add enabledisable() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä 'enable ? "enable" : "disable"' is a fairly common pattern in out debug prints. Let's introduce a helper for it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_ddi.c | 4 ++-- drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 2 +- drivers/gpu/drm/i915/i915_utils.h | 5 +++++ 5 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 4ef573883412..f4249f087fa7 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2334,8 +2334,8 @@ static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0) drm_dbg_kms(&i915->drm, - "Failed to set MSA_TIMING_PAR_IGNORE %s in the sink\n", - enable ? "enable" : "disable"); + "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n", + enabledisable(enable)); } static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 0fb4864a191a..d48dd15a4f6e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -4766,7 +4766,7 @@ static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv, state = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE; drm_WARN(&dev_priv->drm, enable != state, "DBuf slice %d power %s timeout!\n", - slice, enable ? "enable" : "disable"); + slice, enabledisable(enable)); } void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 5ee953aaa00c..44109a4b69aa 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1861,7 +1861,7 @@ void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, if (ret < 0) drm_dbg_kms(&i915->drm, "Failed to %s sink decompression state\n", - enable ? "enable" : "disable"); + enabledisable(enable)); } static void diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c index 4f8337c7fd2e..8e9ac9ba1d38 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c @@ -291,7 +291,7 @@ static void set_vesa_backlight_enable(struct intel_dp *intel_dp, bool enable) if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, reg_val) != 1) { drm_dbg_kms(&i915->drm, "Failed to %s aux backlight\n", - enable ? "enable" : "disable"); + enabledisable(enable)); } } diff --git a/drivers/gpu/drm/i915/i915_utils.h b/drivers/gpu/drm/i915/i915_utils.h index abd4dcd9f79c..f02f52ab5070 100644 --- a/drivers/gpu/drm/i915/i915_utils.h +++ b/drivers/gpu/drm/i915/i915_utils.h @@ -418,6 +418,11 @@ static inline const char *onoff(bool v) return v ? "on" : "off"; } +static inline const char *enabledisable(bool v) +{ + return v ? "enable" : "disable"; +} + static inline const char *enableddisabled(bool v) { return v ? "enabled" : "disabled"; From patchwork Fri Apr 16 17:10:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 12208305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BEC6C433ED for ; Fri, 16 Apr 2021 17:10:43 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 159E26109F for ; Fri, 16 Apr 2021 17:10:43 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 159E26109F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B74E06EC8B; Fri, 16 Apr 2021 17:10:42 +0000 (UTC) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 93D876EC8B for ; Fri, 16 Apr 2021 17:10:41 +0000 (UTC) IronPort-SDR: D4RHsngdI+cYbz4P2R34aY/tBNB+T+Bwn6L69sOuvxlAYV5dO3ONfcEIzS3p17a+C6uM0EFbX1 tCmV5ccT/slA== X-IronPort-AV: E=McAfee;i="6200,9189,9956"; a="194629343" X-IronPort-AV: E=Sophos;i="5.82,226,1613462400"; d="scan'208";a="194629343" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2021 10:10:41 -0700 IronPort-SDR: t6NmdDnzkjOyimpOKcJF47QuP8HV2qCvPS2x83u2J9M1tSl1n5Epn1b6rrt/5cJnRy1v7gUpkO cvbOJ3g6gLFA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,226,1613462400"; d="scan'208";a="422061324" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga007.jf.intel.com with SMTP; 16 Apr 2021 10:10:39 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 16 Apr 2021 20:10:38 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 16 Apr 2021 20:10:11 +0300 Message-Id: <20210416171011.19012-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210416171011.19012-1-ville.syrjala@linux.intel.com> References: <20210416171011.19012-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 8/8] drm/i915: Say "enable foo" instead of "set foo to enabled" X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Use simpler sentences. Just say "enable foo" instead of "set foo to enabled" etc. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++------ drivers/gpu/drm/i915/display/intel_tc.c | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 44109a4b69aa..52ea09fc5e70 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2293,8 +2293,8 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1) - drm_dbg_kms(&i915->drm, "Failed to set protocol converter HDMI mode to %s\n", - enableddisabled(intel_dp->has_hdmi_sink)); + drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n", + enabledisable(intel_dp->has_hdmi_sink)); tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 && intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0; @@ -2302,8 +2302,8 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1) drm_dbg_kms(&i915->drm, - "Failed to set protocol converter YCbCr 4:2:0 conversion mode to %s\n", - enableddisabled(intel_dp->dfp.ycbcr_444_to_420)); + "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n", + enabledisable(intel_dp->dfp.ycbcr_444_to_420)); tmp = 0; if (intel_dp->dfp.rgb_to_ycbcr) { @@ -2340,8 +2340,8 @@ void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0) drm_dbg_kms(&i915->drm, - "Failed to set protocol converter RGB->YCbCr conversion mode to %s\n", - enableddisabled(tmp ? true : false)); + "Failed to %s protocol converter RGB->YCbCr conversion mode\n", + enabledisable(tmp)); } diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 88085486ee59..59de6ca436db 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -267,8 +267,8 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port, PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia)); if (val == 0xffffffff) { drm_dbg_kms(&i915->drm, - "Port %s: PHY in TCCOLD, can't set safe-mode to %s\n", - dig_port->tc_port_name, enableddisabled(enable)); + "Port %s: PHY in TCCOLD, can't %s safe-mode\n", + dig_port->tc_port_name, enabledisable(enable)); return false; }