From patchwork Sun Apr 18 12:29:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Dudziak X-Patchwork-Id: 12210067 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDCA5C43460 for ; Sun, 18 Apr 2021 12:29:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BEE926121D for ; Sun, 18 Apr 2021 12:29:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231289AbhDRMaX (ORCPT ); Sun, 18 Apr 2021 08:30:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231272AbhDRMaX (ORCPT ); Sun, 18 Apr 2021 08:30:23 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAD31C06138D for ; Sun, 18 Apr 2021 05:29:54 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id sd23so40092997ejb.12 for ; Sun, 18 Apr 2021 05:29:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=snejp.pl; s=gmail; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AY49ZkjnSg9kfOd0WfKMTqMjQUL3RB3pacUpkz2Yd+A=; b=FY52ar2b+khkU/uMRuvnpXVjZUqDo/ehJx16Suwl8fKZWh1EQfo1RXEwfMgTDQLbTu cVSHZ8ulOaXnGUhj2NmHsCDo1BH06IJk35TnAH0LUUPfNd2GmtvU/7SsRhe76oAKyBFL kqMFfV26j8xP56c1cqpPmFd+rs2NizKUf/i13TefvF5U7YxmYK5VfyzckVFrH0psWCra 5IXT44EBNcpZpj3ZA7ODCBq/AvGLaTczlqPCAGAcAK6uVqCCHIE6spSdw9JL2G6/QOiN BNOfrbdUuMrSf8LztwWVOkCcFTCYnRNUydVwr9PO3LBReT2vHQeCn3neqB6C1AMCHBYe wPHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AY49ZkjnSg9kfOd0WfKMTqMjQUL3RB3pacUpkz2Yd+A=; b=Q9FJ0QryD6cUs3FtmQdDT6CAC0YzHkJ3oegcftDFyqpVHHTEfusprv0F9HUx6grymt iTFshSneCeEDQd94RJpT02NFMNAi37KiqMpf9ADn9jFQc93H4Fz+XcbOoNuivc1YSXNC 7TTUnXAASj2PfOoMkVCT6LiDOiWWkf0n2oWxehUOkkgOVWhwK4g3kdVie9DrPltsPxeR EiWWpl7CUNa72q+b+8lJh+lKCSf97/skCifx5W6dDHjNv9H3dl0+H/XZbh994pIQBVRK VLADFc84NFK33XR4eMqoe7kNhfwU+34aJosiHkDxyvNWzmcJzyheUAVcOm5sUHBL7p6T Y/Tw== X-Gm-Message-State: AOAM532SRrv7hfAg6IcKHaucj7M7/PxX+M7+3ANX9Pi5gWidVz5XUbcR 4gPv7mWwrW6EsoDpxQ2ERcmsNA== X-Google-Smtp-Source: ABdhPJwcHkDeJOuSa7z1fqurBb+BxTsL/ad2TV7UB8tAkIJiLW3yVGIgSYiNsPmmKXnUmzhLl9MT1g== X-Received: by 2002:a17:906:6a49:: with SMTP id n9mr17225687ejs.397.1618748993499; Sun, 18 Apr 2021 05:29:53 -0700 (PDT) Received: from PackardBell (87-49-44-144-mobile.dk.customer.tdc.net. [87.49.44.144]) by smtp.googlemail.com with ESMTPSA id a27sm8213677ejk.80.2021.04.18.05.29.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 05:29:53 -0700 (PDT) Received: from localhost (PackardBell [local]) by PackardBell (OpenSMTPD) with ESMTPA id bc27f693; Sun, 18 Apr 2021 12:29:49 +0000 (UTC) From: Bartosz Dudziak To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Bartosz Dudziak Subject: [PATCH v2 1/5] dt-bindings: clock: qcom: Add MSM8226 GCC clock bindings Date: Sun, 18 Apr 2021 14:29:05 +0200 Message-Id: <20210418122909.71434-2-bartosz.dudziak@snejp.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210418122909.71434-1-bartosz.dudziak@snejp.pl> References: <20210418122909.71434-1-bartosz.dudziak@snejp.pl> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add compatible device strings and the include files for the MSM8226 GCC. Signed-off-by: Bartosz Dudziak Acked-by: Rob Herring --- Documentation/devicetree/bindings/clock/qcom,gcc.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml index ee0467fb5e..eddf10e6a4 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml @@ -26,8 +26,8 @@ description: | - dt-bindings/reset/qcom,gcc-msm8939.h - dt-bindings/clock/qcom,gcc-msm8660.h - dt-bindings/reset/qcom,gcc-msm8660.h - - dt-bindings/clock/qcom,gcc-msm8974.h - - dt-bindings/reset/qcom,gcc-msm8974.h + - dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974) + - dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974) - dt-bindings/clock/qcom,gcc-msm8994.h - dt-bindings/clock/qcom,gcc-mdm9615.h - dt-bindings/reset/qcom,gcc-mdm9615.h @@ -41,6 +41,7 @@ properties: - qcom,gcc-ipq4019 - qcom,gcc-ipq6018 - qcom,gcc-ipq8064 + - qcom,gcc-msm8226 - qcom,gcc-msm8660 - qcom,gcc-msm8916 - qcom,gcc-msm8939 From patchwork Sun Apr 18 12:29:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Dudziak X-Patchwork-Id: 12210071 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C29F9C43460 for ; Sun, 18 Apr 2021 12:30:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AB6416121D for ; Sun, 18 Apr 2021 12:30:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234974AbhDRMa0 (ORCPT ); Sun, 18 Apr 2021 08:30:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230321AbhDRMaZ (ORCPT ); Sun, 18 Apr 2021 08:30:25 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18973C061760 for ; Sun, 18 Apr 2021 05:29:56 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id w3so48783466ejc.4 for ; Sun, 18 Apr 2021 05:29:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=snejp.pl; s=gmail; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4A6FPGrlO6kpSswS7bbG6MaMQMQDFra9fHiDSeFEH7g=; b=MF9fvBxFoKrpNEHUx/WiR5Y3pqFHBlfVGh+uqOr1jVY+A47/wdiOJQ1vRilwxSEO7e AhNaeDVk+nYNkQrxoQRv+ACJup2ObioyBFppka7bQ5RJUhOSbQHYf6MtylzcX+/Ks0fw aVSpBhiTODanmieZKFERvQi8WlpML5Owsh0pNXSKPQGKS6FIdSv0mDVMDRnhJ5uzMJO2 nmXrIi37ZWCqMe63pvT5QgGpXmNg2LJK51Ex0sT0+Zuobo31PmsZZ2CLWq1iTBDrzj8Y l8HaZNTmxdsg0PLFzrOf0FmyE1FaoFD7CU5rhD1dxBLNbfxKrH4PJDZ7PiLGnQjwlc3U xeMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4A6FPGrlO6kpSswS7bbG6MaMQMQDFra9fHiDSeFEH7g=; b=HKPM4igH43ZlaW5v9qnHOrHpFdckZRPctynitQdgPzjrh3WntKBvoMNDqR+lgxz14X RIH9E8J9lx9Nb+PnoAenG6GrdGe13CeG28HouIaLBaWfXJTgmAFTK067a+yIkh7m5QTq s/E45UCXOvl4Id0g17EKXhdHUbDIvbc1/GKrT1Y0b0aoIFr5hrbXfUmRGBs7Q1Xt/4FG y4dop7/sZ+VYY776qZcbD1306uyvxzSWz85M/P8TFECt84y/w8bfM7hRFJMU8haihc58 KJcpZtv82RgAqYTGDl+bOjNfbJPX/rj4nMdfvPPVfE6Kg+UWsQETEMIamRbjuvGq15K8 hnRQ== X-Gm-Message-State: AOAM530wf7GCDcv0gOtCbjHNb4kMiT28XN9uMckE9j1vZRRKn7MMRo07 Hvy6XhAdpX4b1rXWSZmaCAzB3g== X-Google-Smtp-Source: ABdhPJyyQ/XLKWfuDUdzycN9/1FsuwYBpF53NsU26kE2zcvN+SM6aCaHDLNAcWbPcZ6D/NImYtECXg== X-Received: by 2002:a17:906:3385:: with SMTP id v5mr17293970eja.539.1618748994684; Sun, 18 Apr 2021 05:29:54 -0700 (PDT) Received: from PackardBell (87-49-44-144-mobile.dk.customer.tdc.net. [87.49.44.144]) by smtp.googlemail.com with ESMTPSA id a27sm8213677ejk.80.2021.04.18.05.29.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 05:29:54 -0700 (PDT) Received: from localhost (PackardBell [local]) by PackardBell (OpenSMTPD) with ESMTPA id 7c6259bf; Sun, 18 Apr 2021 12:29:50 +0000 (UTC) From: Bartosz Dudziak To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Bartosz Dudziak Subject: [PATCH v2 2/5] clk: qcom: gcc: Add support for Global Clock controller found on MSM8226 Date: Sun, 18 Apr 2021 14:29:06 +0200 Message-Id: <20210418122909.71434-3-bartosz.dudziak@snejp.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210418122909.71434-1-bartosz.dudziak@snejp.pl> References: <20210418122909.71434-1-bartosz.dudziak@snejp.pl> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Modify existing MSM8974 driver to support MSM8226 SoC. Override frequencies which are different in this older chip. Register all the clocks to the framework for the clients to be able to request for them. Signed-off-by: Bartosz Dudziak --- drivers/clk/qcom/gcc-msm8974.c | 169 +++++++++++++++++++++++++++++++-- 1 file changed, 162 insertions(+), 7 deletions(-) diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c index 740d3c44c0..bf305fa9e5 100644 --- a/drivers/clk/qcom/gcc-msm8974.c +++ b/drivers/clk/qcom/gcc-msm8974.c @@ -719,6 +719,12 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = { }, }; +static const struct freq_tbl ftbl_gcc_ce1_clk_msm8226[] = { + F(50000000, P_GPLL0, 12, 0, 0), + F(100000000, P_GPLL0, 6, 0, 0), + { } +}; + static const struct freq_tbl ftbl_gcc_ce1_clk[] = { F(50000000, P_GPLL0, 12, 0, 0), F(75000000, P_GPLL0, 8, 0, 0), @@ -761,6 +767,11 @@ static struct clk_rcg2 ce2_clk_src = { }, }; +static const struct freq_tbl ftbl_gcc_gp_clk_msm8226[] = { + F(19200000, P_XO, 1, 0, 0), + { } +}; + static const struct freq_tbl ftbl_gcc_gp_clk[] = { F(4800000, P_XO, 4, 0, 0), F(6000000, P_GPLL0, 10, 1, 10), @@ -1955,6 +1966,10 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mss_q6_bimc_axi_clk", + .parent_names = (const char *[]){ + "system_noc_clk_src", + }, + .num_parents = 1, .ops = &clk_branch2_ops, }, }, @@ -1993,6 +2008,20 @@ static struct clk_branch gcc_pdm_ahb_clk = { }, }; +static struct clk_branch gcc_pdm_xo4_clk = { + .halt_reg = 0x0cc8, + .clkr = { + .enable_reg = 0x0cc8, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm_xo4_clk", + .parent_names = (const char *[]){ "xo" }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_prng_ahb_clk = { .halt_reg = 0x0d04, .halt_check = BRANCH_HALT_VOTED, @@ -2430,6 +2459,121 @@ static struct gdsc usb_hs_hsic_gdsc = { .pwrsts = PWRSTS_OFF_ON, }; +static struct clk_regmap *gcc_msm8226_clocks[] = { + [GPLL0] = &gpll0.clkr, + [GPLL0_VOTE] = &gpll0_vote, + [GPLL1] = &gpll1.clkr, + [GPLL1_VOTE] = &gpll1_vote, + [CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr, + [PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr, + [SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr, + [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, + [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, + [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, + [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, + [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, + [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, + [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, + [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, + [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, + [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, + [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, + [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, + [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, + [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, + [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr, + [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr, + [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr, + [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr, + [CE1_CLK_SRC] = &ce1_clk_src.clkr, + [GP1_CLK_SRC] = &gp1_clk_src.clkr, + [GP2_CLK_SRC] = &gp2_clk_src.clkr, + [GP3_CLK_SRC] = &gp3_clk_src.clkr, + [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, + [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, + [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, + [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr, + [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, + [USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr, + [USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr, + [USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr, + [GCC_BAM_DMA_AHB_CLK] = &gcc_bam_dma_ahb_clk.clkr, + [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, + [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, + [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, + [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, + [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, + [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, + [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, + [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, + [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, + [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, + [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, + [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr, + [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr, + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, + [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, + [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, + [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, + [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr, + [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, + [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, + [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr, + [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr, + [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, + [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, + [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, + [GCC_USB_HSIC_AHB_CLK] = &gcc_usb_hsic_ahb_clk.clkr, + [GCC_USB_HSIC_CLK] = &gcc_usb_hsic_clk.clkr, + [GCC_USB_HSIC_IO_CAL_CLK] = &gcc_usb_hsic_io_cal_clk.clkr, + [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr, +}; + +static const struct qcom_reset_map gcc_msm8226_resets[] = { + [GCC_USB_HS_HSIC_BCR] = { 0x0400 }, + [GCC_USB_HS_BCR] = { 0x0480 }, + [GCC_USB2A_PHY_BCR] = { 0x04a8 }, +}; + +static struct gdsc *gcc_msm8226_gdscs[] = { + [USB_HS_HSIC_GDSC] = &usb_hs_hsic_gdsc, +}; + +static const struct regmap_config gcc_msm8226_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x1a80, + .fast_io = true, +}; + +static const struct qcom_cc_desc gcc_msm8226_desc = { + .config = &gcc_msm8226_regmap_config, + .clks = gcc_msm8226_clocks, + .num_clks = ARRAY_SIZE(gcc_msm8226_clocks), + .resets = gcc_msm8226_resets, + .num_resets = ARRAY_SIZE(gcc_msm8226_resets), + .gdscs = gcc_msm8226_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_msm8226_gdscs), +}; + static struct clk_regmap *gcc_msm8974_clocks[] = { [GPLL0] = &gpll0.clkr, [GPLL0_VOTE] = &gpll0_vote, @@ -2682,13 +2826,22 @@ static const struct qcom_cc_desc gcc_msm8974_desc = { }; static const struct of_device_id gcc_msm8974_match_table[] = { - { .compatible = "qcom,gcc-msm8974" }, - { .compatible = "qcom,gcc-msm8974pro" , .data = (void *)1UL }, - { .compatible = "qcom,gcc-msm8974pro-ac", .data = (void *)1UL }, + { .compatible = "qcom,gcc-msm8226", .data = &gcc_msm8226_desc }, + { .compatible = "qcom,gcc-msm8974", .data = &gcc_msm8974_desc }, + { .compatible = "qcom,gcc-msm8974pro", .data = &gcc_msm8974_desc }, + { .compatible = "qcom,gcc-msm8974pro-ac", .data = &gcc_msm8974_desc }, { } }; MODULE_DEVICE_TABLE(of, gcc_msm8974_match_table); +static void msm8226_clock_override(void) +{ + ce1_clk_src.freq_tbl = ftbl_gcc_ce1_clk_msm8226; + gp1_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226; + gp2_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226; + gp3_clk_src.freq_tbl = ftbl_gcc_gp_clk_msm8226; +} + static void msm8974_pro_clock_override(void) { sdcc1_apps_clk_src_init.parent_names = gcc_xo_gpll0_gpll4; @@ -2708,16 +2861,18 @@ static int gcc_msm8974_probe(struct platform_device *pdev) { int ret; struct device *dev = &pdev->dev; - bool pro; const struct of_device_id *id; id = of_match_device(gcc_msm8974_match_table, dev); if (!id) return -ENODEV; - pro = !!(id->data); - if (pro) - msm8974_pro_clock_override(); + if (!of_device_is_compatible(dev->of_node, "qcom,gcc-msm8974")) { + if (id->data == &gcc_msm8226_desc) + msm8226_clock_override(); + else + msm8974_pro_clock_override(); + } ret = qcom_cc_register_board_clk(dev, "xo_board", "xo", 19200000); if (ret) From patchwork Sun Apr 18 12:29:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Dudziak X-Patchwork-Id: 12210073 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD471C43470 for ; Sun, 18 Apr 2021 12:30:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id BA7AC61359 for ; Sun, 18 Apr 2021 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[87.49.44.144]) by smtp.googlemail.com with ESMTPSA id a27sm8213677ejk.80.2021.04.18.05.29.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 05:29:55 -0700 (PDT) Received: from localhost (PackardBell [local]) by PackardBell (OpenSMTPD) with ESMTPA id 70967d3d; Sun, 18 Apr 2021 12:29:50 +0000 (UTC) From: Bartosz Dudziak To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Bartosz Dudziak Subject: [PATCH v2 3/5] arm: dts: qcom: Add support for MSM8226 SoC Date: Sun, 18 Apr 2021 14:29:07 +0200 Message-Id: <20210418122909.71434-4-bartosz.dudziak@snejp.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210418122909.71434-1-bartosz.dudziak@snejp.pl> References: <20210418122909.71434-1-bartosz.dudziak@snejp.pl> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Implement basic device tree support for MSM8226 SoC which belongs to the Snapdragon 400 family. For now, this file adds the basic nodes like gcc, pinctrl and other required configuration for booting up to the serial console. Signed-off-by: Bartosz Dudziak --- arch/arm/boot/dts/qcom-msm8226.dtsi | 147 ++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-msm8226.dtsi diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi new file mode 100644 index 0000000000..2de69d5687 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + chosen { }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0>; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + intc: interrupt-controller@f9000000 { + compatible = "qcom,msm-qgic2"; + reg = <0xf9000000 0x1000>, + <0xf9002000 0x1000>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + gcc: clock-controller@fc400000 { + compatible = "qcom,gcc-msm8226"; + reg = <0xfc400000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + tlmm: pinctrl@fd510000 { + compatible = "qcom,msm8226-pinctrl"; + reg = <0xfd510000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 117>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + blsp1_uart3: serial@f991f000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991f000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + restart@fc4ab000 { + compatible = "qcom,pshold"; + reg = <0xfc4ab000 0x4>; + }; + + rng@f9bff000 { + compatible = "qcom,prng"; + reg = <0xf9bff000 0x200>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + + timer@f9020000 { + compatible = "arm,armv7-timer-mem"; + reg = <0xf9020000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@f9021000 { + frame-number = <0>; + interrupts = , + ; + reg = <0xf9021000 0x1000>, + <0xf9022000 0x1000>; + }; + + frame@f9023000 { + frame-number = <1>; + interrupts = ; + reg = <0xf9023000 0x1000>; + status = "disabled"; + }; + + frame@f9024000 { + frame-number = <2>; + interrupts = ; + reg = <0xf9024000 0x1000>; + status = "disabled"; + }; + + frame@f9025000 { + frame-number = <3>; + interrupts = ; + reg = <0xf9025000 0x1000>; + status = "disabled"; + }; + + frame@f9026000 { + frame-number = <4>; + interrupts = ; + reg = <0xf9026000 0x1000>; + status = "disabled"; + }; + + frame@f9027000 { + frame-number = <5>; + interrupts = ; + reg = <0xf9027000 0x1000>; + status = "disabled"; + }; + + frame@f9028000 { + frame-number = <6>; + interrupts = ; + reg = <0xf9028000 0x1000>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; +}; From patchwork Sun Apr 18 12:29:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Dudziak X-Patchwork-Id: 12210075 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFD74C43462 for ; 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[87.49.44.144]) by smtp.googlemail.com with ESMTPSA id k26sm8483371ejk.29.2021.04.18.05.29.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 05:29:56 -0700 (PDT) Received: from localhost (PackardBell [local]) by PackardBell (OpenSMTPD) with ESMTPA id f2c73f30; Sun, 18 Apr 2021 12:29:50 +0000 (UTC) From: Bartosz Dudziak To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Bartosz Dudziak Subject: [PATCH v2 4/5] dt-bindings: arm: qcom: Document MSM8226 SoC binding Date: Sun, 18 Apr 2021 14:29:08 +0200 Message-Id: <20210418122909.71434-5-bartosz.dudziak@snejp.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210418122909.71434-1-bartosz.dudziak@snejp.pl> References: <20210418122909.71434-1-bartosz.dudziak@snejp.pl> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the MSM8226 SoC device-tree binding. Signed-off-by: Bartosz Dudziak Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 11ec349d56..73902ce46f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -31,6 +31,7 @@ description: | ipq6018 ipq8074 mdm9615 + msm8226 msm8916 msm8974 msm8992 @@ -111,6 +112,11 @@ properties: - qcom,apq8084-sbc - const: qcom,apq8084 + - items: + - enum: + - samsung,s3ve3g + - const: qcom,msm8226 + - items: - enum: - qcom,msm8960-cdp From patchwork Sun Apr 18 12:29:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Dudziak X-Patchwork-Id: 12210077 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A529AC43461 for ; Sun, 18 Apr 2021 12:30:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8BB426121D for ; Sun, 18 Apr 2021 12:30:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236562AbhDRMad (ORCPT ); Sun, 18 Apr 2021 08:30:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235404AbhDRMa1 (ORCPT ); Sun, 18 Apr 2021 08:30:27 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FFDBC061344 for ; Sun, 18 Apr 2021 05:29:58 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id sd23so40093121ejb.12 for ; Sun, 18 Apr 2021 05:29:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=snejp.pl; s=gmail; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Povr2PCX17kPcIjpM7jFhMLFACkEG0pX0j9vA7ZmMlE=; b=N2sdCUsAj7x9gsqUHEMfL4w6zOyWfcNQQPzfaxKL7lIEBqHT3zYA0LjL2pZjtzkRVA 7hLzpX+t5gKlt+I0dECXGu+/m/7c/qsqK6ctZxEnBqOzgH2Dpe60nb7c3mhuVcgPZ84T rd5fyjkkqDDOlwxwRVHg4pI/iyRz4WD4XWWN8c8c8xR2HuoIEa4BIbHPIbCdZ7wKdYA7 U9iTCc/tEqZhTcnOq3ju8vgnXhZ4XbPHmgqbO/qAWzGvtsNifKAPHVb7TSk9JxkQmv0q BJdyFywYCS6rOm7HHNnD1pjhSzqzuSXGaY6Xx+0yvhRXVL0oVXzVXguG/iCLGRv5dCZ8 qTSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Povr2PCX17kPcIjpM7jFhMLFACkEG0pX0j9vA7ZmMlE=; b=GzIw/z+yu8WqVu6rF+H9SXYUl/GUtGtQ/70voUumDJ/znvtu8FWkLsaC5biHg7Lt30 mUzccE1MZEl9oO5zInB2zy02Pt0kXd2lu24qYMIrVRkQjrOJxurAEsUgUcmO2UJEqDw7 X6LyXN1yX23eWZUHi5PBqOznC5mRm0uFB5JiOJoFStLkZGys8FqjoFaBa3jI1Q2M3uxZ tghbI+Jb7MQwzFXaSQiPWQnZ0ODst8yUhQfOqzdndSHhaE1Mh1CgVQftEf4etMslE0L6 H0TXrxsRSDzFP2RKnYMUltnOKTBrrJ0UzFjHgKsGf/ILfwKOTlkwxvZfNCpKSIyHmMxK jGvQ== X-Gm-Message-State: AOAM533i/+U3QDXz+pdlkbZHSMP6926oA2vJPVk0x//VF/kJIDswlOAD lk4jaMt6oeizcl9YQE+xxIG3UA== X-Google-Smtp-Source: ABdhPJwz0rE2CDn2fqqk0+tJA02XvNTkLZp+/wGQZHn1H/gImMIuGi56clWZflH0EgKxzeUsfVSCgA== X-Received: by 2002:a17:906:8921:: with SMTP id fr33mr17141651ejc.151.1618748996975; Sun, 18 Apr 2021 05:29:56 -0700 (PDT) Received: from PackardBell (87-49-44-144-mobile.dk.customer.tdc.net. [87.49.44.144]) by smtp.googlemail.com with ESMTPSA id a27sm8213677ejk.80.2021.04.18.05.29.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Apr 2021 05:29:56 -0700 (PDT) Received: from localhost (PackardBell [local]) by PackardBell (OpenSMTPD) with ESMTPA id 6b81955b; Sun, 18 Apr 2021 12:29:50 +0000 (UTC) From: Bartosz Dudziak To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: Bartosz Dudziak Subject: [PATCH v2 5/5] arm: dts: qcom: Add initial DTS file for Samsung Galaxy S III Neo phone Date: Sun, 18 Apr 2021 14:29:09 +0200 Message-Id: <20210418122909.71434-6-bartosz.dudziak@snejp.pl> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210418122909.71434-1-bartosz.dudziak@snejp.pl> References: <20210418122909.71434-1-bartosz.dudziak@snejp.pl> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add DTS support for the Samsung Galaxy S III Neo (codenamed s3ve3g) phone. Initial version have just a working serial console. Signed-off-by: Bartosz Dudziak --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/qcom-msm8226-samsung-s3ve3g.dts | 25 +++++++++++++++++++ 2 files changed, 26 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8e5d4ab4e7..080ff37fdb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -920,6 +920,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-ipq4019-ap.dk07.1-c2.dtb \ qcom-ipq8064-ap148.dtb \ qcom-ipq8064-rb3011.dtb \ + qcom-msm8226-samsung-s3ve3g.dtb \ qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb \ qcom-msm8974-fairphone-fp2.dtb \ diff --git a/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts b/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts new file mode 100644 index 0000000000..d159188c8b --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#include "qcom-msm8226.dtsi" + +/ { + model = "Samsung Galaxy S III Neo"; + compatible = "samsung,s3ve3g", "qcom,msm8226"; + + aliases { + serial0 = &blsp1_uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&soc { + serial@f991f000 { + status = "ok"; + }; +};