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Signed-off-by: Nava kishore Manne --- .../bindings/misc/xlnx,zynq-afi-fpga.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml diff --git a/Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml b/Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml new file mode 100644 index 000000000000..9c20a192d6a6 --- /dev/null +++ b/Documentation/devicetree/bindings/misc/xlnx,zynq-afi-fpga.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/xlnx,zynq-afi-fpga.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Zynq AFI interface Manager. + +maintainers: + - Nava kishore Manne + +description: | + The Zynq Processing System core provides access from PL masters to PS + internal peripherals, and memory through AXI FIFO interface(AFI) + interfaces. + +properties: + compatible: + items: + - enum: + - xlnx,zynq-afi-fpga + reg: + maxItems: 1 + + xlnx,afi-buswidth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Size of the afi bus width. + 0 - 64-bit AXI data width. + 1 - 32-bit AXI data width. + maxItems: 1 + +required: + - compatible + - reg + - xlnx,afi-buswidth + +additionalProperties: false + +examples: + - | + afi0: afi@f8008000 { + compatible = "xlnx,zynq-afi-fpga"; + reg = <0xf8008000 0x1000>; + xlnx,afi-buswidth = <1>; + }; +... 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Tue, 20 Apr 2021 01:20:28 -0700 Received: from [10.140.6.60] (port=45276 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lYlcR-0007C5-4j; Tue, 20 Apr 2021 01:20:27 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , , , , Subject: [PATCH 2/5] misc: zynq: Add afi config driver Date: Tue, 20 Apr 2021 13:41:50 +0530 Message-ID: <20210420081153.17020-3-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210420081153.17020-1-nava.manne@xilinx.com> References: <20210420081153.17020-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e12b6698-a878-49ce-bba4-08d903d52c21 X-MS-TrafficTypeDiagnostic: SN6PR02MB5022: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:4714; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ETa1Cm+ljiRLwBeL6+BtrSIiCQiFCpxJeSCCq6E3lTuTB0C55bUensUR7/M4FyNCovWzUqpsp2g9DQ6d9h5J8H12PoYt1UnAhQ4OgP7VX2sq0RLOlActCqi82pheX5bdNgj/apFNA/dcSjorFXLCtjZHZZaWrV8407pnK1c6fGdYjYR1nQoc37Ok0qLdstxAVZBvQCG/xehPr58THChjqGkMjDygsi8yBNCS9BwRNnoB77Fwj5dy3DIM1qJflaHQtL92PNt94WB8t3npw3a7rsExweykmqUd4HrZpcjPtRyP2C6D0WDX0SIe74AmlY3cmc/JSKyist+8MrZJRE97gsV6yRQryo8czUV94ldIxZFlx2zE4XYv79QbgYmjD/WP1bMeC4He6MSFUP3ZdTxljEBvt0OsRI+/Ouq6eROjogm8u4MZ9eyTLS53mHd4sEXFvsss+HQN8a3oy3xvVWQSXhWrtt64Kwgej7+Uxo7Au3asIK17yVHNJN5jWxRFHZm5RAXD4U78jhPH9f4NOp3wKqHVUveS29EwZaXrE2+RmMELmWPTaz+K79D5dKi52RuKYWdQxBztxoIjK98F53KCTiehTXLcaU6dYiYIeh+urMYzZskI4BrHSmZT7zO3EqosvtdUAKm9GpSfmJmwMPOj1uqE7oy9MgHkEwKq/gz+D0jC4kA3FS5nTgE3fxqlNGEf7l9xlPtAuw6jCscPVKjkQK0fSEsT5SCsymU/ACCY713bDyQLdnT6MczotxnPhKq+ X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(4636009)(376002)(136003)(346002)(39860400002)(396003)(46966006)(36840700001)(36860700001)(26005)(426003)(356005)(186003)(82310400003)(70586007)(7636003)(8936002)(47076005)(336012)(8676002)(5660300002)(2616005)(110136005)(36756003)(82740400003)(316002)(2906002)(6666004)(7696005)(36906005)(9786002)(921005)(1076003)(6636002)(70206006)(83380400001)(478600001)(102446001)(83996005)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2021 08:20:35.2311 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e12b6698-a878-49ce-bba4-08d903d52c21 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT033.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB5022 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210420_012046_429124_F658A32A X-CRM114-Status: GOOD ( 21.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds zynq afi config driver. This is useful for the configuration of the PS-PL interface on zynq platform. Signed-off-by: Nava kishore Manne --- drivers/misc/Kconfig | 11 ++++++ drivers/misc/Makefile | 1 + drivers/misc/zynq-afi.c | 81 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 93 insertions(+) create mode 100644 drivers/misc/zynq-afi.c diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index f532c59bb59b..877b43b3377d 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -445,6 +445,17 @@ config HISI_HIKEY_USB switching between the dual-role USB-C port and the USB-A host ports using only one USB controller. +config ZYNQ_AFI + tristate "Xilinx ZYNQ AFI support" + help + Zynq AFI driver support for writing to the AFI registers + for configuring PS_PL Bus-width. Xilinx Zynq SoC connect + the PS to the programmable logic (PL) through the AXI port. + This AXI port helps to establish the data path between the + PS and PL.In-order to establish the proper communication path + between PS and PL, the AXI port data path should be configured + with the proper Bus-width values + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 99b6f15a3c70..e9b03843100f 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -56,3 +56,4 @@ obj-$(CONFIG_HABANA_AI) += habanalabs/ obj-$(CONFIG_UACCE) += uacce/ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o +obj-$(CONFIG_ZYNQ_AFI) += zynq-afi.o diff --git a/drivers/misc/zynq-afi.c b/drivers/misc/zynq-afi.c new file mode 100644 index 000000000000..04317d1bdb98 --- /dev/null +++ b/drivers/misc/zynq-afi.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx ZYNQ AFI driver. + * Copyright (c) 2018-2021 Xilinx Inc. + */ + +#include +#include +#include +#include +#include + +/* Registers and special values for doing register-based operations */ +#define AFI_RDCHAN_CTRL_OFFSET 0x00 +#define AFI_WRCHAN_CTRL_OFFSET 0x14 + +#define AFI_BUSWIDTH_MASK 0x01 + +/** + * struct afi_fpga - AFI register description + * @membase: pointer to register struct + * @afi_width: AFI bus width to be written + */ +struct zynq_afi_fpga { + void __iomem *membase; + u32 afi_width; +}; + +static int zynq_afi_fpga_probe(struct platform_device *pdev) +{ + struct zynq_afi_fpga *afi_fpga; + struct resource *res; + u32 reg_val; + u32 val; + + afi_fpga = devm_kzalloc(&pdev->dev, sizeof(*afi_fpga), GFP_KERNEL); + if (!afi_fpga) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + afi_fpga->membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(afi_fpga->membase)) + return PTR_ERR(afi_fpga->membase); + + val = device_property_read_u32(&pdev->dev, "xlnx,afi-width", + &afi_fpga->afi_width); + if (val) { + dev_err(&pdev->dev, "failed to get the afi bus width\n"); + return -EINVAL; + } + + reg_val = readl(afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET); + reg_val &= ~AFI_BUSWIDTH_MASK; + writel(reg_val | afi_fpga->afi_width, + afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET); + reg_val = readl(afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET); + reg_val &= ~AFI_BUSWIDTH_MASK; + writel(reg_val | afi_fpga->afi_width, + afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET); + + return 0; +} + +static const struct of_device_id zynq_afi_fpga_ids[] = { + { .compatible = "xlnx,zynq-afi-fpga" }, + { }, +}; +MODULE_DEVICE_TABLE(of, zynq_afi_fpga_ids); + +static struct platform_driver zynq_afi_fpga_driver = { + .driver = { + .name = "zynq-afi-fpga", + .of_match_table = zynq_afi_fpga_ids, + }, + .probe = zynq_afi_fpga_probe, +}; +module_platform_driver(zynq_afi_fpga_driver); + +MODULE_DESCRIPTION("ZYNQ FPGA AFI module"); +MODULE_AUTHOR("Nava kishore Manne "); +MODULE_LICENSE("GPL v2"); From patchwork Tue Apr 20 08:11:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nava kishore Manne X-Patchwork-Id: 12213529 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D94CC433ED for ; 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Tue, 20 Apr 2021 01:20:31 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , , , , Subject: [PATCH 3/5] firmware: xilinx: Add afi ioctl support Date: Tue, 20 Apr 2021 13:41:51 +0530 Message-ID: <20210420081153.17020-4-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210420081153.17020-1-nava.manne@xilinx.com> References: <20210420081153.17020-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 51ffb443-6cb5-4664-e186-08d903d52ef5 X-MS-TrafficTypeDiagnostic: SA0PR02MB7418: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 1YNGrxuVPYrty8//VXsoO0dO6Ef2cZ5rnMBZ8uGB23lITPHC5mYeTHlJdQvmJXZvEWzV6FAQa5XMB4XBlL2IhbPoIrag5G+j7XS3K6tGUg4z1wNp0WrDqZ8tW3eSpgV8OR+ejxZXO3uaYCfLAKL2IxAjdpUpNOB4oio1wyru9cL+92ekzqhf2ziWe2awcwtX7Uw3q4CfAJXcXu+jMFUuQRbbiIft9GoaLHY03znSbW/GGruknBt9pS8IyQbamapmTesme9v89TBBiUeFT8hLrQk1gFqPgGwldVTuqKcLIPcaEeoZ0z82OPIGf2AB1x45d7BEAZ9UlkFyfIlpJLL7FiIScXSh3oYRcvDa1pdnD3YmX6efxu1tx4k6GUxsXuCyJSGHQtZ9Joj6/0xja8e5tIzINThuyzuvZHZiGxQzSqwN8pTGBXspCQ/QGdh76IXatXBV6RhWWyqN3jpEhnDsrZFdwnIEQjD5DQThGQK4iBL3/pDpql2DmOZI78tvIyGRlseW1tTXsVapNqW9LSe+1TiMUo9toYKz2f4GpaEgswM3DXzZFdEZNnKHDBGJt5rKF0VRBW0lSi+Rhd/1IMhGeJRJd1C1vpjrD9imFockip82kaxOfHU20uv7mD61nr94LjHXZkv8S9jhIdp2Zu2frvU/N1Psy9czNN8FEz+pPGs9ecXJbxJRPf89N766Fx7Sy/EOKG3KaTVDXdz6QDsw43JX6ZEQgVIsIlxZ/2CuYHRdEpRcup7Z3asdmeNJYYwX X-Forefront-Antispam-Report: CIP:149.199.62.198; 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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds afi ioctl to support dynamic PS-PL bus width settings. Signed-off-by: Nava kishore Manne --- drivers/firmware/xilinx/zynqmp.c | 13 +++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 7 +++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 7eb9958662dd..ada9eb9e26e3 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -713,6 +713,19 @@ int zynqmp_pm_read_pggs(u32 index, u32 *value) } EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs); +/** + * zynqmp_pm_afi() - PM API for setting the PS-PL bus width + * @index: Register index value + * @value: value to be written into the register + * + * Return: Returns status, either success or error+reason + */ +int zynqmp_pm_afi(u32 index, u32 value) +{ + return zynqmp_pm_invoke_fn(PM_IOCTL, 0, IOCTL_AFI, index, value, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_afi); + /** * zynqmp_pm_set_boot_health_status() - PM API for setting healthy boot status * @value: Status value to be written diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 71177b17eee5..792fb4f5d86f 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -113,6 +113,7 @@ enum pm_ioctl_id { IOCTL_READ_PGGS = 15, /* Set healthy bit value */ IOCTL_SET_BOOT_HEALTH_STATUS = 17, + IOCTL_AFI = 18, }; enum pm_query_id { @@ -353,6 +354,7 @@ int zynqmp_pm_write_pggs(u32 index, u32 value); int zynqmp_pm_read_pggs(u32 index, u32 *value); int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype); int zynqmp_pm_set_boot_health_status(u32 value); +int zynqmp_pm_afi(u32 index, u32 value); #else static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void) { @@ -537,6 +539,11 @@ static inline int zynqmp_pm_set_boot_health_status(u32 value) { return -ENODEV; } + +static inline int zynqmp_pm_afi(u32 index, u32 value) +{ + return -ENODEV; +} #endif #endif /* __FIRMWARE_ZYNQMP_H__ */ From patchwork Tue Apr 20 08:11:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nava kishore Manne X-Patchwork-Id: 12213533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2179EC433ED for ; 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Tue, 20 Apr 2021 01:20:36 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , , , , Subject: [PATCH 4/5] misc: doc: Add binding doc for the zynqmp afi config driver Date: Tue, 20 Apr 2021 13:41:52 +0530 Message-ID: <20210420081153.17020-5-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210420081153.17020-1-nava.manne@xilinx.com> References: <20210420081153.17020-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e27b8389-648a-4701-028a-08d903d532a0 X-MS-TrafficTypeDiagnostic: SA2PR02MB7514: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:6790; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zLpXFccDsjwiHPRmo3PJoTKcY4vIq5Ukg3NgiNXT0kTvK/TZLexbDMh+ONOk66R1JSTay3OuXpadwIt++hgni3ut/mM/w3E785hD1BcsoSGOhzHQ1foY5cIa6nG19oYg8XhZ0DwWKhRzhTb7Yzpe+FaESvPfxCRnkWInrCLvK2WVFR8LGquDFhNXiFonmCHDzSP8zM4oot5Y4fnLKx066Ec8B6lAz1mWjqOUPCzp8qos+6jiYWXb2SqhE5EuDmOLeXQuz/dKRq4N4m5ML2RjKLCpyNplpd9r8yTJDeZD9QJCcCuWUkjLiGP0d3h8cpBFTEAAHO9rdYNWkEE/QZ9Gk1SiuQ+27WtBfmRJDmkwtzqmFmMDNjRnAgznd9zbBrus3Zt82T5hFUTMFFPK584H0jiZNKmeWeOhGFfRh9DZ+Ztr+qQLYIJMV98MkOs7jWtnXQ40xrh4mL+I7352bGEKqnk0y7RQRYBDzNmP+yADuOKXA9XnH4g9qjBjUtm8BAlLf3T+AmqrvTSqJYzYVNg/Jl203sbfgUbhIlyYen8AifnQSOVJgY1izL0QiWQeRFLDcxgnzwf8MBcsBsXamDXPIjY/KTk7nfBaNccclrN4/Qhej9O8EMm1GVaWCQAebVHpFKu4ZmSz8X60jAA+kTYExIkBfRGjhQ4Qv+qKv+LzLk5yPcrsWrMCWJ3HnjTyEnVyuqtizTDJGUoWE9oye/eIMcAkYG9NhXEJieT1BmN6MmJB9azP+cHLdnyoGEP9gDMEQE4ufq/HMG2hJlWA8QRniGPkNG3SSrE3zmlSrSl8iYwNQNPS03FG8q+O+TeCw/zV X-Forefront-Antispam-Report: CIP:149.199.62.198; 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Signed-off-by: Nava kishore Manne --- .../bindings/misc/xlnx,zynqmp-afi-fpga.yaml | 136 ++++++++++++++++++ 1 file changed, 136 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml diff --git a/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml b/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml new file mode 100644 index 000000000000..3ae22096b22a --- /dev/null +++ b/Documentation/devicetree/bindings/misc/xlnx,zynqmp-afi-fpga.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/xlnx,zynqmp-afi-fpga.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx ZynqMP AFI interface Manager. + +maintainers: + - Nava kishore Manne + +description: | + The Zynq UltraScale+ MPSoC Processing System core provides access from PL + masters to PS internal peripherals, and memory through AXI FIFO interface(AFI) + interfaces. + +properties: + compatible: + items: + - enum: + - xlnx,zynqmp-afi-fpga + + config-afi: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Pairs of + The possible values of regid and values are + regid - Regids of the register to be written possible values + 0- AFIFM0_RDCTRL + 1- AFIFM0_WRCTRL + 2- AFIFM1_RDCTRL + 3- AFIFM1_WRCTRL + 4- AFIFM2_RDCTRL + 5- AFIFM2_WRCTRL + 6- AFIFM3_RDCTRL + 7- AFIFM3_WRCTRL + 8- AFIFM4_RDCTRL + 9- AFIFM4_WRCTRL + 10- AFIFM5_RDCTRL + 11- AFIFM5_WRCTRL + 12- AFIFM6_RDCTRL + 13- AFIFM6_WRCTRL + 14- AFIFS + 15- AFIFS_SS2 + value - Array of values to be written. + for FM0_RDCTRL(0) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM0_WRCTRL(1) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM1_RDCTRL(2) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM1_WRCTRL(3) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM2_RDCTRL(4) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM2_WRCTRL(5) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM3_RDCTRL(6) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM3_WRCTRL(7) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM4_RDCTRL(8) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM4_WRCTRL(9) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM5_RDCTRL(10) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM5_WRCTRL(11) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM6_RDCTRL(12) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for FM6_WRCTRL(13) the valid values-fabric width + 2 - 32-bit + 1 - 64-bit + 0 - 128-bit + for AFI_FA(14) + dw_ss1_sel bits (11:10) + dw_ss0_sel bits (9:8) + 0x0 - 32-bit AXI data width + 0x1 - 64-bit AXI data width + 0x2 - 128-bit AXI data width + All other bits are 0 write ignored. + + for AFI_FA(15) selects for ss2AXI data width valid values + 0x000 - 32-bit AXI data width + 0x100 - 64-bit AXI data width + 0x200 - 128-bit AXI data width + minItems: 1 + maxItems: 15 + +required: + - compatible + - config-afi + +additionalProperties: false + +examples: + - | + firmware { + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + afi0: afi { + compatible = "xlnx,afi-fpga"; + config-afi = <0 2>, <1 1>, <2 1>; + }; + }; + }; + +... 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Tue, 20 Apr 2021 01:20:42 -0700 Received: from [10.140.6.60] (port=45276 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lYlcd-0007C5-R8; Tue, 20 Apr 2021 01:20:40 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , , , , Subject: [PATCH 5/5] misc: zynqmp: Add afi config driver Date: Tue, 20 Apr 2021 13:41:53 +0530 Message-ID: <20210420081153.17020-6-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210420081153.17020-1-nava.manne@xilinx.com> References: <20210420081153.17020-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a4bb4f4f-6122-4067-b44c-08d903d53688 X-MS-TrafficTypeDiagnostic: DM6PR02MB5963: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:4941; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ewVTw1SMrIy+SgwfOx/jDd2AAZCqY3VhQM3JixlgNmqSnEQ18ARHSLdYiDCm0IhbEoCggbhFdaVqW0+JG8Thnq59xdfoP8p8sINuYcPZ+/0GSHnACKT9kBBPjMN7RUGb/Pl+RwU+Qgc/5ba5xTHnfGZCpqrwU+CpC7BoJn8OTVzTYr/02OqXx42GRnDah80B8naanIWkzUGdiPbL49+xNTCc8jcCfOfwiN0E9xQbDv+MA97wI1ExAxdnIf2y5Sum/6qgZ309+tRmYRBV/8+KA2QADAKj1puHdVyDW6/JxEi4RQrwNU/hwLy9jTS9dqbRF352dXOKeMUY3q+xtTGPE46NdiDFEqN2pPQU5D/Ak1S1HD8z0wvq1MQIpSiFKQZZ+fRK2Dc5zHjYnsX4W3KjVaPNEbINmCT6sEg3WiiDZCOO3T3/sJZRKyVWaHqsk6OKxlXlIhfGk/42fO5FFCP+FBsIpOjNbWCuyhfwhkkMKedLj+cqBGZV/IkYaWLENlEnPgu5pPTr4UHtvQXITkmF04VEAUzJ9hiRxskvofMqpyDK3+J1jSU9+S3sHQCHVc/jy7rnG7OePGxvg1z/K3/4sPt71PM+R25HL1kAydjj+jOLrI1n0/MH9v5AgEgmxjyUixABvoi2jQcyMC3EGetkcByd/ORDWWIoyos3hwEkddY9hzUf8rKgqmg/qlp4UBYtbPI5W3iJrT52S4v2xwVi3lnxBPD857mo6+KWhJqR77ShqbGCwmTF3vI3pjH60JGR X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch01.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(4636009)(136003)(376002)(396003)(39860400002)(346002)(36840700001)(46966006)(47076005)(82740400003)(2906002)(7636003)(82310400003)(70206006)(9786002)(8676002)(5660300002)(26005)(83380400001)(356005)(8936002)(2616005)(70586007)(36756003)(426003)(6636002)(7696005)(478600001)(36906005)(110136005)(186003)(6666004)(921005)(316002)(336012)(1076003)(36860700001)(102446001)(83996005)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2021 08:20:52.6002 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a4bb4f4f-6122-4067-b44c-08d903d53688 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BL2NAM02FT038.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB5963 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210420_012057_504704_21D71167 X-CRM114-Status: GOOD ( 21.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds zynqmp afi config driver.This is useful for the configuration of the PS-PL interface on Zynq US+ MPSoC platform. Signed-off-by: Nava kishore Manne --- drivers/misc/Kconfig | 11 ++++++ drivers/misc/Makefile | 1 + drivers/misc/zynqmp-afi.c | 83 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+) create mode 100644 drivers/misc/zynqmp-afi.c diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 877b43b3377d..d1ea1eeb3ac1 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -456,6 +456,17 @@ config ZYNQ_AFI between PS and PL, the AXI port data path should be configured with the proper Bus-width values +config ZYNQMP_AFI + tristate "Xilinx ZYNQMP AFI support" + help + ZynqMP AFI driver support for writing to the AFI registers for + configuring PS_PL Bus-width. Xilinx Zynq US+ MPSoC connect the + PS to the programmable logic (PL) through the AXI port. This AXI + port helps to establish the data path between the PS and PL. + In-order to establish the proper communication path between + PS and PL, the AXI port data path should be configured with + the proper Bus-width values + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index e9b03843100f..54bd0edc511e 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -57,3 +57,4 @@ obj-$(CONFIG_UACCE) += uacce/ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o obj-$(CONFIG_ZYNQ_AFI) += zynq-afi.o +obj-$(CONFIG_ZYNQMP_AFI) += zynqmp-afi.o diff --git a/drivers/misc/zynqmp-afi.c b/drivers/misc/zynqmp-afi.c new file mode 100644 index 000000000000..a318652576d2 --- /dev/null +++ b/drivers/misc/zynqmp-afi.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx FPGA AFI bridge. + * Copyright (c) 2018-2021 Xilinx Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +/** + * struct zynqmp_afi_fpga - AFI register description + * @value: value to be written to the register + * @regid: Register id for the register to be written + */ +struct zynqmp_afi_fpga { + u32 value; + u32 regid; +}; + +static int zynqmp_afi_fpga_probe(struct platform_device *pdev) +{ + struct zynqmp_afi_fpga *zynqmp_afi_fpga; + struct device_node *np = pdev->dev.of_node; + int i, entries, ret; + u32 reg, val; + + zynqmp_afi_fpga = devm_kzalloc(&pdev->dev, + sizeof(*zynqmp_afi_fpga), GFP_KERNEL); + if (!zynqmp_afi_fpga) + return -ENOMEM; + platform_set_drvdata(pdev, zynqmp_afi_fpga); + + entries = of_property_count_u32_elems(np, "config-afi"); + if (!entries || (entries % 2)) { + dev_err(&pdev->dev, "Invalid number of registers\n"); + return -EINVAL; + } + + for (i = 0; i < entries / 2; i++) { + ret = of_property_read_u32_index(np, "config-afi", i * 2, ®); + if (ret) { + dev_err(&pdev->dev, "failed to read register\n"); + return -EINVAL; + } + ret = of_property_read_u32_index(np, "config-afi", i * 2 + 1, + &val); + if (ret) { + dev_err(&pdev->dev, "failed to read value\n"); + return -EINVAL; + } + ret = zynqmp_pm_afi(reg, val); + if (ret < 0) { + dev_err(&pdev->dev, "AFI register write error %d\n", + ret); + return ret; + } + } + return 0; +} + +static const struct of_device_id zynqmp_afi_fpga_ids[] = { + { .compatible = "xlnx,zynqmp-afi-fpga" }, + { }, +}; +MODULE_DEVICE_TABLE(of, zynqmp_afi_fpga_ids); + +static struct platform_driver zynqmp_afi_fpga_driver = { + .driver = { + .name = "zynqmp-afi-fpga", + .of_match_table = zynqmp_afi_fpga_ids, + }, + .probe = zynqmp_afi_fpga_probe, +}; +module_platform_driver(zynqmp_afi_fpga_driver); + +MODULE_DESCRIPTION("ZYNQMP FPGA afi module"); +MODULE_AUTHOR("Nava kishore Manne "); +MODULE_LICENSE("GPL v2");