From patchwork Thu Apr 22 03:04:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 12217427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3D73EC433ED for ; Thu, 22 Apr 2021 03:05:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 002E161406 for ; Thu, 22 Apr 2021 03:05:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234471AbhDVDFw (ORCPT ); Wed, 21 Apr 2021 23:05:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234340AbhDVDFt (ORCPT ); Wed, 21 Apr 2021 23:05:49 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 83EEBC06174A for ; Wed, 21 Apr 2021 20:05:11 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id u73-20020a25ab4f0000b0290410f38a2f81so18204349ybi.22 for ; Wed, 21 Apr 2021 20:05:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=nHcWdzb0XhQi4QlsO7LmwsFD16llxMgU/74d4ZRWlZw=; b=D2JzKJqHjJteWl3sof+pGV0S2zgDoGRVlLX7cwJQ0ayI9xM0VfVLyz3wzh0aAmD9kg ox79dwVivYa6R0m+9ZRqLi1clA7jeolvTu+gadAbyc2WtfuFq6xmicvG1FaZy6pDD/Kf tURIMAfcACywQAyft0l/LLABT7EkjpxONx7o/HAHHpZwnOqfJKYZwNspdpHMK2VGSvGm 0n0barYVkTlHG81oeBrUmrBtrX5478buf7TLuhi8Pz5mKOcLmp8+wpvn6ht3yYjHBpec g26A5Rh9oaGAhGAqsnnxNzwhMEPw3LW4LceDrS+HwVlDPKkk1e00/3UOnFkFEWAKJJGO zuFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=nHcWdzb0XhQi4QlsO7LmwsFD16llxMgU/74d4ZRWlZw=; b=ZssLiWoVqN9IG14mwVGo1azbiepkQpXAfqisEon0Sm/ID6e+ZZtE6TlNqjxt3/wWZo PvUzIlnPQkEZVCX17fOMowTELo9PmpRjUEh6bWQs1BIgJ4SrfmzrGpKHJ9brCdnz9pV+ xHhdF+zWAZZX6HNjuKs0wJTKfATqjokyvyTlbsJarnc47ZtbGdkqRYJUoZfjUohtO3Yq KU0vc14bYtNPDemkdLeun5Ivqqkh1mIRVlXPHIfJzOLUDEm+gtIBZiuYl/tp+k5cdNND 3an9Ss/iJRhcCMgjFeZnTWPSyMNJoPypmu8HnUPezY9/3X2D3oDvwG0HKIsvgS+R8417 Td8w== X-Gm-Message-State: AOAM532RDh7K/0d6Ap/O1RKSyHhNN5aL1blvfdbF91u8AzMur/QVG43u q07Au1/9EzEHodh1plXjXxLlMmj9/Xk= X-Google-Smtp-Source: ABdhPJxLbApf4tEVBeM51RtYEfuL5zZAymNJnucyaoJ8wGyx1OXt4Xn6ufLXYe09rp1WF7zYyXDIXK7kJg0= X-Received: from seanjc798194.pdx.corp.google.com ([2620:15c:f:10:e012:374c:592:6194]) (user=seanjc job=sendgmr) by 2002:a25:5d0:: with SMTP id 199mr1584859ybf.56.1619060710852; Wed, 21 Apr 2021 20:05:10 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 21 Apr 2021 20:04:51 -0700 In-Reply-To: <20210422030504.3488253-1-seanjc@google.com> Message-Id: <20210422030504.3488253-2-seanjc@google.com> Mime-Version: 1.0 References: <20210422030504.3488253-1-seanjc@google.com> X-Mailer: git-send-email 2.31.1.498.g6c1eba8ee3d-goog Subject: [kvm-unit-tests PATCH 01/14] x86/cstart: Don't use MSR_GS_BASE in 32-bit boot code From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Load the per-cpu GS.base for 32-bit build by building a temporary GDT and loading a "real" segment. Using MSR_GS_BASE is wrong and broken, it's a 64-bit only MSR and does not exist on 32-bit CPUs. The current code works only because 32-bit KVM VMX incorrectly disables interception of MSR_GS_BASE, and no one runs KVM on an actual 32-bit physical CPU, i.e. the MSR exists in hardware and so everything "works". 32-bit KVM SVM is not buggy and correctly injects #GP on the WRMSR, i.e. the tests have never worked on 32-bit SVM. Fixes: dfe6cb6 ("Add 32 bit smp initialization code") Signed-off-by: Sean Christopherson --- x86/cstart.S | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/x86/cstart.S b/x86/cstart.S index 489c561..91970a2 100644 --- a/x86/cstart.S +++ b/x86/cstart.S @@ -89,13 +89,31 @@ mb_flags = 0x0 .long mb_magic, mb_flags, 0 - (mb_magic + mb_flags) mb_cmdline = 16 -MSR_GS_BASE = 0xc0000101 - .macro setup_percpu_area lea -4096(%esp), %eax - mov $0, %edx - mov $MSR_GS_BASE, %ecx - wrmsr + + mov %eax, %edx + shl $16, %edx + or $0xffff, %edx + mov %edx, 0x10(%eax) + + mov %eax, %edx + and $0xff000000, %edx + mov %eax, %ecx + shr $16, %ecx + and $0xff, %ecx + or %ecx, %edx + or $0x00cf9300, %edx + mov %edx, 0x14(%eax) + + movw $0x17, 0(%eax) + mov %eax, 2(%eax) + lgdtl (%eax) + + mov $0x10, %ax + mov %ax, %gs + + lgdtl gdt32_descr .endm .macro setup_segments From patchwork Thu Apr 22 03:04:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 12217429 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3D30C433B4 for ; Thu, 22 Apr 2021 03:05:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AE9FB61428 for ; Thu, 22 Apr 2021 03:05:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234475AbhDVDFx (ORCPT ); Wed, 21 Apr 2021 23:05:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234409AbhDVDFu (ORCPT ); Wed, 21 Apr 2021 23:05:50 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BFA00C06138B for ; Wed, 21 Apr 2021 20:05:13 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id s34-20020a252d620000b02904e34d3a48abso18260114ybe.13 for ; Wed, 21 Apr 2021 20:05:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=VekeEJpZiPwgxPOr5FnQtqIOMax6FYTSqbn7yUKIbiU=; b=Rj9vJ/mioslnaY4/4JPrizEckMCfI+1CWYcBIegamHb539S/6PUMaCMFcd6Xf6GLE5 hf0uam+1ItAayJzVIUJLgjjFV/Q5hKCfBKk44sGwWiiOPYtFMM5lsk8azcQ9AB6Z6JmB QvZNH670znCh0LEqMBAJcCZQtQOUi4Qxk3F69tcf1KbWUY+pbz1AexizqhsXc49clkeS vXRYAQNljckNLI+W0CpH9EMCljumGbNtP5mqwKkT0w9ydT1h6APgR7B8o/pP44dFnpsd eaaWOQa07qghmmJDUiqDcHiwsuViwdFsH0iNNeyJst0xTcuojVXD6hrep0TvoyuVL2xc Tw+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=VekeEJpZiPwgxPOr5FnQtqIOMax6FYTSqbn7yUKIbiU=; b=uY1rF78w6swOyr2zeskevTELMOs9r+NdB91EqODDI8VgPOjXevC0RLs//3h1sSUHh9 VkQA5Tz20nYkQZQdo8mkUCJSRJM+IHQwAqFcCSxwhl8tM+8c/4I7efXYL5Xrs7/hEwmf ZGTc9foi+LumZoFJh79qBA9kVvJrsIUte+gC2Ap7m1NgoVE+A5A4h7ZBnK/WGpPIU8vH wbDeGA95TWStsE5q1s2lD16/fFRTYJHKudN/S/nJHa+iieCFWj8BfHV6v5e53pZBip+f 7jRY4/1gpdDIlLGhvqWKLaPgY1t6c0pWz2VjP3Vik8xvyVp82KHUQmSDIsyLslrrfrGM yTfg== X-Gm-Message-State: AOAM532xy2+2iahKUDNirPr3/mvcU5+CNPVi0cZY04/K084Ecd0mMYQj BAbBQI4Z1PkxWO4IJuAx3GOl+UBVBhc= X-Google-Smtp-Source: ABdhPJy57mAFQkl8U/EMjPJUT8aH/Vc9J0YUUo9k2QLbPYWa1OQfQKDlszVc4lWFm1l+vv7dwLDp1AWmaCM= X-Received: from seanjc798194.pdx.corp.google.com ([2620:15c:f:10:e012:374c:592:6194]) (user=seanjc job=sendgmr) by 2002:a25:74c6:: with SMTP id p189mr1547430ybc.251.1619060713094; Wed, 21 Apr 2021 20:05:13 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 21 Apr 2021 20:04:52 -0700 In-Reply-To: <20210422030504.3488253-1-seanjc@google.com> Message-Id: <20210422030504.3488253-3-seanjc@google.com> Mime-Version: 1.0 References: <20210422030504.3488253-1-seanjc@google.com> X-Mailer: git-send-email 2.31.1.498.g6c1eba8ee3d-goog Subject: [kvm-unit-tests PATCH 02/14] x86: msr: Exclude GS/FS_BASE MSRs from 32-bit builds From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Don't test GS/FS_BASE and KERNEL_GS_BASE on 32-bit builds, the MSRs are 64-bit only and should #GP when accessed on 32-bit vCPUs. Fixes: 7d36db3 ("Initial commit from qemu-kvm.git kvm/test/") Signed-off-by: Sean Christopherson --- x86/msr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/x86/msr.c b/x86/msr.c index ce5dabe..757156d 100644 --- a/x86/msr.c +++ b/x86/msr.c @@ -36,6 +36,7 @@ struct msr_info msr_info[] = { .index = 0x00000277, .name = "MSR_IA32_CR_PAT", .val_pairs = {{ .valid = 1, .value = 0x07070707, .expected = 0x07070707}} }, +#ifdef __x86_64__ { .index = 0xc0000100, .name = "MSR_FS_BASE", .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} }, @@ -45,7 +46,6 @@ struct msr_info msr_info[] = { .index = 0xc0000102, .name = "MSR_KERNEL_GS_BASE", .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} }, -#ifdef __x86_64__ { .index = 0xc0000080, .name = "MSR_EFER", .val_pairs = {{ .valid = 1, .value = 0xD00, .expected = 0xD00}} }, From patchwork Thu Apr 22 03:04:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 12217433 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0921C433B4 for ; Thu, 22 Apr 2021 03:05:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 81007613CD for ; Thu, 22 Apr 2021 03:05:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234409AbhDVDF4 (ORCPT ); Wed, 21 Apr 2021 23:05:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234495AbhDVDFz (ORCPT ); Wed, 21 Apr 2021 23:05:55 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8819C06138D for ; Wed, 21 Apr 2021 20:05:15 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id o187-20020a2528c40000b02904e567b4bf7eso18377803ybo.10 for ; Wed, 21 Apr 2021 20:05:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=CFrfdhHcfVHH2B4N1kkHicPXGlQbaEwRSh3X/p7ZWO8=; b=rRFMu29y2q2rLh3Nol3quvg8x+YkZ50Jlt/SAvLAacDEKEJ2qov7jg7NJcYBiQ/x0K +lea+tRxIhyYn9GKoXvOY38zk9p/AewpDtAF2QOTJedmLaczwq+/MpxApfvrkzKv0/82 cv1gM263WECZ0Q6+P1imqjbCaQnBK5Yhh/ar00zGWujrSNU+Atvx8eVZCEnKiO+wFiw9 OEo9Y5Tu/+U5AhNZ5IoTktQLqZ/jepYueP5wvjlfO9tjSh7C/wLSpDFdZBIDHGWP66gK FH8LVhAogdZTFxvyZH949VNU67N4Po/7h7G9+dvsva6c2n2ioNQqgpalc5H44MwDi4q9 DOuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=CFrfdhHcfVHH2B4N1kkHicPXGlQbaEwRSh3X/p7ZWO8=; b=DXagYYUfRcXtBWeBGVtCJAFHhU3ldNIxJVsI+vKn6ArMMZZbJ7meFKEIgc78M13Fhm RLcfhEqOa/2dwYFp8mRyTlUSAE3Qzom3+8n2ooa/XcAF2ErdaITF2uNGeEpf2okUUWvN Ostn45yDYzO9hqE5xrcNci+Nuv6Uhr9n2+0LSm0ejyTuIBNrMPn5uuRFm+Scf8hOPePq N9uQdmWU8cEmWFtEyn/GanMCVoPiSw9bVJzWGfFDwBngjJeb97p77vxQ39Oqv2RT3T7K hZKCyz4A0BHbq9ZLYPX219D+3WiaB4fuevDdYPtRjXxoS2gOBBVW2OS4daeqCagNP3fB PTRg== X-Gm-Message-State: AOAM533N5JEkjJ/DS11DnB+p6FJ6iKsqqOb8BRzYckRDyK83L5obXLZN BUyIXWcz/WjW1ewBJCdxoTX4VstdzAM= X-Google-Smtp-Source: ABdhPJwNejR3BEOg0e6pNe6b5BfqU3WCTVPOoc8AUSNljl6bz40btenbii7kubhnSF4cdnMx8nfQl+l0itQ= X-Received: from seanjc798194.pdx.corp.google.com ([2620:15c:f:10:e012:374c:592:6194]) (user=seanjc job=sendgmr) by 2002:a25:5d0b:: with SMTP id r11mr1600979ybb.380.1619060715130; Wed, 21 Apr 2021 20:05:15 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 21 Apr 2021 20:04:53 -0700 In-Reply-To: <20210422030504.3488253-1-seanjc@google.com> Message-Id: <20210422030504.3488253-4-seanjc@google.com> Mime-Version: 1.0 References: <20210422030504.3488253-1-seanjc@google.com> X-Mailer: git-send-email 2.31.1.498.g6c1eba8ee3d-goog Subject: [kvm-unit-tests PATCH 03/14] x86: msr: Advertise GenuineIntel as vendor to play nice with SYSENTER From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Run msr.flat as vendor GenuineIntel so that KVM SVM will intercept SYSENTER_ESP and SYSENTER_EIP in order to preserve bits 63:32. Alternatively, this could be handled in the test, but fudging the config is easier and it also adds coverage for KVM's aforementioned emulation. Signed-off-by: Sean Christopherson --- x86/unittests.cfg | 3 +++ 1 file changed, 3 insertions(+) diff --git a/x86/unittests.cfg b/x86/unittests.cfg index 0698d15..c2608bc 100644 --- a/x86/unittests.cfg +++ b/x86/unittests.cfg @@ -167,7 +167,10 @@ extra_params = -cpu max arch = x86_64 [msr] +# Use GenuineIntel to ensure SYSENTER MSRs are fully preserved, and to test +# SVM emulation of Intel CPU behavior. file = msr.flat +extra_params = -cpu qemu64,vendor=GenuineIntel [pmu] file = pmu.flat From patchwork Thu Apr 22 03:04:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 12217431 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A8B7C43461 for ; Thu, 22 Apr 2021 03:05:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4B05F61406 for ; Thu, 22 Apr 2021 03:05:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234493AbhDVDFy (ORCPT ); Wed, 21 Apr 2021 23:05:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232618AbhDVDFw (ORCPT ); Wed, 21 Apr 2021 23:05:52 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35DD9C06138E for ; Wed, 21 Apr 2021 20:05:18 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id v63-20020a252f420000b02904ecfc17c803so7053345ybv.18 for ; Wed, 21 Apr 2021 20:05:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=mSSHnXopyMXmFcA+159IyWL+hytDhJaLCTp1FEixKI8=; b=pSvzT9tQOaeyEWRk7E2rJi5lyN54wxyEhDI7Bk9oAynZB5db1xDE7r6K2o15Q56Ip3 /MYlQQkR8u/UbyOFPieLyv2tNFYjbXOoQ/iC4O9aql7BKbq+BumIMG9/mFpl8oQcfJUj 3Soe8zioHjD5KM8+SxR8W80Lr4hMS2xi7NZGx2FrskG4VNOYYLIEaDVU1yL/qnS+6bzE TreuFoZQg3tPY6EKlneV1X9Jd+PD245yLe+rW6KRVBi7eWL82fvlSOzwB0rqTz3Jzgly P4NPjB8A/N+AiRDbwUilNFCte5H5j0gCqPUagXnA64aPKIgwCn8rM114YkEWi2vjdbJo zquw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=mSSHnXopyMXmFcA+159IyWL+hytDhJaLCTp1FEixKI8=; b=Xo4m2xRjmXXJ8rAaqxb3Tk4nEERom9ji7JeaKXXc7QoxWl44BMpclXnQa8gqBclwlZ CgBjich4qpCTG6yrd6T3nK0ZXeN1hhqad4GsunjWyA4ONsPA71wUrlE0nBHtpuHId8lS PA8OiUd6R94d7rVIIZEURhOAqbOFGBARG5X1UPPznDPAl7KcKvnE88ESZcoYAcNwrrJq oiuMqoAy3oYpnGnQspWdWNs953Yg9aSaRM0a86mHij9oeRrxoy5vSvSHEvRPayhbb3Fm RkbQNJel1nzSXCRN8JR18CHzG65Jec8SAZhKAD1/7sRdyX9jU9++wREyKnw3nGr7TEjs bAUg== X-Gm-Message-State: AOAM5328efmaSSS+c/UK/OyeCsD554gLTyC5PyCHNtQma+sX0pXAkunQ abfqdU/twhX5EfZA+pW5LV//cak91Gw= X-Google-Smtp-Source: ABdhPJwnQwsTDVcoKI8g0vYlK6UNL4T6bk/AODRBbTuaEBljurdvtJOgNYFf0rJbzHyS4ugPbappluDELnU= X-Received: from seanjc798194.pdx.corp.google.com ([2620:15c:f:10:e012:374c:592:6194]) (user=seanjc job=sendgmr) by 2002:a5b:788:: with SMTP id b8mr1605507ybq.66.1619060717518; Wed, 21 Apr 2021 20:05:17 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 21 Apr 2021 20:04:54 -0700 In-Reply-To: <20210422030504.3488253-1-seanjc@google.com> Message-Id: <20210422030504.3488253-5-seanjc@google.com> Mime-Version: 1.0 References: <20210422030504.3488253-1-seanjc@google.com> X-Mailer: git-send-email 2.31.1.498.g6c1eba8ee3d-goog Subject: [kvm-unit-tests PATCH 04/14] x86: msr: Restore original MSR value after writing arbitrary test value From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Restore the original MSR value after the WRMSR/RDMSR test. MSR_GS_BASE in particular needs to be restored as it points at per-cpu data. Signed-off-by: Sean Christopherson --- x86/msr.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/x86/msr.c b/x86/msr.c index 757156d..5a3f1c3 100644 --- a/x86/msr.c +++ b/x86/msr.c @@ -77,7 +77,7 @@ static int find_msr_info(int msr_index) static void test_msr_rw(int msr_index, unsigned long long input, unsigned long long expected) { - unsigned long long r = 0; + unsigned long long r, orig; int index; const char *sptr; if ((index = find_msr_info(msr_index)) != -1) { @@ -86,8 +86,11 @@ static void test_msr_rw(int msr_index, unsigned long long input, unsigned long l printf("couldn't find name for msr # %#x, skipping\n", msr_index); return; } + + orig = rdmsr(msr_index); wrmsr(msr_index, input); r = rdmsr(msr_index); + wrmsr(msr_index, orig); if (expected != r) { printf("testing %s: output = %#" PRIx32 ":%#" PRIx32 " expected = %#" PRIx32 ":%#" PRIx32 "\n", sptr, From patchwork Thu Apr 22 03:04:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 12217437 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A670C433B4 for ; Thu, 22 Apr 2021 03:05:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F2E9861406 for ; Thu, 22 Apr 2021 03:05:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234453AbhDVDGA (ORCPT ); Wed, 21 Apr 2021 23:06:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234571AbhDVDF6 (ORCPT ); Wed, 21 Apr 2021 23:05:58 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FEDCC06138C for ; Wed, 21 Apr 2021 20:05:20 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id s34-20020a252d620000b02904e34d3a48abso18260483ybe.13 for ; Wed, 21 Apr 2021 20:05:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=k8kB/uxnv9kzLjc+aLY861fcn3exbD8jjXlTvKbdBc0=; b=hdXZPLc+ALcZLr+R5t4x/u6ggnfVRlH/p85VOmhZ641OOSKlL23jx7dMmTNCCd7qen HJtUFea2ZILlshoC65ebLuRnv+XXiPWfAQ8vNj0mVB6klzzDzS0vnWsw3mH5d86/uOq+ 5vmuJpH6rOOs1V/aoUaPO8e6L57eWzvH3zLYsTccU/HRyshDlSLoJitNieR3gbiPaXYJ KzAeKcN6rwnKIY5NBntxTHF23SJ4X16LhmY9xrjmOQqleRLlkTRqqPV2lkcEiLmG7j8L Hn0z+Lsr2+wu25kbjp+4cizDkGpdDmfq6dvRz5C+ftLeWyYlgc37hlp6YsGosWB1Ks4a jpZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=k8kB/uxnv9kzLjc+aLY861fcn3exbD8jjXlTvKbdBc0=; b=V8EANo5qm0e6xLjYnYI8eU0eNdcUpIRd1wEHEyhulVf8ky8jConS0At+0t2AELGVNq AxL/OrNotfpMprNWB1xRfjEWW0MNlJkG1/qNy2LYIyQO+ETZWZ+oLtqllCTaJVqMOR2j CUWIFm//nndtBtqLTugW153Fc6msc7UDHjIEz31tGcH4B2DGFQoNw4UGznpaZ4Qc9eNg zSEjvyF9xItcxgIypzkLJ6wMmBxQ4F4zkT4zUeeMOiIlnmMaGGAvQ7jNCSZ1rcXL3wFv cn7V2rV46dq3ARla6+scb5gka4Bx2bQ+7FJqAZdWkwC7eGV8d/mHKe/qwuPPDrbH3R/O oDYw== X-Gm-Message-State: AOAM532le6nFi1tmrHOuXSRFSwC1uRXQkf6Ypxwx3Tp2LqbX4hBmhD/i aVnrdtWjJlHBJSo5O08P4u6bCGkQvQA= X-Google-Smtp-Source: ABdhPJyE/C9cLKUhYN8wgjtkmrOqjU+E6l7Z11S+l4wbcqcBK8eEo8gjhALmnidtNSrcHIYqNXtOX13lPo8= X-Received: from seanjc798194.pdx.corp.google.com ([2620:15c:f:10:e012:374c:592:6194]) (user=seanjc job=sendgmr) by 2002:a25:4446:: with SMTP id r67mr1508754yba.54.1619060719812; Wed, 21 Apr 2021 20:05:19 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 21 Apr 2021 20:04:55 -0700 In-Reply-To: <20210422030504.3488253-1-seanjc@google.com> Message-Id: <20210422030504.3488253-6-seanjc@google.com> Mime-Version: 1.0 References: <20210422030504.3488253-1-seanjc@google.com> X-Mailer: git-send-email 2.31.1.498.g6c1eba8ee3d-goog Subject: [kvm-unit-tests PATCH 05/14] x86: Force the compiler to retrieve exception info from per-cpu area From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Tag the exception vector/error code/flags inline asm as volatile so that it's not elided by the compiler. Without "volatile", the compiler may omit the instruction if it inlines the helper and observes that the memory isn't modified between the store in TRY_CATCH() and the load in the helper. Signed-off-by: Sean Christopherson --- lib/x86/desc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/x86/desc.c b/lib/x86/desc.c index 983d4d8..9c1228c 100644 --- a/lib/x86/desc.c +++ b/lib/x86/desc.c @@ -249,7 +249,7 @@ unsigned exception_vector(void) { unsigned char vector; - asm("movb %%gs:4, %0" : "=q"(vector)); + asm volatile("movb %%gs:4, %0" : "=q"(vector)); return vector; } @@ -265,7 +265,7 @@ unsigned exception_error_code(void) { unsigned short error_code; - asm("mov %%gs:6, %0" : "=r"(error_code)); + asm volatile("mov %%gs:6, %0" : "=r"(error_code)); return error_code; } @@ -273,7 +273,7 @@ bool exception_rflags_rf(void) { unsigned char rf_flag; - asm("movb %%gs:5, %b0" : "=q"(rf_flag)); + asm volatile("movb %%gs:5, %b0" : "=q"(rf_flag)); return rf_flag & 1; } From patchwork Thu Apr 22 03:04:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 12217435 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C55F4C433ED for ; Thu, 22 Apr 2021 03:05:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 910E261406 for ; Thu, 22 Apr 2021 03:05:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234613AbhDVDF6 (ORCPT ); Wed, 21 Apr 2021 23:05:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234556AbhDVDF5 (ORCPT ); Wed, 21 Apr 2021 23:05:57 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E4C94C06138B for ; Wed, 21 Apr 2021 20:05:22 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id f7-20020a5b0c070000b02904e9a56ee7e7so18283295ybq.9 for ; Wed, 21 Apr 2021 20:05:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=oqXnB18Ax7b6aAuAH2aihu2SiLN86gXq87hlcE6md0Y=; b=ZSsaE9wLdrwdJaQgqY4AwfoH5qCEJkPX/kiWTYVFS5Pp18DFEe/oYS5pHWw9XjZN48 9Hm2SE1y6ndCmEF30oavTB3tQKJILwpqNvV7XQLUn36Wz65DC3eRbEQTRq/YhSZCj22z GnkCrC6KXR/jt/p7n+qwuXh8ydSLwESQxoYiFeUxGXs5A4A+PaaXrPv8uMqioxbeDGht 5orYv34OUU86JAx6TG9AK1qADlxvQe6IRqL7x98oWbU8KlQ5hXUZOUxXvsbNb1FffyYl RnaSxLgPoJHUFaBMtQAdH0e2eUFBGQv3l/LWf3ACac0ISUHZZuOZsdtOJ1st2ncZD3Fx zQ/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=oqXnB18Ax7b6aAuAH2aihu2SiLN86gXq87hlcE6md0Y=; b=PbuN0lw166eWfqeyjkgoLfnFsdpXBE4RjesypT8IVSxHT+jyMmCnVQwKoKjRd6g59a nAJnjjgm3fp9XEEtTXIxjYiEtVS4MQ4VFRH86Y2uXtMzA2g7nREqksDwg2qqVD2S13FK 0798142oSguV1Jccj+LH96l9J9BB0VZz7g5GitkPi17ZdrPu5DDaOgtclT9pcYEwXz/k aT5oXXK4W0HW8ogJY2q1QTE4j5RKTZAKbteHGeCu9sILGGAWTyMjPeZNhE24XXuDoa+C r0btHOm2eydReYwM6c/e5VbbSXonDv/f2xufpm1EZE49nckuBg95a36cPTmnbvrCJSWe 1Zbg== X-Gm-Message-State: AOAM532RsKYFKqA2981T7LSciRDuvVWSNy3yJe70Zg6MdwvzTfU69Qtq BePXAqSV5ROx7BW087gcwRCgohQ/xYM= X-Google-Smtp-Source: ABdhPJzWOYk0HRj/pAVSEYAcRpOxb28ToHI6Bb5QDAW0IPuULmctDVc8C8sdd6jhw+mVuV3Y229i96uEPCc= X-Received: from seanjc798194.pdx.corp.google.com ([2620:15c:f:10:e012:374c:592:6194]) (user=seanjc job=sendgmr) by 2002:a25:9b46:: with SMTP id u6mr1652057ybo.218.1619060722249; Wed, 21 Apr 2021 20:05:22 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 21 Apr 2021 20:04:56 -0700 In-Reply-To: <20210422030504.3488253-1-seanjc@google.com> Message-Id: <20210422030504.3488253-7-seanjc@google.com> Mime-Version: 1.0 References: <20210422030504.3488253-1-seanjc@google.com> X-Mailer: git-send-email 2.31.1.498.g6c1eba8ee3d-goog Subject: [kvm-unit-tests PATCH 06/14] x86: msr: Replace spaces with tabs in all of msr.c From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The bulk of msr.c is about to get rewritten, replace spaces with tabs so the upcoming changes don't have to propagate the existing indentation, which is a royal pain for folks whose setup assumes kernel coding style. Signed-off-by: Sean Christopherson --- x86/msr.c | 167 +++++++++++++++++++++++++++--------------------------- 1 file changed, 83 insertions(+), 84 deletions(-) diff --git a/x86/msr.c b/x86/msr.c index 5a3f1c3..1589b3b 100644 --- a/x86/msr.c +++ b/x86/msr.c @@ -5,13 +5,13 @@ #include "msr.h" struct msr_info { - int index; - const char *name; - struct tc { - int valid; - unsigned long long value; - unsigned long long expected; - } val_pairs[20]; + int index; + const char *name; + struct tc { + int valid; + unsigned long long value; + unsigned long long expected; + } val_pairs[20]; }; @@ -20,98 +20,97 @@ struct msr_info { struct msr_info msr_info[] = { - { .index = 0x00000174, .name = "IA32_SYSENTER_CS", - .val_pairs = {{ .valid = 1, .value = 0x1234, .expected = 0x1234}} - }, - { .index = 0x00000175, .name = "MSR_IA32_SYSENTER_ESP", - .val_pairs = {{ .valid = 1, .value = addr_ul, .expected = addr_ul}} - }, - { .index = 0x00000176, .name = "IA32_SYSENTER_EIP", - .val_pairs = {{ .valid = 1, .value = addr_ul, .expected = addr_ul}} - }, - { .index = 0x000001a0, .name = "MSR_IA32_MISC_ENABLE", - // reserved: 1:2, 4:6, 8:10, 13:15, 17, 19:21, 24:33, 35:63 - .val_pairs = {{ .valid = 1, .value = 0x400c51889, .expected = 0x400c51889}} - }, - { .index = 0x00000277, .name = "MSR_IA32_CR_PAT", - .val_pairs = {{ .valid = 1, .value = 0x07070707, .expected = 0x07070707}} - }, + { .index = 0x00000174, .name = "IA32_SYSENTER_CS", + .val_pairs = {{ .valid = 1, .value = 0x1234, .expected = 0x1234}} + }, + { .index = 0x00000175, .name = "MSR_IA32_SYSENTER_ESP", + .val_pairs = {{ .valid = 1, .value = addr_ul, .expected = addr_ul}} + }, + { .index = 0x00000176, .name = "IA32_SYSENTER_EIP", + .val_pairs = {{ .valid = 1, .value = addr_ul, .expected = addr_ul}} + }, + { .index = 0x000001a0, .name = "MSR_IA32_MISC_ENABLE", + // reserved: 1:2, 4:6, 8:10, 13:15, 17, 19:21, 24:33, 35:63 + .val_pairs = {{ .valid = 1, .value = 0x400c51889, .expected = 0x400c51889}} + }, + { .index = 0x00000277, .name = "MSR_IA32_CR_PAT", + .val_pairs = {{ .valid = 1, .value = 0x07070707, .expected = 0x07070707}} + }, #ifdef __x86_64__ - { .index = 0xc0000100, .name = "MSR_FS_BASE", - .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} - }, - { .index = 0xc0000101, .name = "MSR_GS_BASE", - .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} - }, - { .index = 0xc0000102, .name = "MSR_KERNEL_GS_BASE", - .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} - }, - { .index = 0xc0000080, .name = "MSR_EFER", - .val_pairs = {{ .valid = 1, .value = 0xD00, .expected = 0xD00}} - }, - { .index = 0xc0000082, .name = "MSR_LSTAR", - .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} - }, - { .index = 0xc0000083, .name = "MSR_CSTAR", - .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} - }, - { .index = 0xc0000084, .name = "MSR_SYSCALL_MASK", - .val_pairs = {{ .valid = 1, .value = 0xffffffff, .expected = 0xffffffff}} - }, + { .index = 0xc0000100, .name = "MSR_FS_BASE", + .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} + }, + { .index = 0xc0000101, .name = "MSR_GS_BASE", + .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} + }, + { .index = 0xc0000102, .name = "MSR_KERNEL_GS_BASE", + .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} + }, + { .index = 0xc0000080, .name = "MSR_EFER", + .val_pairs = {{ .valid = 1, .value = 0xD00, .expected = 0xD00}} + }, + { .index = 0xc0000082, .name = "MSR_LSTAR", + .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} + }, + { .index = 0xc0000083, .name = "MSR_CSTAR", + .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} + }, + { .index = 0xc0000084, .name = "MSR_SYSCALL_MASK", + .val_pairs = {{ .valid = 1, .value = 0xffffffff, .expected = 0xffffffff}} + }, #endif -// MSR_IA32_DEBUGCTLMSR needs svm feature LBRV -// MSR_VM_HSAVE_PA only AMD host +// MSR_IA32_DEBUGCTLMSR needs svm feature LBRV +// MSR_VM_HSAVE_PA only AMD host }; static int find_msr_info(int msr_index) { - int i; - for (i = 0; i < sizeof(msr_info)/sizeof(msr_info[0]) ; i++) { - if (msr_info[i].index == msr_index) { - return i; - } - } - return -1; + int i; + + for (i = 0; i < sizeof(msr_info)/sizeof(msr_info[0]) ; i++) { + if (msr_info[i].index == msr_index) + return i; + } + return -1; } static void test_msr_rw(int msr_index, unsigned long long input, unsigned long long expected) { - unsigned long long r, orig; - int index; - const char *sptr; - if ((index = find_msr_info(msr_index)) != -1) { - sptr = msr_info[index].name; - } else { - printf("couldn't find name for msr # %#x, skipping\n", msr_index); - return; - } + unsigned long long r, orig; + int index; + const char *sptr; - orig = rdmsr(msr_index); - wrmsr(msr_index, input); - r = rdmsr(msr_index); - wrmsr(msr_index, orig); - if (expected != r) { - printf("testing %s: output = %#" PRIx32 ":%#" PRIx32 - " expected = %#" PRIx32 ":%#" PRIx32 "\n", sptr, - (u32)(r >> 32), (u32)r, (u32)(expected >> 32), (u32)expected); - } - report(expected == r, "%s", sptr); + if ((index = find_msr_info(msr_index)) != -1) { + sptr = msr_info[index].name; + } else { + printf("couldn't find name for msr # %#x, skipping\n", msr_index); + return; + } + orig = rdmsr(msr_index); + wrmsr(msr_index, input); + r = rdmsr(msr_index); + wrmsr(msr_index, orig); + if (expected != r) { + printf("testing %s: output = %#" PRIx32 ":%#" PRIx32 + " expected = %#" PRIx32 ":%#" PRIx32 "\n", sptr, + (u32)(r >> 32), (u32)r, (u32)(expected >> 32), (u32)expected); + } + report(expected == r, "%s", sptr); } int main(int ac, char **av) { - int i, j; - for (i = 0 ; i < sizeof(msr_info) / sizeof(msr_info[0]); i++) { - for (j = 0; j < sizeof(msr_info[i].val_pairs) / sizeof(msr_info[i].val_pairs[0]); j++) { - if (msr_info[i].val_pairs[j].valid) { - test_msr_rw(msr_info[i].index, msr_info[i].val_pairs[j].value, msr_info[i].val_pairs[j].expected); - } else { - break; - } - } - } + int i, j; + for (i = 0 ; i < sizeof(msr_info) / sizeof(msr_info[0]); i++) { + for (j = 0; j < sizeof(msr_info[i].val_pairs) / sizeof(msr_info[i].val_pairs[0]); j++) { + if (msr_info[i].val_pairs[j].valid) { + test_msr_rw(msr_info[i].index, msr_info[i].val_pairs[j].value, msr_info[i].val_pairs[j].expected); + } else { + break; + } + } + } - return report_summary(); + return report_summary(); } - From patchwork Thu Apr 22 03:04:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 12217439 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37322C433B4 for ; Thu, 22 Apr 2021 03:05:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0291161406 for ; Thu, 22 Apr 2021 03:05:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234698AbhDVDGF (ORCPT ); Wed, 21 Apr 2021 23:06:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234556AbhDVDGA (ORCPT ); Wed, 21 Apr 2021 23:06:00 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EC61C06174A for ; Wed, 21 Apr 2021 20:05:25 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id z8-20020a2566480000b02904e0f6f67f42so18554642ybm.15 for ; Wed, 21 Apr 2021 20:05:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; 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Wed, 21 Apr 2021 20:05:24 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 21 Apr 2021 20:04:57 -0700 In-Reply-To: <20210422030504.3488253-1-seanjc@google.com> Message-Id: <20210422030504.3488253-8-seanjc@google.com> Mime-Version: 1.0 References: <20210422030504.3488253-1-seanjc@google.com> X-Mailer: git-send-email 2.31.1.498.g6c1eba8ee3d-goog Subject: [kvm-unit-tests PATCH 07/14] x86: msr: Use ARRAY_SIZE() instead of open coded equivalent From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Use ARRAY_SIZE() to iterate over the MSR values to read/write. No functional change intended. Signed-off-by: Sean Christopherson --- x86/msr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/x86/msr.c b/x86/msr.c index 1589b3b..b60ca94 100644 --- a/x86/msr.c +++ b/x86/msr.c @@ -102,8 +102,8 @@ static void test_msr_rw(int msr_index, unsigned long long input, unsigned long l int main(int ac, char **av) { int i, j; - for (i = 0 ; i < sizeof(msr_info) / sizeof(msr_info[0]); i++) { - for (j = 0; j < sizeof(msr_info[i].val_pairs) / sizeof(msr_info[i].val_pairs[0]); j++) { + for (i = 0 ; i < ARRAY_SIZE(msr_info); i++) { + for (j = 0; j < ARRAY_SIZE(msr_info[i].val_pairs); j++) { if (msr_info[i].val_pairs[j].valid) { test_msr_rw(msr_info[i].index, msr_info[i].val_pairs[j].value, msr_info[i].val_pairs[j].expected); } else { From patchwork Thu Apr 22 03:04:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 12217445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F97CC433B4 for ; Thu, 22 Apr 2021 03:05:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D507761428 for ; Thu, 22 Apr 2021 03:05:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234627AbhDVDGL (ORCPT ); Wed, 21 Apr 2021 23:06:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234679AbhDVDGJ (ORCPT ); Wed, 21 Apr 2021 23:06:09 -0400 Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79F4DC06138B for ; Wed, 21 Apr 2021 20:05:27 -0700 (PDT) Received: by mail-yb1-xb49.google.com with SMTP id d89-20020a25a3620000b02904dc8d0450c6so18187314ybi.2 for ; Wed, 21 Apr 2021 20:05:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=OlwYWy4ln3T9i3QnTXhy9ZtTs4wA1cxSHpskq0tbb5I=; b=C9iXc1KHtB3fo2I4oYbmgciCjD/BbUril1/5piSp1ODcouThJ02hAELypt+G4UZyI6 vpPPSMOHBz24cdctxdz9+Hv4uGo+RVzqDN+G5vE+WC0u5rBrhE6tFosv2fKA6FmSrHXW UM/FtWaYuCRQFp3kCZFgfneISOuKi6N/p1iufTbFQGBxGOFpabbXkNFu/6FB+DUkvMOQ lOxJYce7so3M/v1k2FT8CTAOtPPQm9TLggFMZiFyaLtX0eiOeKN9LASFDBhp9hpC+D8B DFnoPEkuXxaBj+Ihd5ATHUw4/VqT2/QRyr3reCnEgPL0lIpBpv8zPClb7U/NaA4bblpY 45KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=OlwYWy4ln3T9i3QnTXhy9ZtTs4wA1cxSHpskq0tbb5I=; b=KZBOJ0QdIxuIJ3XYO0TmXY7xLmkoFAC3ac05h/6Rgfyr1SgDK2iBgJ/4NkirzwPrGe n0hJK+Y1HA42FT1QEv5Z9xboEwEpY5nk7oYbA4rHBrYzVTnR3CavHpoSoUPNsnvIAQYi qq7KbKOlC98q40fnBmd4NsSkUScUrthIRaG4K6UriyfySlpSzyt+6NKbjhflUVOjS92y 3rYMLn9cw6Xul//sAccu/5T3tqDpHzOeEozeC19JHeWU8ylcgQckpAiZRWJtVUGDX4np 3iu1+4NvywCdUqRdMMxTxGPG9CziSpFcn3XJhZLdsVllSutYEMDlZ4ZSxO88ALERQBPo QjCQ== X-Gm-Message-State: AOAM530HnbHkI/yMBrrZzgC1u0PtaOLGFxZIK60UqaNaIb08BHc24lkV Ze+NQRpt2FBRFFIBDW1jnAvtSdywwoE= X-Google-Smtp-Source: ABdhPJzZOu0OVpf3PwP/Sn5vSiOPrFSSpcki2GC6manPm8qAVgYOoZe8TUBD3j/e41aM2Yt5eX7tJ9AmoDU= X-Received: from seanjc798194.pdx.corp.google.com ([2620:15c:f:10:e012:374c:592:6194]) (user=seanjc job=sendgmr) by 2002:a25:8543:: with SMTP id f3mr1590886ybn.80.1619060726784; Wed, 21 Apr 2021 20:05:26 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 21 Apr 2021 20:04:58 -0700 In-Reply-To: <20210422030504.3488253-1-seanjc@google.com> Message-Id: <20210422030504.3488253-9-seanjc@google.com> Mime-Version: 1.0 References: <20210422030504.3488253-1-seanjc@google.com> X-Mailer: git-send-email 2.31.1.498.g6c1eba8ee3d-goog Subject: [kvm-unit-tests PATCH 08/14] x86: msr: Use the #defined MSR indices in favor of open coding the values From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Use the #defines from msr.h in the MSR test, and tweak the SYSENTER names to match for good measure. No functional change intended. Signed-off-by: Sean Christopherson --- x86/msr.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/x86/msr.c b/x86/msr.c index b60ca94..0fc7978 100644 --- a/x86/msr.c +++ b/x86/msr.c @@ -20,42 +20,42 @@ struct msr_info { struct msr_info msr_info[] = { - { .index = 0x00000174, .name = "IA32_SYSENTER_CS", + { .index = MSR_IA32_SYSENTER_CS, .name = "MSR_IA32_SYSENTER_CS", .val_pairs = {{ .valid = 1, .value = 0x1234, .expected = 0x1234}} }, - { .index = 0x00000175, .name = "MSR_IA32_SYSENTER_ESP", + { .index = MSR_IA32_SYSENTER_ESP, .name = "MSR_IA32_SYSENTER_ESP", .val_pairs = {{ .valid = 1, .value = addr_ul, .expected = addr_ul}} }, - { .index = 0x00000176, .name = "IA32_SYSENTER_EIP", + { .index = MSR_IA32_SYSENTER_EIP, .name = "MSR_IA32_SYSENTER_EIP", .val_pairs = {{ .valid = 1, .value = addr_ul, .expected = addr_ul}} }, - { .index = 0x000001a0, .name = "MSR_IA32_MISC_ENABLE", + { .index = MSR_IA32_MISC_ENABLE, .name = "MSR_IA32_MISC_ENABLE", // reserved: 1:2, 4:6, 8:10, 13:15, 17, 19:21, 24:33, 35:63 .val_pairs = {{ .valid = 1, .value = 0x400c51889, .expected = 0x400c51889}} }, - { .index = 0x00000277, .name = "MSR_IA32_CR_PAT", + { .index = MSR_IA32_CR_PAT, .name = "MSR_IA32_CR_PAT", .val_pairs = {{ .valid = 1, .value = 0x07070707, .expected = 0x07070707}} }, #ifdef __x86_64__ - { .index = 0xc0000100, .name = "MSR_FS_BASE", + { .index = MSR_FS_BASE, .name = "MSR_FS_BASE", .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} }, - { .index = 0xc0000101, .name = "MSR_GS_BASE", + { .index = MSR_GS_BASE, .name = "MSR_GS_BASE", .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} }, - { .index = 0xc0000102, .name = "MSR_KERNEL_GS_BASE", + { .index = MSR_KERNEL_GS_BASE, .name = "MSR_KERNEL_GS_BASE", .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} }, - { .index = 0xc0000080, .name = "MSR_EFER", + { .index = MSR_EFER, .name = "MSR_EFER", .val_pairs = {{ .valid = 1, .value = 0xD00, .expected = 0xD00}} }, - { .index = 0xc0000082, .name = "MSR_LSTAR", + { .index = MSR_LSTAR, .name = "MSR_LSTAR", .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} }, - { .index = 0xc0000083, .name = "MSR_CSTAR", + { .index = MSR_CSTAR, .name = "MSR_CSTAR", .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} }, - { .index = 0xc0000084, .name = "MSR_SYSCALL_MASK", + { .index = MSR_SYSCALL_MASK, .name = "MSR_SYSCALL_MASK", .val_pairs = {{ .valid = 1, .value = 0xffffffff, .expected = 0xffffffff}} }, #endif From patchwork Thu Apr 22 03:04:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 12217441 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DA69C433B4 for ; Thu, 22 Apr 2021 03:05:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D725C61406 for ; Thu, 22 Apr 2021 03:05:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234645AbhDVDGI (ORCPT ); Wed, 21 Apr 2021 23:06:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234614AbhDVDGE (ORCPT ); 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d=1e100.net; s=20161025; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=/hPihdfDLlJWXy3VwGT97nXrafoTQe+XsLxpHyUwmm0=; b=KTnSmVGioxIF9/bsh5Ll7xP0swi3yYdwZITTSpTkc1ZjOf2rdC+EEfwNBmwuiT9mN/ jQurxPLMq8HNvtmXYYnI4xd7An+CKWYnc2ukGvdpEl7Ma97tDrWMId/eU2INQWuu3WSI F6sVYO8ByLAY9nJCayvu6ZWL/okZo+psS7yDNNxG+WlEWLT/5noXCFPO3ysG5sCLn8su z/lIk3B/UEnEyXmFHW3GDhJ3t0lrTAAC3eG1NuDnUXnKDx3rvROKTMH429++ejeRMyJg IgsP2dese2XsKnHD/dA8GE9pINFQ/XYcDJgFyjYMbXh21vbH5ihBrXKdU3uaXjFjqDAD pXVQ== X-Gm-Message-State: AOAM531GpS02/F8V7+RhLbPT2j+7E5EpJVpzc9S+ejbDrTZDlzHh5Au8 u1zBokx4WRPdddn3tNB+5IqXKV4AAlA= X-Google-Smtp-Source: ABdhPJyV5LcQ281d42gUiijX8MdxU0V6hftFZK7vQqp/1Y+93V8FWtIWR5uFxWIAx/hDkELVWXIxZmAxJSU= X-Received: from seanjc798194.pdx.corp.google.com ([2620:15c:f:10:e012:374c:592:6194]) (user=seanjc job=sendgmr) by 2002:a25:3450:: with SMTP id b77mr1537793yba.211.1619060729041; Wed, 21 Apr 2021 20:05:29 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 21 Apr 2021 20:04:59 -0700 In-Reply-To: <20210422030504.3488253-1-seanjc@google.com> Message-Id: <20210422030504.3488253-10-seanjc@google.com> Mime-Version: 1.0 References: <20210422030504.3488253-1-seanjc@google.com> X-Mailer: git-send-email 2.31.1.498.g6c1eba8ee3d-goog Subject: [kvm-unit-tests PATCH 09/14] x86: msr: Drop the explicit expected value From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Use the written value as the expected value. For the vast majority of MSRs, including all those currently tested, the expected value will always be the last written value. This will simplify handling EFER on 32-bit vCPUs in a future patch. Signed-off-by: Sean Christopherson --- x86/msr.c | 37 +++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/x86/msr.c b/x86/msr.c index 0fc7978..9031043 100644 --- a/x86/msr.c +++ b/x86/msr.c @@ -21,42 +21,42 @@ struct msr_info { struct msr_info msr_info[] = { { .index = MSR_IA32_SYSENTER_CS, .name = "MSR_IA32_SYSENTER_CS", - .val_pairs = {{ .valid = 1, .value = 0x1234, .expected = 0x1234}} + .val_pairs = {{ .valid = 1, .value = 0x1234 }} }, { .index = MSR_IA32_SYSENTER_ESP, .name = "MSR_IA32_SYSENTER_ESP", - .val_pairs = {{ .valid = 1, .value = addr_ul, .expected = addr_ul}} + .val_pairs = {{ .valid = 1, .value = addr_ul }} }, { .index = MSR_IA32_SYSENTER_EIP, .name = "MSR_IA32_SYSENTER_EIP", - .val_pairs = {{ .valid = 1, .value = addr_ul, .expected = addr_ul}} + .val_pairs = {{ .valid = 1, .value = addr_ul }} }, { .index = MSR_IA32_MISC_ENABLE, .name = "MSR_IA32_MISC_ENABLE", // reserved: 1:2, 4:6, 8:10, 13:15, 17, 19:21, 24:33, 35:63 - .val_pairs = {{ .valid = 1, .value = 0x400c51889, .expected = 0x400c51889}} + .val_pairs = {{ .valid = 1, .value = 0x400c51889 }} }, { .index = MSR_IA32_CR_PAT, .name = "MSR_IA32_CR_PAT", - .val_pairs = {{ .valid = 1, .value = 0x07070707, .expected = 0x07070707}} + .val_pairs = {{ .valid = 1, .value = 0x07070707 }} }, #ifdef __x86_64__ { .index = MSR_FS_BASE, .name = "MSR_FS_BASE", - .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} + .val_pairs = {{ .valid = 1, .value = addr_64 }} }, { .index = MSR_GS_BASE, .name = "MSR_GS_BASE", - .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} + .val_pairs = {{ .valid = 1, .value = addr_64 }} }, { .index = MSR_KERNEL_GS_BASE, .name = "MSR_KERNEL_GS_BASE", - .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} + .val_pairs = {{ .valid = 1, .value = addr_64 }} }, { .index = MSR_EFER, .name = "MSR_EFER", - .val_pairs = {{ .valid = 1, .value = 0xD00, .expected = 0xD00}} + .val_pairs = {{ .valid = 1, .value = 0xD00 }} }, { .index = MSR_LSTAR, .name = "MSR_LSTAR", - .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} + .val_pairs = {{ .valid = 1, .value = addr_64 }} }, { .index = MSR_CSTAR, .name = "MSR_CSTAR", - .val_pairs = {{ .valid = 1, .value = addr_64, .expected = addr_64}} + .val_pairs = {{ .valid = 1, .value = addr_64 }} }, { .index = MSR_SYSCALL_MASK, .name = "MSR_SYSCALL_MASK", - .val_pairs = {{ .valid = 1, .value = 0xffffffff, .expected = 0xffffffff}} + .val_pairs = {{ .valid = 1, .value = 0xffffffff }} }, #endif @@ -75,7 +75,7 @@ static int find_msr_info(int msr_index) return -1; } -static void test_msr_rw(int msr_index, unsigned long long input, unsigned long long expected) +static void test_msr_rw(int msr_index, unsigned long long val) { unsigned long long r, orig; int index; @@ -87,16 +87,17 @@ static void test_msr_rw(int msr_index, unsigned long long input, unsigned long l printf("couldn't find name for msr # %#x, skipping\n", msr_index); return; } + orig = rdmsr(msr_index); - wrmsr(msr_index, input); + wrmsr(msr_index, val); r = rdmsr(msr_index); wrmsr(msr_index, orig); - if (expected != r) { + if (r != val) { printf("testing %s: output = %#" PRIx32 ":%#" PRIx32 " expected = %#" PRIx32 ":%#" PRIx32 "\n", sptr, - (u32)(r >> 32), (u32)r, (u32)(expected >> 32), (u32)expected); + (u32)(r >> 32), (u32)r, (u32)(val >> 32), (u32)val); } - report(expected == r, "%s", sptr); + report(val == r, "%s", sptr); } int main(int ac, char **av) @@ -105,7 +106,7 @@ int main(int ac, char **av) for (i = 0 ; i < ARRAY_SIZE(msr_info); i++) { for (j = 0; j < ARRAY_SIZE(msr_info[i].val_pairs); j++) { if (msr_info[i].val_pairs[j].valid) { - test_msr_rw(msr_info[i].index, msr_info[i].val_pairs[j].value, msr_info[i].val_pairs[j].expected); + test_msr_rw(msr_info[i].index, msr_info[i].val_pairs[j].value); } else { break; } From patchwork Thu Apr 22 03:05:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 12217443 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B75CC433ED for ; Thu, 22 Apr 2021 03:05:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D9D6561406 for ; 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No functional change intended. Signed-off-by: Sean Christopherson --- x86/msr.c | 74 ++++++++++++++++--------------------------------------- 1 file changed, 21 insertions(+), 53 deletions(-) diff --git a/x86/msr.c b/x86/msr.c index 9031043..4473950 100644 --- a/x86/msr.c +++ b/x86/msr.c @@ -7,59 +7,33 @@ struct msr_info { int index; const char *name; - struct tc { - int valid; - unsigned long long value; - unsigned long long expected; - } val_pairs[20]; + unsigned long long value; }; #define addr_64 0x0000123456789abcULL #define addr_ul (unsigned long)addr_64 +#define MSR_TEST(msr, val) \ + { .index = msr, .name = #msr, .value = val } + struct msr_info msr_info[] = { - { .index = MSR_IA32_SYSENTER_CS, .name = "MSR_IA32_SYSENTER_CS", - .val_pairs = {{ .valid = 1, .value = 0x1234 }} - }, - { .index = MSR_IA32_SYSENTER_ESP, .name = "MSR_IA32_SYSENTER_ESP", - .val_pairs = {{ .valid = 1, .value = addr_ul }} - }, - { .index = MSR_IA32_SYSENTER_EIP, .name = "MSR_IA32_SYSENTER_EIP", - .val_pairs = {{ .valid = 1, .value = addr_ul }} - }, - { .index = MSR_IA32_MISC_ENABLE, .name = "MSR_IA32_MISC_ENABLE", - // reserved: 1:2, 4:6, 8:10, 13:15, 17, 19:21, 24:33, 35:63 - .val_pairs = {{ .valid = 1, .value = 0x400c51889 }} - }, - { .index = MSR_IA32_CR_PAT, .name = "MSR_IA32_CR_PAT", - .val_pairs = {{ .valid = 1, .value = 0x07070707 }} - }, + MSR_TEST(MSR_IA32_SYSENTER_CS, 0x1234), + MSR_TEST(MSR_IA32_SYSENTER_ESP, addr_ul), + MSR_TEST(MSR_IA32_SYSENTER_EIP, addr_ul), + // reserved: 1:2, 4:6, 8:10, 13:15, 17, 19:21, 24:33, 35:63 + MSR_TEST(MSR_IA32_MISC_ENABLE, 0x400c51889), + MSR_TEST(MSR_IA32_CR_PAT, 0x07070707), #ifdef __x86_64__ - { .index = MSR_FS_BASE, .name = "MSR_FS_BASE", - .val_pairs = {{ .valid = 1, .value = addr_64 }} - }, - { .index = MSR_GS_BASE, .name = "MSR_GS_BASE", - .val_pairs = {{ .valid = 1, .value = addr_64 }} - }, - { .index = MSR_KERNEL_GS_BASE, .name = "MSR_KERNEL_GS_BASE", - .val_pairs = {{ .valid = 1, .value = addr_64 }} - }, - { .index = MSR_EFER, .name = "MSR_EFER", - .val_pairs = {{ .valid = 1, .value = 0xD00 }} - }, - { .index = MSR_LSTAR, .name = "MSR_LSTAR", - .val_pairs = {{ .valid = 1, .value = addr_64 }} - }, - { .index = MSR_CSTAR, .name = "MSR_CSTAR", - .val_pairs = {{ .valid = 1, .value = addr_64 }} - }, - { .index = MSR_SYSCALL_MASK, .name = "MSR_SYSCALL_MASK", - .val_pairs = {{ .valid = 1, .value = 0xffffffff }} - }, + MSR_TEST(MSR_FS_BASE, addr_64), + MSR_TEST(MSR_GS_BASE, addr_64), + MSR_TEST(MSR_KERNEL_GS_BASE, addr_64), + MSR_TEST(MSR_EFER, 0xD00), + MSR_TEST(MSR_LSTAR, addr_64), + MSR_TEST(MSR_CSTAR, addr_64), + MSR_TEST(MSR_SYSCALL_MASK, 0xffffffff), #endif - // MSR_IA32_DEBUGCTLMSR needs svm feature LBRV // MSR_VM_HSAVE_PA only AMD host }; @@ -102,16 +76,10 @@ static void test_msr_rw(int msr_index, unsigned long long val) int main(int ac, char **av) { - int i, j; - for (i = 0 ; i < ARRAY_SIZE(msr_info); i++) { - for (j = 0; j < ARRAY_SIZE(msr_info[i].val_pairs); j++) { - if (msr_info[i].val_pairs[j].valid) { - test_msr_rw(msr_info[i].index, msr_info[i].val_pairs[j].value); - } else { - break; - } - } - } + int i; + + for (i = 0 ; i < ARRAY_SIZE(msr_info); i++) + test_msr_rw(msr_info[i].index, msr_info[i].value); return report_summary(); } From patchwork Thu Apr 22 03:05:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 12217447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1FBCC43460 for ; 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Wed, 21 Apr 2021 20:05:33 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 21 Apr 2021 20:05:01 -0700 In-Reply-To: <20210422030504.3488253-1-seanjc@google.com> Message-Id: <20210422030504.3488253-12-seanjc@google.com> Mime-Version: 1.0 References: <20210422030504.3488253-1-seanjc@google.com> X-Mailer: git-send-email 2.31.1.498.g6c1eba8ee3d-goog Subject: [kvm-unit-tests PATCH 11/14] x86: msr: Pass msr_info instead of doing a lookup at runtime From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Pass the msr_info to test_msr_rw() instead of passing a subset of the struct info and then using that to look up the struct. Pass the value to write as a separate parameter, doing so will simplify upcoming patches. Signed-off-by: Sean Christopherson --- x86/msr.c | 36 ++++++++---------------------------- 1 file changed, 8 insertions(+), 28 deletions(-) diff --git a/x86/msr.c b/x86/msr.c index 4473950..4642451 100644 --- a/x86/msr.c +++ b/x86/msr.c @@ -38,40 +38,20 @@ struct msr_info msr_info[] = // MSR_VM_HSAVE_PA only AMD host }; -static int find_msr_info(int msr_index) -{ - int i; - - for (i = 0; i < sizeof(msr_info)/sizeof(msr_info[0]) ; i++) { - if (msr_info[i].index == msr_index) - return i; - } - return -1; -} - -static void test_msr_rw(int msr_index, unsigned long long val) +static void test_msr_rw(struct msr_info *msr, unsigned long long val) { unsigned long long r, orig; - int index; - const char *sptr; - if ((index = find_msr_info(msr_index)) != -1) { - sptr = msr_info[index].name; - } else { - printf("couldn't find name for msr # %#x, skipping\n", msr_index); - return; - } - - orig = rdmsr(msr_index); - wrmsr(msr_index, val); - r = rdmsr(msr_index); - wrmsr(msr_index, orig); + orig = rdmsr(msr->index); + wrmsr(msr->index, val); + r = rdmsr(msr->index); + wrmsr(msr->index, orig); if (r != val) { printf("testing %s: output = %#" PRIx32 ":%#" PRIx32 - " expected = %#" PRIx32 ":%#" PRIx32 "\n", sptr, + " expected = %#" PRIx32 ":%#" PRIx32 "\n", msr->name, (u32)(r >> 32), (u32)r, (u32)(val >> 32), (u32)val); } - report(val == r, "%s", sptr); + report(val == r, "%s", msr->name); } int main(int ac, char **av) @@ -79,7 +59,7 @@ int main(int ac, char **av) int i; for (i = 0 ; i < ARRAY_SIZE(msr_info); i++) - test_msr_rw(msr_info[i].index, msr_info[i].value); + test_msr_rw(&msr_info[i], msr_info[i].value); return report_summary(); } From patchwork Thu Apr 22 03:05:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 12217449 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60628C433ED for ; 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Wed, 21 Apr 2021 20:05:35 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 21 Apr 2021 20:05:02 -0700 In-Reply-To: <20210422030504.3488253-1-seanjc@google.com> Message-Id: <20210422030504.3488253-13-seanjc@google.com> Mime-Version: 1.0 References: <20210422030504.3488253-1-seanjc@google.com> X-Mailer: git-send-email 2.31.1.498.g6c1eba8ee3d-goog Subject: [kvm-unit-tests PATCH 12/14] x86: msr: Verify 64-bit only MSRs fault on 32-bit hosts From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Assert that 64-bit only MSRs take a #GP when read or written on 32-bit hosts, as opposed to simply skipping the MSRs on 32-bit builds. Force "cpu -host" so that CPUID can be used to check for 64-bit support. Technically, the unit test could/should be even more aggressive and require KVM to inject faults if the vCPU model doesn't support 64-bit mode. But, there are no plans to go to that level of emulation in KVM, and practically speaking there isn't much benefit as allowing a 32-bit vCPU to access the MSRs on a 64-bit host is a benign virtualization hole. Signed-off-by: Sean Christopherson --- lib/x86/processor.h | 22 +++++++++++++++++ x86/msr.c | 57 ++++++++++++++++++++++++++++++++------------- x86/unittests.cfg | 6 +++-- 3 files changed, 67 insertions(+), 18 deletions(-) diff --git a/lib/x86/processor.h b/lib/x86/processor.h index dda57a1..dfe96d0 100644 --- a/lib/x86/processor.h +++ b/lib/x86/processor.h @@ -2,6 +2,7 @@ #define LIBCFLAT_PROCESSOR_H #include "libcflat.h" +#include "desc.h" #include "msr.h" #include @@ -163,6 +164,7 @@ static inline u8 cpuid_maxphyaddr(void) #define X86_FEATURE_ARCH_CAPABILITIES (CPUID(0x7, 0, EDX, 29)) #define X86_FEATURE_PKS (CPUID(0x7, 0, ECX, 31)) #define X86_FEATURE_NX (CPUID(0x80000001, 0, EDX, 20)) +#define X86_FEATURE_LM (CPUID(0x80000001, 0, EDX, 29)) #define X86_FEATURE_RDPRU (CPUID(0x80000008, 0, EBX, 4)) /* @@ -320,6 +322,26 @@ static inline void wrmsr(u32 index, u64 val) asm volatile ("wrmsr" : : "a"(a), "d"(d), "c"(index) : "memory"); } +static inline int rdmsr_checking(u32 index) +{ + asm volatile (ASM_TRY("1f") + "rdmsr\n\t" + "1:" + : : "c"(index) : "memory", "eax", "edx"); + return exception_vector(); +} + +static inline int wrmsr_checking(u32 index, u64 val) +{ + u32 a = val, d = val >> 32; + + asm volatile (ASM_TRY("1f") + "wrmsr\n\t" + "1:" + : : "a"(a), "d"(d), "c"(index) : "memory"); + return exception_vector(); +} + static inline uint64_t rdpmc(uint32_t index) { uint32_t a, d; diff --git a/x86/msr.c b/x86/msr.c index 4642451..e7ebe8b 100644 --- a/x86/msr.c +++ b/x86/msr.c @@ -6,6 +6,7 @@ struct msr_info { int index; + bool is_64bit_only; const char *name; unsigned long long value; }; @@ -14,26 +15,26 @@ struct msr_info { #define addr_64 0x0000123456789abcULL #define addr_ul (unsigned long)addr_64 -#define MSR_TEST(msr, val) \ - { .index = msr, .name = #msr, .value = val } +#define MSR_TEST(msr, val, only64) \ + { .index = msr, .name = #msr, .value = val, .is_64bit_only = only64 } struct msr_info msr_info[] = { - MSR_TEST(MSR_IA32_SYSENTER_CS, 0x1234), - MSR_TEST(MSR_IA32_SYSENTER_ESP, addr_ul), - MSR_TEST(MSR_IA32_SYSENTER_EIP, addr_ul), + MSR_TEST(MSR_IA32_SYSENTER_CS, 0x1234, false), + MSR_TEST(MSR_IA32_SYSENTER_ESP, addr_ul, false), + MSR_TEST(MSR_IA32_SYSENTER_EIP, addr_ul, false), // reserved: 1:2, 4:6, 8:10, 13:15, 17, 19:21, 24:33, 35:63 - MSR_TEST(MSR_IA32_MISC_ENABLE, 0x400c51889), - MSR_TEST(MSR_IA32_CR_PAT, 0x07070707), + MSR_TEST(MSR_IA32_MISC_ENABLE, 0x400c51889, false), + MSR_TEST(MSR_IA32_CR_PAT, 0x07070707, false), + MSR_TEST(MSR_FS_BASE, addr_64, true), + MSR_TEST(MSR_GS_BASE, addr_64, true), + MSR_TEST(MSR_KERNEL_GS_BASE, addr_64, true), #ifdef __x86_64__ - MSR_TEST(MSR_FS_BASE, addr_64), - MSR_TEST(MSR_GS_BASE, addr_64), - MSR_TEST(MSR_KERNEL_GS_BASE, addr_64), - MSR_TEST(MSR_EFER, 0xD00), - MSR_TEST(MSR_LSTAR, addr_64), - MSR_TEST(MSR_CSTAR, addr_64), - MSR_TEST(MSR_SYSCALL_MASK, 0xffffffff), + MSR_TEST(MSR_EFER, 0xD00, false), #endif + MSR_TEST(MSR_LSTAR, addr_64, true), + MSR_TEST(MSR_CSTAR, addr_64, true), + MSR_TEST(MSR_SYSCALL_MASK, 0xffffffff, true), // MSR_IA32_DEBUGCTLMSR needs svm feature LBRV // MSR_VM_HSAVE_PA only AMD host }; @@ -54,12 +55,36 @@ static void test_msr_rw(struct msr_info *msr, unsigned long long val) report(val == r, "%s", msr->name); } +static void test_wrmsr_fault(struct msr_info *msr, unsigned long long val) +{ + unsigned char vector = wrmsr_checking(msr->index, val); + + report(vector == GP_VECTOR, + "Expected #GP on WRSMR(%s, 0x%llx), got vector %d", + msr->name, val, vector); +} + +static void test_rdmsr_fault(struct msr_info *msr) +{ + unsigned char vector = rdmsr_checking(msr->index); + + report(vector == GP_VECTOR, + "Expected #GP on RDSMR(%s), got vector %d", msr->name, vector); +} + int main(int ac, char **av) { + bool is_64bit_host = this_cpu_has(X86_FEATURE_LM); int i; - for (i = 0 ; i < ARRAY_SIZE(msr_info); i++) - test_msr_rw(&msr_info[i], msr_info[i].value); + for (i = 0 ; i < ARRAY_SIZE(msr_info); i++) { + if (is_64bit_host || !msr_info[i].is_64bit_only) { + test_msr_rw(&msr_info[i], msr_info[i].value); + } else { + test_wrmsr_fault(&msr_info[i], msr_info[i].value); + test_rdmsr_fault(&msr_info[i]); + } + } return report_summary(); } diff --git a/x86/unittests.cfg b/x86/unittests.cfg index c2608bc..29cfe51 100644 --- a/x86/unittests.cfg +++ b/x86/unittests.cfg @@ -168,9 +168,11 @@ arch = x86_64 [msr] # Use GenuineIntel to ensure SYSENTER MSRs are fully preserved, and to test -# SVM emulation of Intel CPU behavior. +# SVM emulation of Intel CPU behavior. Use the host CPU model so that 64-bit +# support follows the host kernel. Running a 32-bit guest on a 64-bit host +# will fail due to shortcomings in KVM. file = msr.flat -extra_params = -cpu qemu64,vendor=GenuineIntel +extra_params = -cpu host,vendor=GenuineIntel [pmu] file = pmu.flat From patchwork Thu Apr 22 03:05:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 12217453 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87A7CC433ED for ; Thu, 22 Apr 2021 03:05:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 61DF5613CD for ; Thu, 22 Apr 2021 03:05:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234751AbhDVDGZ (ORCPT ); Wed, 21 Apr 2021 23:06:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234707AbhDVDGT (ORCPT ); Wed, 21 Apr 2021 23:06:19 -0400 Received: from mail-yb1-xb4a.google.com (mail-yb1-xb4a.google.com [IPv6:2607:f8b0:4864:20::b4a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF952C06174A for ; Wed, 21 Apr 2021 20:05:38 -0700 (PDT) Received: by mail-yb1-xb4a.google.com with SMTP id k5-20020a2524050000b02904e716d0d7b1so18190666ybk.0 for ; Wed, 21 Apr 2021 20:05:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=reply-to:date:in-reply-to:message-id:mime-version:references :subject:from:to:cc; bh=ePlwClNSozxsM4hkTmvffDCYGXRwrtXezElqBmwEyv8=; b=V2Vlo+gMyAyvVHrK24Nhep6dCSAZ0xJqIM8pEwozjlQk+9bUsWh5msEzicvxY96GWV Wpl9La74mcWzsInbh6VBO5WeNkkv6XjoxXfzUd7fjf6z3MNZQ2W5lOFOfL37jXzFoPH2 jkKomUy2Amhas+lzWtnNl+qXwiF6+lYGBkBwGDiW7/sZ7WZEUvFhWapPEkdyO6IRTNvs gmV+p+xbFNMov0lEXp12vkz1QgF3tqo/UR4KGy8aMdTaLD5TCDRCs0KoyIzPTcyMUmud nMXmu+3H6CPzZHWu4wztDCY5NC5T7+7qFtEMcDlRo7bQjJq//jrvltRHkjn0bzu6ULdM J/qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:reply-to:date:in-reply-to:message-id :mime-version:references:subject:from:to:cc; bh=ePlwClNSozxsM4hkTmvffDCYGXRwrtXezElqBmwEyv8=; b=PavXNz5Wx39qK/hH0h2VDIP/wvXW6XjoVf/kfT2G2xu3DSelnyb2xlgsA9iQ+eGLKN SXSMIUaucHW8jP3gCD0LAnlHVBr18quJEgd3T0dDbNTx0cpk67shtlB6fVWUwGHRxWfk 4faFiPLEhIuXYRKIBCdVjDc1+D747YNNdcNXOqKL3JfUvOcL/eExYF+p0tW3RNzpphou MtzRygEqtLvoWKTflVrOQoF0ihpI85kPbjh5q66f63gecgwKRRrKocPsc/pPz5z065+I npIll3ShSxjNF0rc90bkDU3RQsTvXoAzcqxNHIDD8h6tvI6MgopTIYNyMuIe9lmUPWx4 gKwg== X-Gm-Message-State: AOAM531tHvc5LdlAq9A1ALRA3eEeQ+hGUGyQPhc47l/2d26xQIi9spob A0paKECBTFgEJhP8uIEFXpT3uoB8UEE= X-Google-Smtp-Source: ABdhPJz2XJkQSsU0xPvS6yPvnqB1MTA6sy3Wd0TC8kAuKCDsc9BTiBGHNZWsTyvd27+kCviBKk8mT01DxY0= X-Received: from seanjc798194.pdx.corp.google.com ([2620:15c:f:10:e012:374c:592:6194]) (user=seanjc job=sendgmr) by 2002:a25:8884:: with SMTP id d4mr1657363ybl.410.1619060738001; Wed, 21 Apr 2021 20:05:38 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 21 Apr 2021 20:05:03 -0700 In-Reply-To: <20210422030504.3488253-1-seanjc@google.com> Message-Id: <20210422030504.3488253-14-seanjc@google.com> Mime-Version: 1.0 References: <20210422030504.3488253-1-seanjc@google.com> X-Mailer: git-send-email 2.31.1.498.g6c1eba8ee3d-goog Subject: [kvm-unit-tests PATCH 13/14] x86: msr: Test that always-canonical MSRs #GP on non-canonical value From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Verify that WRMSR takes a #GP when writing a non-canonical value to a MSR that always takes a 64-bit address. Specifically, AMD doesn't enforce a canonical address for the SYSENTER MSRs. Signed-off-by: Sean Christopherson --- lib/x86/processor.h | 2 ++ x86/msr.c | 8 ++++++++ x86/vmx_tests.c | 2 -- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/lib/x86/processor.h b/lib/x86/processor.h index dfe96d0..abc04b0 100644 --- a/lib/x86/processor.h +++ b/lib/x86/processor.h @@ -6,6 +6,8 @@ #include "msr.h" #include +#define NONCANONICAL 0xaaaaaaaaaaaaaaaaull + #ifdef __x86_64__ # define R "r" # define W "q" diff --git a/x86/msr.c b/x86/msr.c index e7ebe8b..8a1b0b2 100644 --- a/x86/msr.c +++ b/x86/msr.c @@ -80,6 +80,14 @@ int main(int ac, char **av) for (i = 0 ; i < ARRAY_SIZE(msr_info); i++) { if (is_64bit_host || !msr_info[i].is_64bit_only) { test_msr_rw(&msr_info[i], msr_info[i].value); + + /* + * The 64-bit only MSRs that take an address always perform + * canonical checks on both Intel and AMD. + */ + if (msr_info[i].is_64bit_only && + msr_info[i].value == addr_64) + test_wrmsr_fault(&msr_info[i], NONCANONICAL); } else { test_wrmsr_fault(&msr_info[i], msr_info[i].value); test_rdmsr_fault(&msr_info[i]); diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c index bbb006a..2eb5962 100644 --- a/x86/vmx_tests.c +++ b/x86/vmx_tests.c @@ -21,8 +21,6 @@ #include "smp.h" #include "delay.h" -#define NONCANONICAL 0xaaaaaaaaaaaaaaaaull - #define VPID_CAP_INVVPID_TYPES_SHIFT 40 u64 ia32_pat; From patchwork Thu Apr 22 03:05:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 12217451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48247C433B4 for ; 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Wed, 21 Apr 2021 20:05:40 -0700 (PDT) Reply-To: Sean Christopherson Date: Wed, 21 Apr 2021 20:05:04 -0700 In-Reply-To: <20210422030504.3488253-1-seanjc@google.com> Message-Id: <20210422030504.3488253-15-seanjc@google.com> Mime-Version: 1.0 References: <20210422030504.3488253-1-seanjc@google.com> X-Mailer: git-send-email 2.31.1.498.g6c1eba8ee3d-goog Subject: [kvm-unit-tests PATCH 14/14] x86: msr: Verify that EFER.SCE can be written on 32-bit vCPUs From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Verify that EFER can be written, and that the SYSCALL enable bit can be set, on 32-bit vCPUs. Signed-off-by: Sean Christopherson --- x86/msr.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/x86/msr.c b/x86/msr.c index 8a1b0b2..7a551c4 100644 --- a/x86/msr.c +++ b/x86/msr.c @@ -29,9 +29,7 @@ struct msr_info msr_info[] = MSR_TEST(MSR_FS_BASE, addr_64, true), MSR_TEST(MSR_GS_BASE, addr_64, true), MSR_TEST(MSR_KERNEL_GS_BASE, addr_64, true), -#ifdef __x86_64__ - MSR_TEST(MSR_EFER, 0xD00, false), -#endif + MSR_TEST(MSR_EFER, EFER_SCE, false), MSR_TEST(MSR_LSTAR, addr_64, true), MSR_TEST(MSR_CSTAR, addr_64, true), MSR_TEST(MSR_SYSCALL_MASK, 0xffffffff, true), @@ -44,6 +42,13 @@ static void test_msr_rw(struct msr_info *msr, unsigned long long val) unsigned long long r, orig; orig = rdmsr(msr->index); + /* + * Special case EFER since clearing LME/LMA is not allowed in 64-bit mode, + * and conversely setting those bits on 32-bit CPUs is not allowed. Treat + * the desired value as extra bits to set. + */ + if (msr->index == MSR_EFER) + val |= orig; wrmsr(msr->index, val); r = rdmsr(msr->index); wrmsr(msr->index, orig);