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Shenoy" To: "Rafael J. Wysocki" , Daniel Lezcano , Michael Ellerman , "Aneesh Kumar K.V" , Vaidyanathan Srinivasan Cc: linuxppc-dev@lists.ozlabs.org, linux-pm@vger.kernel.org, joedecke@de.ibm.com, "Gautham R. Shenoy" Subject: [PATCH] cpuidle/pseries: Fixup CEDE0 latency only for POWER10 onwards Date: Thu, 22 Apr 2021 20:37:29 +0530 Message-Id: <1619104049-5118-1-git-send-email-ego@linux.vnet.ibm.com> X-Mailer: git-send-email 1.8.3.1 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: WKU2eVXCss5iPN0ei4XY1NBuKM0NE3_s X-Proofpoint-ORIG-GUID: WKU2eVXCss5iPN0ei4XY1NBuKM0NE3_s X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391,18.0.761 definitions=2021-04-22_06:2021-04-22,2021-04-22 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 clxscore=1011 spamscore=0 mlxlogscore=999 malwarescore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104060000 definitions=main-2104220120 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: "Gautham R. Shenoy" Commit d947fb4c965c ("cpuidle: pseries: Fixup exit latency for CEDE(0)") sets the exit latency of CEDE(0) based on the latency values of the Extended CEDE states advertised by the platform On some of the POWER9 LPARs, the older firmwares advertise a very low value of 2us for CEDE1 exit latency on a Dedicated LPAR. However the measured value is 5us on an average. Due to the low advertised exit latency, we are entering CEDE(0) more aggressively on such platforms. While this helps achieve SMT folding faster, we pay the penalty of having to send an IPI to wakeup the CPU when the target residency is very short. This is showing up as a performance regression on the newer kernels running on the LPARs with older firmware. Hence, set the exit latency of CEDE(0) based on the latency values advertized by platform only from POWER10 onwards. The values advertized on POWER10 platforms is more realistic and informed by the latency measurements. For platforms older than POWER10, retain the hardcoded value of exit latency, which is 10us. Though this is higher than the measured values, we would be erring on the side of caution. Reported-by: Enrico Joedecke Fixes: commit d947fb4c965c ("cpuidle: pseries: Fixup exit latency for CEDE(0)") Signed-off-by: Gautham R. Shenoy Reviewed-by: Vaidyanathan Srinivasan --- drivers/cpuidle/cpuidle-pseries.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cpuidle/cpuidle-pseries.c b/drivers/cpuidle/cpuidle-pseries.c index a2b5c6f..7207467 100644 --- a/drivers/cpuidle/cpuidle-pseries.c +++ b/drivers/cpuidle/cpuidle-pseries.c @@ -419,7 +419,8 @@ static int pseries_idle_probe(void) cpuidle_state_table = shared_states; max_idle_state = ARRAY_SIZE(shared_states); } else { - fixup_cede0_latency(); + if (pvr_version_is(PVR_POWER10)) + fixup_cede0_latency(); cpuidle_state_table = dedicated_states; max_idle_state = NR_DEDICATED_STATES; }