From patchwork Fri Apr 23 01:47:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12219383 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0F9DC43462 for ; Fri, 23 Apr 2021 01:47:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AB40061176 for ; Fri, 23 Apr 2021 01:47:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240129AbhDWBsc (ORCPT ); Thu, 22 Apr 2021 21:48:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235569AbhDWBsa (ORCPT ); Thu, 22 Apr 2021 21:48:30 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79961C06174A; Thu, 22 Apr 2021 18:47:54 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id mh2so50046224ejb.8; Thu, 22 Apr 2021 18:47:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CIfIzGZkRa2NlAensBq+Zlw+3TjmXuG3tgcd/3/lGKI=; b=JlzwpJ/Euj/7X4ge1iIjjqTYcQtDI/+3MVVk07wfdtsaFUA3jY7YWGwy2mVYl2Bjm3 DbiHAwpYXEYGqU95IImGCYvc0P2zkXhZea62Dqzrpkb0xdPpM/7o8aO95qv3tT0xxNiN APg1dLzLFj/mmwgFwpWr6sdvnBMnZLuRzLLExj/4BPVCB9oJW7Azh30uSPtCLNkCi9c/ M7A9DuULoLyPTtsbhNHRkRQBP3iiibweQoVnqjpWbaZRgKbd5RtjDa+9wPCzqOkVxptX NxQQCRRLI21dihb0nXfVqfwDeLnKLo1jTSKhusiHnunDTZJG7t9wvWBwTSjNaTKGGOUW RApQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CIfIzGZkRa2NlAensBq+Zlw+3TjmXuG3tgcd/3/lGKI=; b=rc26KG8yc5mDkAACRLMH3EXNPe96vPjO39I+XqKrS89M6ak4YoSf74w0EAd53zz1dk RFNThvHpnTwqozOyn2kRYmtfl3CiWQhT6qFQOmrI1YFQiYrTi13hhCJb01ULZXzixOgU H5em50Xbxm5YZnKFHGhFBlDTXS7kZbll3f/Fx8A/nC/QqqCZn9ElozMFhkdhKoNiWxCV 0VK2g91TRADY4CthR1V6EiNJQMurQP8qk1xVRl505UPaJ4B6qG+SUiyaw6rWa7j0Ud37 bLqUCFEia8cGnYS6P56sF2n3DVeqMwPuTySHR92s8QIbslcSEvNLwSpqJnwoM1LON3T5 Kzkg== X-Gm-Message-State: AOAM532a7GOzbOPFRL/FFSz1vD1+edWTqlI0kzSAPvy2GzYcZ3YItmW5 94lnRUhPuSgg8FXj3qRF5Hg= X-Google-Smtp-Source: ABdhPJykHko9F5h7yYMHgNh8UDMMTP4nnC63v1uuhQt6Umv3TSULWgGJti3xdS5HYf/LOCkccj3BNQ== X-Received: by 2002:a17:906:138c:: with SMTP id f12mr1611358ejc.180.1619142473184; Thu, 22 Apr 2021 18:47:53 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.47.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:47:52 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/14] drivers: net: dsa: qca8k: handle error with set_page Date: Fri, 23 Apr 2021 03:47:27 +0200 Message-Id: <20210423014741.11858-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Better handle function qca8k_set_page. The original code requires a deleay of 5us and set the current page only if the bus write has not failed. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index cdaf9f85a2cb..a6d35b825c0e 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -133,9 +133,12 @@ qca8k_set_page(struct mii_bus *bus, u16 page) if (page == qca8k_current_page) return; - if (bus->write(bus, 0x18, 0, page) < 0) + if (bus->write(bus, 0x18, 0, page)) { dev_err_ratelimited(&bus->dev, "failed to set qca8k page\n"); + return; + } + qca8k_current_page = page; } From patchwork Fri Apr 23 01:47:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12219385 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A335DC433B4 for ; Fri, 23 Apr 2021 01:48:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7AFBD61176 for ; Fri, 23 Apr 2021 01:48:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235569AbhDWBsf (ORCPT ); Thu, 22 Apr 2021 21:48:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240094AbhDWBsb (ORCPT ); Thu, 22 Apr 2021 21:48:31 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 048D8C061574; Thu, 22 Apr 2021 18:47:56 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id bx20so54579636edb.12; Thu, 22 Apr 2021 18:47:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pvbtV9z9Nr84yi5HQm0Sl3OJ0RmRKTgXaB8Aibs1Fi8=; b=EfRbrmuBOsfwwNIQNwN5GJp3OecEYddJmdaOR6JSbMsoY6lBC76RhjCTvceB0TPBd2 77S72/SYUO+z6E9y6A8iuGSV4h7Q27S0GqdEuhMp1KazW0IJpqyjiScuPSGO0SFRrSAz WnoTOh+LU0E5vUxZO59H1jFFN2CtOiIMRaiUMUZMLw0pucHTvFQc6y64awrM8uR9VXyC bR/dNgD0OPiU9usH0Yfk5ggv9J0E8twIM/Z/oV4dhKml8R43Z4UilpG2gQprQV0Ls0id /uVPlVqt+Oar8hY7GB+milL4VAr8MWSp8tjbxfSvaDpZh79aQvZi/cGsiKKdglcSskyl f1tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pvbtV9z9Nr84yi5HQm0Sl3OJ0RmRKTgXaB8Aibs1Fi8=; b=EUXRBRtv9uTqKjBc+Br08W77oJmjBSAmCDOZf6s8+Zfy2Q9y9r6BtC6sY5yQY6eaQN zTdy7Hof6aYBB0KnI2HqltLOICZct0VSi9im1M/oC6cZmEn2HwL/cuhv/yzcAMS78hkO A36Nb0Cg69wSlKZIEVkd9z8jN9cB648OdszlQWmQWANxtPe0LofRPyismBQOE1WZfgVj CHPXT8afef6xMd/5gj3E2ZDyxljaZUkbW4GvOD5dyI0MKTYS2Yqzrd5Xx+mlNjC0wH58 J3MJkbs45hlv30QiU4AXqoc9UGJJ6SQqiHWNVJWhHTElV1RULuLrQa9hb5qAu937QcAH ZEnQ== X-Gm-Message-State: AOAM5334cXKuHFxvYZWmf48OsJrlkXWuvBdwND10f9WIdN9oexwLAbK9 UmXdUqxNgGOGua+zX6EM2Jw= X-Google-Smtp-Source: ABdhPJxyUWMKaSFu4paSngAiB+5r6Rkz9pq5QLh3DwWoyDCpPTxn6OBbJPJGdeBTBeVqYp6gwZLQKw== X-Received: by 2002:aa7:c78a:: with SMTP id n10mr1527723eds.239.1619142474723; Thu, 22 Apr 2021 18:47:54 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.47.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:47:54 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/14] drivers: net: dsa: qca8k: tweak internal delay to oem spec Date: Fri, 23 Apr 2021 03:47:28 +0200 Message-Id: <20210423014741.11858-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The original code had the internal dalay set to 1 for tx and 2 for rx. Apply the oem internal dalay to fix some switch communication error. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 6 ++++-- drivers/net/dsa/qca8k.h | 9 ++++----- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index a6d35b825c0e..b8bfc7acf6f4 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -849,8 +849,10 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, */ qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN | - QCA8K_PORT_PAD_RGMII_TX_DELAY(QCA8K_MAX_DELAY) | - QCA8K_PORT_PAD_RGMII_RX_DELAY(QCA8K_MAX_DELAY)); + QCA8K_PORT_PAD_RGMII_TX_DELAY(1) | + QCA8K_PORT_PAD_RGMII_RX_DELAY(2) | + QCA8K_PORT_PAD_RGMII_TX_DELAY_EN | + QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); break; diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 7ca4b93e0bb5..e0b679133880 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -32,12 +32,11 @@ #define QCA8K_REG_PORT5_PAD_CTRL 0x008 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c #define QCA8K_PORT_PAD_RGMII_EN BIT(26) -#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) \ - ((0x8 + (x & 0x3)) << 22) -#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) \ - ((0x10 + (x & 0x3)) << 20) -#define QCA8K_MAX_DELAY 3 +#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) ((x) << 22) +#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) ((x) << 20) +#define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25) #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24) +#define QCA8K_MAX_DELAY 3 #define QCA8K_PORT_PAD_SGMII_EN BIT(7) #define QCA8K_REG_PWS 0x010 #define QCA8K_PWS_SERDES_AEN_DIS BIT(7) From patchwork Fri Apr 23 01:47:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12219387 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24199C43461 for ; Fri, 23 Apr 2021 01:48:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id F2B746145E for ; Fri, 23 Apr 2021 01:48:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240248AbhDWBsh (ORCPT ); Thu, 22 Apr 2021 21:48:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236126AbhDWBsd (ORCPT ); Thu, 22 Apr 2021 21:48:33 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D5EFC061574; Thu, 22 Apr 2021 18:47:57 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id r20so21855159ejo.11; Thu, 22 Apr 2021 18:47:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=q9gaocBlk1TPMqWqSo24Pc1wb4Ov1hZl7cSxG+HTprk=; b=Dj+5ckk2rTGumx9FfCWvmxxcDx06KjZjwBK6VYRhtTnCAoh/a9B6l0QFPEPPn6W3ub mtqBtwQliJ17nn4bppWH9j+uJsxY3SxWJm8gY8C1wRBnpoR3bFJr6COtgCLgBDtirELG 8U6HZ5CSXvt4YJVhH89sJbXKsbSdZm3gg7UQqmtuiK37We6oK385EJJnNJtq8zfJcU5b 9Uk9hGLeDcM6epx9chmdlhklIFBh3pVcr3Q2L1y3DeRWa+vosSaz86hGvPoGNkgpcpfh /30g4sLFaqkmp9STm9UOa3UgLVm54nhboXhL5dCdtbESVM0XczRSL7CO0rGpQoAbspbE tcxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=q9gaocBlk1TPMqWqSo24Pc1wb4Ov1hZl7cSxG+HTprk=; b=RSUKKu6TQ7Z+RwcOGM3HxC/QydpHP/81TkntmMhA09uTJp/eRcTMfHYtzVbUS1Ch7A H6pAnJfJo5l8tyFYi1zR34UkXH6nFTGbibMHfwn4EvZXj4xj66bMfJZT3TJBFBsbB3gH H99YuGGTubS2ufEJtSQ6buKFg4fzV+RbeIFz3dS+pf+nxUJZBxFHDek/dh/vjofZNqrO gZEGiu9MmD7h36h/n9NzGHcFkwNvI9+N06UqnG6Jyh5T6FsBY9tDzam5klqKR2bmMufk wqbPHnPt4u6s/7aPzBhBqd7vO0NwmEplC8awPBmIuNfdMkDRRXquJtCLfyKiLTSDisyw U5gg== X-Gm-Message-State: AOAM532ciCRK4H0DFQGk6Ay4tK9cH8JZn8oJTVkfUauri8sF8DCdOjRQ CM3I4MwImtlpCJ9B644XXww= X-Google-Smtp-Source: ABdhPJwtwQQgziVfHwY7UWl0SRDKT0e8BrDzig5Jv05DklRZ2tfQdUYLG2GGAhyp2Kyow6HtXYrikw== X-Received: by 2002:a17:906:b2d8:: with SMTP id cf24mr1561407ejb.305.1619142476265; Thu, 22 Apr 2021 18:47:56 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.47.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:47:55 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/14] drivers: net: mdio: mdio-ip8064: improve busy wait delay Date: Fri, 23 Apr 2021 03:47:29 +0200 Message-Id: <20210423014741.11858-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org With the use of the qca8k dsa driver, some problem arised related to port status detection. With a load on a specific port (for example a simple speed test), the driver starts to bheave in a strange way and garbage data is produced. To address this, enlarge the sleep delay and address a bug for the reg offset 31 that require additional delay for this specific reg. Signed-off-by: Ansuel Smith --- drivers/net/mdio/mdio-ipq8064.c | 36 ++++++++++++++++++++------------- 1 file changed, 22 insertions(+), 14 deletions(-) diff --git a/drivers/net/mdio/mdio-ipq8064.c b/drivers/net/mdio/mdio-ipq8064.c index 1bd18857e1c5..5bd6d0501642 100644 --- a/drivers/net/mdio/mdio-ipq8064.c +++ b/drivers/net/mdio/mdio-ipq8064.c @@ -15,25 +15,26 @@ #include /* MII address register definitions */ -#define MII_ADDR_REG_ADDR 0x10 -#define MII_BUSY BIT(0) -#define MII_WRITE BIT(1) -#define MII_CLKRANGE_60_100M (0 << 2) -#define MII_CLKRANGE_100_150M (1 << 2) -#define MII_CLKRANGE_20_35M (2 << 2) -#define MII_CLKRANGE_35_60M (3 << 2) -#define MII_CLKRANGE_150_250M (4 << 2) -#define MII_CLKRANGE_250_300M (5 << 2) +#define MII_ADDR_REG_ADDR 0x10 +#define MII_BUSY BIT(0) +#define MII_WRITE BIT(1) +#define MII_CLKRANGE(x) ((x) << 2) +#define MII_CLKRANGE_60_100M MII_CLKRANGE(0) +#define MII_CLKRANGE_100_150M MII_CLKRANGE(1) +#define MII_CLKRANGE_20_35M MII_CLKRANGE(2) +#define MII_CLKRANGE_35_60M MII_CLKRANGE(3) +#define MII_CLKRANGE_150_250M MII_CLKRANGE(4) +#define MII_CLKRANGE_250_300M MII_CLKRANGE(5) #define MII_CLKRANGE_MASK GENMASK(4, 2) #define MII_REG_SHIFT 6 #define MII_REG_MASK GENMASK(10, 6) #define MII_ADDR_SHIFT 11 #define MII_ADDR_MASK GENMASK(15, 11) -#define MII_DATA_REG_ADDR 0x14 +#define MII_DATA_REG_ADDR 0x14 -#define MII_MDIO_DELAY_USEC (1000) -#define MII_MDIO_RETRY_MSEC (10) +#define MII_MDIO_DELAY_USEC (1000) +#define MII_MDIO_RETRY_MSEC (10) struct ipq8064_mdio { struct regmap *base; /* NSS_GMAC0_BASE */ @@ -65,7 +66,7 @@ ipq8064_mdio_read(struct mii_bus *bus, int phy_addr, int reg_offset) ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); - usleep_range(8, 10); + usleep_range(10, 13); err = ipq8064_mdio_wait_busy(priv); if (err) @@ -91,7 +92,14 @@ ipq8064_mdio_write(struct mii_bus *bus, int phy_addr, int reg_offset, u16 data) ((reg_offset << MII_REG_SHIFT) & MII_REG_MASK); regmap_write(priv->base, MII_ADDR_REG_ADDR, miiaddr); - usleep_range(8, 10); + + /* For the specific reg 31 extra time is needed or the next + * read will produce grabage data. + */ + if (reg_offset == 31) + usleep_range(30, 43); + else + usleep_range(10, 13); return ipq8064_mdio_wait_busy(priv); } From patchwork Fri Apr 23 01:47:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12219389 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70D19C433ED for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:47:57 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/14] drivers: net: dsa: qca8k: apply suggested packet priority Date: Fri, 23 Apr 2021 03:47:30 +0200 Message-Id: <20210423014741.11858-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The port 5 of the ar8337 have some problem in flood condition. The original legacy driver had some specific buffer and priority settings for the different port suggested by the QCA switch team. Add this missing settings to improve switch stability under load condition. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 42 +++++++++++++++++++++++++++++++++++++++++ drivers/net/dsa/qca8k.h | 24 +++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index b8bfc7acf6f4..7408cbee05c2 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -701,6 +701,7 @@ qca8k_setup(struct dsa_switch *ds) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; int ret, i; + u32 mask; /* Make sure that port 0 is the cpu port */ if (!dsa_is_cpu_port(ds, 0)) { @@ -785,6 +786,47 @@ qca8k_setup(struct dsa_switch *ds) priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN; qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN); + /* The port 5 of the switch ar8337 have some problem in flood condition. + * To fix this the original code has some specific priority values + * suggested by the QCA switch team. + */ + for (i = 0; i < QCA8K_NUM_PORTS; i++) { + switch (i) { + /* The 2 CPU port and port 5 requires some different + * priority than any other ports. + */ + case 0: + case 5: + case 6: + mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | + QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) | + QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) | + QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e); + break; + default: + mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | + QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) | + QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) | + QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19); + } + qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask); + + mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) | + QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | + QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | + QCA8K_PORT_HOL_CTRL1_WRED_EN; + qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i), + QCA8K_PORT_HOL_CTRL1_ING_BUF | + QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | + QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | + QCA8K_PORT_HOL_CTRL1_WRED_EN, + mask); + } + /* Flush the FDB table */ qca8k_fdb_flush(priv); diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index e0b679133880..0ff7abbd40dc 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -163,6 +163,30 @@ #define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16) #define QCA8K_PORT_LOOKUP_LEARN BIT(20) +#define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF GENMASK(7, 4) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) ((x) << 4) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF GENMASK(11, 8) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) ((x) << 8) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF GENMASK(15, 12) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) ((x) << 12) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF GENMASK(19, 16) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) ((x) << 16) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF GENMASK(23, 20) +#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) ((x) << 20) +#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF GENMASK(29, 24) +#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) ((x) << 24) + +#define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8) +#define QCA8K_PORT_HOL_CTRL1_ING_BUF GENMASK(3, 0) +#define QCA8K_PORT_HOL_CTRL1_ING(x) ((x) << 0) +#define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6) +#define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7) +#define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8) +#define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16) + /* Pkt edit registers */ #define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2))) From patchwork Fri Apr 23 01:47:31 2021 Content-Type: text/plain; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.47.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:47:59 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/14] drivers: net: dsa: qca8k: add support for qca8327 switch Date: Fri, 23 Apr 2021 03:47:31 +0200 Message-Id: <20210423014741.11858-6-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org qca8327 switch is a low tier version of the more recent qca8337. It does share the same regs used by the qca8k driver and can be supported with minimal change. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 21 ++++++++++++++++++--- drivers/net/dsa/qca8k.h | 6 ++++++ 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 7408cbee05c2..ca12394c2ff7 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1440,6 +1440,7 @@ static const struct dsa_switch_ops qca8k_switch_ops = { static int qca8k_sw_probe(struct mdio_device *mdiodev) { + const struct qca8k_match_data *data; struct qca8k_priv *priv; u32 id; @@ -1467,11 +1468,16 @@ qca8k_sw_probe(struct mdio_device *mdiodev) gpiod_set_value_cansleep(priv->reset_gpio, 0); } + /* get the switches ID from the compatible */ + data = of_device_get_match_data(&mdiodev->dev); + if (!data) + return -ENODEV; + /* read the switches ID register */ id = qca8k_read(priv, QCA8K_REG_MASK_CTRL); id >>= QCA8K_MASK_CTRL_ID_S; id &= QCA8K_MASK_CTRL_ID_M; - if (id != QCA8K_ID_QCA8337) + if (id != data->id) return -ENODEV; priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); @@ -1537,9 +1543,18 @@ static int qca8k_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(qca8k_pm_ops, qca8k_suspend, qca8k_resume); +static const struct qca8k_match_data qca832x = { + .id = QCA8K_ID_QCA8327, +}; + +static const struct qca8k_match_data qca833x = { + .id = QCA8K_ID_QCA8337, +}; + static const struct of_device_id qca8k_of_match[] = { - { .compatible = "qca,qca8334" }, - { .compatible = "qca,qca8337" }, + { .compatible = "qca,qca8327", .data = &qca832x }, + { .compatible = "qca,qca8334", .data = &qca833x }, + { .compatible = "qca,qca8337", .data = &qca833x }, { /* sentinel */ }, }; diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 0ff7abbd40dc..d94129371a1c 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -15,6 +15,8 @@ #define QCA8K_NUM_PORTS 7 #define QCA8K_MAX_MTU 9000 +#define PHY_ID_QCA8327 0x004dd034 +#define QCA8K_ID_QCA8327 0x12 #define PHY_ID_QCA8337 0x004dd036 #define QCA8K_ID_QCA8337 0x13 @@ -234,6 +236,10 @@ struct ar8xxx_port_status { int enabled; }; +struct qca8k_match_data { + u8 id; +}; + struct qca8k_priv { struct regmap *regmap; struct mii_bus *bus; From patchwork Fri Apr 23 01:47:32 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12219391 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2D97C433B4 for ; Fri, 23 Apr 2021 01:48:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8D339613D1 for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.48.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:48:00 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/14] devicetree: net: dsa: qca8k: Document new compatible qca8327 Date: Fri, 23 Apr 2021 03:47:32 +0200 Message-Id: <20210423014741.11858-7-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Add support for qca8327 in the compatible list. Signed-off-by: Ansuel Smith --- Documentation/devicetree/bindings/net/dsa/qca8k.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt index ccbc6d89325d..1daf68e7ae19 100644 --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt @@ -3,6 +3,7 @@ Required properties: - compatible: should be one of: + "qca,qca8327" "qca,qca8334" "qca,qca8337" From patchwork Fri Apr 23 01:47:33 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12219393 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4889CC433ED for ; Fri, 23 Apr 2021 01:48:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 228E661450 for ; Fri, 23 Apr 2021 01:48:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240456AbhDWBtK (ORCPT ); Thu, 22 Apr 2021 21:49:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240298AbhDWBso (ORCPT ); Thu, 22 Apr 2021 21:48:44 -0400 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E6AB1C061346; Thu, 22 Apr 2021 18:48:03 -0700 (PDT) Received: by mail-ed1-x536.google.com with SMTP id y3so19423484eds.5; Thu, 22 Apr 2021 18:48:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uhLbsqsD1UeBHl9g3+cRO5/yYo+Kk02FCDPrTgf7heY=; b=gfOqBa4VU57XUrhMExIO4kzxF0q76b9VjVo5c0m9+3PkoQG4lW/dfPOWOMxXoEG4Rl rLRjMrt6YoMr/UGZRkfSzs/ZIXRsYnjTvRGnnpI8uvs8M94nXTbgZFljDdxb9aVENmyV GzUOnZ20++UKybTLVQLpt4L7b8jmc96L5L1sYISGZMTewEn+q+htKqfpAsXxEfraH53x dm+6+v/iXdpgBhKBfW0irqG4FdAbPmyfxL4JoPYAxdY5j+42xI08KOliMSlii7gNGeq+ l5lNcrnNsybIKSCPENm2Pir4M+Bx0mRe92fE/vLHk9xRMnfpwSjiXtQwe+eC4NUSilpw CVFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uhLbsqsD1UeBHl9g3+cRO5/yYo+Kk02FCDPrTgf7heY=; b=mSBFWAwfhnNtXqHOJMbYoiJp8FUmYqzcC0Ejw7c8zgk2oI+6h3qWBIqx6kxfNQaBIc fAvxzHTcODXQCtKZahRTl9AIHzWGHY2/uzQ1jeEHiv0A3HXkViNO7vH9qr5HwhkbME8F nYkRoQDy5xOnXCSCiJco3+cgyZ4rnmqo8JC686QnYS9UBHIr341YOSa+zdiP35RTKeF7 2rSWUw0YrNrN9lV0D6iOjaEk7dzYEfgjP2s47UmrJPGpU9CUsABrJW53dFPFZURX1FKU ZGfKYV3rcMHlL/bXzTrhmNTgi0lGK+mPrWt0sEJfZItfU1fiIDktYk/H+jAKtEdEIHY9 eucQ== X-Gm-Message-State: AOAM531NkeHSu0vMCC1OHArduuwCevd/ZEC85XAX0eG05h+TmgnlAr9b 38ogBycwl68DugNKbCVrxYI= X-Google-Smtp-Source: ABdhPJxvpvfxgIEe8vQvP3vgLGG6GwZ6QXsujtBXl3GyinOBxHQ5gjTHTmgXbjMd9/t4ESV7dEbBXw== X-Received: by 2002:a05:6402:5189:: with SMTP id q9mr1574997edd.168.1619142482566; Thu, 22 Apr 2021 18:48:02 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.48.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:48:02 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/14] drivers: net: dsa: qca8k: limit priority tweak to qca8337 switch Date: Fri, 23 Apr 2021 03:47:33 +0200 Message-Id: <20210423014741.11858-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org The packet priority tweak and the rx delay is specific to qca8337. Limit this changes to qca8337 as now we also support 8327 switch. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 84 +++++++++++++++++++++++------------------ 1 file changed, 48 insertions(+), 36 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index ca12394c2ff7..19bb3754d9ec 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -700,9 +700,13 @@ static int qca8k_setup(struct dsa_switch *ds) { struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; + const struct qca8k_match_data *data; int ret, i; u32 mask; + /* get the switches ID from the compatible */ + data = of_device_get_match_data(priv->dev); + /* Make sure that port 0 is the cpu port */ if (!dsa_is_cpu_port(ds, 0)) { pr_err("port 0 is not the CPU port\n"); @@ -790,41 +794,43 @@ qca8k_setup(struct dsa_switch *ds) * To fix this the original code has some specific priority values * suggested by the QCA switch team. */ - for (i = 0; i < QCA8K_NUM_PORTS; i++) { - switch (i) { - /* The 2 CPU port and port 5 requires some different - * priority than any other ports. - */ - case 0: - case 5: - case 6: - mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | - QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | - QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) | - QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) | - QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) | - QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) | - QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e); - break; - default: - mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | - QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | - QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) | - QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) | - QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19); + if (data->id == QCA8K_ID_QCA8337) { + for (i = 0; i < QCA8K_NUM_PORTS; i++) { + switch (i) { + /* The 2 CPU port and port 5 requires some different + * priority than any other ports. + */ + case 0: + case 5: + case 6: + mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | + QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) | + QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) | + QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e); + break; + default: + mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | + QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | + QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) | + QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) | + QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19); + } + qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask); + + mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) | + QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | + QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | + QCA8K_PORT_HOL_CTRL1_WRED_EN; + qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i), + QCA8K_PORT_HOL_CTRL1_ING_BUF | + QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | + QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | + QCA8K_PORT_HOL_CTRL1_WRED_EN, + mask); } - qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask); - - mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) | - QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | - QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | - QCA8K_PORT_HOL_CTRL1_WRED_EN; - qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i), - QCA8K_PORT_HOL_CTRL1_ING_BUF | - QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | - QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | - QCA8K_PORT_HOL_CTRL1_WRED_EN, - mask); } /* Flush the FDB table */ @@ -840,9 +846,13 @@ static void qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, const struct phylink_link_state *state) { + const struct qca8k_match_data *data; struct qca8k_priv *priv = ds->priv; u32 reg, val; + /* get the switches ID from the compatible */ + data = of_device_get_match_data(priv->dev); + switch (port) { case 0: /* 1st CPU port */ if (state->interface != PHY_INTERFACE_MODE_RGMII && @@ -895,8 +905,10 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, QCA8K_PORT_PAD_RGMII_RX_DELAY(2) | QCA8K_PORT_PAD_RGMII_TX_DELAY_EN | QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); - qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, - QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); + /* QCA8337 requires to set rgmii rx delay */ + if (data->id == QCA8K_ID_QCA8337) + qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, + QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); break; case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_1000BASEX: From patchwork Fri Apr 23 01:47:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12219397 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E92C2C433ED for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.48.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:48:03 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/14] drivers: net: dsa: qca8k: add GLOBAL_FC settings needed for qca8327 Date: Fri, 23 Apr 2021 03:47:34 +0200 Message-Id: <20210423014741.11858-9-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Switch qca8327 needs special settings for the GLOBAL_FC_THRES regs. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 10 ++++++++++ drivers/net/dsa/qca8k.h | 6 ++++++ 2 files changed, 16 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 19bb3754d9ec..d469620e9344 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -833,6 +833,16 @@ qca8k_setup(struct dsa_switch *ds) } } + /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */ + if (data->id == QCA8K_ID_QCA8327) { + mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) | + QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496); + qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH, + QCA8K_GLOBAL_FC_GOL_XON_THRES_S | + QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S, + mask); + } + /* Flush the FDB table */ qca8k_fdb_flush(priv); diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index d94129371a1c..308d8410fdb6 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -165,6 +165,12 @@ #define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16) #define QCA8K_PORT_LOOKUP_LEARN BIT(20) +#define QCA8K_REG_GLOBAL_FC_THRESH 0x800 +#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) ((x) << 16) +#define QCA8K_GLOBAL_FC_GOL_XON_THRES_S GENMASK(24, 16) +#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) ((x) << 0) +#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S GENMASK(8, 0) + #define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8) #define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0) #define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0) From patchwork Fri Apr 23 01:47:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12219399 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A2D1C43460 for ; Fri, 23 Apr 2021 01:48:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5553961176 for ; Fri, 23 Apr 2021 01:48:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240596AbhDWBtR (ORCPT ); Thu, 22 Apr 2021 21:49:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240316AbhDWBsr (ORCPT ); Thu, 22 Apr 2021 21:48:47 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF550C06134D; Thu, 22 Apr 2021 18:48:06 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id w3so71654369ejc.4; Thu, 22 Apr 2021 18:48:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ta/24bWMmOyYH0LkZJ/c9X9HhCw4uvrp/JaOe0WLGx8=; b=dnePvmwmfnfjGtaXok0oA+2WEP5op+gEC1ZQBQHoZTvLhzs183bxibVEI7Cf/8+0EY ero1M7J8QiJon23nWQ0SM11QtIOFXlxtsEI12XyyoxrY4vyyx9nsdB65gMrt6eBBVuyQ AH0V+FE0DVd4dgmFFN6rpu33dTRiPWruR9Z25j2OSYGbyGzh99FgkvVHopTzmyjvPyG2 ABTgprwozoi5wB+0fXWcyepunKhuokLgumeWCXAPxmO1vD3mvSqnGcEZAhKHY24tTYbc +83rFjtm8wS251NRPCNf6u45hthvBVEodTdRg4rKghJyotivgcHmnDDFu+V9EIIaxz+C 3Qbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ta/24bWMmOyYH0LkZJ/c9X9HhCw4uvrp/JaOe0WLGx8=; b=NxZVif3At4tm5/O6jPErCfIOx5eal6B1iHTy35QxFDttEr8tIxzGSgf71A8habPpVa /7fX4qoKvHEMVlJ+TQQ89/ilkcZMpLiqJmTl1YzXUyCJ30T/WLxvFf7mkK5G97kh1Hl9 D4tNxrK/ofnehDCZthuSnhC6OavsOA75CproSuRZlcsofKv/BuD3/8TOcJvUc51CCF1j t1iBgt6fm6lQUCLHxXlMIMfTX9FDtKsmiFFdhTc1Qvb7Ea8/YfmtJVrIwINRssMu3UVS Q9nWQlMO8dEsUt9V041ShTa39L/xIA6eRZNGYdeu2kUhcneukJ1uekf/ysjZ+eI/PKCs U0zw== X-Gm-Message-State: AOAM530O4ex8WVxYy7ahyiKvgrx6cBiHc003jPVKspFUtV2oyZRtx8mU RpuZ+Ox7aJMCPHUrU6x6Vs8= X-Google-Smtp-Source: ABdhPJyIn5/kU+wl5mDo1jaJpqVilJxwzjagRUYrR5rhBIUrOAmQHAl/vISyfimWOeJ9QP6+Rmasig== X-Received: by 2002:a17:907:215a:: with SMTP id rk26mr1614122ejb.225.1619142485653; Thu, 22 Apr 2021 18:48:05 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.48.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:48:05 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/14] drivers: net: dsa: qca8k: add support for switch rev Date: Fri, 23 Apr 2021 03:47:35 +0200 Message-Id: <20210423014741.11858-10-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org qca8k switch require some special debug value to be set based on the switch revision. Rework the switch id read function to also read the chip revision and make it accessible to the switch data. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 17 ++++++++++++----- drivers/net/dsa/qca8k.h | 7 +++++-- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index d469620e9344..20b507a35191 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -1459,12 +1459,22 @@ static const struct dsa_switch_ops qca8k_switch_ops = { .phylink_mac_link_up = qca8k_phylink_mac_link_up, }; +static u8 qca8k_read_switch_id(struct qca8k_priv *priv) +{ + u32 val; + + val = qca8k_read(priv, QCA8K_REG_MASK_CTRL); + + priv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK); + + return QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK); +} + static int qca8k_sw_probe(struct mdio_device *mdiodev) { const struct qca8k_match_data *data; struct qca8k_priv *priv; - u32 id; /* allocate the private data struct so that we can probe the switches * ID register @@ -1496,10 +1506,7 @@ qca8k_sw_probe(struct mdio_device *mdiodev) return -ENODEV; /* read the switches ID register */ - id = qca8k_read(priv, QCA8K_REG_MASK_CTRL); - id >>= QCA8K_MASK_CTRL_ID_S; - id &= QCA8K_MASK_CTRL_ID_M; - if (id != data->id) + if (qca8k_read_switch_id(priv) != data->id) return -ENODEV; priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index 308d8410fdb6..dbd54d870a30 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -28,8 +28,10 @@ /* Global control registers */ #define QCA8K_REG_MASK_CTRL 0x000 -#define QCA8K_MASK_CTRL_ID_M 0xff -#define QCA8K_MASK_CTRL_ID_S 8 +#define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0) +#define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0) +#define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8) +#define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8) #define QCA8K_REG_PORT0_PAD_CTRL 0x004 #define QCA8K_REG_PORT5_PAD_CTRL 0x008 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c @@ -247,6 +249,7 @@ struct qca8k_match_data { }; struct qca8k_priv { + u8 switch_revision; struct regmap *regmap; struct mii_bus *bus; struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS]; From patchwork Fri Apr 23 01:47:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12219409 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27F07C433ED for ; Fri, 23 Apr 2021 01:49:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 089D76145A for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.48.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:48:06 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/14] drivers: net: dsa: qca8k: add support for specific QCA access function Date: Fri, 23 Apr 2021 03:47:36 +0200 Message-Id: <20210423014741.11858-11-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Some qca8k switch revision require some special dbg value to be set based on the revision number. Add required function to write and read in these specific registers. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 51 +++++++++++++++++++++++++++++++++++++++++ drivers/net/dsa/qca8k.h | 2 ++ 2 files changed, 53 insertions(+) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 20b507a35191..193c269d8ed3 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -69,6 +69,57 @@ static const struct qca8k_mib_desc ar8327_mib[] = { MIB_DESC(1, 0xa4, "TxLateCol"), }; +/* QCA specific MII registers access function */ +void qca8k_phy_dbg_read(struct qca8k_priv *priv, int phy_addr, u16 dbg_addr, u16 *dbg_data) +{ + struct mii_bus *bus = priv->bus; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr); + *dbg_data = bus->read(bus, phy_addr, MII_ATH_DBG_DATA); + mutex_unlock(&bus->mdio_lock); +} + +void qca8k_phy_dbg_write(struct qca8k_priv *priv, int phy_addr, u16 dbg_addr, u16 dbg_data) +{ + struct mii_bus *bus = priv->bus; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr); + bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data); + mutex_unlock(&bus->mdio_lock); +} + +static inline void qca8k_phy_mmd_prep(struct mii_bus *bus, int phy_addr, u16 addr, u16 reg) +{ + bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr); + bus->write(bus, phy_addr, MII_ATH_MMD_DATA, reg); + bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr | 0x4000); +} + +void qca8k_phy_mmd_write(struct qca8k_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data) +{ + struct mii_bus *bus = priv->bus; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + qca8k_phy_mmd_prep(bus, phy_addr, addr, reg); + bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data); + mutex_unlock(&bus->mdio_lock); +} + +u16 qca8k_phy_mmd_read(struct qca8k_priv *priv, int phy_addr, u16 addr, u16 reg) +{ + struct mii_bus *bus = priv->bus; + u16 data; + + mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); + qca8k_phy_mmd_prep(bus, phy_addr, addr, reg); + data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA); + mutex_unlock(&bus->mdio_lock); + + return data; +} + /* The 32bit switch registers are accessed indirectly. To achieve this we need * to set the page of the register. Track the last page that was set to reduce * mdio writes diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h index dbd54d870a30..de00aa74868b 100644 --- a/drivers/net/dsa/qca8k.h +++ b/drivers/net/dsa/qca8k.h @@ -215,6 +215,8 @@ /* QCA specific MII registers */ #define MII_ATH_MMD_ADDR 0x0d #define MII_ATH_MMD_DATA 0x0e +#define MII_ATH_DBG_ADDR 0x1d +#define MII_ATH_DBG_DATA 0x1e enum { QCA8K_PORT_SPEED_10M = 0, From patchwork Fri Apr 23 01:47:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12219405 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70B4BC43461 for ; Fri, 23 Apr 2021 01:49:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4E64161176 for ; Fri, 23 Apr 2021 01:49:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240284AbhDWBti (ORCPT ); Thu, 22 Apr 2021 21:49:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240403AbhDWBtA (ORCPT ); Thu, 22 Apr 2021 21:49:00 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07B66C06138C; Thu, 22 Apr 2021 18:48:10 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id n2so71582816ejy.7; Thu, 22 Apr 2021 18:48:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=56PL0a5zXu4rcg3HLsKZZ+epvuKuacuxdJ5tVhsmylI=; b=BqZZKKo1hpCxnIbzNFdSp+JpbJurHmDiX2ajEiy5gHkbeTWqo3Au0CAvO/YtkZ+Olw Icw7O0rBzbPPOAEJUGsg2bQmhngSLEwDqLQ3kcBTKMGMmP0/OB3tu4ss35N+wXsubJFl NwNbKhb3dr/+GDSg497I35s3PYRIBi/D1FsXeZgTBfGbiobrrg6/NVs7kCCYmknVnrnX O0cp627DUc6S+PAj2uuQzgFWkc/p5cjTi6iT0wNRsMndA5o6F/Pd/sr5Kni5Jn9wsisP P3qLda360N8KO76Jaf8PtutaUKLsreVGqmdXgBj2I1nGNYUwIlEaIFwMmy95mWUaBxka 9Iog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=56PL0a5zXu4rcg3HLsKZZ+epvuKuacuxdJ5tVhsmylI=; b=f0MWA46c+is9g5PjacWYKl5M6Kr+5q+maca42LsrcOBvbLVYVGWos9sb8bSwYz9+W/ +BeqHm+bmz3f9Rmf9nAhlH0pY9CPZM4YrwSySzCK6rwyzKB9JXbZRjiK0RonIhMzmki5 gLse7dnPfiiEl/BU1+mTnvlb3F4rPa0e0p1tC5KbhwlO7CkGMA38Jybit1jMtEPWgxKh rO5WkEa5zVA7UW3dOU/d2cJFC39XA1QIq5uK09RC7c25UYcDdvHf+jrJQb6Ccn/t8jwg O4syyQxHUwN/n/zjoBpZ3VHlR0ggLSsvMHuNfKm/TvDjeKIXReT6JzxKvonVqGewsawS A/PQ== X-Gm-Message-State: AOAM5336UBLLggSh1uV+lFrGHy7ICTKYIIy09D2siktCM7KQEnwdoRuk QhFZpI/4H/Rq46viV4d1TxY= X-Google-Smtp-Source: ABdhPJzfZqD/Zxc+bJLESHf2GJLG7qiUI1wsupPLBD/+ZmEgQudFNmr6VMSwrpRKt4NkNX23CKd4Qw== X-Received: by 2002:a17:907:3f22:: with SMTP id hq34mr1525547ejc.535.1619142488732; Thu, 22 Apr 2021 18:48:08 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.48.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:48:08 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/14] drivers: net: dsa: qca8k: apply switch revision fix Date: Fri, 23 Apr 2021 03:47:37 +0200 Message-Id: <20210423014741.11858-12-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org qca8k require special debug value based on the switch revision. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 193c269d8ed3..12d2c97d1417 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -909,7 +909,7 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, { const struct qca8k_match_data *data; struct qca8k_priv *priv = ds->priv; - u32 reg, val; + u32 phy, reg, val; /* get the switches ID from the compatible */ data = of_device_get_match_data(priv->dev); @@ -928,7 +928,26 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, case 3: case 4: case 5: - /* Internal PHY, nothing to do */ + /* Internal PHY, apply revision fixup */ + phy = qca8k_port_to_phy(port) % PHY_MAX_ADDR; + switch (priv->switch_revision) { + case 1: + /* For 100M waveform */ + qca8k_phy_dbg_write(priv, phy, 0, 0x02ea); + /* Turn on Gigabit clock */ + qca8k_phy_dbg_write(priv, phy, 0x3d, 0x68a0); + break; + + case 2: + qca8k_phy_mmd_write(priv, phy, 0x7, 0x3c, 0x0); + fallthrough; + case 4: + qca8k_phy_mmd_write(priv, phy, 0x3, 0x800d, 0x803f); + qca8k_phy_dbg_write(priv, phy, 0x3d, 0x6860); + qca8k_phy_dbg_write(priv, phy, 0x5, 0x2c46); + qca8k_phy_dbg_write(priv, phy, 0x3c, 0x6000); + break; + } return; case 6: /* 2nd CPU port / external PHY */ if (state->interface != PHY_INTERFACE_MODE_RGMII && From patchwork Fri Apr 23 01:47:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12219401 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6DEAC433ED for ; Fri, 23 Apr 2021 01:48:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7EB4661458 for ; Fri, 23 Apr 2021 01:48:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240649AbhDWBtb (ORCPT ); Thu, 22 Apr 2021 21:49:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44716 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236126AbhDWBsy (ORCPT ); Thu, 22 Apr 2021 21:48:54 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1FE9C06174A; Thu, 22 Apr 2021 18:48:11 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id r12so71623086ejr.5; Thu, 22 Apr 2021 18:48:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0Nf/+Y+13GJ3s0+R51l6M7NWLkrdPSWKqvmk7zfK1es=; b=GevxPR1q+4lC30fPIiTwR5droZivdeq5304ubvydRjKv+AGkBLB4Paxl1G/JMrDy7U VIV/f1ARCZxFsIE36tIX3do7Vm4KTumfD3ATnkfxGkYxhbsmNh7Z4QrfKopti6eLVLNO kJs8sjpGTNkvm3L4vdUKBlIJ/IZ6gPc+ixGJe1K0LGG7I8ErBaMGWQDAwTp0iRZKWD43 XktvUkt2dt5EYrs6zOqN18XvWdL8E8UMAYrTd1OrFWvfvP+b7pnv2NIV+UQKKkVOPzwK XbHf25SOQwaNf0MRlqoECC0l36hTkALmTYg1oZoyqu9QdAHiPZhU5cS1mG7W9m/Hztov 4t4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0Nf/+Y+13GJ3s0+R51l6M7NWLkrdPSWKqvmk7zfK1es=; b=BAZ0CAuFNBSihsx2GI/zKPLb/EWiFjYv59i199lE90U1d/hzDSMQXSgjv+vdQhTPeH f84kTsjCknazu3GJ/snEBi9ABtZgSeZhJVbi/MO5b4QHFo5mmXdIBeRDq28JMb3TgrJK Gp/OgHO7X7kakNvxWgrG/feTr7TlbIwHUfc+iccOTG8ZRUX0Z4hB8EzkXltdJb6ObSGJ lgzHg3/RVW1cF/w0dkP1/hMoIwMLpE1QOKqqCyBN2DQXynCyupS9KKkygqkqLvWxRGTf IizG2+PmNj49zSz+qIRKBU81mZ+TkBTo2E5raTrVSP0IQmC5Bn1slWngwXXZ0IUjasgu F94g== X-Gm-Message-State: AOAM5323rGEotqURfXKisRZkI4Dz9191mq6kgBCO6K4C5gMfJaZ2vzQG z8nEPkmdHLbsqHkU64WueJo= X-Google-Smtp-Source: ABdhPJwIdyi0HpMxWThh4NHtG+R0F8nQpv0P1MvvoKE/G5pRR/UZpm4tT0l3Z2hwLn+kcEKpQIqSNg== X-Received: by 2002:a17:906:7d82:: with SMTP id v2mr1625907ejo.524.1619142490267; Thu, 22 Apr 2021 18:48:10 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.48.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:48:09 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/14] drivers: net: dsa: qca8k: clear MASTER_EN after phy read/write Date: Fri, 23 Apr 2021 03:47:38 +0200 Message-Id: <20210423014741.11858-13-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org Clear MDIO_MASTER_EN bit from MDIO_MASTER_CTRL after read/write operation. The MDIO_MASTER_EN bit is not reset after read/write operation and the next operation can be wrongly interpreted by the switch as a mdio operation. This cause a production of wrong/garbage data from the switch and underfined bheavior. (random port drop, unplugged port flagged with link up, wrong port speed) Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 12d2c97d1417..88a0234f1a7b 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -613,6 +613,7 @@ static int qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) { u32 phy, val; + int ret; if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) return -EINVAL; @@ -628,8 +629,13 @@ qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); - return qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_BUSY); + ret = qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_BUSY); + + qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_EN); + + return ret; } static int @@ -657,6 +663,9 @@ qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) val = (qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL) & QCA8K_MDIO_MASTER_DATA_MASK); + qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_EN); + return val; } From patchwork Fri Apr 23 01:47:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12219407 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 61BB0C43460 for ; Fri, 23 Apr 2021 01:49:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 358D46145A for ; Fri, 23 Apr 2021 01:49:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240735AbhDWBti (ORCPT ); Thu, 22 Apr 2021 21:49:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240408AbhDWBtA (ORCPT ); Thu, 22 Apr 2021 21:49:00 -0400 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3ABAAC06138E; Thu, 22 Apr 2021 18:48:13 -0700 (PDT) Received: by mail-ej1-x631.google.com with SMTP id r12so71623144ejr.5; Thu, 22 Apr 2021 18:48:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lAG/o0OGYJIRUzC/3iPfA0VGTvJTckfhIeXmdYy8D7s=; b=hP2RhnO2AfBseuJQQrTryszUEBwW99L+V55epRVWN5clVCRfFKOrwkqfJw7a79M/KC ZzEtKZXwaQRJwMDK4jCjP6QpbkBFhPIz3V+a5NX900DkCNMdOmCxF5gF6u/eLy25b+FY pJqdoBAPgrUskY89PmbCOQAAjA+P+kbuIdZSW2MGKSL5Xmg/ZN5xS1mDmHPfE2WZRc3t dAIjRtwZYsRTXy3zvgJ5mzZnGZdOFa/bdmcpYhKcPu/NtXLyteKv8CX4Bn28JnbMXydd tk60VxFeDNY0hARjNRYB7K+7dtkWGqIMYkR97N/ZXegaJrLYv8PlvdTCNNtHBukp7KvT Pg7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lAG/o0OGYJIRUzC/3iPfA0VGTvJTckfhIeXmdYy8D7s=; b=PQEJn7ZDwIataTHUIplXWor8KtmMO43nASq5s+CWhO8nPVsc7Yrv+5oJ/9LHVB7Tch x+B/pOtzwxlcA8LxxLSvheaMgTqq8ToqyPLv81xwsbtxjtFSJlH/KDwPyY85kfhRug2r YccZbmNwgU3YbaOgXZq8u3clx74zdCh83qgWtIMsGAJlyhu1FCWUh69ByV6lbyoHoxUz TJs1ww2iyJBkQDgwY29q+bcwISddIHTYDV9e5sewkoiloiQGPrlu/j4ZaRPlJl9pUvKq F4othPAf2yJSvWRjMWUBNlM6cDtdGyHZmR6UeC6jP1hY2DhccY5dtkMZF0WDIXWo+ptG z0xQ== X-Gm-Message-State: AOAM5309qxBu177P1Y8BcHE2D8Q6FWikNbMDV6EK5axoShvO9vNuUmqp obkqGgve2ifwK/a53vbsNgKktWH4DkRe6Q== X-Google-Smtp-Source: ABdhPJyxJI5kZhM/we67BpwL9wm0tcCVEwsQ9EccqVB6j6qo/2+n6eBWSBmwdgKWrgRQEXbv83xjHw== X-Received: by 2002:a17:906:c44f:: with SMTP id ck15mr1564008ejb.269.1619142491920; Thu, 22 Apr 2021 18:48:11 -0700 (PDT) Received: from Ansuel-xps.localdomain (93-35-189-2.ip56.fastwebnet.it. [93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.48.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:48:11 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 13/14] drivers: net: dsa: qca8k: protect MASTER busy_wait with mdio mutex Date: Fri, 23 Apr 2021 03:47:39 +0200 Message-Id: <20210423014741.11858-14-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org MDIO_MASTER operation have a dedicated busy wait that is not protected by the mdio mutex. This can cause situation where the MASTER operation is done and a normal operation is executed between the MASTER read/write and the MASTER busy_wait. Rework the qca8k_mdio_read/write function to address this issue by binding the lock for the whole MASTER operation and not only the mdio read/write common operation. Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 59 ++++++++++++++++++++++++++++++++++------- 1 file changed, 50 insertions(+), 9 deletions(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index 88a0234f1a7b..d2f5e0b1c721 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -609,9 +609,33 @@ qca8k_port_to_phy(int port) return port - 1; } +static int +qca8k_mdio_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) +{ + unsigned long timeout; + u16 r1, r2, page; + + qca8k_split_addr(reg, &r1, &r2, &page); + + timeout = jiffies + msecs_to_jiffies(20); + + /* loop until the busy flag has cleared */ + do { + u32 val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1); + int busy = val & mask; + + if (!busy) + break; + cond_resched(); + } while (!time_after_eq(jiffies, timeout)); + + return time_after_eq(jiffies, timeout); +} + static int qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) { + u16 r1, r2, page; u32 phy, val; int ret; @@ -627,10 +651,17 @@ qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) QCA8K_MDIO_MASTER_REG_ADDR(regnum) | QCA8K_MDIO_MASTER_DATA(data); - qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); + qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page); + + mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); + + qca8k_set_page(priv->bus, page); + qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val); - ret = qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_BUSY); + ret = qca8k_mdio_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_BUSY); + + mutex_unlock(&priv->bus->mdio_lock); qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, QCA8K_MDIO_MASTER_EN); @@ -641,6 +672,7 @@ qca8k_mdio_write(struct qca8k_priv *priv, int port, u32 regnum, u16 data) static int qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) { + u16 r1, r2, page; u32 phy, val; if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) @@ -654,14 +686,23 @@ qca8k_mdio_read(struct qca8k_priv *priv, int port, u32 regnum) QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | QCA8K_MDIO_MASTER_REG_ADDR(regnum); - qca8k_write(priv, QCA8K_MDIO_MASTER_CTRL, val); + qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page); - if (qca8k_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, - QCA8K_MDIO_MASTER_BUSY)) - return -ETIMEDOUT; + mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); + + qca8k_set_page(priv->bus, page); + qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val); + + if (qca8k_mdio_busy_wait(priv, QCA8K_MDIO_MASTER_CTRL, + QCA8K_MDIO_MASTER_BUSY)) + val = -ETIMEDOUT; + else + val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1); + + mutex_unlock(&priv->bus->mdio_lock); - val = (qca8k_read(priv, QCA8K_MDIO_MASTER_CTRL) & - QCA8K_MDIO_MASTER_DATA_MASK); + if (val >= 0) + val &= QCA8K_MDIO_MASTER_DATA_MASK; qca8k_reg_clear(priv, QCA8K_MDIO_MASTER_CTRL, QCA8K_MDIO_MASTER_EN); From patchwork Fri Apr 23 01:47:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 12219403 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB8B5C433B4 for ; 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[93.35.189.2]) by smtp.googlemail.com with ESMTPSA id t4sm3408635edd.6.2021.04.22.18.48.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Apr 2021 18:48:13 -0700 (PDT) From: Ansuel Smith To: Florian Fainelli Cc: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Heiner Kallweit , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 14/14] drivers: net: dsa: qca8k: enlarge mdio delay and timeout Date: Fri, 23 Apr 2021 03:47:40 +0200 Message-Id: <20210423014741.11858-15-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210423014741.11858-1-ansuelsmth@gmail.com> References: <20210423014741.11858-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org - Enlarge set page delay to QDSK source - Enlarge mdio MASTER timeout busy wait Signed-off-by: Ansuel Smith --- drivers/net/dsa/qca8k.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c index d2f5e0b1c721..2ed1d5e283c2 100644 --- a/drivers/net/dsa/qca8k.c +++ b/drivers/net/dsa/qca8k.c @@ -191,6 +191,7 @@ qca8k_set_page(struct mii_bus *bus, u16 page) } qca8k_current_page = page; + usleep_range(1000, 2000); } static u32 @@ -617,7 +618,7 @@ qca8k_mdio_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) qca8k_split_addr(reg, &r1, &r2, &page); - timeout = jiffies + msecs_to_jiffies(20); + timeout = jiffies + msecs_to_jiffies(2000); /* loop until the busy flag has cleared */ do {