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Fri, 30 Apr 2021 12:38:54 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 01/37] KVM: SVM: Add support to handle AP reset MSR protocol Date: Fri, 30 Apr 2021 07:37:46 -0500 Message-Id: <20210430123822.13825-2-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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Signed-off-by: Tom Lendacky Signed-off-by: Brijesh Singh --- arch/x86/kvm/svm/sev.c | 56 ++++++++++++++++++++++++++++++++++++------ arch/x86/kvm/svm/svm.h | 1 + 2 files changed, 49 insertions(+), 8 deletions(-) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index a9d8d6aafdb8..7bf4c2354a5a 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -57,6 +57,10 @@ module_param_named(sev_es, sev_es_enabled, bool, 0444); #define sev_es_enabled false #endif /* CONFIG_KVM_AMD_SEV */ +#define AP_RESET_HOLD_NONE 0 +#define AP_RESET_HOLD_NAE_EVENT 1 +#define AP_RESET_HOLD_MSR_PROTO 2 + static u8 sev_enc_bit; static DECLARE_RWSEM(sev_deactivate_lock); static DEFINE_MUTEX(sev_bitmap_lock); @@ -2200,6 +2204,9 @@ static int sev_es_validate_vmgexit(struct vcpu_svm *svm) static void pre_sev_es_run(struct vcpu_svm *svm) { + /* Clear any indication that the vCPU is in a type of AP Reset Hold */ + svm->ap_reset_hold_type = AP_RESET_HOLD_NONE; + if (!svm->ghcb) return; @@ -2408,6 +2415,22 @@ static int sev_handle_vmgexit_msr_protocol(struct vcpu_svm *svm) GHCB_MSR_INFO_POS); break; } + case GHCB_MSR_AP_RESET_HOLD_REQ: + svm->ap_reset_hold_type = AP_RESET_HOLD_MSR_PROTO; + ret = kvm_emulate_ap_reset_hold(&svm->vcpu); + + /* + * Preset the result to a non-SIPI return and then only set + * the result to non-zero when delivering a SIPI. + */ + set_ghcb_msr_bits(svm, 0, + GHCB_MSR_AP_RESET_HOLD_RESULT_MASK, + GHCB_MSR_AP_RESET_HOLD_RESULT_POS); + + set_ghcb_msr_bits(svm, GHCB_MSR_AP_RESET_HOLD_RESP, + GHCB_MSR_INFO_MASK, + GHCB_MSR_INFO_POS); + break; case GHCB_MSR_TERM_REQ: { u64 reason_set, reason_code; @@ -2495,6 +2518,7 @@ int sev_handle_vmgexit(struct kvm_vcpu *vcpu) ret = svm_invoke_exit_handler(vcpu, SVM_EXIT_IRET); break; case SVM_VMGEXIT_AP_HLT_LOOP: + svm->ap_reset_hold_type = AP_RESET_HOLD_NAE_EVENT; ret = kvm_emulate_ap_reset_hold(vcpu); break; case SVM_VMGEXIT_AP_JUMP_TABLE: { @@ -2632,13 +2656,29 @@ void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) return; } - /* - * Subsequent SIPI: Return from an AP Reset Hold VMGEXIT, where - * the guest will set the CS and RIP. Set SW_EXIT_INFO_2 to a - * non-zero value. - */ - if (!svm->ghcb) - return; + /* Subsequent SIPI */ + switch (svm->ap_reset_hold_type) { + case AP_RESET_HOLD_NAE_EVENT: + /* + * Return from an AP Reset Hold VMGEXIT, where the guest will + * set the CS and RIP. Set SW_EXIT_INFO_2 to a non-zero value. + */ + ghcb_set_sw_exit_info_2(svm->ghcb, 1); + break; + case AP_RESET_HOLD_MSR_PROTO: + /* + * Return from an AP Reset Hold VMGEXIT, where the guest will + * set the CS and RIP. Set GHCB data field to a non-zero value. + */ + set_ghcb_msr_bits(svm, 1, + GHCB_MSR_AP_RESET_HOLD_RESULT_MASK, + GHCB_MSR_AP_RESET_HOLD_RESULT_POS); - ghcb_set_sw_exit_info_2(svm->ghcb, 1); + set_ghcb_msr_bits(svm, GHCB_MSR_AP_RESET_HOLD_RESP, + GHCB_MSR_INFO_MASK, + GHCB_MSR_INFO_POS); + break; + default: + break; + } } diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 42f8a7b9048f..dad528d9f08f 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -174,6 +174,7 @@ struct vcpu_svm { struct ghcb *ghcb; struct kvm_host_map ghcb_map; bool received_first_sipi; + unsigned int ap_reset_hold_type; /* SEV-ES scratch area support */ void *ghcb_sa; From patchwork Fri Apr 30 12:37:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233285 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A420C433B4 for ; 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Now that KVM supports the basic SEV-SNP, advertisement the support through the hypervisor feature request MSR protocol and NAE VMGEXITs. Signed-off-by: Brijesh Singh --- arch/x86/kvm/svm/sev.c | 14 ++++++++++++++ arch/x86/kvm/svm/svm.h | 1 + 2 files changed, 15 insertions(+) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 7bf4c2354a5a..5f0034e0dacc 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -2174,6 +2174,7 @@ static int sev_es_validate_vmgexit(struct vcpu_svm *svm) case SVM_VMGEXIT_AP_HLT_LOOP: case SVM_VMGEXIT_AP_JUMP_TABLE: case SVM_VMGEXIT_UNSUPPORTED_EVENT: + case SVM_VMGEXIT_HYPERVISOR_FEATURES: break; default: goto vmgexit_err; @@ -2431,6 +2432,13 @@ static int sev_handle_vmgexit_msr_protocol(struct vcpu_svm *svm) GHCB_MSR_INFO_MASK, GHCB_MSR_INFO_POS); break; + case GHCB_MSR_HV_FEATURES_REQ: { + set_ghcb_msr_bits(svm, GHCB_HV_FEATURES_SUPPORTED, + GHCB_MSR_HV_FEATURES_MASK, GHCB_MSR_HV_FEATURES_POS); + set_ghcb_msr_bits(svm, GHCB_MSR_HV_FEATURES_RESP, + GHCB_MSR_INFO_MASK, GHCB_MSR_INFO_POS); + break; + } case GHCB_MSR_TERM_REQ: { u64 reason_set, reason_code; @@ -2546,6 +2554,12 @@ int sev_handle_vmgexit(struct kvm_vcpu *vcpu) ret = 1; break; } + case SVM_VMGEXIT_HYPERVISOR_FEATURES: { + ghcb_set_sw_exit_info_2(ghcb, GHCB_HV_FEATURES_SUPPORTED); + + ret = 1; + break; + } case SVM_VMGEXIT_UNSUPPORTED_EVENT: vcpu_unimpl(vcpu, "vmgexit: unsupported event - exit_info_1=%#llx, exit_info_2=%#llx\n", diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index dad528d9f08f..2b0083753812 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -530,6 +530,7 @@ void svm_vcpu_unblocking(struct kvm_vcpu *vcpu); #define GHCB_VERSION_MAX 1ULL #define GHCB_VERSION_MIN 1ULL +#define GHCB_HV_FEATURES_SUPPORTED 0 extern unsigned int max_sev_asid; From patchwork Fri Apr 30 12:37:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233287 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D258C433ED for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SA0PR12MB4511.namprd12.prod.outlook.com (2603:10b6:806:95::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.26; Fri, 30 Apr 2021 12:38:56 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:38:56 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 03/37] KVM: SVM: Increase the GHCB protocol version Date: Fri, 30 Apr 2021 07:37:48 -0500 Message-Id: <20210430123822.13825-4-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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Signed-off-by: Brijesh Singh --- arch/x86/kvm/svm/svm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 2b0083753812..053f2505a738 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -527,7 +527,7 @@ void svm_vcpu_unblocking(struct kvm_vcpu *vcpu); /* sev.c */ -#define GHCB_VERSION_MAX 1ULL +#define GHCB_VERSION_MAX 2ULL #define GHCB_VERSION_MIN 1ULL #define GHCB_HV_FEATURES_SUPPORTED 0 From patchwork Fri Apr 30 12:37:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5837C43460 for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SA0PR12MB4511.namprd12.prod.outlook.com (2603:10b6:806:95::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.26; Fri, 30 Apr 2021 12:38:56 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:38:56 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 04/37] x86/cpufeatures: Add SEV-SNP CPU feature Date: Fri, 30 Apr 2021 07:37:49 -0500 Message-Id: <20210430123822.13825-5-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: PKxAmJ6gz0Whznqn3TdTkA5UMq2Skjn6pwphOjiG/TDQjrLb0gQdE3ffNAm5lOVz7lr9SBIsFe38R+6WNlz2CmBTSwIDnT2BHb+FtbvOxn9uYqDhpuAqqZ9Z03lawq+9Mjhm3dJbYR3f6BF4m1Ws8hzrvBGxnyd2QyZwUrcTbMbHZvQbCfN9VcHd2zhG6T55QD4MhbT2l8W35sSVxQ3r96tCX3cjmFk3a8K4Pz1wqeKL7tAEtNmECnGSnBCPJZCwYBCFmU/BDRa+Pm2OkReF5p8GvwwpWC4BPByXdLaq9/OUBP77vp6MaOpn4NtthSRaFWF1xge6Db6VvhQ61YYJ2msPVhdFudSmFycDy7XO3cc74ukyh3AWFX7gl4+QQ1aaF2LSyrwc1lfQLYViaHhUQ6u4cW8szX4ga+Q9KTwyZ44/UHqqz4mJebsqmXCVilSh6Wp4MVbuF4Jwg2eGY4vMGwPDnR0bFPBKDwdzqU0dD8uZuum81v8fy6PwNEr8F5qobCD4s4azhgJo4XbT4TlOI5cNVlMKSD+foqz6JsAw8890P0PRGNk0o/6amWzwGjLb1LY+ZxaI+3grK8tOy5CLeFgy9ppxNf+cFO4UAaqGARg0tmyKoWXQiKlIySkWODCo/l9SKzOn3smAFrbr/Bd6X1J9lIu8xMUUlOLRFPSFOTA8qeZ2EJXrhKj4jsbAR2pPg5SGvcpBE8qqLyQ54sk8NLpdX8Jc2AlotUSrGT1gNJOdWMCYnJo9sMBVXHTY33x78OvAyxYr+lxDFUextUBgTTF7Op7/uuE8Ierrv6l/J10SfPCpnr3dpUJP8jkkhoy8ASG25m43LEsPpIG7rymtp1gSiY3qj6VeiW66KMiG7u2B1tdpyg66T76f8ON9/e7xFnvCe6GFiG2rBHFizue6CoFd06HdSPgnsEetx2mati2uD34RzVFr78cj5WPzaXlEuHvzlvaOnNBLVwRkL3uLK8XS5NYf4WC1VbY1x63/eB0V1/mJaJW9FGHtMkmP2KnR61NiCPP3ls3M78imzs+51z8VSTlliaQ3qt/SXRP6Ns4lzA6UpXNah75mflrayps71mVg44SYMTZQXHmqTJA8qd0n1mpncevNqCRSNXV5fi0kX3+WU1X6q/ZDlcq6dXEMdzICunE8iWpNw/HC6UA+wkdIRmSBQNb1UT/Bda9STOjIJrsCbc6s4+ALembUYRAEVatS8vBNC+X5+r6Or6466wgNnv5u9WDXX2mPhmMQu38ufjFWofIF3cobRbpbeJk1wem8birLZEeJ94wsQH6SyjxD5EixI5IvlxV7Co/lgHsa9PXuMM7X8xAZkYLHH1p1 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: ce252337-fa67-44bd-22dc-08d90bd4ebb3 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:38:56.6382 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Ewd4c4rTXPpDPxXMzzwcQPe7S6Cfsoa06IH7MwSLineMS146223xZWXipPDdiXNhd3IdrbLvoQM1POKqu1f3LQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4511 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add CPU feature detection for Secure Encrypted Virtualization with Secure Nested Paging. This feature adds a strong memory integrity protection to help prevent malicious hypervisor-based attacks like data replay, memory re-mapping, and more. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/amd.c | 3 ++- tools/arch/x86/include/asm/cpufeatures.h | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index dddc746b5455..88b21de977d8 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -393,6 +393,7 @@ #define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */ #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */ #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */ +#define X86_FEATURE_SEV_SNP (19*32+ 4) /* AMD Secure Encrypted Virtualization - Secure Nested Paging */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ /* diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index daf6c6e74ff9..15b389ebb019 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -586,7 +586,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) * If BIOS has not enabled SME then don't advertise the * SME feature (set in scattered.c). * For SEV: If BIOS has not enabled SEV then don't advertise the - * SEV and SEV_ES feature (set in scattered.c). + * SEV, SEV_ES and SEV_SNP feature. * * In all cases, since support for SME and SEV requires long mode, * don't advertise the feature under CONFIG_X86_32. @@ -618,6 +618,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) clear_sev: setup_clear_cpu_cap(X86_FEATURE_SEV); setup_clear_cpu_cap(X86_FEATURE_SEV_ES); + setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); } } diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h index cc96e26d69f7..2e78ab5b92ab 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -390,6 +390,7 @@ #define X86_FEATURE_SEV (19*32+ 1) /* AMD Secure Encrypted Virtualization */ #define X86_FEATURE_VM_PAGE_FLUSH (19*32+ 2) /* "" VM Page Flush MSR is supported */ #define X86_FEATURE_SEV_ES (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */ +#define X86_FEATURE_SEV_SNP (19*32+ 4) /* AMD Secure Encrypted Virtualization - Secure Nested Paging */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ /* From patchwork Fri Apr 30 12:37:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94210C433ED for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SA0PR12MB4511.namprd12.prod.outlook.com (2603:10b6:806:95::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.26; Fri, 30 Apr 2021 12:38:57 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:38:57 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 05/37] x86/sev: Add the host SEV-SNP initialization support Date: Fri, 30 Apr 2021 07:37:50 -0500 Message-Id: <20210430123822.13825-6-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: TC86PS4OCR7Ar9W8T/3a0ovhyWALsavxKBlLq0i3Hn1FF8BZtqxInEQR+H1o9T7Gv6Hto761dXdetH0Wc9JUQzgVKihE7IRcn+dVc0MNuu/l2FjMkys3PtI2VETplLIDzIXgPlYXN9AIiihGAqdlTImmsVAl5TMWHdFOTwX2w+GF6VebUAh4FDDiO23o8S3j/3cEv0vSZN0GISjeHjZVAYYls9JQdaJOxGUNszhm/wLs9l2nw6bVDim6JPSgFmXdyipnUD3meo/6edcszFTDWocEst7hU5hiveoHFEFanR0a+l6gsJvgvpL82lOpYpbnoLuiApXSbhrpAlkDznUS7E6U/o6I0qJgIIz4o5oxEnAnxFlLzn3D4ieJBh5WbQ3dhCdTWhVuxZMjm79C1J13WVYRt+25Tr0nS+4UhBRqRroyOvzcHirRwd9YMjZoc0JRu19VIYyzRev3HPvZC2AAQS+2xo0V5lzH3mfMbMjXfDurCnoyZV+dgBaDiliTVdsZANxBYbJ+I6RxhIrC/LBhJPp7BcJtWrdZ8by4TbKsDefC9TUq7EAU+FC73k1KrkrSSEIZH5aDsGeOe/PNhLjW8uNzv93P8lb5BuY+stWiyMQc7inuuuUuOgdv6RDuMJzNS0QbXTFII5VZgfJqVL1zUo34OjU8HWWWedDkwDreJ1vpc0F8e00pA9SL32f8OpQMpEktZqu7oOb1v6Dgh8k/EThERNuwblXnkF2apJg8zFhLQLQqyPYl6LUTmqve0fQ5/glIFFBTZrtKx3JIO7q4qa/6WAkK/EtrOdo+dF5IhKGuCgLnVu00tLjuLVF5G78voshrjT4WYFVXyZHUgsnU+AqqzzlhvgYQWdxFEncgIDgWyoS+b1pqqCJxsy9LBoRvnwlBn4H36Q6laWhY6CfVniumDMferI4oRBe7cx3O/mlsj8VLk6nmaKCw3qOWFyleofs+EIAcHTM11TJvSAZAQOx25YQu75ICt8eubgTAU4DSTSymBqHLry3xCR9feZsW7BR3MYT6ICERDviRK8Papqma9H4uOVvYwhXPXFXCpO39F6m/9niKAct0P3MUCrqay4KVPveEq0elNHwNQR2Ol9Gc/oJsrM13VbLwTeyr3lNYD+tf7FL9OeVJ2UVC1UQYrQmccGaed1+Muw5n90xpOVy9FA6798DgRZE96N1DDF3DTmEB49ORxz5YYHS/ak4UAPBW3HKKPTurB6XLS9iIwmM8L+M91Y5ocyEbtX5ztzqITwAZEDsCG4p0joD/EbCfTBYBfRosq7M6C+hcgKRBeMVkuV+2ZpHXeg8P14o57a1G2BtI0hLAySKwYbBPBuOZ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 192290c4-095f-480d-39ea-08d90bd4ec1a X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:38:57.3568 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: IM2+hk1pSJv06lLcFYByutPeVufg+1+/vccdyRsaGkGiQn0P1Ll11S0f4g8Br1HSI5Uzk1GaeJSA/E4rvnRO2w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4511 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The memory integrity guarantees of SEV-SNP are enforced through a new structure called the Reverse Map Table (RMP). The RMP is a single data structure shared across the system that contains one entry for every 4K page of DRAM that may be used by SEV-SNP VMs. The goal of RMP is to track the owner of each page of memory. Pages of memory can be owned by the hypervisor, owned by a specific VM or owned by the AMD-SP. See APM2 section 15.36.3 for more detail on RMP. The RMP table is used to enforce access control to memory. The table itself is not directly writable by the software. New CPU instructions (RMPUPDATE, PVALIDATE, RMPADJUST) are used to manipulate the RMP entries. Based on the platform configuration, the BIOS reserves the memory used for the RMP table. The start and end address of the RMP table must be queried by reading the RMP_BASE and RMP_END MSRs. If the RMP_BASE and RMP_END are not set then disable the SEV-SNP feature. The SEV-SNP feature is enabled only after the RMP table is successfully initialized. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/disabled-features.h | 8 ++- arch/x86/include/asm/msr-index.h | 6 ++ arch/x86/kernel/sev.c | 91 ++++++++++++++++++++++++ 3 files changed, 104 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index b7dd944dc867..0d5c8d08185c 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -68,6 +68,12 @@ # define DISABLE_SGX (1 << (X86_FEATURE_SGX & 31)) #endif +#ifdef CONFIG_AMD_MEM_ENCRYPT +# define DISABLE_SEV_SNP 0 +#else +# define DISABLE_SEV_SNP (1 << (X86_FEATURE_SEV_SNP & 31)) +#endif + /* * Make sure to add features to the correct mask */ @@ -91,7 +97,7 @@ DISABLE_ENQCMD) #define DISABLED_MASK17 0 #define DISABLED_MASK18 0 -#define DISABLED_MASK19 0 +#define DISABLED_MASK19 (DISABLE_SEV_SNP) #define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20) #endif /* _ASM_X86_DISABLED_FEATURES_H */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 79f7a926476a..862cd2e777d9 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -481,6 +481,8 @@ #define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) #define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT) #define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT) +#define MSR_AMD64_RMP_BASE 0xc0010132 +#define MSR_AMD64_RMP_END 0xc0010133 #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f @@ -538,6 +540,10 @@ #define MSR_AMD64_SYSCFG 0xc0010010 #define MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT 23 #define MSR_AMD64_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT) +#define MSR_AMD64_SYSCFG_SNP_EN_BIT 24 +#define MSR_AMD64_SYSCFG_SNP_EN BIT_ULL(MSR_AMD64_SYSCFG_SNP_EN_BIT) +#define MSR_AMD64_SYSCFG_SNP_VMPL_EN_BIT 25 +#define MSR_AMD64_SYSCFG_SNP_VMPL_EN BIT_ULL(MSR_AMD64_SYSCFG_SNP_VMPL_EN_BIT) #define MSR_K8_INT_PENDING_MSG 0xc0010055 /* C1E active bits in int pending message */ #define K8_INTP_C1E_ACTIVE_MASK 0x18000000 diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index e54a497877e1..126fa441c0f8 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -48,6 +49,9 @@ static struct ghcb boot_ghcb_page __bss_decrypted __aligned(PAGE_SIZE); */ static struct ghcb __initdata *boot_ghcb; +static unsigned long rmptable_start __ro_after_init; +static unsigned long rmptable_end __ro_after_init; + /* #VC handler runtime per-CPU data */ struct sev_es_runtime_data { struct ghcb ghcb_page; @@ -1782,3 +1786,90 @@ unsigned long snp_issue_guest_request(int type, struct snp_guest_request_data *i return ret; } EXPORT_SYMBOL_GPL(snp_issue_guest_request); + +#undef pr_fmt +#define pr_fmt(fmt) "SEV-SNP: " fmt + +static void __snp_enable(void) +{ + u64 val; + + rdmsrl(MSR_AMD64_SYSCFG, val); + + val |= MSR_AMD64_SYSCFG_SNP_EN; + val |= MSR_AMD64_SYSCFG_SNP_VMPL_EN; + + wrmsrl(MSR_AMD64_SYSCFG, val); +} + +static int snp_enable(unsigned int cpu) +{ + if (cpu_feature_enabled(X86_FEATURE_SEV_SNP)) + __snp_enable(); + + return 0; +} + +static __init int __snp_rmptable_init(void) +{ + u64 rmp_base, rmp_end; + unsigned long sz; + void *start; + u64 val; + + rdmsrl(MSR_AMD64_RMP_BASE, rmp_base); + rdmsrl(MSR_AMD64_RMP_END, rmp_end); + + if (!rmp_base || !rmp_end) { + pr_info("Memory for the RMP table has not been reserved by BIOS\n"); + return 1; + } + + sz = rmp_end - rmp_base + 1; + + start = memremap(rmp_base, sz, MEMREMAP_WB); + if (!start) { + pr_err("Failed to map RMP table 0x%llx-0x%llx\n", rmp_base, rmp_end); + return 1; + } + + /* + * Check if SEV-SNP is already enabled, this can happen if we are coming from + * kexec boot. + */ + rdmsrl(MSR_AMD64_SYSCFG, val); + if (val & MSR_AMD64_SYSCFG_SNP_EN) + goto skip_enable; + + /* Initialize the RMP table to zero */ + memset(start, 0, sz); + + /* Flush the caches to ensure that data is written before SNP is enabled. */ + wbinvd_on_all_cpus(); + + __snp_enable(); + +skip_enable: + rmptable_start = (unsigned long)start; + rmptable_end = rmptable_start + sz; + + pr_info("RMP table physical address 0x%016llx - 0x%016llx\n", rmp_base, rmp_end); + + return 0; +} + +static int __init snp_rmptable_init(void) +{ + if (!boot_cpu_has(X86_FEATURE_SEV_SNP)) + return 0; + + if (__snp_rmptable_init()) { + setup_clear_cpu_cap(X86_FEATURE_SEV_SNP); + return 1; + } + + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/rmptable_init:online", snp_enable, NULL); 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Fri, 30 Apr 2021 12:38:58 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 06/37] x86/sev: Add RMP entry lookup helpers Date: Fri, 30 Apr 2021 07:37:51 -0500 Message-Id: <20210430123822.13825-7-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: DmbDIJDrPmIKxQYt5VwsqyEU5wg0nRizDxnL3y7UMqa1vEta5kMnlWBxYjkLEmaKJnx+Zb2LatRnygh6L3e1jwDmok5EMnPwVLmn2A0zqol/9j9NKMsLPIHmuPCeqGCEMLpwLA+6ocWhLX4LQezmG7KuEM/TMqndDbQUenbKjXRcDCrBvjFJbx89dtC42aRQ53v7yP2DgBD8sz0qVPJHwdPVQ8m9OCaf5Z69t3cP/hGpvsUyJSMAXmhYp9eybKJsORhXmgZJglW4DOlaQLFmelEM2cWPzB283QVm6iDFNMDhj9hzubRT8NQoEYy+lRYoHkThTNC0kDqZ5a287Mi2zi2TWD4d74h9OY3EYe5BnxmYebB4gFMe+9rwCGiVRuWtBceuiWSJmh6Md4OqACkyzEr5h6nR71x3QofBOnv8rRn/0vWI3LLuZ7dc7kJN+WBhBiED2teYjZUzsPBNeb8UbuV9GmIvQQnv5dcQtwpPNxgYOkmV/In6OC2XYO1atY9U3E98T76E3D5oQRUv/M4xm8303vqeZexLTuyyR+j+cA+yxUOgATxXn5uKGBdOugZE4e7oro7yywQXUBYXgPgI8ndUZp2dpnB1v3Cg9LkRYfiyw1uzQvnK0sSHYwvzrVR9V1sCDTBhSIDIGyZkmMdQUQIgFGE1kzVzKY+JY46ox6g7zjZYirrXDWuKOsgLmDdn4Dzrjm14AO0t6XKBJmcWpYoDgLWrb1gaBFsjiLwzV1Ttyo1b8iwgde1nMBa4BJ7N4LGwGKd/tGREjS9awfnmQQWeJf4cBq5Ya4gfHhsQAO4DfNXxDk817VVjYF1M3lt9sHOxYjc/hspBlwSAJmhFKM3yEvdly4QfzNu3PmCmmBG/7AfeqIzkBHst5VfkukJ2NsYANhXdtPvbHyDG4ACeBKi9awFKOcOiF+h001Cw1OrU2eKoiB40mHsbsrl+F2MJFoSBVYvnkfs+rjIPd9i72DKZYeuZKmThl2/DOKonB0otGf8h28cqwVw8MnvZAV+XYPMHsbO7zKZrw0B0kn5tLQyWMy6/4qbBnz80e5+EIDCTcNesF7LanjOBLNvNDQavZd56CRlPlkfMZBTl6/noLYdjEGDpT6UZd2tALUC/LpVsEa9mIkoIsV7TdVfzIW6aj4+docvjd8l/4iYVjw7KrsWOCgomPl7JtN5wduexlrAU0eUzFCpDkQCHR8DlsxJmh7j8TU3s4I1CTlxaoMUExQWtKtFef5g7/VFhwxkjWy0CJ39nv7Ww/50G16YM5CffK+BQ1UZDiNfMcIDpPcFdf6LLixjUcyNisGXKuDlMGf8RO7/5DYd/YSUWBYF3Iz+A X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: bcd307f5-92da-4cce-3a9c-08d90bd4ec8b X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:38:58.0854 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 3hSNtlePMb3EHlJwEW4QziuByoD36ZAqgGiuODz0/jGZdaGmZ4unFPWIob2aG6C/Xmq5ZFFJ6EOG1QhgRuRgWg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4511 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The snp_lookup_page_in_rmptable() can be used by the host to read the RMP entry for a given page. The RMP entry format is documented in AMD PPR, see https://bugzilla.kernel.org/attachment.cgi?id=296015. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/sev.h | 5 +--- arch/x86/kernel/sev.c | 28 ++++++++++++++++++++ include/linux/sev.h | 54 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 83 insertions(+), 4 deletions(-) create mode 100644 include/linux/sev.h diff --git a/arch/x86/include/asm/sev.h b/arch/x86/include/asm/sev.h index 7f4c34dd84e1..a65e78fa3d51 100644 --- a/arch/x86/include/asm/sev.h +++ b/arch/x86/include/asm/sev.h @@ -9,6 +9,7 @@ #define __ASM_ENCRYPTED_STATE_H #include +#include #include #include @@ -65,10 +66,6 @@ extern bool handle_vc_boot_ghcb(struct pt_regs *regs); #define PVALIDATE_FAIL_SIZEMISMATCH 6 #define PVALIDATE_FAIL_NOUPDATE 255 /* Software defined (when rFlags.CF = 1) */ -/* RMP page size */ -#define RMP_PG_SIZE_2M 1 -#define RMP_PG_SIZE_4K 0 - #ifdef CONFIG_AMD_MEM_ENCRYPT extern struct static_key_false sev_es_enable_key; extern void __sev_es_ist_enter(struct pt_regs *regs); diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index 126fa441c0f8..dec4f423e232 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -40,6 +40,10 @@ #define DR7_RESET_VALUE 0x400 +#define RMPTABLE_ENTRIES_OFFSET 0x4000 +#define RMPENTRY_SHIFT 8 +#define rmptable_page_offset(x) (RMPTABLE_ENTRIES_OFFSET + (((unsigned long)x) >> RMPENTRY_SHIFT)) + /* For early boot hypervisor communication in SEV-ES enabled guests */ static struct ghcb boot_ghcb_page __bss_decrypted __aligned(PAGE_SIZE); @@ -1873,3 +1877,27 @@ static int __init snp_rmptable_init(void) return 0; } early_initcall(snp_rmptable_init); + +struct rmpentry *snp_lookup_page_in_rmptable(struct page *page, int *level) +{ + unsigned long phys = page_to_pfn(page) << PAGE_SHIFT; + struct rmpentry *entry, *large_entry; + unsigned long vaddr; + + if (!cpu_feature_enabled(X86_FEATURE_SEV_SNP)) + return NULL; + + vaddr = rmptable_start + rmptable_page_offset(phys); + if (unlikely(vaddr > rmptable_end)) + return NULL; + + entry = (struct rmpentry *)vaddr; + + /* Read a large RMP entry to get the correct page level used in RMP entry. */ + vaddr = rmptable_start + rmptable_page_offset(phys & PMD_MASK); + large_entry = (struct rmpentry *)vaddr; + *level = RMP_TO_X86_PG_LEVEL(rmpentry_pagesize(large_entry)); + + return entry; +} +EXPORT_SYMBOL_GPL(snp_lookup_page_in_rmptable); diff --git a/include/linux/sev.h b/include/linux/sev.h new file mode 100644 index 000000000000..ee038d466786 --- /dev/null +++ b/include/linux/sev.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * AMD Secure Encrypted Virtualization + * + * Author: Brijesh Singh + */ + +#ifndef __LINUX_SEV_H +#define __LINUX_SEV_H + +struct __packed rmpentry { + union { + struct { + u64 assigned:1; + u64 pagesize:1; + u64 immutable:1; + u64 rsvd1:9; + u64 gpa:39; + u64 asid:10; + u64 vmsa:1; + u64 validated:1; + u64 rsvd2:1; + } info; + u64 low; + }; + u64 high; +}; + +#define rmpentry_assigned(x) ((x)->info.assigned) +#define rmpentry_pagesize(x) ((x)->info.pagesize) +#define rmpentry_vmsa(x) ((x)->info.vmsa) +#define rmpentry_asid(x) ((x)->info.asid) +#define rmpentry_validated(x) ((x)->info.validated) +#define rmpentry_gpa(x) ((unsigned long)(x)->info.gpa) +#define rmpentry_immutable(x) ((x)->info.immutable) + +/* RMP page size */ +#define RMP_PG_SIZE_2M 1 +#define RMP_PG_SIZE_4K 0 + +/* Macro to convert the x86 page level to the RMP level and vice versa */ +#define X86_TO_RMP_PG_LEVEL(level) (((level) == PG_LEVEL_4K) ? RMP_PG_SIZE_4K : RMP_PG_SIZE_2M) +#define RMP_TO_X86_PG_LEVEL(level) (((level) == RMP_PG_SIZE_4K) ? PG_LEVEL_4K : PG_LEVEL_2M) + +#ifdef CONFIG_AMD_MEM_ENCRYPT +struct rmpentry *snp_lookup_page_in_rmptable(struct page *page, int *level); +#else +static inline struct rmpentry *snp_lookup_page_in_rmptable(struct page *page, int *level) +{ + return NULL; +} + +#endif /* CONFIG_AMD_MEM_ENCRYPT */ +#endif /* __LINUX_SEV_H */ From patchwork Fri Apr 30 12:37:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F0F9C433ED for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2832.namprd12.prod.outlook.com (2603:10b6:805:eb::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.24; Fri, 30 Apr 2021 12:38:58 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:38:58 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 07/37] x86/sev: Add helper functions for RMPUPDATE and PSMASH instruction Date: Fri, 30 Apr 2021 07:37:52 -0500 Message-Id: <20210430123822.13825-8-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: NxUYVi0TnSV4OStFNv3xI3nF1vreHOpCwkalGZaSzqCsO8BIctIvAa8Mjj+rcZrLACxXSFU2HYSN/3TfP2w+xcaYC6Md9iF6Ua1/akZFUEjt1h7DwzOVhXvUta5EUQ8juIE7fJCCYymkjqtvSzZCniXE8KRoU+wrjiO0fBXviJGoJJrMjG9dGR1NWHMonUng4CG7BAu3zZv4zzScaSRzNgpBrKU9HOzLueGL+lJ+4XHwopdXPs4tfl9Gt1gX6JOSFCi22e487G5GiIRn5TrTsEBt/GA+Lil8D32RHaU2OVN1b4EQ2gS9oP4qBcnWvxIrYkzIiysAVwKG6KKNYoYOTn5YQeffcMK1Kb+Cb3Ezo5P8/pVAVICwcVroW6uUfz0ZlkzSSp7zji2cYZxKez1/ovoxjsanzCFGUtBWWNpNT8a6VbcWB/y8t7VHv0u4rAPtHmlapvrehA2tURoDSkiw54I97IC9YnZEE+oCMzfitKP63TlexKR+Ipv6TM2oOK0r1DCF3rZ4knxDNL2Pt0zpTc7BYXqOOl2jKmuXUMSBNISHQUzw2P9JDPQKxWu7p9GR/8VzV3w0KGond6DDAhCK+01bqCuuhl7QzcHi3ZDPPaTgvuuVj+JU6AXLvF1ratge9JJYW36+wyRmMmD8m2/eoiEwulG3lok1NWKljugYG7jU6pcrkGdukqjb3RgLiyoAmncDohnICRgbEcxwTD6OKMVixsYiBh6YrnkLNEzS6jhYjz7mZ3bi2OfcOz9H9Ko/7hVM2bhtiDNleDhpOzpnaFsDUmLwMa4vSZqhlA3stq/5Ano8U385fKts983qOgX76DHfJ5UIfs7hWd+l2c5hpmj6bfMKLjKlB1aRHPbSLCpCT3Y87Dk+rqs0E0mH/xwrY2K88T+0YR1Ipby3dVXUZwzpB2onXGbFJnxomYIRtPXpOTlSgklhYyciV2viutanbupjsCysJv7r7ArQBzjJ2AmU4dIqRHJohr8fXJNibErl8DEDiNX1pmX1+zURtsOFvc6lmn21lwob2tKP7bAzm/he0BZ3/j9U25ofYHoz4fHADhrnkR8l3fPSlDU9r0eBS6zC69qUf4HX+GJ/0DW53FF9ZZBJKWF/0HL6fwcO739nk+g6Iu92txG71FNgr+L0SRvXvDZR7oqXuOF66sMSnrdR1w0v9I7z2EetepdvS3LXCp+i+q++m6D9ciRs1gz/zffBoL5DQP1kZNQMzGD/KevGi10STBWe+5hTWElwkspdQpNvgAvy5yM9ODzpai6XtIqQCUSv3QUqMqrZDEYGIlGh3K8KUVsrO4dxsjvi3GQCx27n4hGtffAMykbS0ReW X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: b6126d84-5735-47ff-e4e6-08d90bd4ecf6 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:38:58.7880 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: VOz2b5Agcu+5PRjkgPNj9hwuMSo4VnC3bHCqY2XFQNpl3NYGB9SeVrBTBZ+0g+oyTcGkglopgsPErZUvRRRWdQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2832 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The RMPUPDATE instruction writes a new RMP entry in the RMP Table. The hypervisor will use the instruction to add pages to the RMP table. See APM3 for details on the instruction operations. The PSMASH instruction expands a 2MB RMP entry into a corresponding set of contiguous 4KB-Page RMP entries. The hypervisor will use this instruction to adjust the RMP entry without invalidating the previous RMP entry. Signed-off-by: Brijesh Singh --- arch/x86/kernel/sev.c | 42 ++++++++++++++++++++++++++++++++++++++++++ include/linux/sev.h | 27 +++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index dec4f423e232..a8a0c6cd22ca 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -1901,3 +1901,45 @@ struct rmpentry *snp_lookup_page_in_rmptable(struct page *page, int *level) return entry; } EXPORT_SYMBOL_GPL(snp_lookup_page_in_rmptable); + +int psmash(struct page *page) +{ + unsigned long spa = page_to_pfn(page) << PAGE_SHIFT; + int ret; + + if (!cpu_feature_enabled(X86_FEATURE_SEV_SNP)) + return -ENXIO; + + /* Retry if another processor is modifying the RMP entry. */ + do { + /* Binutils version 2.36 supports the PSMASH mnemonic. */ + asm volatile(".byte 0xF3, 0x0F, 0x01, 0xFF" + : "=a"(ret) + : "a"(spa) + : "memory", "cc"); + } while (ret == PSMASH_FAIL_INUSE); + + return ret; +} +EXPORT_SYMBOL_GPL(psmash); + +int rmpupdate(struct page *page, struct rmpupdate *val) +{ + unsigned long spa = page_to_pfn(page) << PAGE_SHIFT; + int ret; + + if (!cpu_feature_enabled(X86_FEATURE_SEV_SNP)) + return -ENXIO; + + /* Retry if another processor is modifying the RMP entry. */ + do { + /* Binutils version 2.36 supports the RMPUPDATE mnemonic. */ + asm volatile(".byte 0xF2, 0x0F, 0x01, 0xFE" + : "=a"(ret) + : "a"(spa), "c"((unsigned long)val) + : "memory", "cc"); + } while (ret == RMPUPDATE_FAIL_INUSE); + + return ret; +} +EXPORT_SYMBOL_GPL(rmpupdate); diff --git a/include/linux/sev.h b/include/linux/sev.h index ee038d466786..9855e881e542 100644 --- a/include/linux/sev.h +++ b/include/linux/sev.h @@ -42,13 +42,40 @@ struct __packed rmpentry { #define X86_TO_RMP_PG_LEVEL(level) (((level) == PG_LEVEL_4K) ? RMP_PG_SIZE_4K : RMP_PG_SIZE_2M) #define RMP_TO_X86_PG_LEVEL(level) (((level) == RMP_PG_SIZE_4K) ? PG_LEVEL_4K : PG_LEVEL_2M) +/* Return code of RMPUPDATE */ +#define RMPUPDATE_SUCCESS 0 +#define RMPUPDATE_FAIL_INPUT 1 +#define RMPUPDATE_FAIL_PERMISSION 2 +#define RMPUPDATE_FAIL_INUSE 3 +#define RMPUPDATE_FAIL_OVERLAP 4 + +struct rmpupdate { + u64 gpa; + u8 assigned; + u8 pagesize; + u8 immutable; + u8 rsvd; + u32 asid; +} __packed; + +/* Return code of PSMASH */ +#define PSMASH_SUCCESS 0 +#define PSMASH_FAIL_INPUT 1 +#define PSMASH_FAIL_PERMISSION 2 +#define PSMASH_FAIL_INUSE 3 +#define PSMASH_FAIL_BADADDR 4 + #ifdef CONFIG_AMD_MEM_ENCRYPT struct rmpentry *snp_lookup_page_in_rmptable(struct page *page, int *level); +int psmash(struct page *page); +int rmpupdate(struct page *page, struct rmpupdate *e); #else static inline struct rmpentry *snp_lookup_page_in_rmptable(struct page *page, int *level) { return NULL; } +static inline int psmash(struct page *page) { return -ENXIO; } +static inline int rmpupdate(struct page *page, struct rmpupdate *e) { return -ENXIO; } #endif /* CONFIG_AMD_MEM_ENCRYPT */ #endif /* __LINUX_SEV_H */ From patchwork Fri Apr 30 12:37:53 2021 Content-Type: text/plain; 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Fri, 30 Apr 2021 12:38:59 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 08/37] x86/sev: Split the physmap when adding the page in RMP table Date: Fri, 30 Apr 2021 07:37:53 -0500 Message-Id: <20210430123822.13825-9-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: Q49HaHlwj9gGwuIakfjM++kqt4Jhx1XrhmIB75QAuBGbSVrI2Af/F8gD6brwM7ggJsz3MIOjT0W3skQCquGhqoD+DdldkrFOhgL97e07YnuEGPrw+dr/8Ql+AkzW1xFYqSweutHijFO/XBJjEo7nbC5hlgdOoHwZII63YErJNCWxIJjEjlQlGkBpviwBQsQzh5gW451EYeUnY8n+zJDnsWfI2/XeTppagV1b11eYPhh0gPwlEd7B39PJCE2MIBwQszJCiaHdNgDcgp2W4h9gJU9jOlZsmhwIvmmRxulHuArfWmtS12zVaEXAbBLRZHIy5k/CBtn6kblOVHllyrr07AFaupYUbGH+/FJ+mj5M/8HAd+b7LkWFIef+WQc/tKm8JkNY0D7B/1r0LI8VrTg101zH+E+SUQv31fyZwRjnYb18BE1vHtC56Coq4i9YPwLESgoacsYkVX0bdSPJ5tiQmRrkCpwCqY5NKyW9qIH+vIG8htgeLPUYI0JzU+x4B9AhwBhkB5J/ln6Bngp05ozOChr91Q6h7AyoCcYpgj15LjohJj0NUofH0N2J4JulaE6CJMlLes3mcjAeLl4yy9JA7T67vjgvQhd3rOs4WY4BBWqn0bzqyn/eEK+qDntqTk/4Z5gzfzDUJm1Yb6MblQ4LwTXwZfBe+UXnM4hJGcnNSLuEssyhr3EfhCFVnxRmak9ZgoWIXli/eRjsZqoqYzqKeiXOyPlkoH6/+JOcM7Qzwk/j+VVqG57XN1DDZwo0itpmZHfoL2YjvHxg86ectV8/tvV/847Wi5vtvmYV81vmHlWDi8EYtabRq6kufNoIrHK0Mi9KIVGLmkwwBQixCwkrUPOXUd7n2kvlwfJe+LEu5NuYm0F1UnW84nOx1SR3Lc8xLYmV730+8nhMe/5XMY1r2ow93auVPwoxof8DqTuhK0cU7dTwBeIMac/KMufjn2wgCo3oDYC8VTXB7V8pXmb93zVmoNDvPygPxUM3f5dutBpY0lJnodBOkuEeP8NyLKy5xG9V1c1fvD4lSYsxLMCuIp0E7kozx4eFehSt0XY9AchMxYXe0OiBkcVQlLtisvOkgMdnA3PeNeWgdzkSr1VVupZoLVHxa2cEWiRjnF78gpB6YAo1/GNlQh/Fudh6tqqMUlfxeVM4ujYysdvqIoQoi6ndB8tGJtGh/Yf5/Fmbje6hJCAe3t3TopY8Hf6aHewamWBFMwPm+CXKy3BQ405Jqd2lqn1jFwnAIU7HhnUnW+Xah1hQX/Rnp78Hf57DQs2G6f5SUHuY1vmAuN+XETUvn+b4rZQ0zCFqjZKCumqXI9oi/AOCRlWdt6xPKwthHcuG X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8ec064fe-4ae9-4c00-981d-08d90bd4ed5e X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:38:59.4596 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: QRwZTKhnOy1QE4IDqmK7YZZ9/f3c+ja1rTdsa8NISNUbnZlEHa7cRhQRzghzkYhq66mDh8+3u6cJbDnfLgMsZA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2832 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The integrity guarantee of SEV-SNP is enforced through the RMP table. The RMP is used in conjuntion with standard x86 and IOMMU page tables to enforce memory restrictions and page access rights. The RMP is indexed by system physical address, and is checked at the end of CPU and IOMMU table walks. The RMP check is enforced as soon as SEV-SNP is enabled globally in the system. Not every memory access requires an RMP check. In particular, the read accesses from the hypervisor do not require RMP checks because the data confidentiality is already protected via memory encryption. When hardware encounters an RMP checks failure, it raise a page-fault exception. The RMP bit in fault error code can be used to determine if the fault was due to an RMP checks failure. A write from the hypervisor goes through the RMP checks. When the hypervisor writes to pages, hardware checks to ensures that the assigned bit in the RMP is zero (i.e page is shared). If the page table entry that gives the sPA indicates that the target page size is a large page, then all RMP entries for the 4KB constituting pages of the target must have the assigned bit 0. If one of entry does not have assigned bit 0 then hardware will raise an RMP violation. To resolve it, split the page table entry leading to target page into 4K. This poses a challenge in the Linux memory model. The Linux kernel creates a direct mapping of all the physical memory -- referred to as the physmap. The physmap may contain a valid mapping of guest owned pages. During the page table walk, the host access may get into the situation where one of the pages within the large page is owned by the guest (i.e assigned bit is set in RMP). A write to a non-guest within the large page will raise an RMP violation. To workaround it, call set_memory_4k() to split the physmap before adding the page in the RMP table. This ensures that the pages added in the RMP table are used as 4K in the physmap. The spliting of the physmap is a temporary solution until the kernel page fault handler is improved to split the kernel address on demand. One of the disadvtange of splitting is that eventually, it will end up breaking down the entire physmap unless its coalesce back to a large page. I am open to the suggestation on various approaches we could take to address this problem. Signed-off-by: Brijesh Singh --- arch/x86/kernel/sev.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/kernel/sev.c b/arch/x86/kernel/sev.c index a8a0c6cd22ca..60d62c66778b 100644 --- a/arch/x86/kernel/sev.c +++ b/arch/x86/kernel/sev.c @@ -1931,6 +1931,12 @@ int rmpupdate(struct page *page, struct rmpupdate *val) if (!cpu_feature_enabled(X86_FEATURE_SEV_SNP)) return -ENXIO; + ret = set_memory_4k((unsigned long)page_to_virt(page), 1); + if (ret) { + pr_err("Failed to split physical address 0x%lx (%d)\n", spa, ret); + return ret; + } + /* Retry if another processor is modifying the RMP entry. */ do { /* Binutils version 2.36 supports the RMPUPDATE mnemonic. */ From patchwork Fri Apr 30 12:37:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233299 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE543C43461 for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2832.namprd12.prod.outlook.com (2603:10b6:805:eb::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.24; Fri, 30 Apr 2021 12:39:00 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:00 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 09/37] x86/traps: Define RMP violation #PF error code Date: Fri, 30 Apr 2021 07:37:54 -0500 Message-Id: <20210430123822.13825-10-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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While at it, use the BIT() macro. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/trap_pf.h | 18 +++++++++++------- arch/x86/mm/fault.c | 1 + 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/trap_pf.h b/arch/x86/include/asm/trap_pf.h index 10b1de500ab1..29f678701753 100644 --- a/arch/x86/include/asm/trap_pf.h +++ b/arch/x86/include/asm/trap_pf.h @@ -2,6 +2,8 @@ #ifndef _ASM_X86_TRAP_PF_H #define _ASM_X86_TRAP_PF_H +#include /* BIT() macro */ + /* * Page fault error code bits: * @@ -12,15 +14,17 @@ * bit 4 == 1: fault was an instruction fetch * bit 5 == 1: protection keys block access * bit 15 == 1: SGX MMU page-fault + * bit 31 == 1: fault was an RMP violation */ enum x86_pf_error_code { - X86_PF_PROT = 1 << 0, - X86_PF_WRITE = 1 << 1, - X86_PF_USER = 1 << 2, - X86_PF_RSVD = 1 << 3, - X86_PF_INSTR = 1 << 4, - X86_PF_PK = 1 << 5, - X86_PF_SGX = 1 << 15, + X86_PF_PROT = BIT(0), + X86_PF_WRITE = BIT(1), + X86_PF_USER = BIT(2), + X86_PF_RSVD = BIT(3), + X86_PF_INSTR = BIT(4), + X86_PF_PK = BIT(5), + X86_PF_SGX = BIT(15), + X86_PF_RMP = BIT(31), }; #endif /* _ASM_X86_TRAP_PF_H */ diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index a73347e2cdfc..39d22f6870e1 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c @@ -545,6 +545,7 @@ show_fault_oops(struct pt_regs *regs, unsigned long error_code, unsigned long ad !(error_code & X86_PF_PROT) ? "not-present page" : (error_code & X86_PF_RSVD) ? "reserved bit violation" : (error_code & X86_PF_PK) ? "protection keys violation" : + (error_code & X86_PF_RMP) ? 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dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2832.namprd12.prod.outlook.com (2603:10b6:805:eb::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.24; Fri, 30 Apr 2021 12:39:01 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:01 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 10/37] x86/fault: Add support to handle the RMP fault for kernel address Date: Fri, 30 Apr 2021 07:37:55 -0500 Message-Id: <20210430123822.13825-11-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: Rn/hOGE5zgOc19JGwTzr9KmvYXVOZGr9D0B2OZ0pwjP8JDXIlWcapmAbW8J4HxQ5hPxTjQqbEWes4tNXlfyQFomNxow1NvSSQC2L4wd9GfrtxJ5VlvRteJmg9rvGJtB0FdKqaG31x8MKbeYZGYkUCPiyoaYZtvrcMzvCi9CYjRioCqqtl9wKuTHK2uM42c8iOr6WKfGAiHpfMugyY7QXvjFHYTAnk0FFRIunlh0Nx0XWIcBEXOR9y2A3OvP2KpZTOaT0TJXPvmEoIQOZElmKHfjtX1bglequ6s56hH0+IukBz/BgZg6jib6Lq7sJyQwrmvi1r0/kRcQZsTleD1i3v/MfwzYZrpHMDCLnBy2q5uGIOeTlz/gzGawZO1tIVnqkSUfJzA6V1QuEYSIRP0V50ln5XUZloAg/n+i2uDqFPHDGsxwBI+q405wROfxVkNxX+HcXFZZVrgaUABPHB+qdh/NvQcCFUN+ugNpdOHBcqGBeXPdlNZFxs8f+GZJcL9YlVsGiP5GYTShPuvrUnsMizqgAEmneT/pW9RpwgO74SUobgrpsk9deY5d7tLveC/1CrbKtFI7DEwcSb74FvbzwzJ7B6uPJM8iXtYeMJHuYYBiZ0oRPv4u4eSEhOqTLqpvHMUKPwhfm/Z3Gni/ZlzY5Eiz6GKqdpCDZK7pnV5aYRq1jle9ksT/c2XmSz5cVr0NMz7gG0klpt0rJSTxy+ck1NINE/X5aiQX531FFpnFqGdPu+PJgeolT/NULm4WDWYsb0w3mAB9qvu2T1uJTLqRuOpB97zxjHn7ICD4BSBytSsP6Hk53wJfgKfZftD01372p6GOdrtIKq8CODwFgvcYdVP1NQAwXOXzwQq6QUbValfoOgdHhwDkT+XOh6VWkXi08WzpT3OT/1evbI3dk0hInvN/QJ3iE6Iu4d8gE5UnrCKhKXjMaf2Y3XXL9M2HB/SEDYHdZFLAi2C5ui5tRLbVbrVBPW9ngEHEgq5kzauoCXJcRPXzZ1y/5gT23uxNqYye8eIovo4ACP6tZiW3RTLPK6R+JxC3J/EAJnGuitSZY9jYxTjQPlDftCQrvorHdOLMYVWLZCvgMTOBF0Wk1TrkvBNlIAkyr4E1yOp2ilvPkVY6O56Gak9YxyHmj144tbU/tS+J2uf1PI9QNV5wURZdCKHCGagw4R8BlYRSOLWn8o4DSQsdzMtcSfTAdcaIJ12sgVnzCBjJCdZIk7fpQd9tqZdgalGryE9i1Pz3qZVd8lmLHe+SypU5UVVqUinoxVi4LapE9kTU0JvIEiOwdVBJxvKOrvWq8LwaAzFvnPoHghv82888QiEfJb+iWMQgByPcR X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4bf20d5d-6549-4eb7-7fe1-08d90bd4ee3a X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:00.9198 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: nRmtZyNfrbhpnPFFmRFEmJxYXpLgvKHCLludYJUfRY+KLsL8bj2QBtBCOppziaz/WbjKI0DxMIHu0fzhYeqs3Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2832 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org When SEV-SNP is enabled globally, a write from the host goes through the RMP check. When the host writes to pages, hardware checks the following conditions at the end of page walk: 1. Assigned bit in the RMP table is zero (i.e page is shared). 2. If the page table entry that gives the sPA indicates that the target page size is a large page, then all RMP entries for the 4KB constituting pages of the target must have the assigned bit 0. 3. Immutable bit in the RMP table is not zero. The hardware will raise page fault if one of the above conditions is not met. A host should not encounter the RMP fault in normal execution, but a malicious guest could trick the hypervisor into it. e.g., a guest does not make the GHCB page shared, on #VMGEXIT, the hypervisor will attempt to write to GHCB page. Try resolving the fault instead of crashing the host. To resolve it, forcefully clear the assigned bit from the RMP entry to make the page shared so that the write succeeds. If the fault handler cannot resolve the RMP violation, then dump the RMP entry for debugging purposes. Signed-off-by: Brijesh Singh --- arch/x86/mm/fault.c | 146 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index 39d22f6870e1..d833fe84010f 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c @@ -19,6 +19,7 @@ #include /* faulthandler_disabled() */ #include /* efi_crash_gracefully_on_page_fault()*/ #include +#include /* snp_lookup_page_in_rmptable() */ #include /* boot_cpu_has, ... */ #include /* dotraplinkage, ... */ @@ -1132,6 +1133,145 @@ bool fault_in_kernel_space(unsigned long address) return address >= TASK_SIZE_MAX; } +#define RMP_FAULT_RETRY 0 +#define RMP_FAULT_KILL 1 +#define RMP_FAULT_PAGE_SPLIT 2 + +static inline size_t pages_per_hpage(int level) +{ + return page_level_size(level) / PAGE_SIZE; +} + +static void dump_rmpentry(unsigned long pfn) +{ + struct rmpentry *e; + int level; + + e = snp_lookup_page_in_rmptable(pfn_to_page(pfn), &level); + + /* + * If the RMP entry at the faulting address was not assigned, then dump may not + * provide any useful debug information. Iterate through the entire 2MB region, + * and dump the RMP entries if one of the bit in the RMP entry is set. + */ + if (rmpentry_assigned(e)) { + pr_alert("RMPEntry paddr 0x%lx [assigned=%d immutable=%d pagesize=%d gpa=0x%lx" + " asid=%d vmsa=%d validated=%d]\n", pfn << PAGE_SHIFT, + rmpentry_assigned(e), rmpentry_immutable(e), rmpentry_pagesize(e), + rmpentry_gpa(e), rmpentry_asid(e), rmpentry_vmsa(e), + rmpentry_validated(e)); + + pr_alert("RMPEntry paddr 0x%lx %016llx %016llx\n", pfn << PAGE_SHIFT, + e->high, e->low); + } else { + unsigned long pfn_end; + + pfn = pfn & ~0x1ff; + pfn_end = pfn + PTRS_PER_PMD; + + while (pfn < pfn_end) { + e = snp_lookup_page_in_rmptable(pfn_to_page(pfn), &level); + + if (unlikely(!e)) + return; + + if (e->low || e->high) + pr_alert("RMPEntry paddr 0x%lx: %016llx %016llx\n", + pfn << PAGE_SHIFT, e->high, e->low); + pfn++; + } + } +} + +/* + * Called for all faults where 'address' is part of the kernel address space. + * The function returns RMP_FAULT_RETRY when its able to resolve the fault and + * its safe to retry. + */ +static int handle_kern_rmp_fault(unsigned long hw_error_code, unsigned long address) +{ + int ret, level, rmp_level, mask; + struct rmpupdate val = {}; + struct rmpentry *e; + unsigned long pfn; + pgd_t *pgd; + pte_t *pte; + + if (unlikely(!cpu_feature_enabled(X86_FEATURE_SEV_SNP))) + return RMP_FAULT_KILL; + + pgd = __va(read_cr3_pa()); + pgd += pgd_index(address); + + pte = lookup_address_in_pgd(pgd, address, &level); + + if (unlikely(!pte)) + return RMP_FAULT_KILL; + + switch(level) { + case PG_LEVEL_4K: pfn = pte_pfn(*pte); break; + case PG_LEVEL_2M: pfn = pmd_pfn(*(pmd_t *)pte); break; + case PG_LEVEL_1G: pfn = pud_pfn(*(pud_t *)pte); break; + case PG_LEVEL_512G: pfn = p4d_pfn(*(p4d_t *)pte); break; + default: return RMP_FAULT_KILL; + } + + /* Calculate the PFN within large page. */ + if (level > PG_LEVEL_4K) { + mask = pages_per_hpage(level) - pages_per_hpage(level - 1); + pfn |= (address >> PAGE_SHIFT) & mask; + } + + e = snp_lookup_page_in_rmptable(pfn_to_page(pfn), &rmp_level); + if (unlikely(!e)) + return RMP_FAULT_KILL; + + /* + * If the immutable bit is set, we cannot convert the page to shared + * to resolve the fault. + */ + if (rmpentry_immutable(e)) + goto e_dump_rmpentry; + + /* + * If the host page level is greather than RMP page level then only way to + * resolve the fault is to split the address. We don't support splitting + * kernel address in the fault path yet. + */ + if (level > rmp_level) + goto e_dump_rmpentry; + + /* + * If the RMP page level is higher than host page level then use the PSMASH + * to split the RMP large entry into 512 4K entries. + */ + if (rmp_level > level) { + ret = psmash(pfn_to_page(pfn & ~0x1FF)); + if (ret) { + pr_alert("Failed to psmash pfn 0x%lx (rc %d)\n", pfn, ret); + goto e_dump_rmpentry; + } + } + + /* Log that the RMP fault handler is clearing the assigned bit. */ + if (rmpentry_assigned(e)) + pr_alert("Force address %lx from assigned -> unassigned in RMP table\n", address); + + /* Clear the assigned bit from the RMP table. */ + ret = rmpupdate(pfn_to_page(pfn), &val); + if (ret) { + pr_alert("Failed to unassign address 0x%lx in RMP table\n", address); + goto e_dump_rmpentry; + } + + return RMP_FAULT_RETRY; + +e_dump_rmpentry: + + dump_rmpentry(pfn); + return RMP_FAULT_KILL; +} + /* * Called for all faults where 'address' is part of the kernel address * space. Might get called for faults that originate from *code* that @@ -1179,6 +1319,12 @@ do_kern_addr_fault(struct pt_regs *regs, unsigned long hw_error_code, } #endif + /* Try resolving the RMP fault. */ + if (hw_error_code & X86_PF_RMP) { + if (handle_kern_rmp_fault(hw_error_code, address) == RMP_FAULT_RETRY) + return; + } + if (is_f00f_bug(regs, hw_error_code, address)) return; From patchwork Fri Apr 30 12:37:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 560C8C433ED for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2832.namprd12.prod.outlook.com (2603:10b6:805:eb::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.24; Fri, 30 Apr 2021 12:39:02 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:02 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 11/37] x86/fault: Add support to handle the RMP fault for user address Date: Fri, 30 Apr 2021 07:37:56 -0500 Message-Id: <20210430123822.13825-12-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: zq8g2EYKPlNu6+mGJs8abr5IdI2AedqE/dDlyHZ2DghKbr6putvbjvFTy0mmjHNqGzljj2/8vQFV0GdA9tF4HujOYUZRd/gjQx09DvedTgLgx0PuVoMiOJ/Ibkw5F9CwvBJUaUPqyaNvBjW+Ufm8KPjBAaPy6qMjaqg9Y7V3P6XD3reRYtpm7BJx/d9qZnAlF4ITMARIogkRIlbxLgYpa7wh5WY/0Ch9Pg69caQ6U9CDD4Dao2fTKgOMB+pDHS7v1fSfyDWC3d782iBdyyj1CHcijXbbnA5Js6pYfRcZziqRJlQTGlgs2FUrlEvZUZYdgVFaKGpgEFtRBSNZet2olZ+zNAw1tkzZHrHvHD0pMRO4FnFTFIvyipz3SbEgY1OHhsc8VNpE4dVjfEvpgu/j7BM65ExBcn3EFjQ5U6Fa5qUJkj9jwSzs4akZSOHQv1jq5pVabbxGpbfz8ae/fsAZKRJ3Z2yr2Cq4J35piDWk+yZAgs2eGYLl1zvekQib+JRTHWoszsL17ZQCxQviDCsapMaicMgAR3mu+tUQxTftsC4MP88baGUXFJRox65PT340b6zyk954YMUxDJ8iKmI4cFYpx/3pQ/szNtVK8H/8b0yzgsUE31h419R6a+TmthUXqAzpEX5sVhmmhzeWOMG6KnIcPP0XXLnteYWxs0DQehaxcLKTCmJ3xrLMCnn2IPBUGxZCWaeF4e23QhrTFPX9uKPIgwwD5lQP1JDfPFFecPoqyO4TprvvwCUaWvarlKD0rSLQ5IEhv2KQY04CspbWPfiHsFbl77vtXcvf+9xsWDDFO8rusCWmZMMMuc+VZh8LhkT8i4Rc1glhgpTPiuEgDr3CByE8xOAhvv8SMlxWRZW6+j8Y4XFJWH7ZTyZti+3YftCOG41NPRWE8zkcVj9NRY1zo9ymfk2brtoVt+V0lgEOs/TCQur+2xC/s6Yjoa2pewuF8VH3QXMNc6MMl/MItwCfJ48HC/UjAzx5e/McTqQj32KrAwtJN3Z7X+OmLAKBjAOHBk3J0wyBdNBeswHc/d+/eovViyJ810hVglx8m1TFMw8zuftWLH0dBcZk2wc9LKHWwLG5D2SvDZGYfy76XGvYUpS2njI8hHBEi42OSjOPThOhkEtumdD94WiDTDfRFUejIQQ4XCUK5ASQPHFgXHiiwdjeLXz1Vh95IPGD3Wa81rJns+axuImbwSlhOyu1Vt0ps0/hcrvv7MNklf6dpl1wC2Aedx3I9ULubPNswvW9zpuvH0gIm4kbOLpptomou3+73fwVuRhJBfL0VEbCyXAy80qyQdtUPzQK5ZVtFPFIy3KaDjyB0bliU5i8f+o3 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 18d24d63-1728-4cfc-e468-08d90bd4eeaa X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:01.7753 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: A1Ozx6UCG4J8sxI/UFGgDWh2yJSt8b+/fbIC04nfTio1U8/afTsSVEpikmlx4fr0OJ3wKGBwz3Ay8C9Dg+0hNw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2832 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org When SEV-SNP is enabled globally, a write from the host goes through the RMP check. When the host writes to pages, hardware checks the following conditions at the end of page walk: 1. Assigned bit in the RMP table is zero (i.e page is shared). 2. If the page table entry that gives the sPA indicates that the target page size is a large page, then all RMP entries for the 4KB constituting pages of the target must have the assigned bit 0. 3. Immutable bit in the RMP table is not zero. The hardware will raise page fault if one of the above conditions is not met. Try resolving the fault instead of taking fault again and again. If the host attempts to write to the guest private memory then send the SIGBUG signal to kill the process. If the page level between the host and RMP entry does not match, then split the address to keep the RMP and host page levels in sync. Signed-off-by: Brijesh Singh --- arch/x86/mm/fault.c | 60 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/mm.h | 6 ++++- mm/memory.c | 13 ++++++++++ 3 files changed, 78 insertions(+), 1 deletion(-) diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c index d833fe84010f..4441f5332c2c 100644 --- a/arch/x86/mm/fault.c +++ b/arch/x86/mm/fault.c @@ -1348,6 +1348,49 @@ do_kern_addr_fault(struct pt_regs *regs, unsigned long hw_error_code, } NOKPROBE_SYMBOL(do_kern_addr_fault); +static int handle_user_rmp_page_fault(unsigned long hw_error_code, unsigned long address) +{ + unsigned long pfn, mask; + int rmp_level, level; + struct rmpentry *e; + pte_t *pte; + + if (unlikely(!cpu_feature_enabled(X86_FEATURE_SEV_SNP))) + return RMP_FAULT_KILL; + + /* Get the native page level */ + pte = lookup_address_in_mm(current->mm, address, &level); + if (unlikely(!pte)) + return RMP_FAULT_KILL; + + pfn = pte_pfn(*pte); + if (level > PG_LEVEL_4K) { + mask = pages_per_hpage(level) - pages_per_hpage(level - 1); + pfn |= (address >> PAGE_SHIFT) & mask; + } + + /* Get the page level from the RMP entry. */ + e = snp_lookup_page_in_rmptable(pfn_to_page(pfn), &rmp_level); + if (!e) + return RMP_FAULT_KILL; + + /* + * Check if the RMP violation is due to the guest private page access. We can + * not resolve this RMP fault, ask to kill the guest. + */ + if (rmpentry_assigned(e)) + return RMP_FAULT_KILL; + + /* + * Its a guest shared page, and the backing page level is higher than the RMP + * page level, request to split the page. + */ + if (level > rmp_level) + return RMP_FAULT_PAGE_SPLIT; + + return RMP_FAULT_RETRY; +} + /* * Handle faults in the user portion of the address space. Nothing in here * should check X86_PF_USER without a specific justification: for almost @@ -1365,6 +1408,7 @@ void do_user_addr_fault(struct pt_regs *regs, struct task_struct *tsk; struct mm_struct *mm; vm_fault_t fault; + int ret; unsigned int flags = FAULT_FLAG_DEFAULT; tsk = current; @@ -1445,6 +1489,22 @@ void do_user_addr_fault(struct pt_regs *regs, if (error_code & X86_PF_INSTR) flags |= FAULT_FLAG_INSTRUCTION; + /* + * If its an RMP violation, try resolving it. + */ + if (error_code & X86_PF_RMP) { + ret = handle_user_rmp_page_fault(error_code, address); + if (ret == RMP_FAULT_PAGE_SPLIT) { + flags |= FAULT_FLAG_PAGE_SPLIT; + } else if (ret == RMP_FAULT_KILL) { + fault |= VM_FAULT_SIGBUS; + do_sigbus(regs, error_code, address, fault); + return; + } else { + return; + } + } + #ifdef CONFIG_X86_64 /* * Faults in the vsyscall page might need emulation. The diff --git a/include/linux/mm.h b/include/linux/mm.h index 8ba434287387..b37d9d8aae3b 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -434,6 +434,8 @@ extern pgprot_t protection_map[16]; * @FAULT_FLAG_REMOTE: The fault is not for current task/mm. * @FAULT_FLAG_INSTRUCTION: The fault was during an instruction fetch. * @FAULT_FLAG_INTERRUPTIBLE: The fault can be interrupted by non-fatal signals. + * @FAULT_FLAG_PAGE_SPLIT: The fault was due page size mismatch, split the + * region to smaller page size and retry. * * About @FAULT_FLAG_ALLOW_RETRY and @FAULT_FLAG_TRIED: we can specify * whether we would allow page faults to retry by specifying these two @@ -464,6 +466,7 @@ extern pgprot_t protection_map[16]; #define FAULT_FLAG_REMOTE 0x80 #define FAULT_FLAG_INSTRUCTION 0x100 #define FAULT_FLAG_INTERRUPTIBLE 0x200 +#define FAULT_FLAG_PAGE_SPLIT 0x400 /* * The default fault flags that should be used by most of the @@ -501,7 +504,8 @@ static inline bool fault_flag_allow_retry_first(unsigned int flags) { FAULT_FLAG_USER, "USER" }, \ { FAULT_FLAG_REMOTE, "REMOTE" }, \ { FAULT_FLAG_INSTRUCTION, "INSTRUCTION" }, \ - { FAULT_FLAG_INTERRUPTIBLE, "INTERRUPTIBLE" } + { FAULT_FLAG_INTERRUPTIBLE, "INTERRUPTIBLE" }, \ + { FAULT_FLAG_PAGE_SPLIT, "PAGESPLIT" } /* * vm_fault is filled by the pagefault handler and passed to the vma's diff --git a/mm/memory.c b/mm/memory.c index 550405fc3b5e..21ec049e21ad 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -4358,6 +4358,15 @@ static vm_fault_t handle_pte_fault(struct vm_fault *vmf) return 0; } +static int handle_split_page_fault(struct vm_fault *vmf) +{ + if (!IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT)) + return VM_FAULT_SIGBUS; + + __split_huge_pmd(vmf->vma, vmf->pmd, vmf->address, false, NULL); + return 0; +} + /* * By the time we get here, we already hold the mm semaphore * @@ -4435,6 +4444,10 @@ static vm_fault_t __handle_mm_fault(struct vm_area_struct *vma, pmd_migration_entry_wait(mm, vmf.pmd); return 0; } + + if (flags & FAULT_FLAG_PAGE_SPLIT) + return handle_split_page_fault(&vmf); + if (pmd_trans_huge(orig_pmd) || pmd_devmap(orig_pmd)) { if (pmd_protnone(orig_pmd) && vma_is_accessible(vma)) return do_huge_pmd_numa_page(&vmf, orig_pmd); From patchwork Fri Apr 30 12:37:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8517C433B4 for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2832.namprd12.prod.outlook.com (2603:10b6:805:eb::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.24; Fri, 30 Apr 2021 12:39:02 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:02 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 12/37] crypto:ccp: Define the SEV-SNP commands Date: Fri, 30 Apr 2021 07:37:57 -0500 Message-Id: <20210430123822.13825-13-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: YSXLaK7eyDmowTMEpADwbT41h5cFDKIR+6OQ0q62uIgd8mtSZPXGWgEWM9oJBe8zNYHFwbPS05wODDG/bBC5sIraBDNk3SmhDvqt7zv74PRlpXqB570q9/zNPeC42HgCSdmMyjYT9npYYc+iVtDJWh8+eKCWhXCiPUpGiE3ikIhBa1XWHu0iHCSygQEPG2z7Arez/KLSfCvOvlFAqFQZGrVMfvnorNeglo8OLqP9QOlGONU0Ahebt2czDq7zvkWj1cY/zDFJv0vGl2glO1qhlXpmcobJd2KBwqAhhB1ekBZTPA3D/y+5lByfTZNCqpZIswZ6TXmbOuejicnpl7mxUt+arYe6HbzgGqfBsRNZL2XDJkrp+oLQL2redNiF0Fq5vwG1ieU3zZ+SV0gnx3L7SasVA58QIlx4F0G5zRckTkClAgfm7UpGc6dDfnfVSL/nq/+Fl9qgGg0CzGNdW0fiY2bHoReTiprP6XIfnNS42NDETM37mwzmLNSDRwf5txCUanbzyq4c4aAJtGnfE5w5DKj+zDeD6Eooidi3ygoBrW8EO7fKDHfMbdybMXCPYpZpYMApdUYJAngM0uOu3u/Vftgjoy4qqVeCyEcgsagRTvy+6PylHIrUBQxU/OTXsB24WZCDG42kBKPX7bBxO7gZH+mlI2NRbLPAw40mlvNouk8o/ADnTBYtxgY1kQwIsHrEEVTDJLXla4TdjFMZfITxGIIYFxeIkRgI98QumyAXpmIhmgTcjF6sjVL4cXWEQwaltX9zqD+5WzVP4FBaCuyan9Db7FnEBPIpSXl9yktZY++98eaBv8kYJQhLEId4cu/EWL65HdKhqjkmA+brkFn01hcQeQI65PpLJYWdyDyvlUsdP8E21r+tjJMsGn7aKyPBbtrGEuFLL3VLHnPqsQ8LlYNuCBmNggvNJVQjP9wvIDKxaPXaFSRJX/AWEq6gZrM4CYHxl1P4CrEDQYb4+5HVSkiwjIXdWppow8BjknZsKACQDIkiANp8MLX+SEROUuIS5eOt9yvNsPMt4d9+Zej17/uz39YkfINVaygze+y2b73r4YpfDcWvZF7QEjIXXSBhueUyrWKN3wkm4Uo+q0D6fpMEwsYRWJcLd6kg1/uKzQ7NHwN+6d+ax/qWGN86qN80x+eTyBseJtH0R0dPJeK/DIEFVCj3pWwr1meVrOjte+qiRTV1L8X7vxiXYG/oaQgYwQjfA1dLhLA2a6v+cdPX/rvJ1VPmErSPGc8Ks2M5xO5+lUa9eglbe5RyloftwRtBjV2nUlCx9PstvGJFQoshCXpZGyAO9zsWMM3qLrPzhYZHIQLC7rnp2eBscKuE4MEU X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: dd128264-08c3-4764-9ad8-08d90bd4ef22 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:02.5009 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 8CpG343kGEOXwvc3EwsTPfaUY3Lp3ofJ5AXu/rwCMtZLtMcpB8udbhZA6+v4j+q202dtgXLHqSQX7+lGaF9imA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2832 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org AMD introduced the next generation of SEV called SEV-SNP (Secure Nested Paging). SEV-SNP builds upon existing SEV and SEV-ES functionality while adding new hardware security protection. Define the commands and structures used to communicate with the AMD-SP when creating and managing the SEV-SNP guests. The SEV-SNP firmware spec is available at developer.amd.com/sev. Signed-off-by: Brijesh Singh --- drivers/crypto/ccp/sev-dev.c | 16 ++- include/linux/psp-sev.h | 222 +++++++++++++++++++++++++++++++++++ include/uapi/linux/psp-sev.h | 44 +++++++ 3 files changed, 281 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/ccp/sev-dev.c b/drivers/crypto/ccp/sev-dev.c index 6ee703176049..09d117b99bf5 100644 --- a/drivers/crypto/ccp/sev-dev.c +++ b/drivers/crypto/ccp/sev-dev.c @@ -129,7 +129,21 @@ static int sev_cmd_buffer_len(int cmd) case SEV_CMD_DOWNLOAD_FIRMWARE: return sizeof(struct sev_data_download_firmware); case SEV_CMD_GET_ID: return sizeof(struct sev_data_get_id); case SEV_CMD_ATTESTATION_REPORT: return sizeof(struct sev_data_attestation_report); - case SEV_CMD_SEND_CANCEL: return sizeof(struct sev_data_send_cancel); + case SEV_CMD_SEND_CANCEL: return sizeof(struct sev_data_send_cancel); + case SEV_CMD_SNP_GCTX_CREATE: return sizeof(struct sev_data_snp_gctx_create); + case SEV_CMD_SNP_LAUNCH_START: return sizeof(struct sev_data_snp_launch_start); + case SEV_CMD_SNP_LAUNCH_UPDATE: return sizeof(struct sev_data_snp_launch_update); + case SEV_CMD_SNP_ACTIVATE: return sizeof(struct sev_data_snp_activate); + case SEV_CMD_SNP_DECOMMISSION: return sizeof(struct sev_data_snp_decommission); + case SEV_CMD_SNP_PAGE_RECLAIM: return sizeof(struct sev_data_snp_page_reclaim); + case SEV_CMD_SNP_GUEST_STATUS: return sizeof(struct sev_data_snp_guest_status); + case SEV_CMD_SNP_LAUNCH_FINISH: return sizeof(struct sev_data_snp_launch_finish); + case SEV_CMD_SNP_DBG_DECRYPT: return sizeof(struct sev_data_snp_dbg); + case SEV_CMD_SNP_DBG_ENCRYPT: return sizeof(struct sev_data_snp_dbg); + case SEV_CMD_SNP_PAGE_UNSMASH: return sizeof(struct sev_data_snp_page_unsmash); + case SEV_CMD_SNP_PLATFORM_STATUS: return sizeof(struct sev_data_snp_platform_status_buf); + case SEV_CMD_SNP_GUEST_REQUEST: return sizeof(struct sev_data_snp_guest_request); + case SEV_CMD_SNP_CONFIG: return sizeof(struct sev_data_snp_config); default: return 0; } diff --git a/include/linux/psp-sev.h b/include/linux/psp-sev.h index d48a7192e881..c3755099ab55 100644 --- a/include/linux/psp-sev.h +++ b/include/linux/psp-sev.h @@ -85,6 +85,34 @@ enum sev_cmd { SEV_CMD_DBG_DECRYPT = 0x060, SEV_CMD_DBG_ENCRYPT = 0x061, + /* SNP specific commands */ + SEV_CMD_SNP_INIT = 0x81, + SEV_CMD_SNP_SHUTDOWN = 0x82, + SEV_CMD_SNP_PLATFORM_STATUS = 0x83, + SEV_CMD_SNP_DF_FLUSH = 0x84, + SEV_CMD_SNP_INIT_EX = 0x85, + SEV_CMD_SNP_DECOMMISSION = 0x90, + SEV_CMD_SNP_ACTIVATE = 0x91, + SEV_CMD_SNP_GUEST_STATUS = 0x92, + SEV_CMD_SNP_GCTX_CREATE = 0x93, + SEV_CMD_SNP_GUEST_REQUEST = 0x94, + SEV_CMD_SNP_ACTIVATE_EX = 0x95, + SEV_CMD_SNP_LAUNCH_START = 0xA0, + SEV_CMD_SNP_LAUNCH_UPDATE = 0xA1, + SEV_CMD_SNP_LAUNCH_FINISH = 0xA2, + SEV_CMD_SNP_DBG_DECRYPT = 0xB0, + SEV_CMD_SNP_DBG_ENCRYPT = 0xB1, + SEV_CMD_SNP_PAGE_SWAP_OUT = 0xC0, + SEV_CMD_SNP_PAGE_SWAP_IN = 0xC1, + SEV_CMD_SNP_PAGE_MOVE = 0xC2, + SEV_CMD_SNP_PAGE_MD_INIT = 0xC3, + SEV_CMD_SNP_PAGE_MD_RECLAIM = 0xC4, + SEV_CMD_SNP_PAGE_RO_RECLAIM = 0xC5, + SEV_CMD_SNP_PAGE_RO_RESTORE = 0xC6, + SEV_CMD_SNP_PAGE_RECLAIM = 0xC7, + SEV_CMD_SNP_PAGE_UNSMASH = 0xC8, + SEV_CMD_SNP_CONFIG = 0xC9, + SEV_CMD_MAX, }; @@ -510,6 +538,200 @@ struct sev_data_attestation_report { u32 len; /* In/Out */ } __packed; +/** + * struct sev_data_snp_platform_status_buf - SNP_PLATFORM_STATUS command params + * + * @address: physical address where the status should be copied + */ +struct sev_data_snp_platform_status_buf { + u64 status_paddr; /* In */ +} __packed; + +/** + * struct sev_data_snp_download_firmware - SNP_DOWNLOAD_FIRMWARE command params + * + * @address: physical address of firmware image + * @len: len of the firmware image + */ +struct sev_data_snp_download_firmware { + u64 address; /* In */ + u32 len; /* In */ +} __packed; + +/** + * struct sev_data_snp_gctx_create - SNP_GCTX_CREATE command params + * + * @gctx_paddr: system physical address of the page donated to firmware by + * the hypervisor to contain the guest context. + */ +struct sev_data_snp_gctx_create { + u64 gctx_paddr; /* In */ +} __packed; + +/** + * struct sev_data_snp_activate - SNP_ACTIVATE command params + * + * @gctx_paddr: system physical address guest context page + * @asid: ASID to bind to the guest + */ +struct sev_data_snp_activate { + u64 gctx_paddr; /* In */ + u32 asid; /* In */ +} __packed; + +/** + * struct sev_data_snp_decommission - SNP_DECOMMISSION command params + * + * @address: system physical address guest context page + */ +struct sev_data_snp_decommission { + u64 gctx_paddr; /* In */ +} __packed; + +/** + * struct sev_data_snp_launch_start - SNP_LAUNCH_START command params + * + * @gctx_addr: system physical address of guest context page + * @policy: guest policy + * @ma_gctx_addr: system physical address of migration agent + * @imi_en: launch flow is launching an IMI for the purpose of + * guest-assisted migration. + * @ma_en: the guest is associated with a migration agent + */ +struct sev_data_snp_launch_start { + u64 gctx_paddr; /* In */ + u64 policy; /* In */ + u64 ma_gctx_paddr; /* In */ + u32 ma_en:1; /* In */ + u32 imi_en:1; /* In */ + u32 rsvd:30; + u8 gosvw[16]; /* In */ +} __packed; + +/* SNP support page type */ +enum { + SNP_PAGE_TYPE_NORMAL = 0x1, + SNP_PAGE_TYPE_VMSA = 0x2, + SNP_PAGE_TYPE_ZERO = 0x3, + SNP_PAGE_TYPE_UNMEASURED = 0x4, + SNP_PAGE_TYPE_SECRET = 0x5, + SNP_PAGE_TYPE_CPUID = 0x6, + + SNP_PAGE_TYPE_MAX +}; + +/** + * struct sev_data_snp_launch_update - SNP_LAUNCH_UPDATE command params + * + * @gctx_addr: system physical address of guest context page + * @imi_page: indicates that this page is part of the IMI of the guest + * @page_type: encoded page type + * @page_size: page size 0 indicates 4K and 1 indicates 2MB page + * @address: system physical address of destination page to encrypt + * @vmpl3_perms: VMPL permission mask for VMPL3 + * @vmpl2_perms: VMPL permission mask for VMPL2 + * @vmpl1_perms: VMPL permission mask for VMPL1 + */ +struct sev_data_snp_launch_update { + u64 gctx_paddr; /* In */ + u32 page_size:1; /* In */ + u32 page_type:3; /* In */ + u32 imi_page:1; /* In */ + u32 rsvd:27; + u32 rsvd2; + u64 address; /* In */ + u32 rsvd3:8; + u32 vmpl3_perms:8; /* In */ + u32 vmpl2_perms:8; /* In */ + u32 vmpl1_perms:8; /* In */ + u32 rsvd4; +} __packed; + +/** + * struct sev_data_snp_launch_finish - SNP_LAUNCH_FINISH command params + * + * @gctx_addr: system pphysical address of guest context page + */ +struct sev_data_snp_launch_finish { + u64 gctx_paddr; + u64 id_block_paddr; + u64 id_auth_paddr; + u8 id_block_en:1; + u8 auth_key_en:1; + u64 rsvd:62; + u8 host_data[32]; +} __packed; + +/** + * struct sev_data_snp_guest_status - SNP_GUEST_STATUS command params + * + * @gctx_paddr: system physical address of guest context page + * @address: system physical address of guest status page + */ +struct sev_data_snp_guest_status { + u64 gctx_paddr; + u64 address; +} __packed; + +/** + * struct sev_data_snp_page_reclaim - SNP_PAGE_RECLAIM command params + * + * @paddr: system physical address of page to be claimed. The BIT0 indicate + * the page size. 0h indicates 4 kB and 1h indicates 2 MB page. + */ +struct sev_data_snp_page_reclaim { + u64 paddr; +} __packed; + +/** + * struct sev_data_snp_page_unsmash - SNP_PAGE_UNMASH command params + * + * @paddr: system physical address of page to be unmashed. The BIT0 indicate + * the page size. 0h indicates 4 kB and 1h indicates 2 MB page. + */ +struct sev_data_snp_page_unsmash { + u64 paddr; +} __packed; + +/** + * struct sev_data_dbg - DBG_ENCRYPT/DBG_DECRYPT command parameters + * + * @handle: handle of the VM to perform debug operation + * @src_addr: source address of data to operate on + * @dst_addr: destination address of data to operate on + * @len: len of data to operate on + */ +struct sev_data_snp_dbg { + u64 gctx_paddr; /* In */ + u64 src_addr; /* In */ + u64 dst_addr; /* In */ + u32 len; /* In */ +} __packed; + +/** + * struct sev_snp_guest_request - SNP_GUEST_REQUEST command params + * + * @gctx_paddr: system physical address of guest context page + * @req_paddr: system physical address of request page + * @res_paddr: system physical address of response page + */ +struct sev_data_snp_guest_request { + u64 gctx_paddr; /* In */ + u64 req_paddr; /* In */ + u64 res_paddr; /* In */ +} __packed; + +/** + * struuct sev_data_snp_init - SNP_INIT_EX structure + * + * @init_rmp: indicate that the RMP should be initialized. + */ +struct sev_data_snp_init_ex { + u32 init_rmp:1; + u32 rsvd:31; + u8 rsvd1[60]; +} __packed; + #ifdef CONFIG_CRYPTO_DEV_SP_PSP /** diff --git a/include/uapi/linux/psp-sev.h b/include/uapi/linux/psp-sev.h index 91b4c63d5cbf..f6d02d4dd014 100644 --- a/include/uapi/linux/psp-sev.h +++ b/include/uapi/linux/psp-sev.h @@ -28,6 +28,8 @@ enum { SEV_PEK_CERT_IMPORT, SEV_GET_ID, /* This command is deprecated, use SEV_GET_ID2 */ SEV_GET_ID2, + SNP_PLATFORM_STATUS, + SNP_CONFIG, SEV_MAX, }; @@ -61,6 +63,13 @@ typedef enum { SEV_RET_INVALID_PARAM, SEV_RET_RESOURCE_LIMIT, SEV_RET_SECURE_DATA_INVALID, + SEV_RET_INVALID_PAGE_SIZE, + SEV_RET_INVALID_PAGE_STATE, + SEV_RET_INVALID_MDATA_ENTRY, + SEV_RET_INVALID_PAGE_OWNER, + SEV_RET_INVALID_PAGE_AEAD_OFLOW, + SEV_RET_RMP_INIT_REQUIRED, + SEV_RET_MAX, } sev_ret_code; @@ -147,6 +156,41 @@ struct sev_user_data_get_id2 { __u32 length; /* In/Out */ } __packed; +/** + * struct sev_data_snp_platform_status - Platform status + * + * @major: API major version + * @minor: API minor version + * @state: current platform state + * @build: firmware build id for the API version + * @guest_count: the number of guest currently managed by the firmware + * @tcb_version: current TCB version + */ +struct sev_user_snp_status { + __u8 api_major; /* Out */ + __u8 api_minor; /* Out */ + __u8 state; /* Out */ + __u8 rsvd; + __u32 build_id; /* Out */ + __u32 rsvd1; + __u32 guest_count; /* Out */ + __u64 tcb_version; /* Out */ + __u64 rsvd2; +} __packed; + +/** + * struct sev_data_snp_config - system wide configuration value for SNP. + * + * @reported_tcb: The TCB version to report in the guest attestation report. + * @mask_chip_id: Indicates that the CHID_ID field in the attestation report + * will always be zero. + */ +struct sev_data_snp_config { + __u64 reported_tcb; /* In */ + __u32 mask_chip_id; /* In */ + __u8 rsvd[52]; +} __packed; + /** * struct sev_issue_cmd - SEV ioctl parameters * From patchwork Fri Apr 30 12:37:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EE8EC433ED for ; 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Platform initialization is accomplished via the SNP_INIT command. Signed-off-by: Brijesh Singh --- drivers/crypto/ccp/sev-dev.c | 107 ++++++++++++++++++++++++++++++++++- drivers/crypto/ccp/sev-dev.h | 2 + include/linux/psp-sev.h | 16 ++++++ 3 files changed, 123 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/ccp/sev-dev.c b/drivers/crypto/ccp/sev-dev.c index 09d117b99bf5..852bbeac1019 100644 --- a/drivers/crypto/ccp/sev-dev.c +++ b/drivers/crypto/ccp/sev-dev.c @@ -590,6 +590,92 @@ static int sev_update_firmware(struct device *dev) return ret; } +static void snp_set_hsave_pa(void *arg) +{ + wrmsrl(MSR_VM_HSAVE_PA, 0); +} + +static int __sev_snp_init_locked(int *error) +{ + struct psp_device *psp = psp_master; + struct sev_device *sev; + int rc = 0; + + if (!psp || !psp->sev_data) + return -ENODEV; + + sev = psp->sev_data; + + if (sev->snp_inited) + return 0; + + /* SNP_INIT requires the MSR_VM_HSAVE_PA must be set to 0h across all cores. */ + on_each_cpu(snp_set_hsave_pa, NULL, 1); + + /* Prepare for first SEV guest launch after INIT */ + wbinvd_on_all_cpus(); + + /* Issue the SNP_INIT firmware command. */ + rc = __sev_do_cmd_locked(SEV_CMD_SNP_INIT, NULL, error); + if (rc) + return rc; + + sev->snp_inited = true; + dev_dbg(sev->dev, "SEV-SNP firmware initialized\n"); + + return rc; +} + +int sev_snp_init(int *error) +{ + int rc; + + if (!cpu_feature_enabled(X86_FEATURE_SEV_SNP)) + return -ENODEV; + + mutex_lock(&sev_cmd_mutex); + rc = __sev_snp_init_locked(error); + mutex_unlock(&sev_cmd_mutex); + + return rc; +} +EXPORT_SYMBOL_GPL(sev_snp_init); + +static int __sev_snp_shutdown_locked(int *error) +{ + struct sev_device *sev = psp_master->sev_data; + int ret; + + if (!sev->snp_inited) + return 0; + + ret = __sev_do_cmd_locked(SEV_CMD_SNP_SHUTDOWN, NULL, error); + if (ret) + return ret; + + wbinvd_on_all_cpus(); + + ret = __sev_do_cmd_locked(SEV_CMD_SNP_DF_FLUSH, NULL, error); + if (ret) + dev_err(sev->dev, "SEV-SNP firmware DF_FLUSH failed\n"); + + sev->snp_inited = false; + dev_dbg(sev->dev, "SEV-SNP firmware shutdown\n"); + + return ret; +} + +static int sev_snp_shutdown(int *error) +{ + int rc; + + mutex_lock(&sev_cmd_mutex); + rc = __sev_snp_shutdown_locked(NULL); + mutex_unlock(&sev_cmd_mutex); + + return rc; +} + static int sev_ioctl_do_pek_import(struct sev_issue_cmd *argp, bool writable) { struct sev_device *sev = psp_master->sev_data; @@ -1089,6 +1175,21 @@ void sev_pci_init(void) "SEV: TMR allocation failed, SEV-ES support unavailable\n"); } + /* + * If boot CPU supports the SNP, then let first attempt to initialize + * the SNP firmware. + */ + if (cpu_feature_enabled(X86_FEATURE_SEV_SNP)) { + rc = sev_snp_init(&error); + if (rc) { + /* + * If we failed to INIT SNP then don't abort the probe. + * Continue to initialize the legacy SEV firmware. + */ + dev_err(sev->dev, "SEV-SNP: failed to INIT error %#x\n", error); + } + } + /* Initialize the platform */ rc = sev_platform_init(&error); if (rc && (error == SEV_RET_SECURE_DATA_INVALID)) { @@ -1108,8 +1209,8 @@ void sev_pci_init(void) return; } - dev_info(sev->dev, "SEV API:%d.%d build:%d\n", sev->api_major, - sev->api_minor, sev->build); + dev_info(sev->dev, "SEV%s API:%d.%d build:%d\n", sev->snp_inited ? + "-SNP" : "", sev->api_major, sev->api_minor, sev->build); return; @@ -1132,4 +1233,6 @@ void sev_pci_exit(void) get_order(SEV_ES_TMR_SIZE)); sev_es_tmr = NULL; } + + sev_snp_shutdown(NULL); } diff --git a/drivers/crypto/ccp/sev-dev.h b/drivers/crypto/ccp/sev-dev.h index 666c21eb81ab..186ad20cbd24 100644 --- a/drivers/crypto/ccp/sev-dev.h +++ b/drivers/crypto/ccp/sev-dev.h @@ -52,6 +52,8 @@ struct sev_device { u8 build; void *cmd_buf; + + bool snp_inited; }; int sev_dev_init(struct psp_device *psp); diff --git a/include/linux/psp-sev.h b/include/linux/psp-sev.h index c3755099ab55..1b53e8782250 100644 --- a/include/linux/psp-sev.h +++ b/include/linux/psp-sev.h @@ -748,6 +748,20 @@ struct sev_data_snp_init_ex { */ int sev_platform_init(int *error); +/** + * sev_snp_init - perform SEV SNP_INIT command + * + * @error: SEV command return code + * + * Returns: + * 0 if the SEV successfully processed the command + * -%ENODEV if the SEV device is not available + * -%ENOTSUPP if the SEV does not support SEV + * -%ETIMEDOUT if the SEV command timed out + * -%EIO if the SEV returned a non-zero return code + */ +int sev_snp_init(int *error); + /** * sev_platform_status - perform SEV PLATFORM_STATUS command * @@ -855,6 +869,8 @@ sev_platform_status(struct sev_user_data_status *status, int *error) { return -E static inline int sev_platform_init(int *error) { return -ENODEV; } +static inline int sev_snp_init(int *error) { return -ENODEV; } + static inline int sev_guest_deactivate(struct sev_data_deactivate *data, int *error) { return -ENODEV; } From patchwork Fri Apr 30 12:37:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233313 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B606BC433ED for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2832.namprd12.prod.outlook.com (2603:10b6:805:eb::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.24; Fri, 30 Apr 2021 12:39:04 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:04 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 14/37] crypto: ccp: Shutdown SNP firmware on kexec Date: Fri, 30 Apr 2021 07:37:59 -0500 Message-Id: <20210430123822.13825-15-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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If SEV firmware is initialized then shut it down before kexec'ing the new kernel. Signed-off-by: Brijesh Singh --- drivers/crypto/ccp/sev-dev.c | 50 ++++++++++++++++-------------------- drivers/crypto/ccp/sp-pci.c | 12 +++++++++ 2 files changed, 34 insertions(+), 28 deletions(-) diff --git a/drivers/crypto/ccp/sev-dev.c b/drivers/crypto/ccp/sev-dev.c index 852bbeac1019..23ad6e7696df 100644 --- a/drivers/crypto/ccp/sev-dev.c +++ b/drivers/crypto/ccp/sev-dev.c @@ -1109,6 +1109,22 @@ int sev_dev_init(struct psp_device *psp) return ret; } +static void sev_firmware_shutdown(struct sev_device *sev) +{ + sev_platform_shutdown(NULL); + + if (sev_es_tmr) { + /* The TMR area was encrypted, flush it from the cache */ + wbinvd_on_all_cpus(); + + free_pages((unsigned long)sev_es_tmr, + get_order(SEV_ES_TMR_SIZE)); + sev_es_tmr = NULL; + } + + sev_snp_shutdown(NULL); +} + void sev_dev_destroy(struct psp_device *psp) { struct sev_device *sev = psp->sev_data; @@ -1116,6 +1132,8 @@ void sev_dev_destroy(struct psp_device *psp) if (!sev) return; + sev_firmware_shutdown(sev); + if (sev->misc) kref_put(&misc_dev->refcount, sev_exit); @@ -1146,21 +1164,6 @@ void sev_pci_init(void) if (sev_get_api_version()) goto err; - /* - * If platform is not in UNINIT state then firmware upgrade and/or - * platform INIT command will fail. These command require UNINIT state. - * - * In a normal boot we should never run into case where the firmware - * is not in UNINIT state on boot. But in case of kexec boot, a reboot - * may not go through a typical shutdown sequence and may leave the - * firmware in INIT or WORKING state. - */ - - if (sev->state != SEV_STATE_UNINIT) { - sev_platform_shutdown(NULL); - sev->state = SEV_STATE_UNINIT; - } - if (sev_version_greater_or_equal(0, 15) && sev_update_firmware(sev->dev) == 0) sev_get_api_version(); @@ -1220,19 +1223,10 @@ void sev_pci_init(void) void sev_pci_exit(void) { - if (!psp_master->sev_data) - return; - - sev_platform_shutdown(NULL); - - if (sev_es_tmr) { - /* The TMR area was encrypted, flush it from the cache */ - wbinvd_on_all_cpus(); + struct sev_device *sev = psp_master->sev_data; - free_pages((unsigned long)sev_es_tmr, - get_order(SEV_ES_TMR_SIZE)); - sev_es_tmr = NULL; - } + if (!sev) + return; - sev_snp_shutdown(NULL); + sev_firmware_shutdown(sev); } diff --git a/drivers/crypto/ccp/sp-pci.c b/drivers/crypto/ccp/sp-pci.c index f471dbaef1fb..9210bfda91a2 100644 --- a/drivers/crypto/ccp/sp-pci.c +++ b/drivers/crypto/ccp/sp-pci.c @@ -239,6 +239,17 @@ static int sp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) return ret; } +static void sp_pci_shutdown(struct pci_dev *pdev) +{ + struct device *dev = &pdev->dev; + struct sp_device *sp = dev_get_drvdata(dev); + + if (!sp) + return; + + sp_destroy(sp); +} + static void sp_pci_remove(struct pci_dev *pdev) { struct device *dev = &pdev->dev; @@ -368,6 +379,7 @@ static struct pci_driver sp_pci_driver = { .id_table = sp_pci_table, .probe = sp_pci_probe, .remove = sp_pci_remove, + .shutdown = sp_pci_shutdown, .driver.pm = &sp_pci_pm_ops, }; From patchwork Fri Apr 30 12:38:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3268DC43460 for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2832.namprd12.prod.outlook.com (2603:10b6:805:eb::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.24; Fri, 30 Apr 2021 12:39:05 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:05 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 15/37] crypto:ccp: Provide APIs to issue SEV-SNP commands Date: Fri, 30 Apr 2021 07:38:00 -0500 Message-Id: <20210430123822.13825-16-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: 27iyU0brGfo2Odhyd8eXtLv0v43audoTH1urEQmxUdXjVaFkSf6zdxmuD/YRE/bmUs0YkirpgLT9HfhR+T/1kvcIVgZ6d4E0bg9LVVZBPDicZ2y6NAiRmF407+up2WSWuOcO7oqc5JJJaLmofiNAZfA1miEJ47LgQYM052jJQx9oWkxVVDe5NGyhqT3NsKsnE0HByjjm7m9kNL65EwC9XJ0SJlxpOWVrGbi030qPniIRfplT3mzVXalcDrwCwjxKVGJeqIWTuwBCmuMC5kaXQxBmzzUbpayfkjRXJVc9DSAfMhhUAkJnhmoa60j0lKnvLv392DnFmaG3711/eNieFoopQATvtLia0e2xzWss+q1SkGddqkpDLoVRDtlktoSBcs6kIXoe7D4BQ0vjOBxhxJGY4oLNEoLwK5+mn+mgyZ62pPpb2rX0cFL2fKvdJwhELlECOalQoppF2Aun0uwP/iHtVoBi9jT4yaCv2WDU5cUY5/pBo67oSAPBAgkbMw3b7qdQdwMeVtXlyhEqB4cCElA1fZB6TnmvBhr27D+b29s9E+LgpBYIC/OE/s5xVOZ90qG8AgvaKsPNiuYTEuvSzWyKp7NpkHcJzf19vqICpZ+SaIzZY5CpIym77LdUWArz8890DV3mULMKsfF62dGWLdDiV/VV9+VuZNuwNyU8TJ6aE+sCutj4xsmNVZqdin3ZVyQRL655nDR0Zwq4uTZ7t7s0p4sHxZfWAIgDdGM4czHt/2za1dWMq+H09fr/MY4voq5YifOCSTYB58SoQrFusu4ySnHLhph0NNTaWkCZ+AGCeC7LtK3dJnL+1HSyvHSx5dKJYugWewz34JGEnlSSr5ysPdx4mEJnoQ/GySHdGiZ4/CGEXYNsHGk8SybHy/6E7fuoMbbZYtFYPHhP1zKKLiAa1tcwFvfiKjN+CgMOe0F61//g1inLYyyMhYD9nEkKo3SVhIEtJx+wv7w6MA6PbN07qd9ixKEMUF5VivWsqzbCukwb4k5Xxx+JYI9itlkVl0eQtsGmj8b2NqOjeJaCjouliuNtz3gokihPUBHel5ffC8cE7AeHx6mB7Qr4s1uNxunHybvAWDqbh5pHjW6zqxerhUXByzsrhOBZhPRtu9+abVBT1MGSEG1/Ojfa0aDMzfzBtH3ou3mlOGdVqi55SaNmUtSrI5ieExH9zQNZHcpbKsLs/pXLonPvWtB0HmIg+PiVXtEpJk1T99CdYcL6lljy+o7YTISTAxIekyyCsULzXmtbSgg/ty/mCYWoqqo++uzIfyoLNeloy95f2TDNqLlwIlxOp9EH3iGMHOJuoi0ufM75i88dL+QkyTtEObXN X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: d38fa0e3-871d-4dc5-07c8-08d90bd4f08c X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:04.8505 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: rfQwZgh4lb8MgdPAWmnjliKIq/2CwE4zLI29oDH0L/B2GfCD/Y1QvHiNZIy5Mh8wuFksRUGeoZeE4RsjdAzhAw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2832 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Provide the APIs for the hypervisor to manage an SEV-SNP guest. The commands for SEV-SNP is defined in the SEV-SNP firmware specification. Signed-off-by: Brijesh Singh --- drivers/crypto/ccp/sev-dev.c | 24 ++++++++++++ include/linux/psp-sev.h | 74 ++++++++++++++++++++++++++++++++++++ 2 files changed, 98 insertions(+) diff --git a/drivers/crypto/ccp/sev-dev.c b/drivers/crypto/ccp/sev-dev.c index 23ad6e7696df..75ec67ba2b55 100644 --- a/drivers/crypto/ccp/sev-dev.c +++ b/drivers/crypto/ccp/sev-dev.c @@ -1010,6 +1010,30 @@ int sev_guest_df_flush(int *error) } EXPORT_SYMBOL_GPL(sev_guest_df_flush); +int snp_guest_decommission(struct sev_data_snp_decommission *data, int *error) +{ + return sev_do_cmd(SEV_CMD_SNP_DECOMMISSION, data, error); +} +EXPORT_SYMBOL_GPL(snp_guest_decommission); + +int snp_guest_df_flush(int *error) +{ + return sev_do_cmd(SEV_CMD_SNP_DF_FLUSH, NULL, error); +} +EXPORT_SYMBOL_GPL(snp_guest_df_flush); + +int snp_guest_page_reclaim(struct sev_data_snp_page_reclaim *data, int *error) +{ + return sev_do_cmd(SEV_CMD_SNP_PAGE_RECLAIM, data, error); +} +EXPORT_SYMBOL_GPL(snp_guest_page_reclaim); + +int snp_guest_dbg_decrypt(struct sev_data_snp_dbg *data, int *error) +{ + return sev_do_cmd(SEV_CMD_SNP_DBG_DECRYPT, data, error); +} +EXPORT_SYMBOL_GPL(snp_guest_dbg_decrypt); + static void sev_exit(struct kref *ref) { misc_deregister(&misc_dev->misc); diff --git a/include/linux/psp-sev.h b/include/linux/psp-sev.h index 1b53e8782250..63ef766cbd7a 100644 --- a/include/linux/psp-sev.h +++ b/include/linux/psp-sev.h @@ -860,6 +860,65 @@ int sev_guest_df_flush(int *error); */ int sev_guest_decommission(struct sev_data_decommission *data, int *error); +/** + * snp_guest_df_flush - perform SNP DF_FLUSH command + * + * @sev_ret: sev command return code + * + * Returns: + * 0 if the sev successfully processed the command + * -%ENODEV if the sev device is not available + * -%ENOTSUPP if the sev does not support SEV + * -%ETIMEDOUT if the sev command timed out + * -%EIO if the sev returned a non-zero return code + */ +int snp_guest_df_flush(int *error); + +/** + * snp_guest_decommission - perform SNP_DECOMMISSION command + * + * @decommission: sev_data_decommission structure to be processed + * @sev_ret: sev command return code + * + * Returns: + * 0 if the sev successfully processed the command + * -%ENODEV if the sev device is not available + * -%ENOTSUPP if the sev does not support SEV + * -%ETIMEDOUT if the sev command timed out + * -%EIO if the sev returned a non-zero return code + */ +int snp_guest_decommission(struct sev_data_snp_decommission *data, int *error); + +/** + * snp_guest_page_reclaim - perform SNP_PAGE_RECLAIM command + * + * @decommission: sev_snp_page_reclaim structure to be processed + * @sev_ret: sev command return code + * + * Returns: + * 0 if the sev successfully processed the command + * -%ENODEV if the sev device is not available + * -%ENOTSUPP if the sev does not support SEV + * -%ETIMEDOUT if the sev command timed out + * -%EIO if the sev returned a non-zero return code + */ +int snp_guest_page_reclaim(struct sev_data_snp_page_reclaim *data, int *error); + +/** + * snp_guest_dbg_decrypt - perform SEV SNP_DBG_DECRYPT command + * + * @sev_ret: sev command return code + * + * Returns: + * 0 if the sev successfully processed the command + * -%ENODEV if the sev device is not available + * -%ENOTSUPP if the sev does not support SEV + * -%ETIMEDOUT if the sev command timed out + * -%EIO if the sev returned a non-zero return code + */ +int snp_guest_dbg_decrypt(struct sev_data_snp_dbg *data, int *error); + + void *psp_copy_user_blob(u64 uaddr, u32 len); #else /* !CONFIG_CRYPTO_DEV_SP_PSP */ @@ -887,6 +946,21 @@ sev_issue_cmd_external_user(struct file *filep, unsigned int id, void *data, int static inline void *psp_copy_user_blob(u64 __user uaddr, u32 len) { return ERR_PTR(-EINVAL); } +static inline int +snp_guest_decommission(struct sev_data_snp_decommission *data, int *error) { return -ENODEV; } + +static inline int snp_guest_df_flush(int *error) { return -ENODEV; } + +static inline int snp_guest_page_reclaim(struct sev_data_snp_page_reclaim *data, int *error) +{ + return -ENODEV; +} + +static inline int snp_guest_dbg_decrypt(struct sev_data_snp_dbg *data, int *error) +{ + return -ENODEV; +} + #endif /* CONFIG_CRYPTO_DEV_SP_PSP */ #endif /* __PSP_SEV_H__ */ From patchwork Fri Apr 30 12:38:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233315 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3E7CC433ED for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2832.namprd12.prod.outlook.com (2603:10b6:805:eb::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.24; Fri, 30 Apr 2021 12:39:05 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:05 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 16/37] crypto: ccp: Handle the legacy TMR allocation when SNP is enabled Date: Fri, 30 Apr 2021 07:38:01 -0500 Message-Id: <20210430123822.13825-17-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: JC9Ap7mTfh/tlg4tgM/O+wFShCYhIYWi0taSkQBkedQxoQaunlsTLDDuAgHGfJGyaQXdOS3myIR3lvuzyY1jcGRoIzuihBy5/xygLR7xsvD1hZbeeWTbl0+FdmL5lQuRCC3xpv8keeWKlNBkyUPh8vc5zxrE3FfvXoXv927PD7NpaD8/B8p2zMul9baBbvZt4zKPOxqCqSuujAER6u7R+kaaR1FaqUo9fWPrFvCNx1kcLQTZL7RGr/wMbEB+LsaZboNaLeHFwhf2z28Wl0vuoG3PaMpEQCf9N4bZTmlO8oSseZGvBrgY70JQI1LZamJSNMbDd4+jElsX350CsuGenoi3Q4dze4obhe0W72KUSRlb37GN9uSrb+IlHL+RL1c/u9OkGf9iKA/F46fQDYDlkHB0GAcV0tA1pZZK8y5lGdk9/DJs8Xwc/0q7WenU6Cl87bFg9Q+9W1XTI9iTa03tVwgBRIVfeIYGvIq5KzFwmgYd2EC+f+m2/uwnoeViOuBRLjMkQtT1FEdOsDX7l8YmheYJ9Q5CIj+TQqYXg9t7VqAZ5N9BKvZdfwp2doWNzVUSIA3ivn1BnyBQqZE8k8pI5TWeT4X46wtaOL/MGw24fLigrE8xs+tJjYTYNJSJm9X6M2IdMWyKJbdtNxv5pK+5lQeCCl8ktilIpyAb00Y7m/GtfiYO3yJUpejiF0aNBS9FSny19/cbUMkZmXGANGnFU/5KJq5XXEwOg+h8fivg3qLdKizund0b8nFpPujN94+8FHiGq/yYoibLxJGHRUSrinVD3O3KSSPT2zRWoTVdSOY7M2UTziHfLrTQsVYF7duSCG1iQryViI9lqVqsBpgvHlCsQm7G0bH2S3BPx7UCj5pZge3/bR2ddlfDNdr3l99DncKF81F/0uTKbC9QKczyY06ypfRwLAA4JA08A7FPIvwkD7tG/v15muePs/hIBLNeAG/+4A2DWHSQMssf+s4vHhBJBu0ntgwjNCXODjhIW1HmpkCPDVGxfEyv7+rPm3G7KytE2EDjJrc4qSKn7Vutbcm9sMn1YD5hSvZJDnwrqGt2BZjREEtrQUo1eWOzxKBArmJr6pNC+iHLMlYrL/xk6lq4eXqhMJ0afzx8kJgkELe8iGCxB+g2N0Sii5wyjbbJrp63xpyVu1U+Rc2DO9HU21dBJdJWFwpGT8UNA5hButppfoBLU6hrLFVd3m4ADU5vLHuOCy89XLDb5nclmOuneg+axEs3pAZPKdyHgASkIhxheM6myuODbuOvOGsFHPjwGi5ABj3JzHxlQsgJObSIMeQRUJ7YKF4Ijacys2AYFShhmNPso+4UNOjzrcey6GI1 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 10311aee-1f60-4ec8-85e4-08d90bd4f102 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:05.6171 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: FuYdWFZsgbfPhLD8rw0zIyVB9/BuN3qSQ5meFYayoyRFfBkiWcDVqk1SFsRIsCEKlSR0Qjri8vv6aZYz09Oiyw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2832 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The behavior and requirement for the SEV-legacy command is altered when the SNP firmware is in the INIT state. See SEV-SNP firmware specification for more details. When SNP is INIT state, all the SEV-legacy commands that cause the firmware to write memory must be in the firmware state. The TMR memory is allocated by the host but updated by the firmware, so, it must be in the firmware state. Additionally, the TMR memory must be a 2MB aligned instead of the 1MB, and the TMR length need to be 2MB instead of 1MB. The helper __snp_{alloc,free}_firmware_pages() can be used for allocating and freeing the memory used by the firmware. While at it, provide API that can be used by others to allocate a page that can be used by the firmware. The immediate user for this API will be the KVM driver. The KVM driver to need to allocate a firmware context page during the guest creation. The context page need to be updated by the firmware. See the SEV-SNP specification for further details. Signed-off-by: Brijesh Singh --- drivers/crypto/ccp/sev-dev.c | 130 +++++++++++++++++++++++++++++++---- include/linux/psp-sev.h | 11 +++ 2 files changed, 128 insertions(+), 13 deletions(-) diff --git a/drivers/crypto/ccp/sev-dev.c b/drivers/crypto/ccp/sev-dev.c index 75ec67ba2b55..fe104d50d83d 100644 --- a/drivers/crypto/ccp/sev-dev.c +++ b/drivers/crypto/ccp/sev-dev.c @@ -53,6 +53,14 @@ static int psp_timeout; #define SEV_ES_TMR_SIZE (1024 * 1024) static void *sev_es_tmr; +/* When SEV-SNP is enabled the TMR need to be 2MB aligned and 2MB size. */ +#define SEV_SNP_ES_TMR_SIZE (2 * 1024 * 1024) + +static size_t sev_es_tmr_size = SEV_ES_TMR_SIZE; + +static int __sev_do_cmd_locked(int cmd, void *data, int *psp_ret); +static int sev_do_cmd(int cmd, void *data, int *psp_ret); + static inline bool sev_version_greater_or_equal(u8 maj, u8 min) { struct sev_device *sev = psp_master->sev_data; @@ -150,6 +158,100 @@ static int sev_cmd_buffer_len(int cmd) return 0; } +static int snp_reclaim_page(struct page *page, bool locked) +{ + struct sev_data_snp_page_reclaim data = {}; + int ret, err; + + data.paddr = page_to_pfn(page) << PAGE_SHIFT; + + if (locked) + ret = __sev_do_cmd_locked(SEV_CMD_SNP_PAGE_RECLAIM, &data, &err); + else + ret = sev_do_cmd(SEV_CMD_SNP_PAGE_RECLAIM, &data, &err); + + return ret; +} + +static int snp_set_rmptable_state(unsigned long paddr, int npages, + struct rmpupdate *val, bool locked, bool need_reclaim) +{ + unsigned long pfn = __sme_clr(paddr) >> PAGE_SHIFT; + unsigned long pfn_end = pfn + npages; + int rc; + + while (pfn < pfn_end) { + if (need_reclaim) + if (snp_reclaim_page(pfn_to_page(pfn), locked)) + return -EFAULT; + + rc = rmpupdate(pfn_to_page(pfn), val); + if (rc) + return rc; + + pfn++; + } + + return 0; +} + +static struct page *__snp_alloc_firmware_pages(gfp_t gfp_mask, int order) +{ + struct rmpupdate val = {}; + unsigned long paddr; + struct page *page; + + page = alloc_pages(gfp_mask, order); + if (!page) + return NULL; + + val.assigned = 1; + val.immutable = 1; + paddr = __pa((unsigned long)page_address(page)); + + if (snp_set_rmptable_state(paddr, 1 << order, &val, false, true)) { + __free_pages(page, order); + return NULL; + } + + return page; +} + +void *snp_alloc_firmware_page(gfp_t gfp_mask) +{ + struct page *page; + + page = __snp_alloc_firmware_pages(gfp_mask, 0); + + return page ? page_address(page) : NULL; +} +EXPORT_SYMBOL_GPL(snp_alloc_firmware_page); + +static void __snp_free_firmware_pages(struct page *page, int order) +{ + struct rmpupdate val = {}; + unsigned long paddr; + + if (!page) + return; + + paddr = __pa((unsigned long)page_address(page)); + + if (snp_set_rmptable_state(paddr, 1 << order, &val, false, true)) + return; + + __free_pages(page, order); +} + +void snp_free_firmware_page(void *addr) +{ + if (!addr) + return; + + __snp_free_firmware_pages(virt_to_page(addr), 0); +} +EXPORT_SYMBOL(snp_free_firmware_page); + static int __sev_do_cmd_locked(int cmd, void *data, int *psp_ret) { struct psp_device *psp = psp_master; @@ -272,7 +374,7 @@ static int __sev_platform_init_locked(int *error) data.flags |= SEV_INIT_FLAGS_SEV_ES; data.tmr_address = tmr_pa; - data.tmr_len = SEV_ES_TMR_SIZE; + data.tmr_len = sev_es_tmr_size; } rc = __sev_do_cmd_locked(SEV_CMD_INIT, &data, error); @@ -623,6 +725,8 @@ static int __sev_snp_init_locked(int *error) sev->snp_inited = true; dev_dbg(sev->dev, "SEV-SNP firmware initialized\n"); + sev_es_tmr_size = SEV_SNP_ES_TMR_SIZE; + return rc; } @@ -1141,8 +1245,8 @@ static void sev_firmware_shutdown(struct sev_device *sev) /* The TMR area was encrypted, flush it from the cache */ wbinvd_on_all_cpus(); - free_pages((unsigned long)sev_es_tmr, - get_order(SEV_ES_TMR_SIZE)); + + __snp_free_firmware_pages(virt_to_page(sev_es_tmr), get_order(sev_es_tmr_size)); sev_es_tmr = NULL; } @@ -1192,16 +1296,6 @@ void sev_pci_init(void) sev_update_firmware(sev->dev) == 0) sev_get_api_version(); - /* Obtain the TMR memory area for SEV-ES use */ - tmr_page = alloc_pages(GFP_KERNEL, get_order(SEV_ES_TMR_SIZE)); - if (tmr_page) { - sev_es_tmr = page_address(tmr_page); - } else { - sev_es_tmr = NULL; - dev_warn(sev->dev, - "SEV: TMR allocation failed, SEV-ES support unavailable\n"); - } - /* * If boot CPU supports the SNP, then let first attempt to initialize * the SNP firmware. @@ -1217,6 +1311,16 @@ void sev_pci_init(void) } } + /* Obtain the TMR memory area for SEV-ES use */ + tmr_page = __snp_alloc_firmware_pages(GFP_KERNEL, get_order(sev_es_tmr_size)); + if (tmr_page) { + sev_es_tmr = page_address(tmr_page); + } else { + sev_es_tmr = NULL; + dev_warn(sev->dev, + "SEV: TMR allocation failed, SEV-ES support unavailable\n"); + } + /* Initialize the platform */ rc = sev_platform_init(&error); if (rc && (error == SEV_RET_SECURE_DATA_INVALID)) { diff --git a/include/linux/psp-sev.h b/include/linux/psp-sev.h index 63ef766cbd7a..b72a74f6a4e9 100644 --- a/include/linux/psp-sev.h +++ b/include/linux/psp-sev.h @@ -12,6 +12,8 @@ #ifndef __PSP_SEV_H__ #define __PSP_SEV_H__ +#include + #include #ifdef CONFIG_X86 @@ -920,6 +922,8 @@ int snp_guest_dbg_decrypt(struct sev_data_snp_dbg *data, int *error); void *psp_copy_user_blob(u64 uaddr, u32 len); +void *snp_alloc_firmware_page(gfp_t mask); +void snp_free_firmware_page(void *addr); #else /* !CONFIG_CRYPTO_DEV_SP_PSP */ @@ -961,6 +965,13 @@ static inline int snp_guest_dbg_decrypt(struct sev_data_snp_dbg *data, int *erro return -ENODEV; } +static inline void *snp_alloc_firmware_page(gfp_t mask) +{ + return NULL; +} + +static inline void snp_free_firmware_page(void *addr) { } + #endif /* CONFIG_CRYPTO_DEV_SP_PSP */ #endif /* __PSP_SEV_H__ */ From patchwork Fri Apr 30 12:38:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 725AEC43460 for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2832.namprd12.prod.outlook.com (2603:10b6:805:eb::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.24; Fri, 30 Apr 2021 12:39:06 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:06 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 17/37] crypto: ccp: Handle the legacy SEV command when SNP is enabled Date: Fri, 30 Apr 2021 07:38:02 -0500 Message-Id: <20210430123822.13825-18-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: OSWyrs1AuaObJRA7rIn8Y6sUXvU0g+JaBZfPfTMhmvNGOsrLrWsh/Aef9vrDHKN3hdubb/qmUP7fW8c2zuj9V5tay9UF/PTgl8ib3qQUAVIflPIyywBQ2KVDgAZRx94RkQaFNwn7jhlBW0FvQhYfFKAZd/VsZtiGBdbnki249rJq2rMuxftKcGMfBBYk9THWqZxCwp0o1GAz33aSywWijIz/T8czv1xwIA36Me/tPsOvjP4OI3Nb/caqhj8YXFvoZ7pMRcQHcbobX4BKGawPQ/Vk3xOZq9Vf0LpLuTGvpXPAUSbmfPDdK6FF73zhzXz8xBueSKS1MiEzPe6SA8kR1jHJiXCTmDturUwErW6pxgiWQ0+cNcpGt0jZc8hn3/BnsDA7ejrdM67pLuvFcBZOfcwdp0t3EAlTQXcdGdc6zJAqlIOrXjZymkXobOJDrrWtDqV9jnNGNvDEPmIcqmrypm8iCyx8yizlKI5NdLiM6PWE0uJPJybKE/lsYR8QZ6AAWJmhtKZ4qdN55aZ7+lu5VFY/i0bK9sLUUvSqsjGUq0I3TN3CkiIy1ycriUUAFYgQak68GHfGjmKKoOE4Bk/zxSTyLiGgmoOEGT6HAPCFJJFHPXP7u6aWi6+tFYvTXXCAnRBjUW8Cxg2KX3PxU+mYaOvbIY17YonhOhds79ETEs70073Bm7xMrV6ZAlFlCj7pdIC+WOffqgfsbLaZw8XZSTSsbMwzxGBa4T9o89lSv0iojz+wmAH78NRZWBVYIl7HmH0JVMuK39znz+weKGQXNypheVTGnAWnSCDbMmWtYLL4ftnRYyX7aLckcktdcCI5lyvjtU//n/qmkx3Wfo2JijmnQdpvmd2oV8gDTS/K+4Iu176a+cQXS8tl/vAropBGpDUkUazaK0Wrw2WbnDFlLZSjYTfd3ACmFZzIL8s2zE1A0Ks3zVBjvaFCnQtGvT3mpMge8jHOVjcWkB4SWAm9UG2VsPBr1V9bBiM3RRCHA/Z+4yNzMnogqwqVgKeybNL07mKZ7hL/ZjQz3igDwBH4fwDHD4r+Qq64TDeVp+Xk+/HJKZb6OnxwIBVJhGdh7Skp5se1sa5ZE+uP37c7JeZYuCFMKpPNNR/oDjX41cIPmlu2VofdO1dqDfsPSlGwRBBwrLYL2Eg+nhr/bBRM6HFpZsCPbbOD1YSwj1IH6tPa0VJ1CeQTZigYPCYsmQ4L9qaxdjg5MOm1NGDjFUsVdukpck6DlwuItmIUMa9skTqZvULL+g3JkuG47VFadoU0QPHTckb8fKDFWZLDmNgStN1KqKoeL4K2fYqL6WU7WR5HPFjfjCJzWTHE6qaPMqF+meEz X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2d9a8cd6-ea6a-4b41-3c5c-08d90bd4f17a X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:06.3457 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: eYfEAY4JbpgzgQRc1Wbibs2Ff09nyY6WueXaAaVVTKjsWlcGbK1kY0DsWPpo/MGzeIk5tfYVT9Q2gOCKgiauKQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2832 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The behavior of the SEV-legacy commands is altered when the SNP firmware is in the INIT state. When SNP is in INIT state, all the SEV-legacy commands that cause the firmware to write to memory must be in the firmware state before issuing the command.. A command buffer may contains a system physical address that the firmware may write to. There are two cases that need to be handled: 1) system physical address points to a guest memory 2) system physical address points to a host memory To handle the case #1, map_firmware_writeable() helper simply changes the page state in the RMP table before and after the command is sent to the firmware. For the case #2, the map_firmware_writeable() replaces the host system physical memory with a pre-allocated firmware page, and after the command completes, the unmap_firmware_writeable() copies the content from pre-allocated firmware page to original host system physical. The unmap_firmware_writeable() calls a __sev_do_cmd_locked() to clear the immutable bit from the memory page. To support the nested calling, a separate command buffer is required. Allocate a backup command buffer and keep reference count of it. If a nested call is detected then use the backup cmd_buf to complete the command submission. Signed-off-by: Brijesh Singh --- drivers/crypto/ccp/sev-dev.c | 348 ++++++++++++++++++++++++++++++++++- drivers/crypto/ccp/sev-dev.h | 12 ++ 2 files changed, 350 insertions(+), 10 deletions(-) diff --git a/drivers/crypto/ccp/sev-dev.c b/drivers/crypto/ccp/sev-dev.c index fe104d50d83d..5b3f3f718cfb 100644 --- a/drivers/crypto/ccp/sev-dev.c +++ b/drivers/crypto/ccp/sev-dev.c @@ -252,12 +252,299 @@ void snp_free_firmware_page(void *addr) } EXPORT_SYMBOL(snp_free_firmware_page); +static int alloc_snp_host_map(struct sev_device *sev) +{ + struct page *page; + int i; + + for (i = 0; i < MAX_SNP_HOST_MAP_BUFS; i++) { + struct snp_host_map *map = &sev->snp_host_map[i]; + + memset(map, 0, sizeof(*map)); + + page = __snp_alloc_firmware_pages(GFP_KERNEL_ACCOUNT, + get_order(SEV_FW_BLOB_MAX_SIZE)); + if (!page) + return -ENOMEM; + + map->host = page_address(page); + } + + return 0; +} + +static void free_snp_host_map(struct sev_device *sev) +{ + int i; + + for (i = 0; i < MAX_SNP_HOST_MAP_BUFS; i++) { + struct snp_host_map *map = &sev->snp_host_map[i]; + + if (map->host) { + __snp_free_firmware_pages(virt_to_page(map->host), + get_order(SEV_FW_BLOB_MAX_SIZE)); + memset(map, 0, sizeof(*map)); + } + } +} + +static int map_firmware_writeable(u64 *paddr, u32 len, bool guest, struct snp_host_map *map) +{ + unsigned int npages = PAGE_ALIGN(len) >> PAGE_SHIFT; + int ret; + + map->active = false; + + if (!paddr || !len) + return 0; + + map->paddr = *paddr; + map->len = len; + + /* If paddr points to a guest memory then change the page state to firmwware. */ + if (guest) { + struct rmpupdate val = {}; + + val.immutable = true; + val.assigned = true; + ret = snp_set_rmptable_state(*paddr, npages, &val, true, false); + if (ret) + return ret; + + goto done; + } + + if (unlikely(!map->host)) + return -EINVAL; + + /* Check if the pre-allocated buffer can be used to fullfil the request. */ + if (unlikely(len > SEV_FW_BLOB_MAX_SIZE)) + return -EINVAL; + + /* Set the paddr to use an intermediate firmware buffer */ + *paddr = __psp_pa(map->host); + +done: + map->active = true; + return 0; +} + +static int unmap_firmware_writeable(u64 *paddr, u32 len, bool guest, struct snp_host_map *map) +{ + unsigned int npages = PAGE_ALIGN(len) >> PAGE_SHIFT; + int ret; + + if (!map->active) + return 0; + + /* If paddr points to a guest memory then restore the page state to hypervisor. */ + if (guest) { + struct rmpupdate val = {}; + + ret = snp_set_rmptable_state(*paddr, npages, &val, true, true); + if (ret) + return ret; + + goto done; + } + + /* Copy the response data firmware buffer to the callers buffer. */ + memcpy(__va(__sme_clr(map->paddr)), map->host, min_t(size_t, len, map->len)); + *paddr = map->paddr; + +done: + map->active = false; + return 0; +} + +static bool sev_legacy_cmd_buf_writable(int cmd) +{ + switch (cmd) { + case SEV_CMD_PLATFORM_STATUS: + case SEV_CMD_GUEST_STATUS: + case SEV_CMD_LAUNCH_START: + case SEV_CMD_RECEIVE_START: + case SEV_CMD_LAUNCH_MEASURE: + case SEV_CMD_SEND_START: + case SEV_CMD_SEND_UPDATE_DATA: + case SEV_CMD_SEND_UPDATE_VMSA: + case SEV_CMD_PEK_CSR: + case SEV_CMD_PDH_CERT_EXPORT: + case SEV_CMD_GET_ID: + case SEV_CMD_ATTESTATION_REPORT: + return true; + default: + return false; + } +} + +#define prep_buffer(name, addr, len, guest, map) \ + func(&((typeof(name *))cmd_buf)->addr, ((typeof(name *))cmd_buf)->len, guest, map) + +static int __snp_cmd_buf_copy(int cmd, void *cmd_buf, bool to_fw, int fw_err) +{ + int (*func)(u64 *, u32, bool, struct snp_host_map *); + struct sev_device *sev = psp_master->sev_data; + struct rmpupdate val = {}; + bool from_fw = !to_fw; + int ret; + + /* + * After the command is completed, change the command buffer memory to + * hypervisor state. + * + * The immutable bit is automatically cleared by the firmware, so + * no not need to reclaim the page. + */ + if (from_fw && sev_legacy_cmd_buf_writable(cmd)) { + ret = snp_set_rmptable_state(__pa(cmd_buf), 1, &val, true, false); + if (ret) + return ret; + + /* No need to go further if firmware failed to execute command. */ + if (fw_err) + return 0; + } + + if (to_fw) + func = map_firmware_writeable; + else + func = unmap_firmware_writeable; + + /* + * A command buffer may contains a system physical address. If the address + * points to a host memory then use an intermediate firmware page otherwise + * change the page state in the RMP table. + */ + switch (cmd) { + case SEV_CMD_PDH_CERT_EXPORT: + if (prep_buffer(struct sev_data_pdh_cert_export, pdh_cert_address, + pdh_cert_len, false, &sev->snp_host_map[0])) + goto err; + if (prep_buffer(struct sev_data_pdh_cert_export, cert_chain_address, + cert_chain_len, false, &sev->snp_host_map[1])) + goto err; + break; + case SEV_CMD_GET_ID: + if (prep_buffer(struct sev_data_get_id, address, len, + false, &sev->snp_host_map[0])) + goto err; + break; + case SEV_CMD_PEK_CSR: + if (prep_buffer(struct sev_data_pek_csr, address, len, + false, &sev->snp_host_map[0])) + goto err; + break; + case SEV_CMD_LAUNCH_UPDATE_DATA: + if (prep_buffer(struct sev_data_launch_update_data, address, len, + true, &sev->snp_host_map[0])) + goto err; + break; + case SEV_CMD_LAUNCH_UPDATE_VMSA: + if (prep_buffer(struct sev_data_launch_update_vmsa, address, len, + true, &sev->snp_host_map[0])) + goto err; + break; + case SEV_CMD_LAUNCH_MEASURE: + if (prep_buffer(struct sev_data_launch_measure, address, len, + false, &sev->snp_host_map[0])) + goto err; + break; + case SEV_CMD_LAUNCH_UPDATE_SECRET: + if (prep_buffer(struct sev_data_launch_secret, guest_address, guest_len, + true, &sev->snp_host_map[0])) + goto err; + break; + case SEV_CMD_DBG_DECRYPT: + if (prep_buffer(struct sev_data_dbg, dst_addr, len, false, + &sev->snp_host_map[0])) + goto err; + break; + case SEV_CMD_DBG_ENCRYPT: + if (prep_buffer(struct sev_data_dbg, dst_addr, len, true, + &sev->snp_host_map[0])) + goto err; + break; + case SEV_CMD_ATTESTATION_REPORT: + if (prep_buffer(struct sev_data_attestation_report, address, len, + false, &sev->snp_host_map[0])) + goto err; + break; + case SEV_CMD_SEND_START: + if (prep_buffer(struct sev_data_send_start, session_address, + session_len, false, &sev->snp_host_map[0])) + goto err; + break; + case SEV_CMD_SEND_UPDATE_DATA: + if (prep_buffer(struct sev_data_send_update_data, hdr_address, hdr_len, + false, &sev->snp_host_map[0])) + goto err; + if (prep_buffer(struct sev_data_send_update_data, trans_address, + trans_len, false, &sev->snp_host_map[1])) + goto err; + break; + case SEV_CMD_SEND_UPDATE_VMSA: + if (prep_buffer(struct sev_data_send_update_vmsa, hdr_address, hdr_len, + false, &sev->snp_host_map[0])) + goto err; + if (prep_buffer(struct sev_data_send_update_vmsa, trans_address, + trans_len, false, &sev->snp_host_map[1])) + goto err; + break; + case SEV_CMD_RECEIVE_UPDATE_DATA: + if (prep_buffer(struct sev_data_receive_update_data, guest_address, + guest_len, true, &sev->snp_host_map[0])) + goto err; + break; + case SEV_CMD_RECEIVE_UPDATE_VMSA: + if (prep_buffer(struct sev_data_receive_update_vmsa, guest_address, + guest_len, true, &sev->snp_host_map[0])) + goto err; + break; + default: + break; + } + + /* The command buffer need to be in the firmware state. */ + if (to_fw && sev_legacy_cmd_buf_writable(cmd)) { + val.assigned = true; + val.immutable = true; + ret = snp_set_rmptable_state(__pa(cmd_buf), 1, &val, true, false); + if (ret) + return ret; + } + + return 0; + +err: + return -EINVAL; +} + +static inline bool need_firmware_copy(int cmd) +{ + struct sev_device *sev = psp_master->sev_data; + + /* After SNP is INIT'ed, the behavior of legacy SEV command is changed. */ + return ((cmd < SEV_CMD_SNP_INIT) && sev->snp_inited) ? true : false; +} + +static int snp_aware_copy_to_firmware(int cmd, void *data) +{ + return __snp_cmd_buf_copy(cmd, data, true, 0); +} + +static int snp_aware_copy_from_firmware(int cmd, void *data, int fw_err) +{ + return __snp_cmd_buf_copy(cmd, data, false, fw_err); +} + static int __sev_do_cmd_locked(int cmd, void *data, int *psp_ret) { struct psp_device *psp = psp_master; struct sev_device *sev; unsigned int phys_lsb, phys_msb; unsigned int reg, ret = 0; + void *cmd_buf; int buf_len; if (!psp || !psp->sev_data) @@ -277,12 +564,26 @@ static int __sev_do_cmd_locked(int cmd, void *data, int *psp_ret) * work for some memory, e.g. vmalloc'd addresses, and @data may not be * physically contiguous. */ - if (data) - memcpy(sev->cmd_buf, data, buf_len); + if (data) { + if (unlikely(sev->cmd_buf_active > 2)) + return -EBUSY; + + cmd_buf = sev->cmd_buf_active ? sev->cmd_buf_backup : sev->cmd_buf; + + memcpy(cmd_buf, data, buf_len); + sev->cmd_buf_active++; + + /* + * The behavior of the SEV-legacy commands is altered when the + * SNP firmware is in the INIT state. + */ + if (need_firmware_copy(cmd) && snp_aware_copy_to_firmware(cmd, sev->cmd_buf)) + return -EFAULT; + } /* Get the physical address of the command buffer */ - phys_lsb = data ? lower_32_bits(__psp_pa(sev->cmd_buf)) : 0; - phys_msb = data ? upper_32_bits(__psp_pa(sev->cmd_buf)) : 0; + phys_lsb = data ? lower_32_bits(__psp_pa(cmd_buf)) : 0; + phys_msb = data ? upper_32_bits(__psp_pa(cmd_buf)) : 0; dev_dbg(sev->dev, "sev command id %#x buffer 0x%08x%08x timeout %us\n", cmd, phys_msb, phys_lsb, psp_timeout); @@ -323,15 +624,24 @@ static int __sev_do_cmd_locked(int cmd, void *data, int *psp_ret) ret = -EIO; } - print_hex_dump_debug("(out): ", DUMP_PREFIX_OFFSET, 16, 2, data, - buf_len, false); - /* * Copy potential output from the PSP back to data. Do this even on * failure in case the caller wants to glean something from the error. */ - if (data) - memcpy(data, sev->cmd_buf, buf_len); + if (data) { + /* + * Restore the page state after the command completes. + */ + if (need_firmware_copy(cmd) && + snp_aware_copy_from_firmware(cmd, cmd_buf, ret)) + return -EFAULT; + + memcpy(data, cmd_buf, buf_len); + sev->cmd_buf_active--; + } + + print_hex_dump_debug("(out): ", DUMP_PREFIX_OFFSET, 16, 2, data, + buf_len, false); return ret; } @@ -1195,10 +1505,12 @@ int sev_dev_init(struct psp_device *psp) if (!sev) goto e_err; - sev->cmd_buf = (void *)devm_get_free_pages(dev, GFP_KERNEL, 0); + sev->cmd_buf = (void *)devm_get_free_pages(dev, GFP_KERNEL, 1); if (!sev->cmd_buf) goto e_sev; + sev->cmd_buf_backup = (uint8_t *)sev->cmd_buf + PAGE_SIZE; + psp->sev_data = sev; sev->dev = dev; @@ -1250,6 +1562,12 @@ static void sev_firmware_shutdown(struct sev_device *sev) sev_es_tmr = NULL; } + /* + * The host map need to clear the immutable bit so it must be free'd before the + * SNP firmware shutdown. + */ + free_snp_host_map(sev); + sev_snp_shutdown(NULL); } @@ -1309,6 +1627,14 @@ void sev_pci_init(void) */ dev_err(sev->dev, "SEV-SNP: failed to INIT error %#x\n", error); } + + /* + * Allocate the intermediate buffers used for the legacy command handling. + */ + if (alloc_snp_host_map(sev)) { + dev_notice(sev->dev, "Failed to alloc host map (disabling legacy SEV)\n"); + goto skip_legacy; + } } /* Obtain the TMR memory area for SEV-ES use */ @@ -1340,12 +1666,14 @@ void sev_pci_init(void) return; } +skip_legacy: dev_info(sev->dev, "SEV%s API:%d.%d build:%d\n", sev->snp_inited ? "-SNP" : "", sev->api_major, sev->api_minor, sev->build); return; err: + free_snp_host_map(sev); psp_master->sev_data = NULL; } diff --git a/drivers/crypto/ccp/sev-dev.h b/drivers/crypto/ccp/sev-dev.h index 186ad20cbd24..fe5d7a3ebace 100644 --- a/drivers/crypto/ccp/sev-dev.h +++ b/drivers/crypto/ccp/sev-dev.h @@ -29,11 +29,20 @@ #define SEV_CMDRESP_CMD_SHIFT 16 #define SEV_CMDRESP_IOC BIT(0) +#define MAX_SNP_HOST_MAP_BUFS 2 + struct sev_misc_dev { struct kref refcount; struct miscdevice misc; }; +struct snp_host_map { + u64 paddr; + u32 len; + void *host; + bool active; +}; + struct sev_device { struct device *dev; struct psp_device *psp; @@ -52,8 +61,11 @@ struct sev_device { u8 build; void *cmd_buf; + void *cmd_buf_backup; + int cmd_buf_active; bool snp_inited; + struct snp_host_map snp_host_map[MAX_SNP_HOST_MAP_BUFS]; }; int sev_dev_init(struct psp_device *psp); From patchwork Fri Apr 30 12:38:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233327 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02D3BC433ED for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2832.namprd12.prod.outlook.com (2603:10b6:805:eb::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.24; Fri, 30 Apr 2021 12:39:07 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:07 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 18/37] KVM: SVM: make AVIC backing, VMSA and VMCB memory allocation SNP safe Date: Fri, 30 Apr 2021 07:38:03 -0500 Message-Id: <20210430123822.13825-19-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: Sxqr0lsepIZH1a53CZhnMOMrIOaEXCWeaNvaFkSENw0X/lZZAYy6Vb6tRClV82ajWQdCQQPsY6cXPGqeG+CHtsSq6K5Aqowt6RKSGJeoKspXVpb+tkNWZ+xFpOXJWIqwIo8qiDSHX5/eyYk3wzqUUCfeozIYHzQGRVDbeRKsgrWpwgKX8dFRVSg9X3yLu4bmQkH1AowhTrwFQy3RdMVeg2U6dX0GKk9jXBHNxk64MK5e0UHHYzn6ePBLMToQKSHlZnCtOMvcwQ8B7/6prVh3gxsTsoiWq5IeeNy7oOoTtIBELIpKcLx5UR08c8qOVYcBv0cEOIzI7SRamgnZuKFYO49DBonxwPslx4Mc2QBR06SNrzCt7yXmwtPLEK5mqjLW5vLTkuZCe3uXagiiL47NV6iaeYZpxanHjghQWmViKbMSxuxzw5JGj49nYfZjX4GAf3NikZdkOrQ9AI5RTVllZd9YmhRgUYOPOu6Q2oEEdqMj2OI9e7CbFz/staxv9oHsv+wEqvqnC1bZa9UaKWOGB9B/UN/7PELXNXxX8wFJpW67fxSBjluq5cFibUkgOvi1SvB7O8MmViEiBNxW72at75UqmYYpO+rX2e+mJRVz5XvS0YkAa2OM+6lfZ2WTvN0uFh8iIPUY+78FkTGcqf4ivN6PRAUCzUE0MR4j0p2OWelAexEj7n0RCeVu80QiFdVuPHOgA2GnJDR9SrKleqsf6fx6Vk1d9xukoeUpcTF+5Uiwy5OmQwoDxoKv04VifsWAqFO9BJywJBS07zsl5t3bGMHpHzy7BDn2ACulqI5I0gkeg2yYjKUoHIrBBD82SmNftT47OWkxZbwF3xqGkv07qp1NWTuBOClBKdT6bChEOHQbdkfnvQk2zY3RzgU7g+9Nil8anPF0khm9uhKIY8Lw7q+3p3zPUEbD8zL4wTBPiasV318J3arj0dY0p98y5iw/W281LqYIV7Z9NdYn1n1K9sDRz7oK4HqA127dUnQdIo1kOsUNBEhSgzJv/vCmPGvcvnrCXwy1RGyADiv94DIYjDW+8mP39SnNV9WCk4GR84nyUUZI5PlTrCj2Ik9ye/fdn7DlzUSD42gfhzuubBatEnVN7TrS8gnTw9c+05XyM3DLKpPPO14KuNRc719Az+WzWLPzgy509rcdmLaF6pF91QiScheFx+dA13jubyemH4Ch9dljbGnu9Id3w5nUTbaald8ivFyu3tQ2VV7rlHmBDnRxkCtY3CmM/v9yGdY0UO8pL2cNbRpCCImKYBikAAHMPtsAznyPAg3wA50E8K/wM3/G8plVGC+e7NO8Igv9E1+NhG4af3tV7MELUqSwpvx0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 22f2ca94-b83a-4ee7-27ea-08d90bd4f1e3 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:07.0722 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Od5QoALLHSygoy7ID93fwTjvcFLrBmbQjuQq84TuamcojcFAOTxWqyk/UnQxZjlEBtLkGx1zlOjNOH4akuXoLQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2832 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org When SEV-SNP is globally enabled on a system, the VMRUN instruction performs additional security checks on AVIC backing, VMSA, and VMCB page. On a successful VMRUN, these pages are marked "in-use" by the hardware in the RMP entry, and any attempt to modify the RMP entry for these pages will result in page-fault (RMP violation check). While performing the RMP check, hardware will try to create a 2MB TLB entry for the large page accesses. When it does this, it first reads the RMP for the base of 2MB region and verifies that all this memory is safe. If AVIC backing, VMSA, and VMCB memory happen to be the base of 2MB region, then RMP check will fail because of the "in-use" marking for the base entry of this 2MB region. e.g. 1. A VMCB was allocated on 2MB-aligned address. 2. The VMRUN instruction marks this RMP entry as "in-use". 3. Another process allocated some other page of memory that happened to be within the same 2MB region. 4. That process tried to write its page using physmap. If the physmap entry in step #4 uses a large (1G/2M) page, then the hardware will attempt to create a 2M TLB entry. The hardware will find that the "in-use" bit is set in the RMP entry (because it was a VMCB page) and will cause an RMP violation check. See APM2 section 15.36.12 for more information on VMRUN checks when SEV-SNP is globally active. A generic allocator can return a page which are 2M aligned and will not be safe to be used when SEV-SNP is globally enabled. Add a snp_safe_alloc_page() helper that can be used for allocating the SNP safe memory. The helper allocated 2 pages and splits them into order-1 allocation. It frees one page and keeps one of the page which is not 2M aligned. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/lapic.c | 5 ++++- arch/x86/kvm/svm/sev.c | 27 +++++++++++++++++++++++++++ arch/x86/kvm/svm/svm.c | 16 ++++++++++++++-- arch/x86/kvm/svm/svm.h | 1 + 5 files changed, 47 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index ad22d4839bcc..71e79a1998ad 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1381,6 +1381,7 @@ struct kvm_x86_ops { int (*complete_emulated_msr)(struct kvm_vcpu *vcpu, int err); void (*vcpu_deliver_sipi_vector)(struct kvm_vcpu *vcpu, u8 vector); + void *(*alloc_apic_backing_page)(struct kvm_vcpu *vcpu); }; struct kvm_x86_nested_ops { diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 152591f9243a..897ce6ebdd7c 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2441,7 +2441,10 @@ int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns) vcpu->arch.apic = apic; - apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); + if (kvm_x86_ops.alloc_apic_backing_page) + apic->regs = kvm_x86_ops.alloc_apic_backing_page(vcpu); + else + apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); if (!apic->regs) { printk(KERN_ERR "malloc apic regs error for vcpu %x\n", vcpu->vcpu_id); diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 5f0034e0dacc..b750e435626a 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -2696,3 +2696,30 @@ void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector) break; } } + +struct page *snp_safe_alloc_page(struct kvm_vcpu *vcpu) +{ + unsigned long pfn; + struct page *p; + + if (!cpu_feature_enabled(X86_FEATURE_SEV_SNP)) + return alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); + + p = alloc_pages(GFP_KERNEL_ACCOUNT | __GFP_ZERO, 1); + if (!p) + return NULL; + + /* split the page order */ + split_page(p, 1); + + /* Find a non-2M aligned page */ + pfn = page_to_pfn(p); + if (IS_ALIGNED(__pfn_to_phys(pfn), PMD_SIZE)) { + pfn++; + __free_page(p); + } else { + __free_page(pfn_to_page(pfn + 1)); + } + + return pfn_to_page(pfn); +} diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 392d44a2756d..ede3cf460894 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -1323,7 +1323,7 @@ static int svm_create_vcpu(struct kvm_vcpu *vcpu) svm = to_svm(vcpu); err = -ENOMEM; - vmcb01_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); + vmcb01_page = snp_safe_alloc_page(vcpu); if (!vmcb01_page) goto out; @@ -1332,7 +1332,7 @@ static int svm_create_vcpu(struct kvm_vcpu *vcpu) * SEV-ES guests require a separate VMSA page used to contain * the encrypted register state of the guest. */ - vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); + vmsa_page = snp_safe_alloc_page(vcpu); if (!vmsa_page) goto error_free_vmcb_page; @@ -4480,6 +4480,16 @@ static int svm_vm_init(struct kvm *kvm) return 0; } +static void *svm_alloc_apic_backing_page(struct kvm_vcpu *vcpu) +{ + struct page *page = snp_safe_alloc_page(vcpu); + + if (!page) + return NULL; + + return page_address(page); +} + static struct kvm_x86_ops svm_x86_ops __initdata = { .hardware_unsetup = svm_hardware_teardown, .hardware_enable = svm_hardware_enable, @@ -4605,6 +4615,8 @@ static struct kvm_x86_ops svm_x86_ops __initdata = { .complete_emulated_msr = svm_complete_emulated_msr, .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector, + + .alloc_apic_backing_page = svm_alloc_apic_backing_page, }; static struct kvm_x86_init_ops svm_init_ops __initdata = { diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 053f2505a738..894e828227d9 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -553,6 +553,7 @@ void sev_es_init_vmcb(struct vcpu_svm *svm); void sev_es_create_vcpu(struct vcpu_svm *svm); void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); void sev_es_prepare_guest_switch(struct vcpu_svm *svm, unsigned int cpu); +struct page *snp_safe_alloc_page(struct kvm_vcpu *vcpu); /* vmenter.S */ From patchwork Fri Apr 30 12:38:04 2021 Content-Type: text/plain; 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Fri, 30 Apr 2021 12:39:07 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 19/37] KVM: SVM: Add initial SEV-SNP support Date: Fri, 30 Apr 2021 07:38:04 -0500 Message-Id: <20210430123822.13825-20-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: Xu9GIyKGec+Nl8/wjELYLXnDKd9URnn7SehkDt1fFD8cQg5Hp+eefrKjH3suu4RV8VUiVGWzJMe6r/RJCMCczesnGZX27NH11YI1+JNU0H7MbBwzxBVBVuHUHtNpqj7kYu6YDbFUhIsKu3CykYDnJIlGnVxwN9yKEYLt5FiZ8Apv+JP4Mk8ZtDnsQm/xxhf7c1AJzEROOGiyrl2hlHWXuB1aM/84wN5dFnGmiJUrV55K+EEvP+BuEPesgIH+4ZrE+ZQJLKNkHV9SsV+nSeNqyq56jceCO+te5FLyHnlm+CxJ4fwE+oGUrL35igz/9h7t7Y2JCtqzOWAKEMrmVwA66Y10sg+tF18FUOF1VUWK5IK3t/MR+UtqGAqQeHHCBFte1rOGgV8eHWVlQu95w8Pi4wzCzSJtYCHCCy0BlxI4DQpmdZK325l9SNlmRlzrE78YOgF+Y8Qjgovr7oPRIPrZrd9VfIwdkv5ZNi8eN8RWsP05fUx6474lia6hT9YkiiTi7Yqq4AS4/q15KzOjtWw06pa/jn4NpIdHBScgml4FENy5nNuYhSqhG+ZLBJ3FCJZsM1697KNF7ASxlZsoEW65S0W/WZvXgoH8a3mMWumVjK7juXAAkpEKstwfeZqdjqcDNPxUey8HI/+Qg3bHH04YfOcAeV4CxuxLiVnxUMTXHQxZeSq6wvmCY4/1wkek054ujYhFr0zkuivaT29pbbZs0rIO8q/sgjz/4DrrrNhWAMZmiAvO+uK65z1jKfJ4X/A2pcW/80vOvgpQD7/1w5KqWKvCMp51WOacWZxqLeTPl0NDT4CO+4r7xzcb/IiKM7Dm6evpTaqu9FNhll089zN6msjOwhb+wOI35qIsYmkzUAJyImSjSZu/trBo4v4Cl6fIJ8SooxvacL3HMQmkoOqv1QuJJRZ5GfifTYJyjaNoIce7sNC1Cr5j1FsiJnTcChLUrvkK0im1yiwNuyZRxVZcdusyEJCwDYezU7s965LlG6XS2HrLbHXTgWjEhc8PgOa6+jOyD1M2BO8d/L3g0Ezh6ifSKyfpTH9XOA9HAdEK2YqsbEYaB+XHFYOQN5A09Zi/lk56x+zDwFeR+ElytbswZ410qJuEJdtwEq91lhECgF50GOabym+bxKLXyKRQo5+7KAXmg6N83LHd6Vk15dVAOSi0vWa+l9gnnyWVJ12P2ACeaBT/bVq+53lnotGwljvu9FmKIs1cHKFxR45OZadVhJF/AszA25IZ2TKoIN7KQknUqtdZf2d2otAiXFsS121svIw+gewC46Yc3CUiZePL8T13IbR2shGmYv5pxKOaIOhPJlL6DswPoUtTokOaBGu9 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: adbbbe28-cdb0-43cd-d0e7-08d90bd4f260 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:07.8448 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +bE/7CdhVydKmJ2/A13w3uqWOmPOptP1Sx0vioD6E2xs3qISKlWVj37uE/rKSXdih3GOPDnZegNWcNnGb4D8uA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2832 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The next generation of SEV is called SEV-SNP (Secure Nested Paging). SEV-SNP builds upon existing SEV and SEV-ES functionality while adding new hardware based security protection. SEV-SNP adds strong memory encryption integrity protection to help prevent malicious hypervisor-based attacks such as data replay, memory re-mapping, and more, to create an isolated execution environment. The SNP feature can be enabled in the KVM by passing the sev-snp module parameter. Signed-off-by: Brijesh Singh --- arch/x86/kvm/svm/sev.c | 18 ++++++++++++++++++ arch/x86/kvm/svm/svm.h | 12 ++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index b750e435626a..200d227f9232 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -52,9 +52,14 @@ module_param_named(sev, sev_enabled, bool, 0444); /* enable/disable SEV-ES support */ static bool sev_es_enabled = true; module_param_named(sev_es, sev_es_enabled, bool, 0444); + +/* enable/disable SEV-SNP support */ +static bool sev_snp_enabled = true; +module_param_named(sev_snp, sev_snp_enabled, bool, 0444); #else #define sev_enabled false #define sev_es_enabled false +#define sev_snp_enabled false #endif /* CONFIG_KVM_AMD_SEV */ #define AP_RESET_HOLD_NONE 0 @@ -1826,6 +1831,7 @@ void __init sev_hardware_setup(void) { #ifdef CONFIG_KVM_AMD_SEV unsigned int eax, ebx, ecx, edx, sev_asid_count, sev_es_asid_count; + bool sev_snp_supported = false; bool sev_es_supported = false; bool sev_supported = false; @@ -1889,9 +1895,21 @@ void __init sev_hardware_setup(void) pr_info("SEV-ES supported: %u ASIDs\n", sev_es_asid_count); sev_es_supported = true; + /* SEV-SNP support requested? */ + if (!sev_snp_enabled) + goto out; + + /* Is SEV-SNP enabled? */ + if (!cpu_feature_enabled(X86_FEATURE_SEV_SNP)) + goto out; + + pr_info("SEV-SNP supported: %u ASIDs\n", min_sev_asid - 1); + sev_snp_supported = true; + out: sev_enabled = sev_supported; sev_es_enabled = sev_es_supported; + sev_snp_enabled = sev_snp_supported; #endif } diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 894e828227d9..85a2d5857ffb 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -58,6 +58,7 @@ enum { struct kvm_sev_info { bool active; /* SEV enabled guest */ bool es_active; /* SEV-ES enabled guest */ + bool snp_active; /* SEV-SNP enabled guest */ unsigned int asid; /* ASID used for this guest */ unsigned int handle; /* SEV firmware handle */ int fd; /* SEV device fd */ @@ -232,6 +233,17 @@ static inline bool sev_es_guest(struct kvm *kvm) #endif } +static inline bool sev_snp_guest(struct kvm *kvm) +{ +#ifdef CONFIG_KVM_AMD_SEV + struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; 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dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2832.namprd12.prod.outlook.com (2603:10b6:805:eb::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.24; Fri, 30 Apr 2021 12:39:08 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:08 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 20/37] KVM: SVM: define new SEV_FEATURES field in the VMCB Save State Area Date: Fri, 30 Apr 2021 07:38:05 -0500 Message-Id: <20210430123822.13825-21-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: u+h8JxwtQISEIqQnohVaNXUx6Swe8spI00s5oHnBU730CoFucsOVILL1YXnl8YhUTIN686+AiMYZQ28w5w7gXnfezzlLCKpluQZHOZQ91OYAnizpzUjeEKdJ5BMI+cHcKEX0ifEg5OVBTvsgmvgW2wuW8Uqw31Qy31E3730pRODfqoC7V4jr0up/X7bJOTAFa+T5vjooKYFMToPkIzKTtjEYC4nahnpuxqQAI0fxRYO2KS8Zjc9Gr5TieIClWjmj/Tj+AvfezHW/lBu4Ow1X/q/0MhbYhjdCyRIIfWymQegOgxJorL22inXWB/5/Fr+LZSB7Y7MIEi3VZ5hV0VvJQXWEaARnFRudLpgXYxjeGeYryTdoie5OmS+8wR5eY0jpvuYRj3mnJpGDRETKy4HanTNeDcRcx4EM48Sn6YBVeH9Kv+VryUe9EJZ1Jm7U5rjkQyLBwoYWcGu69GW3cdEA0lREZ9uEDRNXqG0jz2LbSyMF3WgKO3cdXcFTP6sZkKOHztwuNEjYmPBO8LbyLQQAITEa7v5nFfoTmNKvE3mozsGQVoY2UQPnoNB0bAGO5Mh8dVUULGdmArQnpkXxH5sM1o81g63LR70nFVhfLGG5EqotM9pMspNhMl077jkyIgsS7qbz0bsyNJ9cXj5I422Mknnut4zyZqSGURVKTqGjGy8I3YyUmeJvCqVZCmvaT2zE+Alf+g1YXDm/HUp4hAsgtKGcvhDMG2+xDGXxw+9wrmE+qgNeX58/xEUaAZus6CIwB7Ayvmbs0+V80nIBSxKy88jv5dS7VYsCMO7gEzJjP0S844A+uA5qqiArD9UcidK2T7L7t9dlq/UUJQPemtA+7awWYGGhqAmqDEe+zn5kjF0kfO/Svtv7ZVlJylgZCl/zUsWI0dfRtZCmFHoNtxOZF0ckmL7kHTgq10ClF3x2q+ptU9gs1KiAP7pn5CUKcnKI5yTXQUV5XsCXTRec3VUCPmKcNO8aXNnj8+zgTCjLp7CuXCG2fZlT8yL+cuSeEWmyPqVwqVvs0bwRla9P5r30U8+3ZZogPnAXNBqFzYMuT9wxHrnySx9L2x3Q38xIRE/4OPNRHn1KAwZqIqrOKhCFr/Kz/DfKovmJcdM9Zmq3dF5xhW/jYjvWz12IeYpkkhe7CrRiK8kAbcYxAoVbTNXn5UjNpCrZyT6zttIdHcudXHUEf8IBHqGwzzg408W9aj9Zu/KEtMKjGw1W639vX50P/wmAuvck/4I6ipLz8+VyurIsx7eichxnzsQNkIpMB3ZZgHdMwuO7iRXJDtQGY9dsJCmDLHX0SRNUyJKLen/uJPF9exHVCapCLRxhFfR9tUDX X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0f35ffee-1ab1-494f-e7fc-08d90bd4f2c7 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:08.5324 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: cyuDUIBgyQen1jcXFc51cFiMNN0Gex3xvGWApCQygaARxvllRPe2xjAIPdgRhoVC1IMVVdfWoFtfkzi+MvIH2g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2832 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The hypervisor uses the SEV_FEATURES field (offset 3B0h) in the Save State Area to control the SEV-SNP guest features such as SNPActive, vTOM, ReflectVC etc. An SEV-SNP guest can read the SEV_FEATURES fields through the SEV_STATUS MSR. While at it, define the VMPL field and update the dump_vmcb(). See APM2 Table 15-34 and B-4 for more details. --- arch/x86/include/asm/svm.h | 15 +++++++++++++-- arch/x86/kvm/svm/svm.c | 4 ++-- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 772e60efe243..ff614cdcf628 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -212,6 +212,15 @@ struct __attribute__ ((__packed__)) vmcb_control_area { #define SVM_NESTED_CTL_SEV_ENABLE BIT(1) #define SVM_NESTED_CTL_SEV_ES_ENABLE BIT(2) +#define SVM_SEV_FEATURES_SNP_ACTIVE BIT(0) +#define SVM_SEV_FEATURES_VTOM BIT(1) +#define SVM_SEV_FEATURES_REFLECT_VC BIT(2) +#define SVM_SEV_FEATURES_RESTRICTED_INJECTION BIT(3) +#define SVM_SEV_FEATURES_ALTERNATE_INJECTION BIT(4) +#define SVM_SEV_FEATURES_DEBUG_SWAP BIT(5) +#define SVM_SEV_FEATURES_PREVENT_HOST_IBS BIT(6) +#define SVM_SEV_FEATURES_BTB_ISOLATION BIT(7) + struct vmcb_seg { u16 selector; u16 attrib; @@ -230,7 +239,8 @@ struct vmcb_save_area { struct vmcb_seg ldtr; struct vmcb_seg idtr; struct vmcb_seg tr; - u8 reserved_1[43]; + u8 reserved_1[42]; + u8 vmpl; u8 cpl; u8 reserved_2[4]; u64 efer; @@ -295,7 +305,8 @@ struct vmcb_save_area { u64 sw_exit_info_1; u64 sw_exit_info_2; u64 sw_scratch; - u8 reserved_11[56]; + u64 sev_features; + u8 reserved_11[48]; u64 xcr0; u8 valid_bitmap[16]; u64 x87_state_gpa; diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index ede3cf460894..1b9091d750fc 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -3191,8 +3191,8 @@ static void dump_vmcb(struct kvm_vcpu *vcpu) "tr:", save01->tr.selector, save01->tr.attrib, save01->tr.limit, save01->tr.base); - pr_err("cpl: %d efer: %016llx\n", - save->cpl, save->efer); + pr_err("vmpl: %d cpl: %d efer: %016llx\n", + save->vmpl, save->cpl, save->efer); pr_err("%-15s %016llx %-13s %016llx\n", "cr0:", save->cr0, "cr2:", save->cr2); pr_err("%-15s %016llx %-13s %016llx\n", From patchwork Fri Apr 30 12:38:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233341 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD8A0C433ED for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2832.namprd12.prod.outlook.com (2603:10b6:805:eb::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.24; Fri, 30 Apr 2021 12:39:09 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:09 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 21/37] KVM: SVM: Add KVM_SNP_INIT command Date: Fri, 30 Apr 2021 07:38:06 -0500 Message-Id: <20210430123822.13825-22-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: ZdduA1WnReu/9uEHoYrvcBSOo5ndb/NXT2hCl4UJiRQBKUexFyEVKvKrF4RSNEZcYEXCYuohVAJ6cuJpfGdxjygQtXFQdWNFe0TcZkwMChXv5T7KiIMQLWZhTa3Lhfipq5orMo0XkfpWN2oN/pB81s57Fwq6xma1QyrLLJbO79AGKx9h1KjqUeIdUOttk/GuIbAy7tAtk6CrMPF2CxR+pcauzNlYlieY6ng0g57Mj7MkMFCBLLMQcR7nR6TUor1Dl3ei+olvupoMhADDvu3iGv0Y6Wej4Meo3E6JcvfPUjL7vMhRzXFDXzoQ+FZGaQ8SHN/ZTJjVjnZNB6Tr2SXDNXmU/XijkeDs5i9R9mAVUrhw3QzLGAmtQxBVloA7enuiSaNS/iD9Qa8c93yfV7d0wansKOvc9nR5yGyzyLPr/67QRoAeXA3Jzz0Ovz93D5uKNIWuIT6LvSJjwwJwcadO30SLhzSdVEv6nnXvLutSEyiA51D50FH0ipwaVHovTu1quOSzlhVYgfQV9cePsGjhB6aAIEZY0XTZXLkrHfLmSPbn5dn6EjajykXQ7z651lh+vdoGKQvugStlYZHrdb+Ie6q8psM/+vAOlizCIcDnn30Zl4WdK5IiglhRBrQtv92sw6F9k75oi81SStqxTWrE4egaP6c8XUQcXPtsg+NuH6xGb6U5gWYOfDR+j7UBOxyCTpG+M2zpoCvpD64Rhvlgm220/kX5svSpd6W32vjWfFa36aAPIa97SDv7pTutjRil1+1RbxWmcNPp7Sgm/4N5PGVlAEmHR6QhDUKjvHRCasaq5NnYMJA+82Kn9tFDMoDtit8T6Iimxt6Gw+sHtu24ZvUSndgdeHXSRfG9rthGFyTVCkEkpAD7KCQ5HSWO1ILcxTKVmbavFJ0pL+mb683SpzpaVUH9cd9ZpZeGX0OMLEZj35np0LSdWvBCSDsFziOIMKKDUoGV5Yf5l92ITgAFOcmVD7zY6+PfcJgHjLPEVRF4yOGDMq3msPfAQC47eTod8IYu7kHI2AVNCWoiCXPOIpuLt0SVE1XFn/BKl6YX95inLn4n3RY5tn82odT80yqucKwnnQEfX+mxQ3qNYy/2tcFLFQRtkv9BvvTnHgzArVsy9UroutESrVfovQX7p9FlcRA0j6yjBJO7S75AXbf7GXSykDaTAl6QjtBQ1JBMSYfnx0qoc+HTETiTM9lr42NZhdoe6ekpzTgT928n3LPiOeGlFJxxL7Jxu7TwCJ3Nh9uROEzuUiVJSYnlNOhnc1dE+iVxeOHPUjKVzOA3vRpjThDgObvDS8IQ6Um8Qbz5YxI9P7pp6KML7pV/BxQ9cF0l X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4394f92d-f035-4393-84d3-08d90bd4f339 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:09.3010 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: zZaB7RZ+muUJKYD8laMGV1U7+WDwuASa62fMJy6/HhHZT1V6SV9BlmxPQiCngrP9/msG8zcdj228JQDqMNr5Hw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2832 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The KVM_SNP_INIT command is used by the hypervisor to initialize the SEV-SNP platform context. In a typical workflow, this command should be the first command issued. When creating SEV-SNP guest, the VMM must use this command instead of the KVM_SEV_INIT or KVM_SEV_ES_INIT. Signed-off-by: Brijesh Singh --- arch/x86/kvm/svm/sev.c | 18 ++++++++++++++++-- include/uapi/linux/kvm.h | 3 +++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 200d227f9232..ea74dd9e03d3 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -230,8 +230,9 @@ static void sev_unbind_asid(struct kvm *kvm, unsigned int handle) static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp) { + bool es_active = (argp->id == KVM_SEV_ES_INIT || argp->id == KVM_SEV_SNP_INIT); struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; - bool es_active = argp->id == KVM_SEV_ES_INIT; + bool snp_active = argp->id == KVM_SEV_SNP_INIT; int asid, ret; if (kvm->created_vcpus) @@ -242,12 +243,16 @@ static int sev_guest_init(struct kvm *kvm, struct kvm_sev_cmd *argp) return ret; sev->es_active = es_active; + sev->snp_active = snp_active; asid = sev_asid_new(sev); if (asid < 0) goto e_no_asid; sev->asid = asid; - ret = sev_platform_init(&argp->error); + if (snp_active) + ret = sev_snp_init(&argp->error); + else + ret = sev_platform_init(&argp->error); if (ret) goto e_free; @@ -583,6 +588,9 @@ static int sev_es_sync_vmsa(struct vcpu_svm *svm) save->pkru = svm->vcpu.arch.pkru; save->xss = svm->vcpu.arch.ia32_xss; + if (sev_snp_guest(svm->vcpu.kvm)) + save->sev_features |= SVM_SEV_FEATURES_SNP_ACTIVE; + /* * SEV-ES will use a VMSA that is pointed to by the VMCB, not * the traditional VMSA that is part of the VMCB. Copy the @@ -1525,6 +1533,12 @@ int svm_mem_enc_op(struct kvm *kvm, void __user *argp) } switch (sev_cmd.id) { + case KVM_SEV_SNP_INIT: + if (!sev_snp_enabled) { + r = -ENOTTY; + goto out; + } + fallthrough; case KVM_SEV_ES_INIT: if (!sev_es_enabled) { r = -ENOTTY; diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 3fd9a7e9d90c..aaa2d62f09b5 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -1678,6 +1678,9 @@ enum sev_cmd_id { /* Guest Migration Extension */ KVM_SEV_SEND_CANCEL, + /* SNP specific commands */ + KVM_SEV_SNP_INIT, + KVM_SEV_NR_MAX, }; From patchwork Fri Apr 30 12:38:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233361 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29492C43460 for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2832.namprd12.prod.outlook.com (2603:10b6:805:eb::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.24; Fri, 30 Apr 2021 12:39:10 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:10 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 22/37] KVM: SVM: Add KVM_SEV_SNP_LAUNCH_START command Date: Fri, 30 Apr 2021 07:38:07 -0500 Message-Id: <20210430123822.13825-23-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: 3FvzbVgGUBQMt5CjEktBKGgNkrCSX4LbbEDWzxPAqol4TPNvwKRg7EN7YWPXzK4M9v3yUAGd5+Gy0vsIErYoHczd7BhvRNLKb1fj1aewxb+ctBxQ55/wghoAZJiv3spihes4nXZaLxDRNJvGqTShADt3CB6J5wQErcwoqYwkMKttO+EBTTyaXZkdgOlcH0rT0SRMqlBZgnfLRJR11293qsgvASAS8lI66xRSuOT5/yhFNaxFGrObdie/mTPjPcCX1i9fXygYR3Re4yNnxJH1sNnMHT/G6+5op/G/VA38ecdtRcY34JQdy4qaa3muOFYLkBMhLFBrRcowj15e7pOXAZB/0N5y7waMLolcHHFa/CuqpPHj9a9ZiJQ1OEg5tYg95m50v7b+uz58YBpqQ7qrIpiWVUV3jqS7GYQsW5rJ9KPQICEy6RrGyX5B16vpIPkcEDevcVha05ddr5qbIPL9FwKvyx6G86CtRB7Uw+snMzHoXDb+r/h0zVwpRexxD4Cx3Z/zQH0o3iUgR557UbFensFj+g7nhojrMOb53uvIjO2UgJGXPOj28VrMl06r3ZWpSk+YGGoBUSahhiuR1RVCwtrA1271lIHUg4P8UgmSTPo7lOlz4kcUT+FJGx+U4LrgAjgOl+reZ9GAV2yBqImRMZmwXAY+xLKTp9IzHq4fLJ4zVGOFjDzCGKRO7m/LYgdToW3JSh1RUk2KmwvjnGUSV+q3TYpTZe6qMe34XX8v4kE4mx4cFCJH+JTfpXtkFa5VLkjQ4LukN5jXhJv+5BISpzqBgc2iSbf5j2/3DO7JqZynXiZHHTc5ED/P3A0GcWZdVr7UzwYNvYAynV0AzFJiacGekrXxpRyyxNWjkRylrIWvAGDlhitnYYtISz9jFpwdQswAZObWwtNmh6bQYoOJ4XlqTJ0WLl5jXrzK1/VMbDh77Q+QD92lgQOom1Um1GwNz+YkeX8gkxIyaMZUs8l58GOi40ASjpnu6Wzwna+h1S9pr+q78w9CjQ/qREOB8ApKPQpzJJNa1RkPSjtuK+ipypU82OZffU8twjM8rcCeV1H349QG2G8dPAxzEdvMDT352NPliDfHqtTAY4Z+LkdTni2hKzy/Qjs0a4CaFbrfXgl3C+lhf7MEB5SZQVDnXXpeenMC7/PtGKQq0Z9i2P1N4cB9eavE1lq/7ZLy0O/SmuTUqiyInNGCGRJHfx5l/pWthOKwrCLufFWy4PjwmGptjgWlokZWSiW2aVctj8wyYo8iqZPhvg1ZfYdHKIqDGxGPd4TBxeDHBDGl+1PsCyzvGAFT7vTD2hLlCUmCIM5ZU5HY+aPuKNXhTPfCcl1bTn9P X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 66e5f7c0-9d78-4260-ff1d-08d90bd4f3a8 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:09.9806 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2emZaHVrUkTHS5XaJ7onDvA3uVd0EDlhoF7f9Q0H9+WWeAdBtELohsFWVGhL2oladAbwRToYJjzVtnCn5eUjbw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2832 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org KVM_SEV_SNP_LAUNCH_START begins the launch process for an SEV-SNP guest. The command initializes a cryptographic digest context used to construct the measurement of the guest. If the guest is expected to be migrated, the command also binds a migration agent (MA) to the guest. For more information see the SEV-SNP specification. Signed-off-by: Brijesh Singh --- arch/x86/kvm/svm/sev.c | 132 ++++++++++++++++++++++++++++++++++++++- arch/x86/kvm/svm/svm.h | 1 + include/uapi/linux/kvm.h | 9 +++ 3 files changed, 141 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index ea74dd9e03d3..90d70038b607 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -20,6 +20,7 @@ #include #include +#include #include "x86.h" #include "svm.h" @@ -75,6 +76,8 @@ static unsigned long sev_me_mask; static unsigned long *sev_asid_bitmap; static unsigned long *sev_reclaim_asid_bitmap; +static int snp_decommission_context(struct kvm *kvm); + struct enc_region { struct list_head list; unsigned long npages; @@ -1510,6 +1513,100 @@ static int sev_receive_finish(struct kvm *kvm, struct kvm_sev_cmd *argp) return sev_issue_cmd(kvm, SEV_CMD_RECEIVE_FINISH, &data, &argp->error); } +static void *snp_context_create(struct kvm *kvm, struct kvm_sev_cmd *argp) +{ + struct sev_data_snp_gctx_create data = {}; + void *context; + int rc; + + /* Allocate memory for context page */ + context = snp_alloc_firmware_page(GFP_KERNEL_ACCOUNT); + if (!context) + return NULL; + + data.gctx_paddr = __psp_pa(context); + rc = __sev_issue_cmd(argp->sev_fd, SEV_CMD_SNP_GCTX_CREATE, &data, &argp->error); + if (rc) { + snp_free_firmware_page(context); + return NULL; + } + + return context; +} + +static int snp_bind_asid(struct kvm *kvm, int *error) +{ + struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; + struct sev_data_snp_activate data = {}; + int asid = sev_get_asid(kvm); + int ret, retry_count = 0; + + /* Activate ASID on the given context */ + data.gctx_paddr = __psp_pa(sev->snp_context); + data.asid = asid; +again: + ret = sev_issue_cmd(kvm, SEV_CMD_SNP_ACTIVATE, &data, error); + + /* Check if the DF_FLUSH is required, and try again */ + if (ret && (*error == SEV_RET_DFFLUSH_REQUIRED) && (!retry_count)) { + /* Guard DEACTIVATE against WBINVD/DF_FLUSH used in ASID recycling */ + down_read(&sev_deactivate_lock); + wbinvd_on_all_cpus(); + ret = snp_guest_df_flush(error); + up_read(&sev_deactivate_lock); + + if (ret) + return ret; + + /* only one retry */ + retry_count = 1; + + goto again; + } + + return ret; +} + +static int snp_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp) +{ + struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; + struct sev_data_snp_launch_start start = {}; + struct kvm_sev_snp_launch_start params; + int rc; + + if (!sev_snp_guest(kvm)) + return -ENOTTY; + + if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params))) + return -EFAULT; + + /* Initialize the guest context */ + sev->snp_context = snp_context_create(kvm, argp); + if (!sev->snp_context) + return -ENOTTY; + + /* Issue the LAUNCH_START command */ + start.gctx_paddr = __psp_pa(sev->snp_context); + start.policy = params.policy; + memcpy(start.gosvw, params.gosvw, sizeof(params.gosvw)); + rc = __sev_issue_cmd(argp->sev_fd, SEV_CMD_SNP_LAUNCH_START, &start, &argp->error); + if (rc) + goto e_free_context; + + /* Bind ASID to this guest */ + sev->fd = argp->sev_fd; + rc = snp_bind_asid(kvm, &argp->error); + if (rc) + goto e_free_context; + + return 0; + +e_free_context: + snp_decommission_context(kvm); + + return rc; +} + int svm_mem_enc_op(struct kvm *kvm, void __user *argp) { struct kvm_sev_cmd sev_cmd; @@ -1599,6 +1696,9 @@ int svm_mem_enc_op(struct kvm *kvm, void __user *argp) case KVM_SEV_RECEIVE_FINISH: r = sev_receive_finish(kvm, &sev_cmd); break; + case KVM_SEV_SNP_LAUNCH_START: + r = snp_launch_start(kvm, &sev_cmd); + break; default: r = -EINVAL; goto out; @@ -1791,6 +1891,28 @@ int svm_vm_copy_asid_from(struct kvm *kvm, unsigned int source_fd) return ret; } +static int snp_decommission_context(struct kvm *kvm) +{ + struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; + struct sev_data_snp_decommission data = {}; + int ret; + + /* If context is not created then do nothing */ + if (!sev->snp_context) + return 0; + + data.gctx_paddr = __sme_pa(sev->snp_context); + ret = snp_guest_decommission(&data, NULL); + if (ret) + return ret; + + /* free the context page now */ + snp_free_firmware_page(sev->snp_context); + sev->snp_context = NULL; + + return 0; +} + void sev_vm_destroy(struct kvm *kvm) { struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; @@ -1829,7 +1951,15 @@ void sev_vm_destroy(struct kvm *kvm) mutex_unlock(&kvm->lock); - sev_unbind_asid(kvm, sev->handle); + if (sev_snp_guest(kvm)) { + if (snp_decommission_context(kvm)) { + pr_err("Failed to free SNP guest context, leaking asid!\n"); + return; + } + } else { + sev_unbind_asid(kvm, sev->handle); + } + sev_asid_free(sev); } diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 85a2d5857ffb..a870bbb64ce7 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -67,6 +67,7 @@ struct kvm_sev_info { u64 ap_jump_table; /* SEV-ES AP Jump Table address */ struct kvm *enc_context_owner; /* Owner of copied encryption context */ struct misc_cg *misc_cg; /* For misc cgroup accounting */ + void *snp_context; /* SNP guest context page */ }; struct kvm_svm { diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index aaa2d62f09b5..00427707d053 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -1680,6 +1680,7 @@ enum sev_cmd_id { /* SNP specific commands */ KVM_SEV_SNP_INIT, + KVM_SEV_SNP_LAUNCH_START, KVM_SEV_NR_MAX, }; @@ -1777,6 +1778,14 @@ struct kvm_sev_receive_update_data { __u32 trans_len; }; +struct kvm_sev_snp_launch_start { + __u64 policy; + __u64 ma_uaddr; + __u8 ma_en; + __u8 imi_en; + __u8 gosvw[16]; +}; + #define KVM_DEV_ASSIGN_ENABLE_IOMMU (1 << 0) #define KVM_DEV_ASSIGN_PCI_2_3 (1 << 1) #define KVM_DEV_ASSIGN_MASK_INTX (1 << 2) From patchwork Fri Apr 30 12:38:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233359 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 618F0C433ED for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2832.namprd12.prod.outlook.com (2603:10b6:805:eb::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.24; Fri, 30 Apr 2021 12:39:10 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:10 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 23/37] KVM: SVM: Add KVM_SEV_SNP_LAUNCH_UPDATE command Date: Fri, 30 Apr 2021 07:38:08 -0500 Message-Id: <20210430123822.13825-24-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: by1PALNaVqnCItOfCpjVMfI/AeJ8Su60ypM07VIp09uTea7WtQo6VcmbCDWMMnreQkOiTsoOlLAYPgaZgDbEXlPNmoAOeUyHHUFHReJs9T9CoBvjTr5EAE6ZTQCZac/5ojGcjrG7QrV3uSZpq2U3j6mw4FF1p24re6I+xcLn/GgrNeIgWBoNKcDNzc5gJSwea97hXHXulaAZU1Y9JEPRm7wlKP/iCWpbdi++c3DqO5pysuNZbwkh3O1TdcikuTEMpN3Cn2+b6tWMElHXRVYyOJLcVeUtCkID20XGR/5Ip/Pqx48ZBGwFqwGu9VRsqO03vfE1Bg17a04nL2ABSq+dcThAK3tYiD863ihkry8T5DrGDD2tPz+1WXX6+smotw3gm1EdaqRF+YJWnCuhmiwZp9rL0SLejAy7G5+IF0bRTDWg6I05Q/fnkS41VjPOQvciNHv/VvEF3r6xDjVMMpakCY0TCkugcDNEOyjL9iWWptuqUaaCTQJOZFobbcA+P5wRxiRae4FhWfIfbTMsNxB+xnNYzOKgp6yChbucpaRFzFqJHZTvAke0hqSWDmS5k1W/huCw3X4l8uq3JigmqCzm2ECKZ4PjqytoPw7hAAnqmHlzSOIk9BFU9sERqffZgN0GhBBVzkuPWBZ/qTsbFIQdhYZaSCz9KH/emrF1Oc/2Q9cRO5f5sV9EUMJ8ibAESSxlsytVgFF6aIqnva5CQ1TqBXct8ML3rHMumqdjWuN6HCq5dV6txH/jG540gn8Sf6XYZ8oLBSI4Y2Vp1Y3Q+E4t0CZP4RsAdX4LZDF2KjidEAHJjdCLLB/LJuVDc6dGnXiYkWLLQdkl9hUAqZNleKDbTdCcOc+liIc+oCk+kJ/YJbztZLaMH/RQPkpbVfPZTxePDHl7N2rX+9pjwLUszSYs1nvCqTOg8DCkPbd84W/fxN/twP/eZv18N+ZYfJ2yXTrEalIEVkUHEYfamoThqcp6WZLjl3FeSMKZC2aI2Y5ZDM9G/YFCh7lKmkNBcN9X3rZpKg7EZM5mmKiIVa9KMlNeZ3hUqaD8nYWNvUl+9EGNOVM47NmIbnDg8NoIBsLqIUhalvxJasmOTy2e6G7livpN898AXCHwjGLv7rnNFEcRFiqTGlLdEzcCDFCg+TL82jnExOxgpB+LeD9+orTMjPft6/lZ7sCdOlG5G0VzXidVmpUdJoPdK1Nvwfc9VLwl/x3+6j/XvDClqNPS2vRDqkLNvRT9QM54n68JMdbJwJZAplS0foC0B8W1R1Hf2LwNrWzfzThYZudyuRWzFXYu2ieHdIY3UrNUAef1OnyjuhAL6zZwgw34yitm2mJHH0MzWJ8R X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 07ad746d-3541-46e8-0de0-08d90bd4f40b X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:10.6582 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: F6vFigq9ANOxPRjRSmk0heaxQdiTlxS2eDG2GT1yiXbNqlsSuUXwnYYR4nAmc09nBNq+IeXghNNAlxfkARrxPQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2832 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The KVM_SEV_SNP_LAUNCH_UPDATE command can be used to insert data into the guest's memory. The data is encrypted with the cryptographic context created with the KVM_SEV_SNP_LAUNCH_START. In addition to the inserting data, it can insert a two special pages into the guests memory: the secrets page and the CPUID page. For more information see the SEV-SNP specification. Signed-off-by: Brijesh Singh --- arch/x86/kvm/svm/sev.c | 139 +++++++++++++++++++++++++++++++++++++++ include/uapi/linux/kvm.h | 18 +++++ 2 files changed, 157 insertions(+) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 90d70038b607..d97f37df1f3b 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -1607,6 +1608,141 @@ static int snp_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp) return rc; } +static struct kvm_memory_slot *hva_to_memslot(struct kvm *kvm, unsigned long hva) +{ + struct kvm_memslots *slots = kvm_memslots(kvm); + struct kvm_memory_slot *memslot; + + kvm_for_each_memslot(memslot, slots) { + if (hva >= memslot->userspace_addr && + hva < memslot->userspace_addr + (memslot->npages << PAGE_SHIFT)) + return memslot; + } + + return NULL; +} + +static bool hva_to_gpa(struct kvm *kvm, unsigned long hva, gpa_t *gpa) +{ + struct kvm_memory_slot *memslot; + gpa_t gpa_offset; + + memslot = hva_to_memslot(kvm, hva); + if (!memslot) + return false; + + gpa_offset = hva - memslot->userspace_addr; + *gpa = ((memslot->base_gfn << PAGE_SHIFT) + gpa_offset); + + return true; +} + +static int snp_page_reclaim(struct page *page, int rmppage_size) +{ + struct sev_data_snp_page_reclaim data = {}; + struct rmpupdate e = {}; + int rc, err; + + data.paddr = __sme_page_pa(page) | rmppage_size; + rc = snp_guest_page_reclaim(&data, &err); + if (rc) + return rc; + + return rmpupdate(page, &e); +} + +static int snp_launch_update(struct kvm *kvm, struct kvm_sev_cmd *argp) +{ + unsigned long npages, vaddr, vaddr_end, i, next_vaddr; + struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; + struct sev_data_snp_launch_update data = {}; + struct kvm_sev_snp_launch_update params; + int *error = &argp->error; + struct kvm_vcpu *vcpu; + struct page **inpages; + struct rmpupdate e; + int ret; + + if (!sev_snp_guest(kvm)) + return -ENOTTY; + + if (!sev->snp_context) + return -EINVAL; + + if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params))) + return -EFAULT; + + data.gctx_paddr = __psp_pa(sev->snp_context); + + /* Lock the user memory. */ + inpages = sev_pin_memory(kvm, params.uaddr, params.len, &npages, 1); + if (!inpages) + return -ENOMEM; + + vcpu = kvm_get_vcpu(kvm, 0); + vaddr = params.uaddr; + vaddr_end = vaddr + params.len; + + for (i = 0; vaddr < vaddr_end; vaddr = next_vaddr, i++) { + unsigned long psize, pmask; + int level = PG_LEVEL_4K; + gpa_t gpa; + + if (!hva_to_gpa(kvm, vaddr, &gpa)) { + ret = -EINVAL; + goto e_unpin; + } + + psize = page_level_size(level); + pmask = page_level_mask(level); + gpa = gpa & pmask; + + /* Transition the page state to pre-guest */ + memset(&e, 0, sizeof(e)); + e.assigned = 1; + e.gpa = gpa; + e.asid = sev_get_asid(kvm); + e.immutable = true; + e.pagesize = X86_TO_RMP_PG_LEVEL(level); + ret = rmpupdate(inpages[i], &e); + if (ret) { + ret = -EFAULT; + goto e_unpin; + } + + data.address = __sme_page_pa(inpages[i]); + data.page_size = e.pagesize; + data.page_type = params.page_type; + ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_SNP_LAUNCH_UPDATE, &data, error); + if (ret) { + snp_page_reclaim(inpages[i], e.pagesize); + goto e_unpin; + } + + next_vaddr = (vaddr & pmask) + psize; + } + +e_unpin: + /* Content of memory is updated, mark pages dirty */ + memset(&e, 0, sizeof(e)); + for (i = 0; i < npages; i++) { + set_page_dirty_lock(inpages[i]); + mark_page_accessed(inpages[i]); + + /* + * If its an error, then update RMP entry to change page ownership + * to the hypervisor. + */ + if (ret) + rmpupdate(inpages[i], &e); + } + + /* Unlock the user pages */ + sev_unpin_memory(kvm, inpages, npages); + + return ret; +} + int svm_mem_enc_op(struct kvm *kvm, void __user *argp) { struct kvm_sev_cmd sev_cmd; @@ -1699,6 +1835,9 @@ int svm_mem_enc_op(struct kvm *kvm, void __user *argp) case KVM_SEV_SNP_LAUNCH_START: r = snp_launch_start(kvm, &sev_cmd); break; + case KVM_SEV_SNP_LAUNCH_UPDATE: + r = snp_launch_update(kvm, &sev_cmd); + break; default: r = -EINVAL; goto out; diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 00427707d053..dfc4975820d6 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -1681,6 +1681,7 @@ enum sev_cmd_id { /* SNP specific commands */ KVM_SEV_SNP_INIT, KVM_SEV_SNP_LAUNCH_START, + KVM_SEV_SNP_LAUNCH_UPDATE, KVM_SEV_NR_MAX, }; @@ -1786,6 +1787,23 @@ struct kvm_sev_snp_launch_start { __u8 gosvw[16]; }; +#define KVM_SEV_SNP_PAGE_TYPE_NORMAL 0x1 +#define KVM_SEV_SNP_PAGE_TYPE_VMSA 0x2 +#define KVM_SEV_SNP_PAGE_TYPE_ZERO 0x3 +#define KVM_SEV_SNP_PAGE_TYPE_UNMEASURED 0x4 +#define KVM_SEV_SNP_PAGE_TYPE_SECRETS 0x5 +#define KVM_SEV_SNP_PAGE_TYPE_CPUID 0x6 + +struct kvm_sev_snp_launch_update { + __u64 uaddr; + __u32 len; + __u8 imi_page; + __u8 page_type; + __u8 vmpl3_perms; + __u8 vmpl2_perms; + __u8 vmpl1_perms; +}; + #define KVM_DEV_ASSIGN_ENABLE_IOMMU (1 << 0) #define KVM_DEV_ASSIGN_PCI_2_3 (1 << 1) #define KVM_DEV_ASSIGN_MASK_INTX (1 << 2) From patchwork Fri Apr 30 12:38:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233369 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4749C433B4 for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2832.namprd12.prod.outlook.com (2603:10b6:805:eb::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4065.24; Fri, 30 Apr 2021 12:39:11 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:11 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 24/37] KVM: SVM: Reclaim the guest pages when SEV-SNP VM terminates Date: Fri, 30 Apr 2021 07:38:09 -0500 Message-Id: <20210430123822.13825-25-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: O+rijlrRp5EzsANXAilamwWgzwJMqwv540cCck/V5DptxycDzvvD/kN7cSYgFVR36l2t9nQHNhDkbNRZwVY9eWr1VoyfqPuHHewRK6SvBWpYcKJ/zEOUNz6nIlVrCtK6QGdtVOyqW9I46eNuCxIiKuvSuGYCtilfz6r1RqrNJHpv+yujJ5nED5lJPIVZ6vJPCY5BRfs4feVpR34/yuUt6mBbWwfjWHlbu+ilapgCK9Y5rqWIUphNaj8m70pP9aLid16TySowmfBjSjMxi5w5kV0I7kUYx0tom3YmICDrnS+SUPD1KrdhalAle1TS6K6Cu5+HPHaAet4q3ZLlDzB2ngUr+k675OHyGxM8q/YrOSqP35j0zKsur13BkhRuxnvWsEnVYOWboIsxEhNWX9nntpnnaawmOAxmGR24zvFAl16HTd6JxcHTrTa2Y5BuTEk+ANXdac2N8UDZ2iyHSFpyMTs4F2zjEaCA6hTTY//r3IL5DejEvsKabY9dj29blKwUGirGc0Yo7BtTlKkrJRKi0a+N2mi4V14Bdg9yya//8PbibKH9ohfS9J3hohDFPjsoGNhI43CQEQFJjdb5tGKFElEHfjrhD2qpTL0ADnO1zFQ8WkIkkb3mT/6XUoc08i/g/LyOxm/RwVsX7gNLLYjcCLMPVGzX3qnBl1+67C8QvXT35vqufmBwuwq+qPGwCqcQW4yAgBEm8K4aSsECXlXyyrfdir4yE9xlrBCqV3eXA8wkZHGe7S1YP0x1ILhO/fkfk7H2OdSa8nyP7C8Ewigp2js52OerU3kBrzT8VCs2+UsbYrphyps4G5X20xbTC8zB2pENy4srH7QS+myht9cVomKBwl5jmIdDfnxWJGC3zmZ1swQ2jCVSQn+IMBVXchjiG8Pw0RjBr16VFuCYnNagtSDXkDDviCIJlQknWl21IyKp9mkeDPhP7TO6HXF6TdNbjMSPditzvTQCoa/wQRh7j9W7W55TAKKaGeCGx/n0dSouWB3XZ8tUp6JMMTrZ5l5sBNalWJDXWvztVDh67gtoakgI0g7AIXE0QBBj+K3ef+QBWgzQCC+hr4mO3G14LEGR/CdaSIYIEMLPAJFEo4E9LLpwYCpKMhgnV9iYeawWFR2T/BpflJ7YmJMq5w86MPfMM2NGkKYjyucfhIozr3kZyL7ScocOTv37pCk+tZoPvE8hGwuFTsXtg8WzZDi6KCF2iok6zpqoYZSd/eb6NDlVMn68lUPX1oNUzJvBX+pn+28GkozWGMFcBenXdZSMuCoDodlkCVfYCbs6E9S4dol8YfA2r5Ax04aCBQssiA8UFp8ZmRPlyTYbjBUyd9yeQkHv X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8ccd6fb5-7afa-4d9a-28c7-08d90bd4f479 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:11.3598 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: glGq7LFJ7jyRG/3t4yHpomwtvMPnKt1AGRz4KEf0895/0kIhCOVl5FUroL7EFhu0Bq4bcScAToWpayDVUGNSkA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2832 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The guest pages of the SEV-SNP VM maybe added as a private page in the RMP entry (assigned bit is set). The guest private pages must be transitioned to the hypervisor state before its freed. Signed-off-by: Brijesh Singh --- arch/x86/kvm/svm/sev.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index d97f37df1f3b..4ce91c2583a3 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -1920,6 +1920,45 @@ find_enc_region(struct kvm *kvm, struct kvm_enc_region *range) static void __unregister_enc_region_locked(struct kvm *kvm, struct enc_region *region) { + struct rmpupdate val = {}; + unsigned long i, pfn; + struct rmpentry *e; + int level, rc; + + /* + * The guest memory pages are assigned in the RMP table. Unassign it + * before releasing the memory. + */ + if (sev_snp_guest(kvm)) { + for (i = 0; i < region->npages; i++) { + pfn = page_to_pfn(region->pages[i]); + + if (need_resched()) + schedule(); + + e = snp_lookup_page_in_rmptable(region->pages[i], &level); + if (unlikely(!e)) + continue; + + /* If its not a guest assigned page then skip it. */ + if (!rmpentry_assigned(e)) + continue; + + /* Is the page part of a 2MB RMP entry? */ + if (level == PG_LEVEL_2M) { + val.pagesize = RMP_PG_SIZE_2M; + pfn &= ~(KVM_PAGES_PER_HPAGE(PG_LEVEL_2M) - 1); + } else { + val.pagesize = RMP_PG_SIZE_4K; + } + + /* Transition the page to hypervisor owned. */ + rc = rmpupdate(pfn_to_page(pfn), &val); + if (rc) + pr_err("Failed to release pfn 0x%lx ret=%d\n", pfn, rc); + } + } + sev_unpin_memory(kvm, region->pages, region->npages); list_del(®ion->list); kfree(region); From patchwork Fri Apr 30 12:38:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233303 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB75FC43460 for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2688.namprd12.prod.outlook.com (2603:10b6:805:6f::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4087.35; Fri, 30 Apr 2021 12:39:12 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:12 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 25/37] KVM: SVM: Add KVM_SEV_SNP_LAUNCH_FINISH command Date: Fri, 30 Apr 2021 07:38:10 -0500 Message-Id: <20210430123822.13825-26-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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While finalizing the launch flow, it also issues the LAUNCH_UPDATE command to encrypt the VMSA pages. Signed-off-by: Brijesh Singh --- arch/x86/kvm/svm/sev.c | 125 +++++++++++++++++++++++++++++++++++++++ include/uapi/linux/kvm.h | 13 ++++ 2 files changed, 138 insertions(+) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 4ce91c2583a3..7da24b3600c4 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -1743,6 +1743,111 @@ static int snp_launch_update(struct kvm *kvm, struct kvm_sev_cmd *argp) return ret; } +static int snp_launch_update_vmsa(struct kvm *kvm, struct kvm_sev_cmd *argp) +{ + struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; + struct sev_data_snp_launch_update data = {}; + int i, ret; + + data.gctx_paddr = __psp_pa(sev->snp_context); + data.page_type = SNP_PAGE_TYPE_VMSA; + + for (i = 0; i < kvm->created_vcpus; i++) { + struct vcpu_svm *svm = to_svm(kvm->vcpus[i]); + struct rmpupdate e = {}; + + /* Perform some pre-encryption checks against the VMSA */ + ret = sev_es_sync_vmsa(svm); + if (ret) + return ret; + + /* Transition the VMSA page to a firmware state. */ + e.assigned = 1; + e.immutable = 1; + e.asid = sev->asid; + e.gpa = -1; + e.pagesize = RMP_PG_SIZE_4K; + ret = rmpupdate(virt_to_page(svm->vmsa), &e); + if (ret) + return ret; + + /* Issue the SNP command to encrypt the VMSA */ + data.address = __sme_pa(svm->vmsa); + ret = __sev_issue_cmd(argp->sev_fd, SEV_CMD_SNP_LAUNCH_UPDATE, + &data, &argp->error); + if (ret) { + snp_page_reclaim(virt_to_page(svm->vmsa), RMP_PG_SIZE_4K); + return ret; + } + + svm->vcpu.arch.guest_state_protected = true; + } + + return 0; +} + +static int snp_launch_finish(struct kvm *kvm, struct kvm_sev_cmd *argp) +{ + struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; + struct sev_data_snp_launch_finish *data; + void *id_block = NULL, *id_auth = NULL; + struct kvm_sev_snp_launch_finish params; + int ret; + + if (!sev_snp_guest(kvm)) + return -ENOTTY; + + if (!sev->snp_context) + return -EINVAL; + + if (copy_from_user(¶ms, (void __user *)(uintptr_t)argp->data, sizeof(params))) + return -EFAULT; + + /* Measure all vCPUs using LAUNCH_UPDATE before we finalize the launch flow. */ + ret = snp_launch_update_vmsa(kvm, argp); + if (ret) + return ret; + + data = kzalloc(sizeof(*data), GFP_KERNEL_ACCOUNT); + if (!data) + return -ENOMEM; + + if (params.id_block_en) { + id_block = psp_copy_user_blob(params.id_block_uaddr, KVM_SEV_SNP_ID_BLOCK_SIZE); + if (IS_ERR(id_block)) { + ret = PTR_ERR(id_block); + goto e_free; + } + + data->id_block_en = 1; + data->id_block_paddr = __sme_pa(id_block); + } + + if (params.auth_key_en) { + id_auth = psp_copy_user_blob(params.id_auth_uaddr, KVM_SEV_SNP_ID_AUTH_SIZE); + if (IS_ERR(id_auth)) { + ret = PTR_ERR(id_auth); + goto e_free_id_block; + } + + data->auth_key_en = 1; + data->id_auth_paddr = __sme_pa(id_auth); + } + + data->gctx_paddr = __psp_pa(sev->snp_context); + ret = sev_issue_cmd(kvm, SEV_CMD_SNP_LAUNCH_FINISH, data, &argp->error); + + kfree(id_auth); + +e_free_id_block: + kfree(id_block); + +e_free: + kfree(data); + + return ret; +} + int svm_mem_enc_op(struct kvm *kvm, void __user *argp) { struct kvm_sev_cmd sev_cmd; @@ -1838,6 +1943,9 @@ int svm_mem_enc_op(struct kvm *kvm, void __user *argp) case KVM_SEV_SNP_LAUNCH_UPDATE: r = snp_launch_update(kvm, &sev_cmd); break; + case KVM_SEV_SNP_LAUNCH_FINISH: + r = snp_launch_finish(kvm, &sev_cmd); + break; default: r = -EINVAL; goto out; @@ -2325,8 +2433,25 @@ void sev_free_vcpu(struct kvm_vcpu *vcpu) if (vcpu->arch.guest_state_protected) sev_flush_guest_memory(svm, svm->vmsa, PAGE_SIZE); + + /* + * If its an SNP guest, then VMSA was added in the RMP entry as a guest owned page. + * Transition the page to hyperivosr state before releasing it back to the system. + */ + if (sev_snp_guest(vcpu->kvm)) { + struct rmpupdate e = {}; + int rc; + + rc = rmpupdate(virt_to_page(svm->vmsa), &e); + if (rc) { + pr_err("Failed to release SNP guest VMSA page (rc %d), leaking it\n", rc); + goto skip_vmsa_free; + } + } + __free_page(virt_to_page(svm->vmsa)); +skip_vmsa_free: if (svm->ghcb_sa_free) kfree(svm->ghcb_sa); } diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index dfc4975820d6..33f8919afac2 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -1682,6 +1682,7 @@ enum sev_cmd_id { KVM_SEV_SNP_INIT, KVM_SEV_SNP_LAUNCH_START, KVM_SEV_SNP_LAUNCH_UPDATE, + KVM_SEV_SNP_LAUNCH_FINISH, KVM_SEV_NR_MAX, }; @@ -1693,6 +1694,18 @@ struct kvm_sev_cmd { __u32 sev_fd; }; +#define KVM_SEV_SNP_ID_BLOCK_SIZE 96 +#define KVM_SEV_SNP_ID_AUTH_SIZE 4096 +#define KVM_SEV_SNP_FINISH_DATA_SIZE 32 + +struct kvm_sev_snp_launch_finish { + __u64 id_block_uaddr; + __u64 id_auth_uaddr; + __u8 id_block_en; + __u8 auth_key_en; + __u8 host_data[KVM_SEV_SNP_FINISH_DATA_SIZE]; +}; + struct kvm_sev_launch_start { __u32 handle; __u32 policy; From patchwork Fri Apr 30 12:38:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233311 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FF55C433ED for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2688.namprd12.prod.outlook.com (2603:10b6:805:6f::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4087.35; Fri, 30 Apr 2021 12:39:13 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:13 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 26/37] KVM: X86: Add kvm_x86_ops to get the max page level for the TDP Date: Fri, 30 Apr 2021 07:38:11 -0500 Message-Id: <20210430123822.13825-27-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: O7xpLd2lvI3kkgFCRZbwDNJpAN6XSs2sHwlS86cdkcdEM5zoK+Ol6r0TDQXC1ZX72yiTHPPmKgOhv/wohI6d35m5GVq2EVh0/6kipR+d5J4HvyZ+FF5relG+rc6RRUpIJNhFv3YT9QNQQxHq/ohEfxZb8zUrvL/1y9BWrE/aQX83bWxJK+M/lrBORWwofSUvz8EtCu52+ZJE2tWpy39dnsbc9D1MuCDYoirKK9sI6kgB/R0OjyrjXLy1WpBi9YMMlONkqSkCVCYXqvEX83CMqTZgJjphiZ9otOWRWmsLJOMP94aO0xIkdLm+xWEjYHuARpZUGwKZ1bJbR9nZiyrEYygvax1sjAL9tAh/Xghek8S2BOuROTXxQp8yymvwL9CtMWh49ZroCpx6PpRsA3tWkLn95XdpUbEsB6YfqidQKeRYo3IwcchUZjKnP9TAZ1/L9IMqUlQ4WAqh13X9FJzvD8pX0HJxWMOP7xiSxbynRRbLGuHjUtKxOZzJI7l69C2r8uk5Rhb7kcj1QuIkUCZBlpJ9ksI0XXK+k/3EL3o2Eu8n5HW0Sw9476AWFzuPjj0h5iYDB2o2Zed6b/EBSDkeUK369hULZhp3biihE6M6isJdSA97im6wSHXCVjj5eGqYDEKcgIts1dcr1ashxdRERZrPfqLjiQ7eCRwvrOrZpzkBsSElafBbzAIvuHetPM3Iuh7XZMr6rmODHCPhJaa6x2LII2HPbpr3FXcwNOqDIFE2y6LMvTyfAZjzYeV11dP8XjsLcYS5a+CXjQ7Tmnod2OTrtpAEXorFwe3bJBIFVuG3rUoiaxrntm6iz1Gw8bpZ0GjNEgvKEzo/2xt6wUqvygnWu3/xD92mIyLzU5typFTLdz++xYeyV2NL3GQK2OXW0vVTlV3126D0GRW6p92XVSFpBMN46d9msW0zZMJcC7sL0hMjQw69JiwW9TfwZn99UFDN8pcSe+9qgv03MZXbII7TaJ/cId4txmrzLs7aNrCU49v65C9jAPAgnr7ZB3nLabDOmtPd8bBCXQC3LnrN+MU7VmdaGifug2knyErb91JqwRNSLvCpBPtkfob6MTTn5jw/RFu7N7SDiIzHK1CQ/eP0afv5RSzVax0Ls9ERdZGylsc3qm45JH8uoRjX1He+eRseWMTgjHT5cxDN9W3LyAX54g0ADwgGDheEZws/Af8aZpwYoZpprxcRU4skLn6JB/23PKgZtCPSgnJAja1UmKNXjWWhGA5qvrV+BT0LjVAhMdGOYufvzMt3uzGYlPDlR8Ld47X2JSZenzB+Wl5Zn7KSZU7IHXjuf35i9lYEbDxKHI6g2OnGDe2CxRgU/ZXp X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 21b2d423-bea4-4ea1-0f47-08d90bd4f567 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:13.0118 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: h3wHyFisLVhMlV7m16Aq04cN/vExMJTOskaZnxSnyFzZFT56sQrEM05FkglnIJ9DWgw7OXBI9C1JQk/ulACFGQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2688 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org When running an SEV-SNP VM, the sPA used to index the RMP entry is obtained through the TDP translation (gva->gpa->spa). The TDP page level is checked against the page level programmed in the RMP entry. If the page level does not match, then it will cause a nested page fault with the RMP bit set to indicate the RMP violation. To keep the TDP and RMP page level's in sync, the KVM fault handle kvm_handle_page_fault() will call get_tdp_max_page_level() to get the maximum allowed page level so that it can limit the TDP level. In the case of SEV-SNP guest, the get_tdp_max_page_level() will consult the RMP table to compute the maximum allowed page level for a given GPA. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/mmu/mmu.c | 6 ++++-- arch/x86/kvm/svm/sev.c | 20 ++++++++++++++++++++ arch/x86/kvm/svm/svm.c | 1 + arch/x86/kvm/svm/svm.h | 1 + arch/x86/kvm/vmx/vmx.c | 8 ++++++++ 6 files changed, 35 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 71e79a1998ad..88033147a6bf 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1382,6 +1382,7 @@ struct kvm_x86_ops { void (*vcpu_deliver_sipi_vector)(struct kvm_vcpu *vcpu, u8 vector); void *(*alloc_apic_backing_page)(struct kvm_vcpu *vcpu); + int (*get_tdp_max_page_level)(struct kvm_vcpu *vcpu, gpa_t gpa, int max_level); }; struct kvm_x86_nested_ops { diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index 930ac8a7e7c9..fe2c5a704a16 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -3781,11 +3781,13 @@ static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, bool prefault) { + int max_level = kvm_x86_ops.get_tdp_max_page_level(vcpu, gpa, PG_LEVEL_2M); + pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code); /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */ return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault, - PG_LEVEL_2M, false); + max_level, false); } int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, @@ -3826,7 +3828,7 @@ int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, { int max_level; - for (max_level = KVM_MAX_HUGEPAGE_LEVEL; + for (max_level = kvm_x86_ops.get_tdp_max_page_level(vcpu, gpa, KVM_MAX_HUGEPAGE_LEVEL); max_level > PG_LEVEL_4K; max_level--) { int page_num = KVM_PAGES_PER_HPAGE(max_level); diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 7da24b3600c4..3203abbd22f3 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -3188,3 +3188,23 @@ struct page *snp_safe_alloc_page(struct kvm_vcpu *vcpu) return pfn_to_page(pfn); } + +int sev_get_tdp_max_page_level(struct kvm_vcpu *vcpu, gpa_t gpa, int max_level) +{ + struct rmpentry *e; + kvm_pfn_t pfn; + int level; + + if (!sev_snp_guest(vcpu->kvm)) + return max_level; + + pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa)); + if (is_error_noslot_pfn(pfn)) + return max_level; + + e = snp_lookup_page_in_rmptable(pfn_to_page(pfn), &level); + if (unlikely(!e)) + return max_level; + + return min_t(uint32_t, level, max_level); +} diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 1b9091d750fc..81a83a7c1229 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4617,6 +4617,7 @@ static struct kvm_x86_ops svm_x86_ops __initdata = { .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector, .alloc_apic_backing_page = svm_alloc_apic_backing_page, + .get_tdp_max_page_level = sev_get_tdp_max_page_level, }; static struct kvm_x86_init_ops svm_init_ops __initdata = { diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index a870bbb64ce7..cf9f0e6c6827 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -567,6 +567,7 @@ void sev_es_create_vcpu(struct vcpu_svm *svm); void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); void sev_es_prepare_guest_switch(struct vcpu_svm *svm, unsigned int cpu); struct page *snp_safe_alloc_page(struct kvm_vcpu *vcpu); +int sev_get_tdp_max_page_level(struct kvm_vcpu *vcpu, gpa_t gpa, int max_level); /* vmenter.S */ diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 10b610fc7bbc..6733f1557016 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -7670,6 +7670,12 @@ static bool vmx_check_apicv_inhibit_reasons(ulong bit) return supported & BIT(bit); } + +static int vmx_get_tdp_max_page_level(struct kvm_vcpu *vcpu, gpa_t gpa, int max_level) +{ + return max_level; +} + static struct kvm_x86_ops vmx_x86_ops __initdata = { .hardware_unsetup = hardware_unsetup, @@ -7800,6 +7806,8 @@ static struct kvm_x86_ops vmx_x86_ops __initdata = { .complete_emulated_msr = kvm_complete_insn_gp, .vcpu_deliver_sipi_vector = kvm_vcpu_deliver_sipi_vector, + + .get_tdp_max_page_level = vmx_get_tdp_max_page_level, }; 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Fri, 30 Apr 2021 12:39:13 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 27/37] KVM: X86: Introduce kvm_mmu_map_tdp_page() for use by SEV Date: Fri, 30 Apr 2021 07:38:12 -0500 Message-Id: <20210430123822.13825-28-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: iBM2oknEn7Z8sppps+bSjRgsmj0+nXrHB28zd54nuZ+aC8woHEmQR1/d5xnfduXQNZ74G8YvZLQlXG1o5YrEB9OdFBdpfjHxexxYNcuw8JJDx1NV4POmALVfa/FbiF9oQqY6wvNyssvL0Il41eP1H/BdddUsvuWoydlqa1t2YS6XtMZdyloyNqiKq1v3okZsvupmM32g82JvcGMEirH8oHV/qW/cTQxwTOilFbvRHBVbqUf5RuV53Cow1rs5AI30unvPFk1HoS8WyjmzYu18otMlfBHkVWag20VTq1o36nUp9uqhEkWCJEVhm7Ch4PZ2kdS08xztbabfNgTmDQfz0YanzGTlXTMTbOtif0l6C0X2GmgZRXEORaKJTdDIPsCy2URa1GFttu0FJV0STEh3YUvU06CftmHUlr61sxFCLi3El/UQB5pGAnZIYMwzhEVwKhuiN/9QxIlJJ2NsEDLSUKF4ZOS8To7P6eV8fodv/cyGxkfrAnQi5FtaqwcNHOA/OLZ8o/txunRCUz7S4I48b10km2eOw2lMh9ZPA4EBaLFKe2GIs79YKtpPxV1U7BgZbRzUQqq4cns/1Z23oomDwf3YcMiaOI6mDF4ZYJCZFsbCDxsMhFzWaRGmTchYZMTWCVzY1FuGsU1RcTJLA0/KeztChFpnv8pSD8EdCKY3iE/lSR5BQ6e0yhuxAyn5d/VPJ/I/Z+Dy9a5c9Zzu/dE5JqYgIpoXs284xhXUehUV49PIIY4R72dw6SshF5xcH01RHJG2954+xV8YsjvMzq/H3XoLIPNiOAskG2Wr/g5rwanycUyBGcKRIXUdPXsAKOeY8TGeN3gl/1O6fq3xo4fGwoN6gPggghj9yyhHLOqa5vagdGICPyED+yQbX/4vZq1FC4k7vvXdFuW7bBwGjGvAWw3IIJjc21excTHkEE7zb/FFga6QrvB9iC0ldPkdjUHL6TKo2xtMfzsQ72DHhC3sqmrpoHoDD7wP81i0YabBJXrto1PGBe1KP4dt/WAem9Y55GcCj+zGGydoF9htUNWQf/7Y7EbXTVMCgKq3Zg0L8Byng6p0gqMe4d1g+cFtlUSBbtE8MB7C3jfJj61NCOjeWxAxfnmyJm+kWCO7YyMOECgiPQVM77BrwIboBjE/6D9oSTwyPgMpw34VYn0fBbtWuIz4tpga0I4zu+fo8k+T2xYy/4LbE6LOrvstN0CEqIh4yCV3XM4wt1/MNDBalSVM0i20vIcs9dFkfjN61H7j1wlFF6fbmtZC5xkHt0Wdb0vL7TAfBaH5PFMZDv7I/XAOYd4UnK3qQ2x372IQUaYQGFQH4FGACBvBP6ayc+JoJu4r X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9f27436c-6eef-40c9-0b75-08d90bd4f5da X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:13.8204 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: xMf1nX1+ozugPj8BViO81zFTImd7lVkSMhtbhnfJwsxsmA8DBTYj5ZOxOd4DrI5X1jxtek/r8VkpjA657lm2zw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2688 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Introduce a helper to directly fault-in a TDP page without going through the full page fault path. This allows SEV-SNP to build the netsted page table while handling the page state change VMGEXIT. A guest may issue a page state change VMGEXIT before accessing the page. Create a fault so that VMGEXIT handler can get the TDP page level and keep the TDP and RMP page level in sync. Signed-off-by: Brijesh Singh --- arch/x86/kvm/mmu.h | 2 ++ arch/x86/kvm/mmu/mmu.c | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h index 88d0ed5225a4..005ce139c97d 100644 --- a/arch/x86/kvm/mmu.h +++ b/arch/x86/kvm/mmu.h @@ -114,6 +114,8 @@ static inline void kvm_mmu_load_pgd(struct kvm_vcpu *vcpu) int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, bool prefault); +int kvm_mmu_map_tdp_page(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, int max_level); + static inline int kvm_mmu_do_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u32 err, bool prefault) { diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index fe2c5a704a16..d150201cf10c 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -3842,6 +3842,26 @@ int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, max_level, true); } +int kvm_mmu_map_tdp_page(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, int max_level) +{ + int r; + + /* + * Loop on the page fault path to handle the case where an mmu_notifier + * invalidation triggers RET_PF_RETRY. In the normal page fault path, + * KVM needs to resume the guest in case the invalidation changed any + * of the page fault properties, i.e. the gpa or error code. For this + * path, the gpa and error code are fixed by the caller, and the caller + * expects failure if and only if the page fault can't be fixed. + */ + do { + r = direct_page_fault(vcpu, gpa, error_code, false, max_level, true); + } while (r == RET_PF_RETRY); + + return r; +} +EXPORT_SYMBOL_GPL(kvm_mmu_map_tdp_page); + static void nonpaging_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context) { From patchwork Fri Apr 30 12:38:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233321 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 623AAC433ED for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2688.namprd12.prod.outlook.com (2603:10b6:805:6f::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4087.35; Fri, 30 Apr 2021 12:39:15 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:15 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 28/37] KVM: X86: Introduce kvm_mmu_get_tdp_walk() for SEV-SNP use Date: Fri, 30 Apr 2021 07:38:13 -0500 Message-Id: <20210430123822.13825-29-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: DSp62iNQIVzHpvBtXX38jsmUaBtoZw7Bk2nHeTdiU5GLosgeFScfK+BPTeMi6giKZbgfP7Gm6zBzppBejlMYHUDy7UryooOeeYO+/k8OOkZD7os8uwX6cjeSrJE9XAJYdzqICB3Hx73Ortsf8thibBD+LBqqfgxUczCiNlNKAGK5ozuX5AO1jtZROrMB3rTa1AzLQSGss1ckPu77EXtNB/+TtpeIaW5XSJwF6onsUeN0ICDv0/c3o16CbWWZYC3chIg2seENmz577tlCBhqDfJwGkGRgon17S0o/+M4YM0bEaanSMQFtv0AAJnf8yy+WLZixa7Ub7AO8fU7H/mvhBPilwl2WZUHi4GVxrmsaHO3Fa7gJGFO/KS7rFdf0i6NvGzHtZK3hRQB2/ccSbbuGHstCC44z48WqpxDJiUCuKGSXC6WHi1PozuxVgF1Qu/u6Vr2CMNNNyvcLP2J7SYODx41GQntHUr32lVi1RLizg5hDHf+PvGVH0Uo6kxfUOqAcKoDJiIKejVkwTCjtGBxiOPxBpRMsVUaGh5Jpzldy66wv8V3vlWSn3Q14mTo3uiOz54yX2emq7IkM7VDFc3o++bMoKlePlYkaK/w5XZ2k1pAwnZDU/8AEPn/t02cxfBwuechak2M8d9jPbKp9jCL+EM+a4383TC7RPAqyv/cxJFGO+Yt6rRoEMzFqjZPEOrr4eXO2J9PNJmzUpyey98UQMCruJPwAMCq0fgwot0/WyGcqL6+2NeT8xLJ+IkuLJ0Epvg8w9yECAZqtpHiTiBPz4thhI5sToz2KdEdHES6UNCkEppXuwr24JfwoYV1qspJlufMYROJY4JlmMbPUREZXhgWF5GYTekuUmWeGKJacHzNza1IVkvuPTjNlEpfYJbNRIjAR3tsdIUs6xNzYLzzZ6bZ5SOWznCf0Ety91/9KbU9vRTeWdrAXthyI68SvYtJN0HBc06QqHPcmyrqyDrtsY9eGve57EpO65dp54ePXh/+vB3eo8jGaDevsVrCCSYtw5uhopm7FbKbJbOGNrX4b1YJHcEwUD7sB2mjMiKgH4WzXIEmaVqEy6bM0gdeBOePWpIZBsWgCtStxAV7Wr9+j01pz69yE7OeG4ExKPawIppYsCmkPWig0KLSXxgnNsyNCtuIGwEn96wGVKgE7C55jESg3K6XDEVjE4+wKHuWUxEi2QGsa4RPJXHnHRyClXkxFLD6O0wXK0yHaDvCpvNktnyNIkaHka1+RxTEqJ14hWNeSSK5MIXZP3gnF84QeKHdW8QJLu+AOVozuWa5MAZRSuEOgP73LTx+lqrkdijGEaZe1UzlLh8Gf+/hSVHSw6nHS X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: ea22ed2c-2ec6-4395-ba42-08d90bd4f680 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:14.9857 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: cliChkMZfXHCCZkUlz22qC8PR6ZCK6hNl470PLYfoNmenkTXViQsEJMfedid77c63nqOQe+91JeQxD0j0K0sxg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2688 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The SEV-SNP VMs may call the page state change VMGEXIT to add the GPA as private or shared in the RMP table. The page state change VMGEXIT will contain the RMP page level to be used in the RMP entry. If the page level between the TDP and RMP does not match then, it will result in nested-page-fault (RMP violation). The SEV-SNP VMGEXIT handler will use the kvm_mmu_get_tdp_walk() to get the current page-level in the TDP for the given GPA and calculate a workable page level. If a GPA is mapped as a 4K-page in the TDP, but the guest requested to add the GPA as a 2M in the RMP entry then the 2M request will be broken into 4K-pages to keep the RMP and TDP page-levels in sync. Signed-off-by: Brijesh Singh --- arch/x86/kvm/mmu.h | 1 + arch/x86/kvm/mmu/mmu.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h index 005ce139c97d..147e76ab1536 100644 --- a/arch/x86/kvm/mmu.h +++ b/arch/x86/kvm/mmu.h @@ -115,6 +115,7 @@ int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, bool prefault); int kvm_mmu_map_tdp_page(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, int max_level); +bool kvm_mmu_get_tdp_walk(struct kvm_vcpu *vcpu, gpa_t gpa, kvm_pfn_t *pfn, int *level); static inline int kvm_mmu_do_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u32 err, bool prefault) diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index d150201cf10c..956bbc747167 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -3862,6 +3862,35 @@ int kvm_mmu_map_tdp_page(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code, int m } EXPORT_SYMBOL_GPL(kvm_mmu_map_tdp_page); +bool kvm_mmu_get_tdp_walk(struct kvm_vcpu *vcpu, gpa_t gpa, kvm_pfn_t *pfn, int *level) +{ + u64 sptes[PT64_ROOT_MAX_LEVEL + 1]; + int leaf, root; + + if (is_tdp_mmu_root(vcpu->kvm, vcpu->arch.mmu->root_hpa)) + leaf = kvm_tdp_mmu_get_walk(vcpu, gpa, sptes, &root); + else + leaf = get_walk(vcpu, gpa, sptes, &root); + + if (unlikely(leaf < 0)) + return false; + + /* Check if the leaf SPTE is present */ + if (!is_shadow_present_pte(sptes[leaf])) + return false; + + *pfn = spte_to_pfn(sptes[leaf]); + if (leaf > PG_LEVEL_4K) { + u64 page_mask = KVM_PAGES_PER_HPAGE(leaf) - KVM_PAGES_PER_HPAGE(leaf - 1); + *pfn |= (gpa_to_gfn(gpa) & page_mask); + } + + *level = leaf; + + return true; +} +EXPORT_SYMBOL_GPL(kvm_mmu_get_tdp_walk); + static void nonpaging_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context) { From patchwork Fri Apr 30 12:38:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233323 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3BFCC433ED for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2688.namprd12.prod.outlook.com (2603:10b6:805:6f::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4087.35; Fri, 30 Apr 2021 12:39:15 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:15 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 29/37] KVM: X86: Define new RMP check related #NPF error bits Date: Fri, 30 Apr 2021 07:38:14 -0500 Message-Id: <20210430123822.13825-30-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: 4PWhMzi6axe6AsOM7nhew6h0ff9VYPWKYz9h6JYTJRPEc47NXfZjUS52WfDkgqSBgeFvuanamQjf7ihJ1LHaw1nTDIV2o2RmUV2hellUG86T5GJpT430lFExvzAJ72VSmboGXa2Q8syW8mpqwqZNLvZO8Dx/+hAzXybWdARzVqCzRi4PlTyCVw5Z9mn0cR8CJ4lcRT/vAzXC8MFP8Mo57434iQyWAqURBqQibf/cmT4hyHJtB8uVeAW35Uda7D0th+Uha64rN3HYGy2CyZ0J5DhLRk+FCpDczXQxGCV9f6a+ip7+MNxCIJPc2j0Bi/YcdeV6UkNxa2dE6IwECAaJHb9ARhxZyma3Mzh/7kDJ80UGNB6sayiOjnkKwf3JJ7OKI10OUJ8s5PP6fu4jWN3JP7mxyMd3Wb6mnHlgbAMtau73wI+0/uDOuZoRW2EBvdWX8HjNGNsoSkN2GFUntVAsOdFvTHmqJszZDghXe4Il5SPjerFnJeoPN62DsyCGo9Nwhlo+SlKuIKZiRMfUbVqvLKsGJCgOJreAFO9i/d5MRhlMSlLwGUim99uB8ddexQKtZYQL6FFBhYGLl3EcDrTnqj/vp3pQdN4fO2cZLrHCWfW9c/o+5VurkkvrEivG011XPHGDfuz8r01ad0BQ1z24B0pg5iW8tONAoD1cWt4vhr8Bi+z9Kkqapt/W2mGyLHfHutoQZewxPX0l7kwsLSSdggkju2vBL8i6+I6YgZY2HWGjFjTMCzC8jK8GFAE0m2Uj9RHYUphfe7dvigIjhnkvv/L8tueMHfXqriA8B1B14uqJxo9ObBNFhNZ3Z7QCfyFkxnO8i+ofpkN+b7tPryM07g43NIpxWQA4CGNTXH22qIxA5OMPLYmY1aTjKde/L21cDwiOgp4sEWrffJnc5x031iB61OBkc9gaV8s+dYajt1ZVGf3xzcFszSPLLidIROeMc74DDMoamNnyZul+LmIWyisf5snUMEg0pTNrgb8CDwMPobZQoND3AoclKnHFSBZ02JSqf6nSGiX16j0glxXylMGRisTRsLDCXgopw6hfrkZJnXRi1EfqoLXzLIaiucXxG5AAC8lvGezjMKtHyxZmB+o9Es/eDosdirL3TQsydFvKJePhVV+77CLsdfUjaFKYPisLYGH1/4Y2Bz96YWVhFeYg0ITj7F0gmf0twm2qYex33pRuCkODZ0NxgAyOhUIa8HktQZRg1nnBtAwiD8LG+Dl2M4D/XfFK6I6IlOBfyP/v1JxDwERPcu3ALWTdC/ppYBa2PRIZ/NxLkdXMM4zsEv0BCxLXuDBMytEQfYkSVVCq9nfVf8fonOXITWolzYsm X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 094800a3-a37f-435d-b00b-08d90bd4f710 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:15.7213 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ApNh8wq+OHA08baAsjsQzrO3jx0XHnR4/iuYRJuyrZoP8aJV9LJJblEdbtSqUGMwUc41un/Jkmyx9IaVFiyfyw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2688 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org When SEV-SNP is enabled globally, the hardware places restrictions on all memory accesses based on the RMP entry, whether the hyperviso or a VM, performs the accesses. When hardware encounters an RMP access violation during a guest access, it will cause a #VMEXIT(NPF). See APM2 section 16.36.10 for more details. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/kvm_host.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 88033147a6bf..ad01fe9f4c43 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -237,8 +237,12 @@ enum x86_intercept_stage; #define PFERR_FETCH_BIT 4 #define PFERR_PK_BIT 5 #define PFERR_SGX_BIT 15 +#define PFERR_GUEST_RMP_BIT 31 #define PFERR_GUEST_FINAL_BIT 32 #define PFERR_GUEST_PAGE_BIT 33 +#define PFERR_GUEST_ENC_BIT 34 +#define PFERR_GUEST_SIZEM_BIT 35 +#define PFERR_GUEST_VMPL_BIT 36 #define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT) #define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT) @@ -249,6 +253,10 @@ enum x86_intercept_stage; #define PFERR_SGX_MASK (1U << PFERR_SGX_BIT) #define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT) #define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT) +#define PFERR_GUEST_RMP_MASK (1ULL << PFERR_GUEST_RMP_BIT) +#define PFERR_GUEST_ENC_MASK (1ULL << PFERR_GUEST_ENC_BIT) +#define PFERR_GUEST_SIZEM_MASK (1ULL << PFERR_GUEST_SIZEM_BIT) +#define PFERR_GUEST_VMPL_MASK (1ULL << PFERR_GUEST_VMPL_BIT) #define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \ PFERR_WRITE_MASK | \ From patchwork Fri Apr 30 12:38:15 2021 Content-Type: text/plain; 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Fri, 30 Apr 2021 12:39:46 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 30/37] KVM: X86: update page-fault trace to log the 64-bit error code Date: Fri, 30 Apr 2021 07:38:15 -0500 Message-Id: <20210430123822.13825-31-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: o5No8qrilln7rG5Qnsxabv5K5Zcka62idTw0eDrgnb0f8/1rf/EYclrC+dzwdbdbVzx61SDaufB/to31CWc1R23b1aHcRKDrsdPkQfR4LtCd/J1iZVJBsZA3i6uTliDCb4I8isqnK0QveOwUFub7WnQtMmbDMydyLEof2nEUbWSoO/scuqdf478zq2sbaVfsNFYR1z5/XUgr/ndTaukgQtmeVdSZNy8KIluAJAIcMved5tmX0EvUmxcyB7jzW3sk11p5cM+rNfCbypA9EsxtnUmDid+/laV8M10X8Iw7Sh+pA6GiPJCz6aBm4gboZFriGydA7OozpTDExQqMXBJrIF4cX2vOsjIFvAPr6Xdbc96J6BeNJIW05sj8q/kVTfxZc5RWch3NwLvt1wKNzPGSyuWJuCSNNreFa3SgcQEshZdC9EhtzfXZovUA4TR2FOTaBWpToWvVVB2Q79S72q2cpMsuxqj5xi3cs1zVe5wnRFA+HHU8YKiPVlD6rMat1ZqbcuLf2AEeh0HPF7m6YmOEwmESs+khkT461GvooEsRClxr1DjGhvZeFZPtd01Q1v73pvPqyUtCbA/1HY/gHAZl5Le9DLKTaWIPwRwBXYbzUwGa2x9gQDEkWcROf7Mq1mcWYSrRnledgpj123+Oe1IAggkEZmHnPdqv7Wr6XaarzqmqGAlxT//DZrPVHOQunz+bwMWrj6ONoA5MxgXLbeg0aw+Uo8gHK7+jZv8zMfNHqWXv5Qyqlhqx1joNLxfs6qnb7Y3wuGp90maXhpeUWiBh43KtJQlPMdGplXjt9Z+glGJ6692lQCAFGTjoXLuSOzmlf5/zfM/zf/S4oqq1zlvMGQPQmjVd2tlceZHXpiRkevHFaZtwv/a1FfcECgHD+SDGurw68AV0QmHaGs+gHqdigagOy8+BVu4ZnuNcr4TrZZh2dzZ4EJrJ62e0NLQO/wOZ091qjTHN7Upv8nATEjvNJJLUTxXvoc9qEb65chs/fUo2J30O1Zk7BH+14ERbTnE91+CZ+yAoOdoJIWtb+O6xetEHD7MqnwH8J7TV+ZQBh3NzkbtShtruJ47/mBIaxGWiGTMk1IIkseeqZ3WMXT0wfw+NMb99mZfPyfLa5cOtSaDct31pJ5e5NKerYM5zIcOlkztSg/QO91HzxzIo1BdP3OYbucxIEnKuUB8cc2JCd8V/jKpU+9zAxU2NeJbWOVq/T6/INLs+xMvZ6Fzf1Qkp7rkZTbvWAVGC8S0O6VpDWLZMqO6kx5paIhGfqEd7Ui4WkkMrvMelM2KFgIQZKX2TXsbQpjUGzbVC3mMtYQzTBMtdbn7j67O18i9y20WP9MxF X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3cf173de-a802-4d0e-40b9-08d90bd4f776 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:16.3759 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ckMlq0wJsGshKVB36Bh/aUMtNJmD1lFMGSXDz3Eq9K91UqHikwpjCxX5EJtJpdkV3GwGAfVkI4u10ezDE0A1Qg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2688 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The page-fault error code is a 64-bit value, but the trace prints only the lower 32-bits. Some of the SEV-SNP RMP fault error codes are available in the upper 32-bits. Signed-off-by: Brijesh Singh --- arch/x86/kvm/trace.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/trace.h b/arch/x86/kvm/trace.h index a61c015870e3..78cbf53bf412 100644 --- a/arch/x86/kvm/trace.h +++ b/arch/x86/kvm/trace.h @@ -365,12 +365,12 @@ TRACE_EVENT(kvm_inj_exception, * Tracepoint for page fault. */ TRACE_EVENT(kvm_page_fault, - TP_PROTO(unsigned long fault_address, unsigned int error_code), + TP_PROTO(unsigned long fault_address, u64 error_code), TP_ARGS(fault_address, error_code), TP_STRUCT__entry( __field( unsigned long, fault_address ) - __field( unsigned int, error_code ) + __field( u64, error_code ) ), TP_fast_assign( @@ -378,7 +378,7 @@ TRACE_EVENT(kvm_page_fault, __entry->error_code = error_code; ), - TP_printk("address %lx error_code %x", + TP_printk("address %lx error_code %llx", __entry->fault_address, __entry->error_code) ); From patchwork Fri Apr 30 12:38:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233333 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE544C433ED for ; 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X-MS-Exchange-AntiSpam-MessageData: DL48X5PPogF2uXtRIpjK8Xfm0zkcAdjrZ4ioKpH9B682UYae7eKZG7C+QGFHvGYO0RjdKkfQgFnhjfuQ3wsHx+jlyZe2eBj34QBSfQxE1Tv7sMpaAnstzRAF7Lw4ZJNIAdivLtlzrRsjiZXba+FLt0hs2UFk2p+UAu08bwiZIyehRiJbLP3GyTH7sokqqhdZdFgB+wpYK4EFLXHFJ+UKmdZv+RWs3IGkwN7P0Bqlpe8m/BEGE+GkK/aYcq1MHZ7bMuCUKGuVIWr2kk+IKUVrUqkKGDEiBcXv0og2HzsFbT1RPN8X4K/3JnPKcZ3QE79X4ib3k7A8B9yrdyKGkrenNRIVsXwI6apt7RL2qHKOfrVTzOncE8zvavvdyxNJQLQqYlNkkFVGhnSRo5fgn2H8/KASjH91KkCqj89B7KvU3jw+gih0PlPdtdDpiioJWg/y1RV5UuPApFzk45Zrrjk3k8ueiqwASN8pXY9w1WWS3A7MAdFZlDLOloQILCTOxIBKMrkm937diRMEQ9zqDcaV/0+vNvdZI1/k8FDnRmiTsQQC1eMbR0MPTScCseUrKveK+0US5w3+7W+j5qjHSnbMOaa8CCLKNEjTQdcXV8bu03R0t07qD3czEYEoZIAZLkMm0G4lNEre6Lx6depcCbmlslr/1RxCm118rGWiz4Lu0nFlQ1iDxvnzpwA8SZYtZFpW9Z7TftGu8+xpe53wIQSUrHwKGfXAdCemFXRFc1zxXlEDH/cI9PNK+8e+V/AWp2V6mUWLZ0WzFYf7scxyRO9PmW8S2rqKXW3qLnI1a9F+apkVfneEI04VEO9q2MkfVMYRJ4tVujLadvNeuTK+9OLnJOK6BwDEetXk5gcwfE0Ic1469NHPWy6vPhCMC+aSF2Wrgt0eNBaUHLWqCnDvLLVwKVuFGAA00mv7Ce8Cg3/pCxSzy0SSSKfyEJ5A0l80Ak70ui+bNqBDcj8NmYrEzsaWZRmqe1CIfWfCtBv+/HtFwQ3GlT4sB0Vu2yYj0kmb+h/WIWUBndcKhxu3HOZVQUt/aBoQJfg6Bn8nJCGdjBLA4l5vXm8IGGer8eTE9Gwl4LQMl7VwLYjdVu+7w8TLutWgOhbV99qO6EKRFo3ziVJ5zhZhEbtZtVPjvHk/4E1gywoeMVM3AJFMZWMZTlKAPQYgim5u/9Zvu0nS23ax3M0KnYcWSwrke9G6GfdDWxDZmKlaqgXM1YD+FhGak05QzZoAxVqu1msHoTrTPBtSVO4esb6ITPX64K1ftNk41IjOqeQbI25l4J9TG/WUWQWJTj2h2D6tJ+oY8XXej3wdeB11cU3f3a2K6MNxHiHuVD58dUw7 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: f56c63c3-60bd-4a68-0e35-08d90bd4f7db X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:17.0615 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: wRIf0NIcej3ORwXp8eMgGS4ml/FFQqCebVwlpprAScR9/yXTTZizXDQIfjZhr4crm/rYLrJbgqSZtUxKIvGlsg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2688 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org SEV-SNP guests are required to perform a GHCB GPA registration (see section 2.5.2 in GHCB specification). Before using a GHCB GPA for a vCPU the first time, a guest must register the vCPU GHCB GPA. If hypervisor can work with the guest requested GPA then it must respond back with the same GPA otherwise return -1. On VMEXIT, Verify that GHCB GPA matches with the registered value. If a mismatch is detected then abort the guest. Signed-off-by: Brijesh Singh --- arch/x86/kvm/svm/sev.c | 25 +++++++++++++++++++++++++ arch/x86/kvm/svm/svm.h | 7 +++++++ 2 files changed, 32 insertions(+) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 3203abbd22f3..1cba9d770860 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -2904,6 +2904,25 @@ static int sev_handle_vmgexit_msr_protocol(struct vcpu_svm *svm) GHCB_MSR_INFO_MASK, GHCB_MSR_INFO_POS); break; } + case GHCB_MSR_GPA_REG_REQ: { + kvm_pfn_t pfn; + u64 gfn; + + gfn = get_ghcb_msr_bits(svm, GHCB_MSR_GPA_REG_VALUE_MASK, + GHCB_MSR_GPA_REG_VALUE_POS); + + pfn = kvm_vcpu_gfn_to_pfn(vcpu, gfn); + if (is_error_noslot_pfn(pfn)) + gfn = GHCB_MSR_GPA_REG_ERROR; + else + svm->ghcb_registered_gpa = gfn_to_gpa(gfn); + + set_ghcb_msr_bits(svm, gfn, GHCB_MSR_GPA_REG_VALUE_MASK, + GHCB_MSR_GPA_REG_VALUE_POS); + set_ghcb_msr_bits(svm, GHCB_MSR_GPA_REG_RESP, GHCB_MSR_INFO_MASK, + GHCB_MSR_INFO_POS); + break; + } case GHCB_MSR_TERM_REQ: { u64 reason_set, reason_code; @@ -2952,6 +2971,12 @@ int sev_handle_vmgexit(struct kvm_vcpu *vcpu) return -EINVAL; } + /* SEV-SNP guest requires that the GHCB GPA must be registered */ + if (sev_snp_guest(svm->vcpu.kvm) && !ghcb_gpa_is_registered(svm, ghcb_gpa)) { + vcpu_unimpl(&svm->vcpu, "vmgexit: GHCB GPA [%#llx] is not registered.\n", ghcb_gpa); + return -EINVAL; + } + svm->ghcb = svm->ghcb_map.hva; ghcb = svm->ghcb_map.hva; diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index cf9f0e6c6827..243503fa3fd6 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -185,6 +185,8 @@ struct vcpu_svm { bool ghcb_sa_free; bool guest_state_loaded; + + u64 ghcb_registered_gpa; }; struct svm_cpu_data { @@ -245,6 +247,11 @@ static inline bool sev_snp_guest(struct kvm *kvm) #endif } +static inline bool ghcb_gpa_is_registered(struct vcpu_svm *svm, u64 val) +{ + return svm->ghcb_registered_gpa == val; +} + static inline void vmcb_mark_all_dirty(struct vmcb *vmcb) { vmcb->control.clean = 0; From patchwork Fri Apr 30 12:38:17 2021 Content-Type: text/plain; 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Fri, 30 Apr 2021 12:39:47 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 32/37] KVM: SVM: Add support to handle MSR based Page State Change VMGEXIT Date: Fri, 30 Apr 2021 07:38:17 -0500 Message-Id: <20210430123822.13825-33-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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Before changing the page state in the RMP entry, we lookup the page in the TDP to make sure that there is a valid mapping for it. If the mapping exist then try to find a workable page level between the TDP and RMP for the page. If the page is not mapped in the TDP, then create a fault such that it gets mapped before we change the page state in the RMP entry. Signed-off-by: Brijesh Singh --- arch/x86/kvm/svm/sev.c | 137 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 1cba9d770860..cc2628d8ef1b 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -28,6 +28,7 @@ #include "svm_ops.h" #include "cpuid.h" #include "trace.h" +#include "mmu.h" #define __ex(x) __kvm_handle_fault_on_reboot(x) @@ -2825,6 +2826,127 @@ static void set_ghcb_msr(struct vcpu_svm *svm, u64 value) svm->vmcb->control.ghcb_gpa = value; } +static int snp_rmptable_psmash(struct kvm_vcpu *vcpu, kvm_pfn_t pfn) +{ + pfn = pfn & ~(KVM_PAGES_PER_HPAGE(PG_LEVEL_2M) - 1); + + return psmash(pfn_to_page(pfn)); +} + +static int snp_make_page_shared(struct kvm_vcpu *vcpu, gpa_t gpa, kvm_pfn_t pfn, int level) +{ + struct rmpupdate val; + int rc, rmp_level; + struct rmpentry *e; + + e = snp_lookup_page_in_rmptable(pfn_to_page(pfn), &rmp_level); + if (!e) + return -EINVAL; + + if (!rmpentry_assigned(e)) + return 0; + + /* Log if the entry is validated */ + if (rmpentry_validated(e)) + pr_debug_ratelimited("Remove RMP entry for a validated gpa 0x%llx\n", gpa); + + /* + * Is the page part of an existing 2M RMP entry ? Split the 2MB into multiple + * of 4K-page before making the memory shared. + */ + if ((level == PG_LEVEL_4K) && (rmp_level == PG_LEVEL_2M)) { + rc = snp_rmptable_psmash(vcpu, pfn); + if (rc) + return rc; + } + + memset(&val, 0, sizeof(val)); + val.pagesize = X86_TO_RMP_PG_LEVEL(level); + return rmpupdate(pfn_to_page(pfn), &val); +} + +static int snp_make_page_private(struct kvm_vcpu *vcpu, gpa_t gpa, kvm_pfn_t pfn, int level) +{ + struct kvm_sev_info *sev = &to_kvm_svm(vcpu->kvm)->sev_info; + struct rmpupdate val; + struct rmpentry *e; + int rmp_level; + + e = snp_lookup_page_in_rmptable(pfn_to_page(pfn), &rmp_level); + if (!e) + return -EINVAL; + + /* Log if the entry is validated */ + if (rmpentry_validated(e)) + pr_err_ratelimited("Asked to make a pre-validated gpa %llx private\n", gpa); + + memset(&val, 0, sizeof(val)); + val.gpa = gpa; + val.asid = sev->asid; + val.pagesize = X86_TO_RMP_PG_LEVEL(level); + val.assigned = true; + + return rmpupdate(pfn_to_page(pfn), &val); +} + +static int __snp_handle_page_state_change(struct kvm_vcpu *vcpu, int op, gpa_t gpa, int level) +{ + struct kvm *kvm = vcpu->kvm; + int rc, tdp_level; + kvm_pfn_t pfn; + gpa_t gpa_end; + + gpa_end = gpa + page_level_size(level); + + while (gpa < gpa_end) { + /* + * Get the pfn and level for the gpa from the nested page table. + * + * If the TDP walk failed, then its safe to say that we don't have a valid + * mapping for the gpa in the nested page table. Create a fault to map the + * page is nested page table. + */ + if (!kvm_mmu_get_tdp_walk(vcpu, gpa, &pfn, &tdp_level)) { + pfn = kvm_mmu_map_tdp_page(vcpu, gpa, PFERR_USER_MASK, level); + if (is_error_noslot_pfn(pfn)) + goto out; + + if (!kvm_mmu_get_tdp_walk(vcpu, gpa, &pfn, &tdp_level)) + goto out; + } + + /* Adjust the level so that we don't go higher than the backing page level */ + level = min_t(size_t, level, tdp_level); + + write_lock(&kvm->mmu_lock); + + switch (op) { + case SNP_PAGE_STATE_SHARED: + rc = snp_make_page_shared(vcpu, gpa, pfn, level); + break; + case SNP_PAGE_STATE_PRIVATE: + rc = snp_make_page_private(vcpu, gpa, pfn, level); + break; + default: + rc = -EINVAL; + break; + } + + write_unlock(&kvm->mmu_lock); + + if (rc) { + pr_err_ratelimited("Error op %d gpa %llx pfn %llx level %d rc %d\n", + op, gpa, pfn, level, rc); + goto out; + } + + gpa = gpa + page_level_size(level); + } + +out: + return rc; +} + static int sev_handle_vmgexit_msr_protocol(struct vcpu_svm *svm) { struct vmcb_control_area *control = &svm->vmcb->control; @@ -2923,6 +3045,21 @@ static int sev_handle_vmgexit_msr_protocol(struct vcpu_svm *svm) GHCB_MSR_INFO_POS); break; } + case GHCB_MSR_PSC_REQ: { + gfn_t gfn; + int ret; + u8 op; + + gfn = get_ghcb_msr_bits(svm, GHCB_MSR_PSC_GFN_MASK, GHCB_MSR_PSC_GFN_POS); + op = get_ghcb_msr_bits(svm, GHCB_MSR_PSC_OP_MASK, GHCB_MSR_PSC_OP_POS); + + ret = __snp_handle_page_state_change(vcpu, op, gfn_to_gpa(gfn), PG_LEVEL_4K); + + set_ghcb_msr_bits(svm, ret, GHCB_MSR_PSC_ERROR_MASK, GHCB_MSR_PSC_ERROR_POS); + set_ghcb_msr_bits(svm, 0, GHCB_MSR_PSC_RSVD_MASK, GHCB_MSR_PSC_RSVD_POS); + set_ghcb_msr_bits(svm, GHCB_MSR_PSC_RESP, GHCB_MSR_INFO_MASK, GHCB_MSR_INFO_POS); + break; + } case GHCB_MSR_TERM_REQ: { u64 reason_set, reason_code; From patchwork Fri Apr 30 12:38:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233337 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4929C433B4 for ; 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Signed-off-by: Brijesh Singh --- arch/x86/kvm/svm/sev.c | 58 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index cc2628d8ef1b..bd71ece35597 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -2641,6 +2641,7 @@ static int sev_es_validate_vmgexit(struct vcpu_svm *svm) case SVM_VMGEXIT_AP_JUMP_TABLE: case SVM_VMGEXIT_UNSUPPORTED_EVENT: case SVM_VMGEXIT_HYPERVISOR_FEATURES: + case SVM_VMGEXIT_SNP_PAGE_STATE_CHANGE: break; default: goto vmgexit_err; @@ -2927,6 +2928,7 @@ static int __snp_handle_page_state_change(struct kvm_vcpu *vcpu, int op, gpa_t g case SNP_PAGE_STATE_PRIVATE: rc = snp_make_page_private(vcpu, gpa, pfn, level); break; + /* TODO: Add USMASH and PSMASH support */ default: rc = -EINVAL; break; @@ -2947,6 +2949,53 @@ static int __snp_handle_page_state_change(struct kvm_vcpu *vcpu, int op, gpa_t g return rc; } +static unsigned long snp_handle_page_state_change(struct vcpu_svm *svm, struct ghcb *ghcb) +{ + struct snp_page_state_entry *entry; + struct kvm_vcpu *vcpu = &svm->vcpu; + struct snp_page_state_change *info; + unsigned long rc; + int level, op; + gpa_t gpa; + + if (!sev_snp_guest(vcpu->kvm)) + return -ENXIO; + + if (!setup_vmgexit_scratch(svm, true, sizeof(ghcb->save.sw_scratch))) { + pr_err("vmgexit: scratch area is not setup.\n"); + return -EINVAL; + } + + info = (struct snp_page_state_change *)svm->ghcb_sa; + entry = &info->entry[info->header.cur_entry]; + + if ((info->header.cur_entry >= VMGEXIT_PSC_MAX_ENTRY) || + (info->header.end_entry >= VMGEXIT_PSC_MAX_ENTRY) || + (info->header.cur_entry > info->header.end_entry)) + return VMGEXIT_PSC_INVALID_HEADER; + + while (info->header.cur_entry <= info->header.end_entry) { + entry = &info->entry[info->header.cur_entry]; + gpa = gfn_to_gpa(entry->gfn); + level = RMP_TO_X86_PG_LEVEL(entry->pagesize); + op = entry->operation; + + if (!IS_ALIGNED(gpa, page_level_size(level))) { + rc = VMGEXIT_PSC_INVALID_ENTRY; + goto out; + } + + rc = __snp_handle_page_state_change(vcpu, op, gpa, level); + if (rc) + goto out; + + info->header.cur_entry++; + } + +out: + return rc; +} + static int sev_handle_vmgexit_msr_protocol(struct vcpu_svm *svm) { struct vmcb_control_area *control = &svm->vmcb->control; @@ -3187,6 +3236,15 @@ int sev_handle_vmgexit(struct kvm_vcpu *vcpu) ret = 1; break; } + case SVM_VMGEXIT_SNP_PAGE_STATE_CHANGE: { + unsigned long rc; + + ret = 1; + + rc = snp_handle_page_state_change(svm, ghcb); + ghcb_set_sw_exit_info_2(ghcb, rc); + break; + } case SVM_VMGEXIT_UNSUPPORTED_EVENT: vcpu_unimpl(vcpu, "vmgexit: unsupported event - exit_info_1=%#llx, exit_info_2=%#llx\n", From patchwork Fri Apr 30 12:38:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233357 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 421A5C433ED for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2688.namprd12.prod.outlook.com (2603:10b6:805:6f::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4087.35; Fri, 30 Apr 2021 12:39:49 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:49 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 34/37] KVM: X86: Export the kvm_zap_gfn_range() for the SNP use Date: Fri, 30 Apr 2021 07:38:19 -0500 Message-Id: <20210430123822.13825-35-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: +qAQfwSYln8nXnQvdPwyeQJEjBUuMaONqY2mtB3bzjlnL0bZr/oyP9yYLgqN4kDQhaLHdYlh8cZr043rMUkpZU6SeLcpAkDbCGlvQBxUWN92VtjcYFUpd3SGUcn5Yz8Fo4OhsqxbKN7IlVfL3nUBgkhGii+GCS7paxM/FkKRtyggkjeHEK1T92vrYOt0ySuAjUnquKSts9W0O7BCL8YtAUda7iqc/sCx+RQlaQBn67F79jSZ/5GY9KCztLg4sH/bSXi5Fl3QxYCQi3LTqb6rBfksD1v/XNe1/vf5AcJjC6YCg03VppQdjSCymhX2Y2Q2wYapXI7TeQ5uIg/k03fOWa1CXfTubpKKMshe4yHPZPoi/aYsvlvvPXYV3pXxA+NeDod7ji2+j3yoYsSNE8+g7unTu+Lgxpe68NS6N52dshgCBQPjCHiTxRoQftdqMbPwwAji1AhkZ0dRzhsJ4lR8EJGy6J0Vx0dZQVjgWjX5y8qkqpKLk353f9Z+XuQQ3le6KALXyleUcntidZw2u4OfCXRIAnN3zO/rjFerM0opupA+f2SElvARHphgDxxEXbG2VIU7aq4aohB1uAp6+RZOuZWk+oQyA7EIP39r4ZG8bOjoDfco7TEu/slnIYT3oxld8Yvr9aKBLqw9oxaHiiO7VVRkRrzvTSdykARi2OMqan7hGuGFed9Jrt5wywCwOaCTF/zaYposi0K4S1t7tIW8nqCVULnObxlZ/SerIX+NlC26h8uS6pFrp5OP4nCRPbVw9hliiF48fwJABH0EA1km1TI7q4wpnPDn5GaEsWqbh8IkyEVC4lMqm+Al0NGDCQlY6CKozu4Cm7Ty9upVyv5V35hnKYY+ZoJiC2HfuVgP+D/ZsZrrn0B04pdlTVyJdzBb7OiHsKzp7MiFKUF7O+EMBVpmTAUub3ZAhser3uuzm/3V57VDPnJI7NCM7Uwa0UyWT68kUj3AW+6XT5lXbbYQ53dgowYtbsqWWiwlyNdSoObVYVNskxPJFXXUssxPaWunu6a4JMihQ/neFbBlTBeNkDBsC9vEfeaiaEGwA2DS+lvvpzo3qmTuQKbAGCDMn7QPb7S7kpu9DVqLqlNYbT7REReosMxaRqOQLv1vIKn45thOZ2KVTqN8HY60RXNY0SuMQzbAwISYwW88CRXMS2TDvYP4sO03/Rn9TdZCYbapiRmA7nsjzuk2b3UmIlxnu29UaqnvwwcnEsTsDHLq4gyu4EU/wuKb0LXKQDfW31LO6SMt3bbDp/El/ZpTI13BpRwPSCIpQZrARYohoVs7Da91yYuJQUBgPNHsa3XDb/d9PH8hnJIA/0Vfascl+/47MP3w X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 257f7f71-95f9-4601-e60d-08d90bd4f91d X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:19.2133 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: wTWmLG+LqckUMj+QQyX1iwMibOoifXY8RsdTnM+sDYnaqD4gI2IGprUYtSjYdL6nAPtYtT4Zh6SCLERX8YxYHA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2688 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org While resolving the RMP page fault, we may run into cases where the page level between the RMP entry and TDP does not match and the 2M RMP entry must be split into 4K RMP entries. Or a 2M TDP page need to be broken into multiple of 4K pages. To keep the RMP and TDP page level in sync, we will zap the gfn range after splitting the pages in the RMP entry. The zap should force the TDP to gets rebuilt with the new page level. Signed-off-by: Brijesh Singh --- arch/x86/include/asm/kvm_host.h | 2 ++ arch/x86/kvm/mmu.h | 2 -- arch/x86/kvm/mmu/mmu.c | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index ad01fe9f4c43..7d4db88b94f3 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1481,6 +1481,8 @@ void kvm_mmu_zap_all(struct kvm *kvm); void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen); unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm); void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long kvm_nr_mmu_pages); +void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end); + int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3); bool pdptrs_changed(struct kvm_vcpu *vcpu); diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h index 147e76ab1536..eec62011bb2e 100644 --- a/arch/x86/kvm/mmu.h +++ b/arch/x86/kvm/mmu.h @@ -228,8 +228,6 @@ static inline u8 permission_fault(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, return -(u32)fault & errcode; } -void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end); - int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu); int kvm_mmu_post_init_vm(struct kvm *kvm); diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index 956bbc747167..d484f9e8a6b5 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -5657,6 +5657,7 @@ static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, return need_tlb_flush; } +EXPORT_SYMBOL_GPL(kvm_zap_gfn_range); void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, const struct kvm_memory_slot *memslot) From patchwork Fri Apr 30 12:38:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233363 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02289C43460 for ; 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Signed-off-by: Brijesh Singh --- arch/x86/include/asm/kvm_host.h | 2 ++ arch/x86/kvm/mmu/mmu.c | 20 ++++++++++++ arch/x86/kvm/svm/sev.c | 57 +++++++++++++++++++++++++++++++++ arch/x86/kvm/svm/svm.c | 1 + arch/x86/kvm/svm/svm.h | 2 ++ 5 files changed, 82 insertions(+) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 7d4db88b94f3..8413220f3a83 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1391,6 +1391,8 @@ struct kvm_x86_ops { void (*vcpu_deliver_sipi_vector)(struct kvm_vcpu *vcpu, u8 vector); void *(*alloc_apic_backing_page)(struct kvm_vcpu *vcpu); int (*get_tdp_max_page_level)(struct kvm_vcpu *vcpu, gpa_t gpa, int max_level); + int (*handle_rmp_page_fault)(struct kvm_vcpu *vcpu, gpa_t gpa, kvm_pfn_t pfn, + int level, u64 error_code); }; struct kvm_x86_nested_ops { diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index d484f9e8a6b5..0a2bf3c2af14 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -5096,6 +5096,18 @@ static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, write_unlock(&vcpu->kvm->mmu_lock); } +static int handle_rmp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u64 error_code) +{ + kvm_pfn_t pfn; + int level; + + if (unlikely(!kvm_mmu_get_tdp_walk(vcpu, gpa, &pfn, &level))) + return RET_PF_RETRY; + + kvm_x86_ops.handle_rmp_page_fault(vcpu, gpa, pfn, level, error_code); + return RET_PF_RETRY; +} + int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code, void *insn, int insn_len) { @@ -5112,6 +5124,14 @@ int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code, goto emulate; } + if (unlikely(error_code & PFERR_GUEST_RMP_MASK)) { + r = handle_rmp_page_fault(vcpu, cr2_or_gpa, error_code); + if (r == RET_PF_RETRY) + return 1; + else + return r; + } + if (r == RET_PF_INVALID) { r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa, lower_32_bits(error_code), false); diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index bd71ece35597..8e4783e105b9 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -3428,3 +3428,60 @@ int sev_get_tdp_max_page_level(struct kvm_vcpu *vcpu, gpa_t gpa, int max_level) return min_t(uint32_t, level, max_level); } + +int snp_handle_rmp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, kvm_pfn_t pfn, + int level, u64 error_code) +{ + struct rmpentry *e; + int rlevel, rc = 0; + bool private; + gfn_t gfn; + + e = snp_lookup_page_in_rmptable(pfn_to_page(pfn), &rlevel); + if (!e) + return 1; + + private = !!(error_code & PFERR_GUEST_ENC_MASK); + + /* + * See APM section 15.36.11 on how to handle the RMP fault for the large pages. + * + * npt rmp access action + * -------------------------------------------------- + * 4k 2M C=1 psmash + * x x C=1 if page is not private then add a new RMP entry + * x x C=0 if page is private then make it shared + * 2M 4k C=x zap + */ + if ((error_code & PFERR_GUEST_SIZEM_MASK) || + ((level == PG_LEVEL_4K) && (rlevel == PG_LEVEL_2M) && private)) { + rc = snp_rmptable_psmash(vcpu, pfn); + goto zap_gfn; + } + + /* + * If it's a private access, and the page is not assigned in the RMP table, create a + * new private RMP entry. + */ + if (!rmpentry_assigned(e) && private) { + rc = snp_make_page_private(vcpu, gpa, pfn, PG_LEVEL_4K); + goto zap_gfn; + } + + /* + * If it's a shared access, then make the page shared in the RMP table. + */ + if (rmpentry_assigned(e) && !private) + rc = snp_make_page_shared(vcpu, gpa, pfn, PG_LEVEL_4K); + +zap_gfn: + /* + * Now that we have updated the RMP pagesize, zap the existing rmaps for + * large entry ranges so that nested page table gets rebuilt with the updated RMP + * pagesize. + */ + gfn = gpa_to_gfn(gpa) & ~(KVM_PAGES_PER_HPAGE(PG_LEVEL_2M) - 1); + kvm_zap_gfn_range(vcpu->kvm, gfn, gfn + 512); + + return 0; +} diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 81a83a7c1229..fd58f7358386 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4618,6 +4618,7 @@ static struct kvm_x86_ops svm_x86_ops __initdata = { .alloc_apic_backing_page = svm_alloc_apic_backing_page, .get_tdp_max_page_level = sev_get_tdp_max_page_level, + .handle_rmp_page_fault = snp_handle_rmp_page_fault, }; static struct kvm_x86_init_ops svm_init_ops __initdata = { diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 243503fa3fd6..011374e6b2b2 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -575,6 +575,8 @@ void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector); void sev_es_prepare_guest_switch(struct vcpu_svm *svm, unsigned int cpu); struct page *snp_safe_alloc_page(struct kvm_vcpu *vcpu); int sev_get_tdp_max_page_level(struct kvm_vcpu *vcpu, gpa_t gpa, int max_level); +int snp_handle_rmp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, kvm_pfn_t pfn, + int level, u64 error_code); /* vmenter.S */ From patchwork Fri Apr 30 12:38:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brijesh Singh X-Patchwork-Id: 12233365 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MSGID_FROM_MTA_HEADER,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6711DC433ED for ; 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dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN6PR12MB2688.namprd12.prod.outlook.com (2603:10b6:805:6f::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4087.35; Fri, 30 Apr 2021 12:39:50 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::9898:5b48:a062:db94%6]) with mapi id 15.20.4065.027; Fri, 30 Apr 2021 12:39:50 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 36/37] KVM: SVM: Provide support for SNP_GUEST_REQUEST NAE event Date: Fri, 30 Apr 2021 07:38:21 -0500 Message-Id: <20210430123822.13825-37-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: Swv9rZhmgFnc0SxzwWNDbPuk255SdUeIeXg+kboZ5lVU/OPk/yWD+Jn1phOlw5cDZQYmwgDa1duEAV/fc7bTCTaeCiYu4FWuArXggWAePQvXYWGtpWx9bnu7HTAnNp/Y0fdR00tbdpuvCoK6eg1d0ny9w29d+YX/AR24GZoNDE47EWt5ddEdSin5A0yM4Gsbb54q8oZVsE3JTfafCmKAKf9r99kETn/jO12VJ0noAx9iNsIHbDyvXIyxw+Ob4kB/E3hhREsDSRa5zpDAY5MuZjlcj9nTddYyz7eIAZHu77FbIYQwDepR6gEjq7g0DOIsjA3Ole0pnqmar8bWmfjlslppbGMNBCz42fC3NxFsctPyEu94UC9OipQEdfypYGY00mdrOcbsOiXXJKCBBs3taC0Ik7IpQlor4AF1UB0WJq1HHDDV20Us87QMZXs7sRdtT/UOMBlWFsPJ2qC/km+1UjgnwP+SH1rQUlZLigN33X+d1fmDV1GX3QYOjLQt/PPYByPff5SekrewR6eqliQnOmUSjqDHmom+/Qm/FFvMDN4Kkw4pJfbUdIMqkLT/SDqzsxD3jn/sRjuGRvbfnJn3xZJBy4/Zke8XGhoT4H7Y4Z+U/yOwppGvW8mFY58uqrXTyzReAzGQ+TZwj7PmVn0C2tcWPVV0TL9pkB/Mf/KzK/PjiupKD13NKUMhGBOk872lAsJvqf3hhQ0zkUm4hofAI5YoKogf+z6c+RHtiIKptVPVXv43JzYrbrfVLyFVW627CmZjTrHTb7y1kcsK+hek/AFuGf29GpGMYT1nc1WVQFIhxY3KzFm7wFM0czJfww6i9Eb9JhOoDAOlGCSydTTbnewg1udAU7S4lz5c9V5mPeO4bC01XeI3eeNEmqhbatmBDg3Zjo35uQQbhU4r2bGYvLaLCkiD7Sa/j0ibEaaOqy/t3jUZKv0XtXBwIjaitTFXOPx9kOaW90tUvnZHfSUiSZTwBHi9B+cOcJ5/uc91j0rasNjeUcoKo7T2YgUG2MYxOwTKLAlrIzPPby8WfdxJn7Xa+edPIf3n0ylsdP5Exeum95d2Xwc4bFuO4SZtclJqgEow9ENEKLeBX4eduliGGgpv3O9nrR92xNQwqZ0U6JNSHXJer71cx11mUmvWHSG/AvypGLAsic1H/fQayiPYO74HR9FbJk6a48a68M6jlLvD1AC71Yi2ua3pq45cgwhghB4x3IoDM35ikfemxWaInOBcHE4QpUmf0LEajvIajktGyuJHl8IBzVtQB4CyQkr0Yk/kTD3NAmy88Ti2PFgaPG/SGbwmbyy/HdR5VnGWgEHZe7OwMZYoRSXO0gsZKDEP X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 60b8c46a-73ac-4ba6-2947-08d90bd4f9f4 X-MS-Exchange-CrossTenant-AuthSource: SN6PR12MB2718.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2021 12:39:20.6145 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 7GvnWTv4rf1p5NNbbhyd6Eu103rp+7f/dhbOONAB3UctuHHQi1WuE3jvG2UeBy+R+TykUof11gzLM23/W/Q05g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2688 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Version 2 of GHCB specification added the support SNP Guest Request Message NAE event. The event allows for an SEV-SNP guest to make request to the SEV-SNP firmware through hypervisor using the SNP_GUEST_REQUEST API define in the SEV-SNP firmware specification. The SNP_GUEST_REQUEST requires two unique pages, one page for the request and one page for the response. The response page need to be in the firmware state. The GHCB specification says that both the pages need to be in the hypervisor state but before executing the SEV-SNP command the response page need to be in the firmware state. In order to minimize the page state transition during the command handling, pre-allocate a firmware page on guest creation. Use the pre-allocated firmware page to complete the command execution and copy the result in the guest response page. Ratelimit the handling of SNP_GUEST_REQUEST NAE to avoid the possibility of a guest creating a denial of service attack aginst the SNP firmware. Signed-off-by: Brijesh Singh --- arch/x86/kvm/svm/sev.c | 106 +++++++++++++++++++++++++++++++++++++++-- arch/x86/kvm/svm/svm.h | 3 ++ 2 files changed, 106 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 8e4783e105b9..da4158da644b 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -1517,6 +1518,7 @@ static int sev_receive_finish(struct kvm *kvm, struct kvm_sev_cmd *argp) static void *snp_context_create(struct kvm *kvm, struct kvm_sev_cmd *argp) { + struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; struct sev_data_snp_gctx_create data = {}; void *context; int rc; @@ -1526,14 +1528,24 @@ static void *snp_context_create(struct kvm *kvm, struct kvm_sev_cmd *argp) if (!context) return NULL; - data.gctx_paddr = __psp_pa(context); - rc = __sev_issue_cmd(argp->sev_fd, SEV_CMD_SNP_GCTX_CREATE, &data, &argp->error); - if (rc) { + /* Allocate a firmware buffer used during the guest command handling. */ + sev->snp_resp_page = snp_alloc_firmware_page(GFP_KERNEL_ACCOUNT); + if (!sev->snp_resp_page) { snp_free_firmware_page(context); return NULL; } + data.gctx_paddr = __psp_pa(context); + rc = __sev_issue_cmd(argp->sev_fd, SEV_CMD_SNP_GCTX_CREATE, &data, &argp->error); + if (rc) + goto e_free; + return context; + +e_free: + snp_free_firmware_page(context); + snp_free_firmware_page(sev->snp_resp_page); + return NULL; } static int snp_bind_asid(struct kvm *kvm, int *error) @@ -1601,6 +1613,9 @@ static int snp_launch_start(struct kvm *kvm, struct kvm_sev_cmd *argp) if (rc) goto e_free_context; + /* Used for rate limiting SNP guest message request, use the default settings */ + ratelimit_default_init(&sev->snp_guest_msg_rs); + return 0; e_free_context: @@ -2197,6 +2212,9 @@ static int snp_decommission_context(struct kvm *kvm) snp_free_firmware_page(sev->snp_context); sev->snp_context = NULL; + /* Free the response page. */ + snp_free_firmware_page(sev->snp_resp_page); + return 0; } @@ -2642,6 +2660,7 @@ static int sev_es_validate_vmgexit(struct vcpu_svm *svm) case SVM_VMGEXIT_UNSUPPORTED_EVENT: case SVM_VMGEXIT_HYPERVISOR_FEATURES: case SVM_VMGEXIT_SNP_PAGE_STATE_CHANGE: + case SVM_VMGEXIT_SNP_GUEST_REQUEST: break; default: goto vmgexit_err; @@ -2996,6 +3015,81 @@ static unsigned long snp_handle_page_state_change(struct vcpu_svm *svm, struct g return rc; } +static void snp_handle_guest_request(struct vcpu_svm *svm, struct ghcb *ghcb, + gpa_t req_gpa, gpa_t resp_gpa) +{ + struct sev_data_snp_guest_request data = {}; + struct kvm_vcpu *vcpu = &svm->vcpu; + struct kvm *kvm = vcpu->kvm; + kvm_pfn_t req_pfn, resp_pfn; + struct kvm_sev_info *sev; + int rc, err = 0; + + if (!sev_snp_guest(vcpu->kvm)) { + rc = -ENODEV; + goto e_fail; + } + + sev = &to_kvm_svm(kvm)->sev_info; + + if (!__ratelimit(&sev->snp_guest_msg_rs)) { + pr_info_ratelimited("svm: too many guest message requests\n"); + rc = -EAGAIN; + goto e_fail; + } + + if (!IS_ALIGNED(req_gpa, PAGE_SIZE) || !IS_ALIGNED(resp_gpa, PAGE_SIZE)) { + pr_err("svm: guest request (%#llx) or response (%#llx) is not page aligned\n", + req_gpa, resp_gpa); + goto e_term; + } + + req_pfn = gfn_to_pfn(kvm, gpa_to_gfn(req_gpa)); + if (is_error_noslot_pfn(req_pfn)) { + pr_err("svm: guest request invalid gpa=%#llx\n", req_gpa); + goto e_term; + } + + resp_pfn = gfn_to_pfn(kvm, gpa_to_gfn(resp_gpa)); + if (is_error_noslot_pfn(resp_pfn)) { + pr_err("svm: guest response invalid gpa=%#llx\n", resp_gpa); + goto e_term; + } + + data.gctx_paddr = __psp_pa(sev->snp_context); + data.req_paddr = __sme_set(req_pfn << PAGE_SHIFT); + data.res_paddr = __psp_pa(sev->snp_resp_page); + + mutex_lock(&kvm->lock); + + rc = sev_issue_cmd(kvm, SEV_CMD_SNP_GUEST_REQUEST, &data, &err); + if (rc) { + mutex_unlock(&kvm->lock); + + /* If we have a firmware error code then use it. */ + if (err) + rc = err; + + goto e_fail; + } + + /* Copy the response after the firmware returns success. */ + rc = kvm_write_guest(kvm, resp_gpa, sev->snp_resp_page, PAGE_SIZE); + + mutex_unlock(&kvm->lock); + +e_fail: + ghcb_set_sw_exit_info_2(ghcb, rc); + return; + +e_term: + ghcb_set_sw_exit_info_1(ghcb, 1); + ghcb_set_sw_exit_info_2(ghcb, + X86_TRAP_GP | + SVM_EVTINJ_TYPE_EXEPT | + SVM_EVTINJ_VALID); +} + static int sev_handle_vmgexit_msr_protocol(struct vcpu_svm *svm) { struct vmcb_control_area *control = &svm->vmcb->control; @@ -3245,6 +3339,12 @@ int sev_handle_vmgexit(struct kvm_vcpu *vcpu) ghcb_set_sw_exit_info_2(ghcb, rc); break; } + case SVM_VMGEXIT_SNP_GUEST_REQUEST: { + snp_handle_guest_request(svm, ghcb, control->exit_info_1, control->exit_info_2); + + ret = 1; + break; + } case SVM_VMGEXIT_UNSUPPORTED_EVENT: vcpu_unimpl(vcpu, "vmgexit: unsupported event - exit_info_1=%#llx, exit_info_2=%#llx\n", diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 011374e6b2b2..ecd466721c23 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -18,6 +18,7 @@ #include #include #include +#include #include #include @@ -68,6 +69,8 @@ struct kvm_sev_info { struct kvm *enc_context_owner; /* Owner of copied encryption context */ struct misc_cg *misc_cg; /* For misc cgroup accounting */ void *snp_context; /* SNP guest context page */ + void *snp_resp_page; /* SNP guest response page */ + struct ratelimit_state snp_guest_msg_rs; /* Rate limit the SNP guest message */ }; struct kvm_svm { From patchwork Fri Apr 30 12:38:22 2021 Content-Type: text/plain; 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Fri, 30 Apr 2021 12:39:50 +0000 From: Brijesh Singh To: x86@kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: tglx@linutronix.de, bp@alien8.de, jroedel@suse.de, thomas.lendacky@amd.com, pbonzini@redhat.com, mingo@redhat.com, dave.hansen@intel.com, rientjes@google.com, seanjc@google.com, peterz@infradead.org, hpa@zytor.com, tony.luck@intel.com, Brijesh Singh Subject: [PATCH Part2 RFC v2 37/37] KVM: SVM: Advertise the SEV-SNP feature support Date: Fri, 30 Apr 2021 07:38:22 -0500 Message-Id: <20210430123822.13825-38-brijesh.singh@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210430123822.13825-1-brijesh.singh@amd.com> References: <20210430123822.13825-1-brijesh.singh@amd.com> X-Originating-IP: [165.204.77.1] X-ClientProxiedBy: SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) To SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sbrijesh-desktop.amd.com (165.204.77.1) by SN4PR0501CA0089.namprd05.prod.outlook.com (2603:10b6:803:22::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.8 via Frontend Transport; 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Signed-off-by: Brijesh Singh --- arch/x86/kvm/svm/svm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index ecd466721c23..f344ffd5afd6 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -553,7 +553,7 @@ void svm_vcpu_unblocking(struct kvm_vcpu *vcpu); #define GHCB_VERSION_MAX 2ULL #define GHCB_VERSION_MIN 1ULL -#define GHCB_HV_FEATURES_SUPPORTED 0 +#define GHCB_HV_FEATURES_SUPPORTED GHCB_HV_FEATURES_SNP extern unsigned int max_sev_asid;