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Tue, 4 May 2021 03:22:43 -0700 Envelope-to: git@xilinx.com, mdf@kernel.org, trix@redhat.com, robh+dt@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, linus.walleij@linaro.org, zou_wei@huawei.com, linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, chinnikishore369@gmail.com Received: from [10.140.6.60] (port=35290 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1ldsCO-000192-RO; Tue, 04 May 2021 03:22:41 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , , , , , , , , , Subject: [RFC PATCH 1/4] drivers: firmware: Add user encrypted key load API support Date: Tue, 4 May 2021 15:52:24 +0530 Message-ID: <20210504102227.15475-2-nava.manne@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504102227.15475-1-nava.manne@xilinx.com> References: <20210504102227.15475-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 38e6d033-e19c-4990-18ed-08d90ee69760 X-MS-TrafficTypeDiagnostic: MWHPR02MB2638: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:1775; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2021 10:22:59.3090 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 38e6d033-e19c-4990-18ed-08d90ee69760 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT040.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR02MB2638 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org This patch adds user encrypted key load API to support User key encrypted images loading use cases from Linux. Signed-off-by: Nava kishore Manne --- drivers/firmware/xilinx/zynqmp.c | 17 +++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 7 +++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 15b138326ecc..2fa5687a75f8 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -787,6 +787,23 @@ int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags) } EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_load); +/** + * zynqmp_pm_fpga_key_load - Perform to load the bitstream encrypted key + * @address: Address to write + * @size: encrypted key size + * + * This function provides access to pmufw. To transfer + * the required encrypted key. + * + * Return: Returns status, either success or error+reason + */ +int zynqmp_pm_fpga_enc_key_load(const u64 address, const u32 size) +{ + return zynqmp_pm_invoke_fn(PM_ENC_KEY_LOAD, lower_32_bits(address), + upper_32_bits(address), size, 0, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_enc_key_load); + /** * zynqmp_pm_fpga_get_status - Read value from PCAP status register * @value: Value to read diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 9d1a5c175065..7aa9ad40ff53 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -91,6 +91,7 @@ enum pm_api_id { PM_CLOCK_GETPARENT = 44, PM_SECURE_AES = 47, PM_FEATURE_CHECK = 63, + PM_ENC_KEY_LOAD = 64, }; /* PMU-FW return status codes */ @@ -411,6 +412,7 @@ int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param, u32 *value); int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, u32 value); +int zynqmp_pm_fpga_enc_key_load(const u64 address, const u32 size); #else static inline int zynqmp_pm_get_api_version(u32 *version) { @@ -622,6 +624,11 @@ static inline int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, { return -ENODEV; } + +static inline int zynqmp_pm_fpga_enc_key_load(const u64 address, const u32 size) +{ + return -ENODEV; +} #endif #endif /* __FIRMWARE_ZYNQMP_H__ */ From patchwork Tue May 4 10:22:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Nava kishore Manne X-Patchwork-Id: 12237921 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11FEEC433ED for ; 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Tue, 04 May 2021 03:22:46 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , , , , , , , , , Subject: [RFC PATCH 2/4] fpga: Add new properties to support user-key encrypted bitstream loading Date: Tue, 4 May 2021 15:52:25 +0530 Message-ID: <20210504102227.15475-3-nava.manne@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504102227.15475-1-nava.manne@xilinx.com> References: <20210504102227.15475-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e4a67f74-eb95-4564-6a4e-08d90ee69ad1 X-MS-TrafficTypeDiagnostic: BN7PR02MB4993: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fcZbw9ZFPLaiZ5AR8rRtvTjW5nkglqe2prp6kDSYpkMsWmzYxFzDO7FnOJlldl13RF1ry0ydXg4PROzcbZyqJN2PaXuhSE07fZTNjibGbCLwpbXQ0gbL77fdMEQiWv5NNFfwjKbi9IcDZhSUYRJe8fTTPB1UTDGpYVLd78BSqdlLmma203usiMCu6Syf6855dqiFSD+iTfl3Gce4uK7YIEKhAKJGy3JssMmddJGmOzUcphy9E6bW4UxINOv0koIkZd2U7fRfzDv8j0C+KU+/r7QbkUeY3a52HqErql+TWyZm1vsVVmgzVT0JXh9/UoFlL2H11Z3pGKUQ+MGsm6P2ZuFPIf6OFzoNtlvOeu9KUePnGe6KnoFmnqtuURC5JhkZ6NXZ219yIQvgZZeDXGjuaeOXJ/MnD8iYmzn+a+KwpcOSm61+UUfQROjy6I3mzJhixbKaNsI6G8/LALY+KkMaAVS5snoyGHWIGOLu6tQYzx92Am2HzSWXjBBMKx7iCRY8bhwKkLDTT1XbUSgMueOZ5REdNDIOXSnhPFT/mvlToG+YhkuGvFwE0dW7xPVG+dcHP5OCU68GX4XIj13n7H1rXmLtCXkBfwMSTvrjt15t7Ojb8y7sr7qDWchek+Gy4gdJBqVvnYeg357d/SZUZ4QBuOfBb/SghrmHEPRrTL17pHnP65JmJvVDhMyqVKah8AL4/McLlnq6YFjzRBmKj4H6hnVZPqw+Lyq38+0Ih31zTYaff8+v1i/e9uxUxwiDRYv4 X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch02.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(4636009)(346002)(39850400004)(396003)(376002)(136003)(46966006)(36840700001)(8676002)(82310400003)(9786002)(82740400003)(7416002)(83380400001)(8936002)(6666004)(7696005)(36860700001)(2616005)(26005)(186003)(110136005)(70586007)(70206006)(5660300002)(36756003)(921005)(336012)(426003)(47076005)(2906002)(356005)(36906005)(316002)(478600001)(7636003)(1076003)(102446001)(83996005)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2021 10:23:05.0898 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e4a67f74-eb95-4564-6a4e-08d90ee69ad1 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT015.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR02MB4993 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org This patch Adds ‘encrypted-key-name’ and ‘encrypted-user-key-fpga-config’ properties to support user-key encrypted bitstream loading use case. Signed-off-by: Nava kishore Manne --- Documentation/devicetree/bindings/fpga/fpga-region.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.txt b/Documentation/devicetree/bindings/fpga/fpga-region.txt index d787d57491a1..957dc6cbcd9e 100644 --- a/Documentation/devicetree/bindings/fpga/fpga-region.txt +++ b/Documentation/devicetree/bindings/fpga/fpga-region.txt @@ -177,6 +177,9 @@ Optional properties: it indicates that the FPGA has already been programmed with this image. If this property is in an overlay targeting a FPGA region, it is a request to program the FPGA with that image. +- encrypted-key-name : should contain the name of an encrypted key file located + on the firmware search path. It will be used to decrypt the FPGA image + file. - fpga-bridges : should contain a list of phandles to FPGA Bridges that must be controlled during FPGA programming along with the parent FPGA bridge. This property is optional if the FPGA Manager handles the bridges. @@ -187,6 +190,8 @@ Optional properties: - external-fpga-config : boolean, set if the FPGA has already been configured prior to OS boot up. - encrypted-fpga-config : boolean, set if the bitstream is encrypted +- encrypted-user-key-fpga-config : boolean, set if the bitstream is encrypted + with user key. - region-unfreeze-timeout-us : The maximum time in microseconds to wait for bridges to successfully become enabled after the region has been programmed. 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Tue, 4 May 2021 03:22:52 -0700 Envelope-to: git@xilinx.com, mdf@kernel.org, trix@redhat.com, robh+dt@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, linus.walleij@linaro.org, zou_wei@huawei.com, linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, chinnikishore369@gmail.com Received: from [10.140.6.60] (port=35290 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1ldsCZ-000192-Ej; Tue, 04 May 2021 03:22:51 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , , , , , , , , , Subject: [RFC PATCH 3/4] drivers: fpga: Add user-key encrypted FPGA Image loading support Date: Tue, 4 May 2021 15:52:26 +0530 Message-ID: <20210504102227.15475-4-nava.manne@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504102227.15475-1-nava.manne@xilinx.com> References: <20210504102227.15475-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9c189947-b1e2-4d56-56a5-08d90ee69706 X-MS-TrafficTypeDiagnostic: MWHPR02MB2399: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:5236; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2021 10:22:58.7868 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9c189947-b1e2-4d56-56a5-08d90ee69706 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT040.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR02MB2399 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org This patch adds user-key encrypted FPGA Image loading support to the framework. Signed-off-by: Nava kishore Manne --- drivers/fpga/fpga-mgr.c | 15 +++++++++++++++ drivers/fpga/of-fpga-region.c | 13 +++++++++++++ include/linux/fpga/fpga-mgr.h | 7 +++++++ 3 files changed, 35 insertions(+) diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c index b85bc47c91a9..3e79ab8cc86f 100644 --- a/drivers/fpga/fpga-mgr.c +++ b/drivers/fpga/fpga-mgr.c @@ -325,6 +325,7 @@ static int fpga_mgr_firmware_load(struct fpga_manager *mgr, const char *image_name) { struct device *dev = &mgr->dev; + const struct firmware *enc_fw; const struct firmware *fw; int ret; @@ -339,8 +340,22 @@ static int fpga_mgr_firmware_load(struct fpga_manager *mgr, return ret; } + if (info->encrypted_key_name) { + ret = request_firmware(&enc_fw, info->encrypted_key_name, dev); + if (ret) { + mgr->state = FPGA_MGR_STATE_FIRMWARE_REQ_ERR; + dev_err(dev, "Error requesting firmware %s\n", + info->encrypted_key_name); + return ret; + } + info->enc_key_buf = enc_fw->data; + info->enc_key_buf_size = enc_fw->size; + } + ret = fpga_mgr_buf_load(mgr, info, fw->data, fw->size); + if (info->encrypted_key_name) + release_firmware(enc_fw); release_firmware(fw); return ret; diff --git a/drivers/fpga/of-fpga-region.c b/drivers/fpga/of-fpga-region.c index e405309baadc..19faa463d96e 100644 --- a/drivers/fpga/of-fpga-region.c +++ b/drivers/fpga/of-fpga-region.c @@ -195,6 +195,7 @@ static struct fpga_image_info *of_fpga_region_parse_ov( { struct device *dev = ®ion->dev; struct fpga_image_info *info; + const char *encrypted_key_name; const char *firmware_name; int ret; @@ -228,6 +229,18 @@ static struct fpga_image_info *of_fpga_region_parse_ov( if (of_property_read_bool(overlay, "encrypted-fpga-config")) info->flags |= FPGA_MGR_ENCRYPTED_BITSTREAM; + if (of_property_read_bool(overlay, "encrypted-user-key-fpga-config")) { + if (!of_property_read_string(overlay, "encrypted-key-name", + &encrypted_key_name)) { + info->encrypted_key_name = + devm_kstrdup(dev, encrypted_key_name, GFP_KERNEL); + if (!info->encrypted_key_name) + return ERR_PTR(-ENOMEM); + } + + info->flags |= FPGA_MGR_ENCRYPTED_USER_KEY_BITSTREAM; + } + if (!of_property_read_string(overlay, "firmware-name", &firmware_name)) { info->firmware_name = devm_kstrdup(dev, firmware_name, diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h index 2bc3030a69e5..ac86f4398c3c 100644 --- a/include/linux/fpga/fpga-mgr.h +++ b/include/linux/fpga/fpga-mgr.h @@ -67,12 +67,15 @@ enum fpga_mgr_states { * %FPGA_MGR_BITSTREAM_LSB_FIRST: SPI bitstream bit order is LSB first * * %FPGA_MGR_COMPRESSED_BITSTREAM: FPGA bitstream is compressed + * %FPGA_MGR_ENCRYPTED_USER_KEY_BITSTREAM: indicates bitstream is encrypted + * with user-key */ #define FPGA_MGR_PARTIAL_RECONFIG BIT(0) #define FPGA_MGR_EXTERNAL_CONFIG BIT(1) #define FPGA_MGR_ENCRYPTED_BITSTREAM BIT(2) #define FPGA_MGR_BITSTREAM_LSB_FIRST BIT(3) #define FPGA_MGR_COMPRESSED_BITSTREAM BIT(4) +#define FPGA_MGR_ENCRYPTED_USER_KEY_BITSTREAM BIT(5) /** * struct fpga_image_info - information specific to a FPGA image @@ -82,6 +85,7 @@ enum fpga_mgr_states { * @config_complete_timeout_us: maximum time for FPGA to switch to operating * status in the write_complete op. * @firmware_name: name of FPGA image firmware file + * @encrypted_key_name: name of the FPGA image encrypted user-key file * @sgt: scatter/gather table containing FPGA image * @buf: contiguous buffer containing FPGA image * @count: size of buf @@ -95,8 +99,11 @@ struct fpga_image_info { u32 disable_timeout_us; u32 config_complete_timeout_us; char *firmware_name; + char *encrypted_key_name; struct sg_table *sgt; + const char *enc_key_buf; const char *buf; + size_t enc_key_buf_size; size_t count; int region_id; struct device *dev; From patchwork Tue May 4 10:22:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nava kishore Manne X-Patchwork-Id: 12237923 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68593C43460 for ; Tue, 4 May 2021 10:23:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 414BF61176 for ; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 May 2021 10:23:12.8275 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6502a95d-6585-4c42-f0d4-08d90ee69f6d X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BN1NAM02FT015.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR02MB2417 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org This patch adds support to load the user-key encrypted FPGA Image loading to the Xilinx ZynqMP Soc. Signed-off-by: Nava kishore Manne --- drivers/fpga/zynqmp-fpga.c | 24 ++++++++++++++++++++++-- include/linux/firmware/xlnx-zynqmp.h | 2 ++ 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c index 125743c9797f..565ebe9e1610 100644 --- a/drivers/fpga/zynqmp-fpga.c +++ b/drivers/fpga/zynqmp-fpga.c @@ -22,6 +22,8 @@ */ struct zynqmp_fpga_priv { struct device *dev; + const char *key_buf; + size_t key_size; u32 flags; }; @@ -33,6 +35,8 @@ static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr, priv = mgr->priv; priv->flags = info->flags; + priv->key_buf = info->enc_key_buf; + priv->key_size = info->enc_key_buf_size; return 0; } @@ -41,9 +45,9 @@ static int zynqmp_fpga_ops_write(struct fpga_manager *mgr, const char *buf, size_t size) { struct zynqmp_fpga_priv *priv; - dma_addr_t dma_addr; + dma_addr_t dma_addr, key_addr; u32 eemi_flags = 0; - char *kbuf; + char *kbuf, *key_kbuf; int ret; priv = mgr->priv; @@ -54,13 +58,29 @@ static int zynqmp_fpga_ops_write(struct fpga_manager *mgr, memcpy(kbuf, buf, size); + if (priv->flags & FPGA_MGR_ENCRYPTED_USER_KEY_BITSTREAM) { + eemi_flags |= XILINX_ZYNQMP_PM_FPGA_ENC_USER_KEY; + key_kbuf = dma_alloc_coherent(priv->dev, size, &key_addr, + GFP_KERNEL); + if (!key_kbuf) + return -ENOMEM; + memcpy(key_kbuf, priv->key_buf, priv->key_size); + } + wmb(); /* ensure all writes are done before initiate FW call */ if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG) eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL; + if (priv->flags & FPGA_MGR_ENCRYPTED_USER_KEY_BITSTREAM) + ret = zynqmp_pm_fpga_enc_key_load(key_addr, priv->key_size); + ret = zynqmp_pm_fpga_load(dma_addr, size, eemi_flags); + if (priv->flags & FPGA_MGR_ENCRYPTED_USER_KEY_BITSTREAM) + dma_free_coherent(priv->dev, priv->key_size, + key_kbuf, key_addr); + dma_free_coherent(priv->dev, size, kbuf, dma_addr); return ret; diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 7aa9ad40ff53..a767386d930a 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -56,9 +56,11 @@ * Firmware FPGA Manager flags * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration + * XILINX_ZYNQMP_PM_FPGA_ENC_USER_KEY: User-key Encrypted FPGA reconfiguration */ #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0) +#define XILINX_ZYNQMP_PM_FPGA_ENC_USER_KEY BIT(3) enum pm_api_id { PM_GET_API_VERSION = 1,