From patchwork Mon Nov 26 18:45:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 10698921 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1A26613BF for ; Mon, 26 Nov 2018 18:46:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2BD9C2A3AD for ; Mon, 26 Nov 2018 18:46:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1FB2C2A3A0; Mon, 26 Nov 2018 18:46:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED,DKIM_VALID,FREEMAIL_FROM,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 928EE2A3AF for ; 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Tested on a imx6ul-evk. Signed-off-by: Fabio Estevam --- Hi, This is based on the following commit: commit 2acb79e15119512da9b6a49906840e7678cfb618 Author: Geert Uytterhoeven Date: Mon May 7 15:19:52 2018 +0200 ARM: dts: r8a7790: Correct mask for GIC PPI interrupts R-Car H2 (r8a7790) contains four Cortex-A15 and four Cortex-A7 cores, hence the second interrupt specifier cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(8)", to make sure interrupts can be delivered to all 8 processor cores. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman and the confirmation from Liviu Dudau that GIC_CPU_MASK_SIMPLE() should take the number of cores in the system as the argument: http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/315298.html arch/arm/boot/dts/imx6ul.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index c71d2d6..b8f5ef2 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -108,10 +108,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; interrupt-parent = <&intc>; status = "disabled"; }; From patchwork Mon Nov 26 18:45:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 10698923 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id CF17013AD for ; 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Mon, 26 Nov 2018 10:46:06 -0800 (PST) Received: from localhost.localdomain ([201.82.144.36]) by smtp.gmail.com with ESMTPSA id i33sm427489qtb.97.2018.11.26.10.46.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 26 Nov 2018 10:46:06 -0800 (PST) From: Fabio Estevam To: shawnguo@kernel.org Subject: [RFC 2/2] ARM: dts: imx7: Correct mask for GIC PPI interrupts Date: Mon, 26 Nov 2018 16:45:55 -0200 Message-Id: <1543257955-8910-2-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1543257955-8910-1-git-send-email-festevam@gmail.com> References: <1543257955-8910-1-git-send-email-festevam@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181126_104618_415801_50A4D256 X-CRM114-Status: GOOD ( 12.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marc.zyngier@arm.com, liviu.dudau@arm.com, linux-imx@nxp.com, kernel@pengutronix.de, Fabio Estevam , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The GIC_CPU_MASK_SIMPLE() macro should take as its argument the actual number of CPU cores the interrupt controller is wired to. i.MX7S contains a single Cortex-A7, hence the second interrupt specifier cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(1)". Likewise, i.MX7D contains two Cortex-A7 cores, so it should use "GIC_CPU_MASK_SIMPLE(2)" instead. Tested on a imx7s-warp. Signed-off-by: Fabio Estevam --- arch/arm/boot/dts/imx7d.dtsi | 9 +++++++++ arch/arm/boot/dts/imx7s.dtsi | 8 ++++---- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 826224b..b066749 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -24,6 +24,15 @@ }; }; + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + }; + cpu0_opp_table: opp-table { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 477901c..be02a10 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -160,10 +160,10 @@ timer { compatible = "arm,armv7-timer"; interrupt-parent = <&intc>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; }; soc {