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Miller" , Jakub Kicinski , netdev@vger.kernel.org, Maxime Coquelin , Joakim Zhang , sebastien.laveze@oss.nxp.com Cc: Yannick Vignon Subject: [PATCH net v1] net: stmmac: Do not enable RX FIFO overflow interrupts Date: Thu, 6 May 2021 16:33:12 +0200 Message-Id: <20210506143312.20784-1-yannick.vignon@oss.nxp.com> X-Mailer: git-send-email 2.17.1 X-Originating-IP: [81.1.10.98] X-ClientProxiedBy: AM0PR04CA0124.eurprd04.prod.outlook.com (2603:10a6:208:55::29) To DU2PR04MB8807.eurprd04.prod.outlook.com (2603:10a6:10:2e2::23) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from sopdpuats09.ea.freescale.net (81.1.10.98) by AM0PR04CA0124.eurprd04.prod.outlook.com (2603:10a6:208:55::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.25 via Frontend Transport; Thu, 6 May 2021 14:33:32 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 95fa544b-b3b1-4ab7-95fb-08d9109bed15 X-MS-TrafficTypeDiagnostic: DU2PR04MB8998: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 1LSfNwL7ZsxI8w2EOWCsFUYjIgMBy2lFwa4vyG8okntgVzVGt+ZHY9KW3+xpc1nfZ9GwFSlCEeJN+rCtQ7oj6jYTAiE29UGD/IfaIAFASXLAMeZxrQBsg/oNuuOXJKnCxsJvQbzhyRJucmlNZ2IZwzIfVIdoBbAsDOU8jFGL3ToGJ4DjM9I6lAtdtDkGm2pHZAUlQRmlMZBzz+cXb0Z8jHJtKJdtWbv0jqTnQF6e7qCv4WY6IbtPagzXfpf6Rt4VDh/IgainLuD7bi5LKoEz4TUnfkikaFP1ls2wEly4NzvbX5tZgGX3NzUi1ihF/R88v2G9Y7CtL6YDQd5/5muaarMg4TcFd2R90bfBNiFwei6oaKpMUOgU3mNL0XYgqbujEplcrOyMdq2vQTvqfMc5c+vlQ+iu53U5UPtHN8ehrBcGYU/M+mjBakTUZD1Ea+e05LX7xqJjisS5RbR4RUMUoiAXNYfWiwMxZ2UMvDcTvfeWzvNWSKMKfxSx27eXtib2MVOOIwkvEmnIgny5Lh24zfEHjY7DTqto1lv8W21gaI0sezhEait2F3D9fAjdAO9aHMQlEbXoz7pDdTNrWZ459dvjCa0o9fdWUPfVxc/3RUsNBbyY9hBTTGJ8HfU61Xol6V7m+W3WQAFT1rKD+TJ315Ijt3DK5vi5sKI4pjufyqc= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DU2PR04MB8807.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(376002)(366004)(396003)(39850400004)(136003)(346002)(86362001)(5660300002)(52116002)(6512007)(66946007)(4326008)(8676002)(316002)(956004)(2906002)(6666004)(6636002)(8936002)(478600001)(6486002)(83380400001)(44832011)(186003)(16526019)(6506007)(38350700002)(66556008)(26005)(2616005)(38100700002)(66476007)(1076003)(110136005)(3714002);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData: aTWz0n2Ax4HNNI7wyyX1oMdwB9hm74D27pc97GE562ftfKLnEzx9gNhzQ4K/wgJhjsu8kO1BgxCNA2LlIzHqotEBnj5XkM/azu2w+/K18CeExnIH+Q67LaiZ2QF6MncxFz5Vlj6LknK0v7BzR/eb0M61+PV8OucH4NBPSihBiBERgbVm7o8vntzpSW8n28cafKfQTh49SgzgJApzkWG7TC1yl1rjzQrA3LTaFofO0BsvXeufjsbn3UH5P0Z26i/XUQ8UbMqJefCBwKlTRcvHp94fox8MO9C6j4cVuXsqCTD5bDWtlm1KrMYHwGQcwTj6CUsoTVAn9rS/UkZth5jn0+So3+tDlTBPcGOjyg8jdp+jjyMpcwYBykSXQjh+QkcIrGPYU73XVapADDYfVR4VI1FaRbNB9RWNQRFpyN0BrsehXRvW8cKyOCrQa3N/p3sH5Pu2jFateQXWl0O8lP5xXvkSPBILLMFJmAzmIFsVBerrBiCBUTzlGtj14745fprzKEzy0scgVjeTF69v+3fu+vjSBaIALlDPnsemoJNG/yrkmh3f9jyG6fm47Kaf199VUiMaLmV7nAXWxWqEeEhGrr2McvKsnGEy7RuifLQox91fWIQYBYTqxDMQvQDPNYLNIpLpAszVhweWoWS5htDVzUOa/RGj6+2ve7O0zmK9F7YhwqxXJygdxanbwm7c43trFK6Hr1MPgykdll/4uJyZystsPctfqIB/HF/Q0fNPNPMk+AL0y9D+NptR0Uz+4t26sZwNcytqeDJ0qTsiJvwmKiPNfG8roRPnQdUYKqVSC73LZRZIQ0Q5pg4/au+noLjOCgqV2Fq6nIM9lizg0KJlMxFwFYGKUUfuo4r9i3gzJ+TZu9gYin1rBZGFwbfP9+Sfeggo/KRKogvLy3Eh3PdkooCsJPAlJ2ktHi2l27jca5SjwnalkviZsGGoZ3S46eeqHSsVm5XCd/dTXLS/h2kOYWCbNZEaghCC685uebXJ6RS3T+2qIWOjYgIERfwRkimKcqMNnnqbpi1mtvjQ+n1z86Tx+7UCP97L5BHEyWqNGtJkthPj/gFqMIo/y48DwLSLE2wm2+IA/esNU4RqBBZWJYBjpwSJAzSNjpaiAii/pEbfwOMdwieX90gD5gaJyeG0XDcCiB1/0deg3PNgWQL8Clet8MaOw87NSgbu/CdTZF3eVdHrHGnX31k3BO/cfiXSJiSo4To5HmkHcYWRD//D1Io0YqbgajqvI5Z/6buHeVPiDkj00RUKE2IY7ckIAYAEC8FnBFhsqLr3X65gmalUDoCVTzulXtLZgeytxgKBpSuIW/gns5EZB8Y2lvfVxLMx X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 95fa544b-b3b1-4ab7-95fb-08d9109bed15 X-MS-Exchange-CrossTenant-AuthSource: DU2PR04MB8807.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 May 2021 14:33:33.5486 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: /25zQLtvOAGvDAQEOzWR/TqMueAxouVUvIT+oTiUpcyBCt1FWBRoLNunVbJlmle8yR927Q5FwSKqlnYNmTUQUQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB8998 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Yannick Vignon The RX FIFO overflows when the system is not able to process all received packets and they start accumulating (first in the DMA queue in memory, then in the FIFO). An interrupt is then raised for each overflowing packet and handled in stmmac_interrupt(). This is counter-productive, since it brings the system (or more likely, one CPU core) to its knees to process the FIFO overflow interrupts. stmmac_interrupt() handles overflow interrupts by writing the rx tail ptr into the corresponding hardware register (according to the MAC spec, this has the effect of restarting the MAC DMA). However, without freeing any rx descriptors, the DMA stops right away, and another overflow interrupt is raised as the FIFO overflows again. Since the DMA is already restarted at the end of stmmac_rx_refill() after freeing descriptors, disabling FIFO overflow interrupts and the corresponding handling code has no side effect, and eliminates the interrupt storm when the RX FIFO overflows. Signed-off-by: Yannick Vignon --- drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 7 +------ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 14 ++------------ 2 files changed, 3 insertions(+), 18 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c index a602d16b9e53..5be8e6a631d9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c @@ -232,7 +232,7 @@ static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode, u32 channel, int fifosz, u8 qmode) { unsigned int rqs = fifosz / 256 - 1; - u32 mtl_rx_op, mtl_rx_int; + u32 mtl_rx_op; mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel)); @@ -293,11 +293,6 @@ static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode, } writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel)); - - /* Enable MTL RX overflow */ - mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel)); - writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN, - ioaddr + MTL_CHAN_INT_CTRL(channel)); } static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode, diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index e0b7eebcb512..345b4c6d1fd4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -5587,7 +5587,6 @@ static void stmmac_common_interrupt(struct stmmac_priv *priv) /* To handle GMAC own interrupts */ if ((priv->plat->has_gmac) || xmac) { int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); - int mtl_status; if (unlikely(status)) { /* For LPI we need to save the tx status */ @@ -5598,17 +5597,8 @@ static void stmmac_common_interrupt(struct stmmac_priv *priv) } for (queue = 0; queue < queues_count; queue++) { - struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; - - mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw, - queue); - if (mtl_status != -EINVAL) - status |= mtl_status; - - if (status & CORE_IRQ_MTL_RX_OVERFLOW) - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, - rx_q->rx_tail_addr, - queue); + status = stmmac_host_mtl_irq_status(priv, priv->hw, + queue); } /* PCS link status */